x86: Patches to enable running U-Boot from coreboot

This is a ulong for some architectures and just unsigned for others. Change x86 to be consistent.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/include/asm/u-boot.h |    2 +-
 common/cmd_bdinfo.c           |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

arch/x86/include/asm/u-boot.h +1 -1

index da667c5..0671b8d 100644
@@ -48,7 +48,7 @@ typedef struct bd_info {
        unsigned short  bi_ethspeed;    /* Ethernet speed in Mbps */
        unsigned long   bi_intfreq;     /* Internal Freq, in MHz */
        unsigned long   bi_busfreq;     /* Bus Freq, in MHz */
-       unsigned int    bi_baudrate;    /* Console Baudrate */
+       unsigned long   bi_baudrate;    /* Console Baudrate */
        unsigned long   bi_boot_params; /* where this board expects params */
        struct                          /* RAM configuration */
        {

common/cmd_bdinfo.c +1 -2

index 23bd8a5..9bc0ebc 100644
@@ -439,7 +439,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        printf("ip_addr     = %s\n", getenv("ipaddr"));
        print_mhz("ethspeed",       bd->bi_ethspeed);
 #endif
-       printf("baudrate    = %d bps\n", bd->bi_baudrate);
+       printf("baudrate    = %ld bps\n", bd->bi_baudrate);
 
        return 0;
 }
--

1.7.7.3

This is a ulong for some architectures and just unsigned for others. Change x86 to be consistent.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/include/asm/u-boot.h |    2 +-
 common/cmd_bdinfo.c           |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

arch/x86/include/asm/u-boot.h +1 -1

index da667c5..0671b8d 100644
@@ -48,7 +48,7 @@ typedef struct bd_info {
        unsigned short  bi_ethspeed;    /* Ethernet speed in Mbps */
        unsigned long   bi_intfreq;     /* Internal Freq, in MHz */
        unsigned long   bi_busfreq;     /* Bus Freq, in MHz */
-       unsigned int    bi_baudrate;    /* Console Baudrate */
+       unsigned long   bi_baudrate;    /* Console Baudrate */
        unsigned long   bi_boot_params; /* where this board expects params */
        struct                          /* RAM configuration */
        {

common/cmd_bdinfo.c +1 -2

index 23bd8a5..9bc0ebc 100644
@@ -439,7 +439,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        printf("ip_addr     = %s\n", getenv("ipaddr"));
        print_mhz("ethspeed",       bd->bi_ethspeed);
 #endif
-       printf("baudrate    = %d bps\n", bd->bi_baudrate);
+       printf("baudrate    = %ld bps\n", bd->bi_baudrate);
 
        return 0;
 }
--

1.7.7.3

This is a ulong for some architectures and just unsigned for others. Change x86 to be consistent.

Dear Simon Glass,

Quoted 2 lines · In message <[email protected]> you wrote:

This is a ulong for some architectures and just unsigned for others. Change x86 to be consistent.

Given the limited range for this variable it makes no sense to use a long for this. Please fix this the other way round, i. e. change the architectures that use a long.

Dear Simon Glass,

Quoted 2 lines · In message <[email protected]> you wrote:

This is a ulong for some architectures and just unsigned for others. Change x86 to be consistent.

Given the limited range for this variable it makes no sense to use a long for this. Please fix this the other way round, i. e. change the architectures that use a long.

Thanks.

Best regards,

Wolfgang Denk

--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Always try to do things in chronological order; it's less confusing that way.

Hi Wolfgang,

Quoted 3 lines · Wolfgang Denk

Dear Simon Glass,

In message <[email protected]> you wrote:

Quoted 6 lines

Quoted 2 lines

This is a ulong for some architectures and just unsigned for others. Change x86 to be consistent.

Given the limited range for this variable it makes no sense to use a long for this. Please fix this the other way round, i. e. change the architectures that use a long.

OK I will send out a series that changes them to unsigned long.

Hi Simon,

Quoted 9 lines · Simon Glass

Hi Wolfgang,

Quoted 6 lines · Wolfgang Denk

Dear Simon Glass,

Quoted 2 lines · In message <[email protected]> you wrote:

This is a ulong for some architectures and just unsigned for others. Change x86 to be consistent.

Quoted 5 lines

Quoted 3 lines

Given the limited range for this variable it makes no sense to use a long for this. Please fix this the other way round, i. e. change the architectures that use a long.

OK I will send out a series that changes them to unsigned long.

Should we just change them all to u32 to be clear on the value range?

Regards,

Graeme

Hi,

Quoted 16 lines · Graeme Russ

Hi Simon,

Quoted 13 lines · Simon Glass

Hi Wolfgang,

Quoted 9 lines · Wolfgang Denk

Dear Simon Glass,

Quoted 2 lines · In message <[email protected]> you wrote:

This is a ulong for some architectures and just unsigned for others. Change x86 to be consistent.

Given the limited range for this variable it makes no sense to use a long for this. Please fix this the other way round, i. e. change the architectures that use a long.

Quoted 3 lines

Quoted 1 line

OK I will send out a series that changes them to unsigned long.

Should we just change them all to u32 to be clear on the value range?

Sorry, I meant unsigned int.

Are there architectures in U-Boot which use a 16-bit int?

Hi Simon,

Quoted 19 lines · Simon Glass

Hi,

Quoted 16 lines · Graeme Russ

Hi Simon,

Quoted 13 lines · Simon Glass

Hi Wolfgang,

Quoted 9 lines · Wolfgang Denk

Dear Simon Glass,

Quoted 2 lines · In message <[email protected]> you wrote:

This is a ulong for some architectures and just unsigned for others. Change x86 to be consistent.

Given the limited range for this variable it makes no sense to use a long for this. Please fix this the other way round, i. e. change the architectures that use a long.

Quoted 7 lines

Quoted 3 lines

Quoted 1 line

OK I will send out a series that changes them to unsigned long.

Should we just change them all to u32 to be clear on the value range?

Sorry, I meant unsigned int.

Are there architectures in U-Boot which use a 16-bit int?

The C standard does not guarantee unsigned int will be at least 32-bits. It is possible (although I have not checked it) that compiling 'real-mode' x86 code can produce 16-bit ints (not that we do that in U-Boot)

using u32 will always guarantee a 32-bit unsigned value - better to be safe than sorry

Regards,

Graeme

These are available on other architectures, so add them on x86.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/include/asm/io.h |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

arch/x86/include/asm/io.h +8 -1

index 9b757d4..b12bdd8 100644
@@ -234,4 +234,12 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
        return (phys_addr_t)(vaddr);
 }
 
+/*
+ * TODO: The kernel offers some more advanced versions of barriers, it might
+ * have some advantages to use them instead of the simple one here.
+ */
+#define dmb()          __asm__ __volatile__ ("" : : : "memory")
+#define __iormb()      dmb()
+#define __iowmb()      dmb()
+
 #endif
--

1.7.7.3

From: Gabe Black <[email protected]>

When running from coreboot we don't want this code.

This version works by ifdef-ing out all of the code that would go into those sections and all the code that refers to it. The sections are then empty, and the linker will either leave them empty for the loader to ignore or remove them entirely.

Signed-off-by Gabe Black <[email protected]>

Signed-off-by Simon Glass <[email protected]>

---
Changes in v2:
- Put CONFIG_NO_RESET_CODE into Makefile instead of source files

 Makefile                |    7 +++++--
 arch/x86/cpu/Makefile   |    5 ++++-
 arch/x86/cpu/u-boot.lds |    3 +++
 3 files changed, 12 insertions(+), 3 deletions(-)

Makefile +5 -2

index 34d9075..6c2f357 100644
@@ -212,9 +212,12 @@ endif
 # U-Boot objects....order is important (i.e. start must be first)
 
 OBJS  = $(CPUDIR)/start.o
+OBJS  = $(CPUDIR)/start.o
 ifeq ($(CPU),x86)
-OBJS += $(CPUDIR)/start16.o
-OBJS += $(CPUDIR)/resetvec.o
+       ifneq ($(CONFIG_NO_RESET_CODE),y)
+               OBJS += $(CPUDIR)/start16.o
+               OBJS += $(CPUDIR)/resetvec.o
+       endif
 endif
 ifeq ($(CPU),ppc4xx)
 OBJS += $(CPUDIR)/resetvec.o

arch/x86/cpu/Makefile +4 -1

index 7f1fc18..1eb70a7 100644
@@ -28,7 +28,10 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(CPU).o
 
-START  = start.o start16.o resetvec.o
+START  = start.o
+ifneq ($(CONFIG_NO_RESET_CODE),y)
+START  += resetvec.o start16.o
+endif
 COBJS  = interrupts.o cpu.o
 
 SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)

arch/x86/cpu/u-boot.lds +3 -1

index fe28030..2a90a01 100644
@@ -85,6 +85,8 @@ SECTIONS
        __bios_start = LOADADDR(.bios);
        __bios_size = SIZEOF(.bios);
 
+#ifndef CONFIG_NO_RESET_CODE
+
        /*
         * The following expressions place the 16-bit Real-Mode code and
         * Reset Vector at the end of the Flash ROM

@@ -94,4 +96,5 @@ SECTIONS
 
        . = RESET_VEC_LOC;
        .resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); }
+#endif
 }
--

1.7.7.3

From: Gabe Black <[email protected]>

When running from coreboot we don't want this code.

This version works by ifdef-ing out all of the code that would go into those sections and all the code that refers to it. The sections are then empty, and the linker will either leave them empty for the loader to ignore or remove them entirely.

Signed-off-by Gabe Black <[email protected]>

Signed-off-by Simon Glass <[email protected]>

---
Changes in v2:
- Put CONFIG_NO_RESET_CODE into Makefile instead of source files

 Makefile                |    7 +++++--
 arch/x86/cpu/Makefile   |    5 ++++-
 arch/x86/cpu/u-boot.lds |    3 +++
 3 files changed, 12 insertions(+), 3 deletions(-)

Makefile +0 -0

index 34d9075..6c2f357 100644
@@ -212,9 +212,12 @@ endif
 # U-Boot objects....order is important (i.e. start must be first)

Dear Simon Glass,

Quoted 9 lines · In message <[email protected]> you wrote:

From: Gabe Black <[email protected]>

When running from coreboot we don't want this code.

This version works by ifdef-ing out all of the code that would go into those sections and all the code that refers to it. The sections are then empty, and the linker will either leave them empty for the loader to ignore or remove them entirely.

Quoted 5 lines

Signed-off-by Gabe Black <[email protected]>

Signed-off-by Simon Glass <[email protected]>

---
Changes in v2:
- Put CONFIG_NO_RESET_CODE into Makefile instead of source files

What exactly is CONFIG_NO_RESET_CODE ?

There is no documentation anywhere for such a config option as is mandatory when introducing it, nor is there any comment why it would be needed, nor are there any users for it.

Quoted 12 lines

 Makefile                |    7 +++++--
 arch/x86/cpu/Makefile   |    5 ++++-
 arch/x86/cpu/u-boot.lds |    3 +++
 3 files changed, 12 insertions(+), 3 deletions(-)

Makefile +0 -0

index 34d9075..6c2f357 100644
@@ -212,9 +212,12 @@ endif
 # U-Boot objects....order is important (i.e. start must be first)

Makefile endif · line 220

Quoted 10 lines

Makefile +5 -2

 
 OBJS  = $(CPUDIR)/start.o
+OBJS  = $(CPUDIR)/start.o
 ifeq ($(CPU),x86)
-OBJS += $(CPUDIR)/start16.o
-OBJS += $(CPUDIR)/resetvec.o
+     ifneq ($(CONFIG_NO_RESET_CODE),y)
+             OBJS += $(CPUDIR)/start16.o
+             OBJS += $(CPUDIR)/resetvec.o
+     endif

NAK. Bad indentation, and please do without 'if's or the like.

arch/x86/cpu/Makefile include $(TOPDIR)/config.mk · line 34

Quoted 11 lines

arch/x86/cpu/Makefile +4 -1

@@ -28,7 +28,10 @@ include $(TOPDIR)/config.mk
 
 LIB  = $(obj)lib$(CPU).o
 
-START        = start.o start16.o resetvec.o
+START        = start.o
+ifneq ($(CONFIG_NO_RESET_CODE),y)
+START        += resetvec.o start16.o
+endif

Ditto.

arch/x86/cpu/u-boot.lds SECTIONS · line 88

Quoted 7 lines

arch/x86/cpu/u-boot.lds +1 -0

@@ -85,6 +85,8 @@ SECTIONS
      __bios_start = LOADADDR(.bios);
      __bios_size = SIZEOF(.bios);
 
+#ifndef CONFIG_NO_RESET_CODE

Undocumented.

Best regards,

Wolfgang Denk

--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de If I can have honesty, it's easier to overlook mistakes.

        -- Kirk, "Space Seed", stardate 3141.9

From: Gabe Black <[email protected]>

I suspect these includes were usually available because something else included them earlier or because they were brought in transitively.

Signed-off-by Gabe Black <[email protected]>

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/include/asm/global_data.h |    2 ++
 arch/x86/include/asm/u-boot.h      |    3 +++
 2 files changed, 5 insertions(+), 0 deletions(-)

arch/x86/include/asm/global_data.h +2 -0

index 6d29c0b..3c79508 100644
@@ -33,6 +33,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/u-boot.h>
+
 typedef        struct global_data {
        /* NOTE: gd_addr MUST be first member of struct global_data! */
        unsigned long   gd_addr;        /* Location of Global Data */

arch/x86/include/asm/u-boot.h +3 -1

index 0671b8d..e2ba845 100644
@@ -36,6 +36,9 @@
 #ifndef _U_BOOT_H_
 #define _U_BOOT_H_     1
 
+#include <config.h>
+#include <compiler.h>
+
 typedef struct bd_info {
        unsigned long   bi_memstart;    /* start of DRAM memory */
        phys_size_t     bi_memsize;     /* size  of DRAM memory in bytes */
--

1.7.7.3

From: Stefan Reinauer <[email protected]>

coreboot.c and coreboot_pci.c don't contain board specific but only coreboot specific code. Hence move it to the coreboot directory in arch/x86/cpu (which should probably be moved out of cpu/ in another commit)

Signed-off-by Stefan Reinauer <[email protected]>

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/coreboot/Makefile                     |    2 ++
 .../x86/cpu}/coreboot/coreboot.c                   |    0
 .../coreboot_pci.c => arch/x86/cpu/coreboot/pci.c  |    0
 board/chromebook-x86/coreboot/Makefile             |    2 --
 4 files changed, 2 insertions(+), 2 deletions(-)
 rename {board/chromebook-x86 => arch/x86/cpu}/coreboot/coreboot.c (100%)
 rename board/chromebook-x86/coreboot/coreboot_pci.c => arch/x86/cpu/coreboot/pci.c (100%)

arch/x86/cpu/coreboot/Makefile +2 -0

index 13f5f8a..fbf5a00 100644
@@ -33,10 +33,12 @@ include $(TOPDIR)/config.mk
 
 LIB    := $(obj)lib$(SOC).o
 
+COBJS-$(CONFIG_SYS_COREBOOT) += coreboot.o
 COBJS-$(CONFIG_SYS_COREBOOT) += tables.o
 COBJS-$(CONFIG_SYS_COREBOOT) += ipchecksum.o
 COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o
 COBJS-$(CONFIG_SYS_COREBOOT) += sysinfo.o
+COBJS-$(CONFIG_PCI) += pci.o
 
 SOBJS-$(CONFIG_SYS_COREBOOT) += coreboot_car.o
 

arch/x86/cpu/coreboot/coreboot.c renamed from board/chromebook-x86/coreboot/coreboot.c +0 -0

similarity index 100%
rename from board/chromebook-x86/coreboot/coreboot.c
rename to arch/x86/cpu/coreboot/coreboot.c

arch/x86/cpu/coreboot/pci.c renamed from board/chromebook-x86/coreboot/coreboot_pci.c +0 -0

similarity index 100%
rename from board/chromebook-x86/coreboot/coreboot_pci.c
rename to arch/x86/cpu/coreboot/pci.c

board/chromebook-x86/coreboot/Makefile +0 -3

index cfcc0df..2bddf04 100644
@@ -32,8 +32,6 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
-COBJS-y        += coreboot.o
-COBJS-$(CONFIG_PCI) += coreboot_pci.o
 SOBJS-y        += coreboot_start16.o
 SOBJS-y        += coreboot_start.o
 
--

1.7.7.3

From: Gabe Black <[email protected]>

U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point.

It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it.

Signed-off-by Gabe Black <[email protected]>

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/coreboot/pci.c |   15 +++++++++++++++
 arch/x86/include/asm/pci.h  |    2 +-
 2 files changed, 16 insertions(+), 1 deletions(-)

arch/x86/cpu/coreboot/pci.c +15 -0

index 732ca3c..0ddc975 100644
@@ -25,6 +25,21 @@
  * MA 02111-1307 USA
  */
 
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+
+static struct pci_controller coreboot_hose;
+
 void pci_init_board(void)
 {
+       coreboot_hose.first_busno = 0;
+       coreboot_hose.last_busno = 0xff;
+       coreboot_hose.region_count = 0;
+
+       pci_setup_type1(&coreboot_hose);
+
+       pci_register_hose(&coreboot_hose);
+
+       coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose);
 }

arch/x86/include/asm/pci.h +1 -2

index 37cc7e3..6d68ab6 100644
@@ -24,7 +24,7 @@
  */
 
 #ifndef _PCI_I386_H_
-#define _PCI_I386_H_   1
+#define _PCI_I386_H_
 
 #define DEFINE_PCI_DEVICE_TABLE(_table) \
        const struct pci_device_id _table[]
--

1.7.7.3

From: Vadim Bendebury <[email protected]>

This prevents the preprocessor from complaining when processing variadic macros

Signed-off-by Vadim Bendebury <[email protected]>

Signed-off-by Simon Glass <[email protected]>

---

 board/chromebook-x86/coreboot/config.mk |   37 +++++++++++++++++++++++++++++++
 1 files changed, 37 insertions(+), 0 deletions(-)
 create mode 100644 board/chromebook-x86/coreboot/config.mk

board/chromebook-x86/coreboot/config.mk new file +37 -1

new file mode 100644
index 0000000..f720851
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above
+# copyright notice, this list of conditions and the following disclaimer
+# in the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of Google Inc. nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Alternatively, this software may be distributed under the terms of the
+# GNU General Public License ("GPL") version 2 as published by the Free
+# Software Foundation.
+#
+
+HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
--

1.7.7.3

From: Gabe Black <[email protected]>

A hook is installed to configure PCI bus bridges as they encountered by u-boot. The hook extracts the secondary bus number from the bridge's config space and then recursively scans that bus.

On Coreboot, the PCI bus address space has identity mapping with the physical address space, so declare it as such to ensure that the "pci_map_bar" function used by some PCI drivers is behaving properly. This fixes the EHCI PCI driver initialization on Stumpy.

This was tested as follows:

Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on bus 1, and empty busses 2 through 5. This matches the bridges reported on bus 0 and the PCI configuration output from coreboot.

Signed-off-by Gabe Black <[email protected]>

Signed-off-by Vincent Palatin <[email protected]>

Signed-off-by Stefan Reinauer <[email protected]>

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/coreboot/pci.c |   26 +++++++++++++++++++++++---
 1 files changed, 23 insertions(+), 3 deletions(-)

arch/x86/cpu/coreboot/pci.c +23 -4

index 0ddc975..8f94167 100644
@@ -31,15 +31,35 @@
 
 static struct pci_controller coreboot_hose;
 
+static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
+                             struct pci_config_table *table)
+{
+       u8 secondary;
+       hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
+       hose->last_busno = max(hose->last_busno, secondary);
+       pci_hose_scan_bus(hose, secondary);
+}
+
+static struct pci_config_table pci_coreboot_config_table[] = {
+       /* vendor, device, class, bus, dev, func */
+       { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
+               PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
+       {}
+};
+
 void pci_init_board(void)
 {
+       coreboot_hose.config_table = pci_coreboot_config_table;
        coreboot_hose.first_busno = 0;
-       coreboot_hose.last_busno = 0xff;
-       coreboot_hose.region_count = 0;
+       coreboot_hose.last_busno = 0;
+
+       pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
+               PCI_REGION_MEM);
+       coreboot_hose.region_count = 1;
 
        pci_setup_type1(&coreboot_hose);
 
        pci_register_hose(&coreboot_hose);
 
-       coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose);
+       pci_hose_scan(&coreboot_hose);
 }
--

1.7.7.3

Coreboot boards have an LPC TPM connected, so enable this. We also need to skip the reset code.

Signed-off-by Simon Glass <[email protected]>

---

 include/configs/coreboot.h |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

include/configs/coreboot.h +5 -2

index 2c65d74..75db176 100644
@@ -37,7 +37,7 @@
 #define CONFIG_SYS_COREBOOT
 #undef CONFIG_SHOW_BOOT_PROGRESS
 #define CONFIG_LAST_STAGE_INIT
-
+#define CONFIG_NO_RESET_CODE
 
 /*-----------------------------------------------------------------------
  * Watchdog Configuration

@@ -45,6 +45,10 @@
 #undef CONFIG_WATCHDOG
 #undef CONFIG_HW_WATCHDOG
 
+/* Generic TPM interfaced through LPC bus */
+#define CONFIG_GENERIC_LPC_TPM
+#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
+
 /*-----------------------------------------------------------------------
  * Real Time Clock Configuration
  */
--

1.7.7.3

Hi Simon,

Quoted 40 lines · Simon Glass

Coreboot boards have an LPC TPM connected, so enable this. We also need to skip the reset code.

Signed-off-by Simon Glass <[email protected]>

---

 include/configs/coreboot.h |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

include/configs/coreboot.h +1 -1

index 2c65d74..75db176 100644
@@ -37,7 +37,7 @@
 
 #define CONFIG_SYS_COREBOOT
 #undef CONFIG_SHOW_BOOT_PROGRESS
 #define CONFIG_LAST_STAGE_INIT
 
-
+#define CONFIG_NO_RESET_CODE
 

/*---------------------------------------------------------------------- -

* Watchdog Configuration

include/configs/coreboot.h +4 -0

@@ -45,6 +45,10 @@
 
 #undef CONFIG_WATCHDOG
 #undef CONFIG_HW_WATCHDOG
 
+/* Generic TPM interfaced through LPC bus */
+#define CONFIG_GENERIC_LPC_TPM
+#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
+
 
 /*----------------------------------------------------------------------

-

Quoted 5 lines

* Real Time Clock Configuration
*/

--
1.7.7.3

Acked-by Graeme Russ <[email protected]>

Dear Graeme Russ,

Quoted 46 lines

Hi Simon,

Quoted 43 lines · Simon Glass

Coreboot boards have an LPC TPM connected, so enable this. We also need to skip the reset code.

Signed-off-by Simon Glass <[email protected]>

---

 include/configs/coreboot.h |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

include/configs/coreboot.h +1 -1

index 2c65d74..75db176 100644
@@ -37,7 +37,7 @@
 
 #define CONFIG_SYS_COREBOOT
 #undef CONFIG_SHOW_BOOT_PROGRESS
 #define CONFIG_LAST_STAGE_INIT
 
-
+#define CONFIG_NO_RESET_CODE
 

/*---------------------------------------------------------------------- -

* Watchdog Configuration

include/configs/coreboot.h +4 -0

@@ -45,6 +45,10 @@
 
 #undef CONFIG_WATCHDOG
 #undef CONFIG_HW_WATCHDOG
 
+/* Generic TPM interfaced through LPC bus */
+#define CONFIG_GENERIC_LPC_TPM
+#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
+
 
 /*----------------------------------------------------------------------

-

* Real Time Clock Configuration
*/

Quoted 4 lines

Quoted 2 lines

--
1.7.7.3

Acked-by Graeme Russ <[email protected]>

Well, spliting it into two patches -- since each hunk does something else -- won't hurt. But I think it doesn't matter.

Now that coreboot doesn't need the start16 code, remove it.

Signed-off-by Simon Glass <[email protected]>

---
Changes in v2:
- Add new patch to remove coreboot start16 code.

 board/chromebook-x86/coreboot/coreboot_start16.S |   13 -------------
 1 files changed, 0 insertions(+), 13 deletions(-)

board/chromebook-x86/coreboot/coreboot_start16.S +0 -14

index 9ad06df..6b3d92d 100644
@@ -22,19 +22,6 @@
  * MA 02111-1307 USA
  */
 
-/*
- * 16bit initialization code.
- * This code have to map the area of the boot flash
- * that is used by U-boot to its final destination.
- */
-
-.text
-.section .start16, "ax"
-.code16
-.globl board_init16
-board_init16:
-       jmp     board_init16_ret
-
 .section .bios, "ax"
 .code16
 .globl realmode_reset
--

1.7.7.3