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ipu common: reset ipuv3 correctly

PATCH New Liu Ying 3 participants 3 messages Oct 6, 2012 – Oct 19, 2012 Framebuffer layer

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Liu Ying

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#0 lore raw

PATCH 1/1 ipu common: reset ipuv3 correctly

From: Liu Ying <[email protected]>

This patch checks self-clear sw_ipu_rst bit in SCR register of SRC controller to be cleared after setting it to high to reset IPUv3. This makes sure that IPUv3 finishes sofware reset. A timeout mechanism is added to stop polling on the bit status in case the bit could not be cleared by the hardware automatically within 10 millisecond.

Signed-off-by Liu Ying <[email protected]>
---
 drivers/video/ipu_common.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)
drivers/video/ipu_common.c +10 -0
index 2020da9..fcc1745 100644
@@ -94,6 +94,7 @@ struct ipu_ch_param {
 	temp1; \
 })
 
+#define IPU_SW_RST_TOUT_USEC	(10000)
 
 void clk_enable(struct clk *clk)
 {

@@ -392,11 +393,20 @@ void ipu_reset(void)
 {
 	u32 *reg;
 	u32 value;
+	int timeout = IPU_SW_RST_TOUT_USEC;
 
 	reg = (u32 *)SRC_BASE_ADDR;
 	value = __raw_readl(reg);
 	value = value | SW_IPU_RST;
 	__raw_writel(value, reg);
+
+	while (__raw_readl(reg) & SW_IPU_RST) {
+		udelay(1);
+		if (!(timeout--)) {
+			printf("ipu software reset timeout\n");
+			break;
+		}
+	};
 }
 
 /*
Signature · 1 line
1.7.1
#1 lore raw

PATCH 1/1 ipu common: reset ipuv3 correctly

Hi Liu Ying,

Quoted 39 lines · Liu Ying

From: Liu Ying<[email protected]>

This patch checks self-clear sw_ipu_rst bit in SCR register of SRC controller to be cleared after setting it to high to reset IPUv3. This makes sure that IPUv3 finishes sofware reset. A timeout mechanism is added to stop polling on the bit status in case the bit could not be cleared by the hardware automatically within 10 millisecond.

Signed-off-by Liu Ying<[email protected]>
---
  drivers/video/ipu_common.c |   10 ++++++++++
  1 files changed, 10 insertions(+), 0 deletions(-)
drivers/video/ipu_common.c +3 -0
index 2020da9..fcc1745 100644
@@ -94,6 +94,7 @@ struct ipu_ch_param {
  	temp1; \
  })
 
+#define IPU_SW_RST_TOUT_USEC	(10000)
 
  void clk_enable(struct clk *clk)
  {

@@ -392,11 +393,20 @@ void ipu_reset(void)
  {
  	u32 *reg;
  	u32 value;
+	int timeout = IPU_SW_RST_TOUT_USEC;
 
  	reg = (u32 *)SRC_BASE_ADDR;
  	value = __raw_readl(reg);
  	value = value | SW_IPU_RST;
  	__raw_writel(value, reg);
+

drivers/video/ipu_common.c void ipu_reset(void) · line 412

Quoted 10 lines
drivers/video/ipu_common.c +7 -0
+	while (__raw_readl(reg)&  SW_IPU_RST) {
+		udelay(1);
+		if (!(timeout--)) {
+			printf("ipu software reset timeout\n");
+			break;
+		}
+	};
  }
 
  /*

Tested in the normal (successful) case on SABRE Lite.

Is there a situation under which this is known to fail or is that a hypothetical?

Applied
#2 lore raw

PATCH 1/1 ipu common: reset ipuv3 correctly

In reply to Liu Ying

Hi,

Quoted 11 lines · On Sat, 6 Oct 2012 22:16:04 +0800 Liu Ying <[email protected]> wrote:

From: Liu Ying <[email protected]>

This patch checks self-clear sw_ipu_rst bit in SCR register of SRC controller to be cleared after setting it to high to reset IPUv3. This makes sure that IPUv3 finishes sofware reset. A timeout mechanism is added to stop polling on the bit status in case the bit could not be cleared by the hardware automatically within 10 millisecond.

Quoted 4 lines
Signed-off-by Liu Ying <[email protected]>
---
 drivers/video/ipu_common.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

applied, thanks!

Anatolij