arm:socfpga: Enable SMP for socfpga

PATCH Superseded dinguyen at altera.com 5 participants 11 messages Oct 18, 2012 – Oct 27, 2012

Subsystems (4)

Device tree bindings Arm (32-bit) Arm sub-architectures Arm/socfpga architecture

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dinguyen at altera.com

author

2012-10-18 17:32 UTC #0 lore raw

PATCH v2 1/1 arm:socfpga: Enable SMP for socfpga

From: Dinh Nguyen <[email protected]>

Enable SMP for the SOCFPGA platform.

Signed-off-by Pavel Machek <[email protected]>

Signed-off-by Dinh Nguyen <[email protected]>

---
v2:
-Remove pen_release code
-Remove code that was already done by v7_setup
-Add bindings document for reset and system manager -Move socfpga_sysmgr_init from platsmp.c to socfpga.c, because we will need to use the reset and system manager for more than SMP. -Move core.h to mach-socfpga from mach-socfpga/include/mach

---
 .../bindings/arm/altera/socfpga-reset.txt          |   11 ++
 .../bindings/arm/altera/socfpga-system.txt         |   11 ++
 arch/arm/boot/dts/socfpga.dtsi                     |   10 ++
 arch/arm/configs/socfpga_defconfig                 |    9 +-
 arch/arm/mach-socfpga/Kconfig                      |    1 +
 arch/arm/mach-socfpga/Makefile                     |    1 +
 arch/arm/mach-socfpga/core.h                       |   34 ++++++
 arch/arm/mach-socfpga/headsmp.S                    |   24 ++++
 arch/arm/mach-socfpga/platsmp.c                    |  117 ++++++++++++++++++++
 arch/arm/mach-socfpga/socfpga.c                    |   45 +++++++-
 10 files changed, 259 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
 create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-system.txt
 create mode 100644 arch/arm/mach-socfpga/core.h
 create mode 100644 arch/arm/mach-socfpga/headsmp.S
 create mode 100644 arch/arm/mach-socfpga/platsmp.c

Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt new file +11 -0

new file mode 100644
index 0000000..ecdb57d
@@ -0,0 +1,11 @@
+Altera SOCFPGA Reset Manager
+
+Required properties:
+- compatible : "altr,rst-mgr"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+	 rstmgr at ffd05000 {
+		compatible = "altr,rst-mgr";
+		reg = <0xffd05000 0x1000>;
+	};

Documentation/devicetree/bindings/arm/altera/socfpga-system.txt new file +11 -0

new file mode 100644
index 0000000..07c65e3
@@ -0,0 +1,11 @@
+Altera SOCFPGA System Manager
+
+Required properties:
+- compatible : "altr,sys-mgr"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+	 sysmgr at ffd08000 {
+		compatible = "altr,sys-mgr";
+		reg = <0xffd08000 0x1000>;
+	};

arch/arm/boot/dts/socfpga.dtsi +10 -0

index 0772f57..19aec42 100644
@@ -143,5 +143,15 @@
 			reg-shift = <2>;
 			reg-io-width = <4>;
 		};
+
+		rstmgr at ffd05000 {
+				compatible = "altr,rst-mgr";
+				reg = <0xffd05000 0x1000>;
+			};
+
+		sysmgr at ffd08000 {
+				compatible = "altr,sys-mgr";
+				reg = <0xffd08000 0x4000>;
+			};
 	};
 };

arch/arm/configs/socfpga_defconfig +6 -3

index 0ac1293..349ac22 100644
@@ -1,5 +1,5 @@
 CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14

@@ -16,10 +16,13 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_MACH_SOCFPGA_CYCLONE5=y
-CONFIG_ARM_THUMBEE=y
+# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
 CONFIG_VMSPLIT_2G=y
 CONFIG_NR_CPUS=2
 CONFIG_AEABI=y

arch/arm/mach-socfpga/Kconfig +1 -0

index 803a328..566e804 100644
@@ -12,5 +12,6 @@ config ARCH_SOCFPGA
 	select GENERIC_CLOCKEVENTS
 	select GPIO_PL061 if GPIOLIB
 	select HAVE_ARM_SCU
+	select HAVE_SMP
 	select SPARSE_IRQ
 	select USE_OF

arch/arm/mach-socfpga/Makefile +1 -0

index 4fb9324..6dd7a93 100644
@@ -3,3 +3,4 @@
 #
 
 obj-y					:= socfpga.o
+obj-$(CONFIG_SMP)	+= headsmp.o platsmp.o

arch/arm/mach-socfpga/core.h new file +34 -0

new file mode 100644
index 0000000..9941caa
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2012 Pavel Machek <[email protected]>
+ * Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __MACH_CORE_H
+#define __MACH_CORE_H
+
+extern void secondary_startup(void);
+extern void __iomem *socfpga_scu_base_addr;
+
+extern void socfpga_init_clocks(void);
+extern void socfpga_sysmgr_init(void);
+
+extern struct smp_operations socfpga_smp_ops;
+extern char secondary_trampoline, secondary_trampoline_end;
+
+#define SOCFPGA_SCU_VIRT_BASE   0xfffec000
+
+#endif

arch/arm/mach-socfpga/headsmp.S new file +24 -0

new file mode 100644
index 0000000..17d6eaf
@@ -0,0 +1,24 @@
+/*
+ *  Copyright (c) 2003 ARM Limited
+ *  Copyright (c) u-boot contributors
+ *  Copyright (c) 2012 Pavel Machek <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+	__INIT
+
+#define CPU1_START_ADDR 	        0xffd08010
+
+ENTRY(secondary_trampoline)
+	movw	r0, #:lower16:CPU1_START_ADDR
+	movt  r0, #:upper16:CPU1_START_ADDR
+
+	ldr	r1, [r0]
+	bx	r1
+
+ENTRY(secondary_trampoline_end)

arch/arm/mach-socfpga/platsmp.c new file +117 -0

117 lines not on this page · raw message

arch/arm/mach-socfpga/socfpga.c +44 -1

73 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Pavel Machek

2012-10-24 22:43 UTC #1 lore raw

PATCH v2 1/1 arm:socfpga: Enable SMP for socfpga

Hi!

Quoted 3 lines

From: Dinh Nguyen <[email protected]>
Enable SMP for the SOCFPGA platform.

Arnd, there were no comments on this, and at least Rob Herring reviewed PATCHv1. I guess that means that this patch is perfect. Could we get it applied somewhere?
Pavel

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Thomas Petazzoni

2012-10-24 22:57 UTC #2 lore raw

PATCH v2 1/1 arm:socfpga: Enable SMP for socfpga

In reply to dinguyen at altera.com

Dear dinguyen at altera.com,

arch/arm/mach-socfpga/platsmp.c line 54

Quoted 9 lines · dinguyen at altera.com

arch/arm/mach-socfpga/platsmp.c new file +9 -0

+static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
+
+	memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+
+	__raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
+
+	pen_release = 0;

Are you sure that this code builds? In your v1, this variable was declared in your assembly file, but it is no longer here, and you mention in your changelog that it has been removed. But not completely apparently.

Best regards,

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Dinh Nguyen

author

2012-10-25 16:21 UTC #3 lore raw

PATCH v2 1/1 arm:socfpga: Enable SMP for socfpga

Hi Thomas,

Quoted 4 lines · Thomas Petazzoni

Dear dinguyen at altera.com,
On Thu, 18 Oct 2012 11:32:47 -0600, dinguyen at altera.com wrote:

Quoted 14 lines

arch/arm/mach-socfpga/platsmp.c line 54
Quoted 9 lines
arch/arm/mach-socfpga/platsmp.c new file +9 -0
+static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
+
+	memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+
+	__raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
+
+	pen_release = 0;
Are you sure that this code builds? In your v1, this variable was declared in your assembly file, but it is no longer here, and you mention in your changelog that it has been removed. But not completely apparently.

It builds because pen_release is in <asm/smp.h> for arm. But you're right, there is no need for this variable anymore. Thanks for the review.

Dinh

Quoted 4 lines

Best regards,
Thomas

Rob Herring

2012-10-24 23:01 UTC #4 lore raw

PATCH v2 1/1 arm:socfpga: Enable SMP for socfpga

In reply to dinguyen at altera.com

Quoted 12 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>
Enable SMP for the SOCFPGA platform.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>
---
v2:
(quoted diff) +0 -4
-Remove pen_release code
-Remove code that was already done by v7_setup
-Add bindings document for reset and system manager
-Move socfpga_sysmgr_init from platsmp.c to socfpga.c, because

Quoted 2 lines

we will need to use the reset and system manager for more than SMP. -Move core.h to mach-socfpga from mach-socfpga/include/mach

Just some lingering comments on the defconfig. Otherwise,

Reviewed-by Rob Herring <[email protected]>

arch/arm/configs/socfpga_defconfig

Quoted 4 lines

arch/arm/configs/socfpga_defconfig +0 -0
index 0ac1293..349ac22 100644

I'm still not clear why multi_v7 config does not work for you?

Quoted 8 lines

arch/arm/configs/socfpga_defconfig +1 -1

@@ -1,5 +1,5 @@
 CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14

arch/arm/configs/socfpga_defconfig CONFIG_MODULE_UNLOAD=y · line 23

Quoted 10 lines

arch/arm/configs/socfpga_defconfig +3 -2

@@ -16,10 +16,13 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_MACH_SOCFPGA_CYCLONE5=y
-CONFIG_ARM_THUMBEE=y
+# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_ARM_ARCH_TIMER=y

You're an A9, right? You don't have arch timers.

arch/arm/configs/socfpga_defconfig CONFIG_MODULE_UNLOAD=y · line 24

Quoted 1 line

arch/arm/configs/socfpga_defconfig +1 -0
+CONFIG_HIGHMEM=y

How much RAM? You need more than 2GB with CONFIG_VMSPLIT_2G.

Quoted 4 lines

arch/arm/configs/socfpga_defconfig +1 -0

+CONFIG_HIGHPTE=y
 CONFIG_VMSPLIT_2G=y
 CONFIG_NR_CPUS=2
 CONFIG_AEABI=y

Dinh Nguyen

author

2012-10-25 16:25 UTC #5 lore raw

PATCH v2 1/1 arm:socfpga: Enable SMP for socfpga

Hi Rob,

Quoted 18 lines · Rob Herring

Quoted 12 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
Enable SMP for the SOCFPGA platform.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>
---
v2:
(quoted diff) +0 -4
-Remove pen_release code
-Remove code that was already done by v7_setup
-Add bindings document for reset and system manager
-Move socfpga_sysmgr_init from platsmp.c to socfpga.c, because
Quoted 2 lines
we will need to use the reset and system manager for more than SMP. -Move core.h to mach-socfpga from mach-socfpga/include/mach
Just some lingering comments on the defconfig. Otherwise,

Quoted 8 lines

Reviewed-by Rob Herring <[email protected]>
arch/arm/configs/socfpga_defconfig
Quoted 4 lines
arch/arm/configs/socfpga_defconfig +0 -0
index 0ac1293..349ac22 100644
I'm still not clear why multi_v7 config does not work for you?

multi_v7 works fine for me. But I need +#CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set

in order for SMP to work correctly on our platform.

Quoted 13 lines

arch/arm/configs/socfpga_defconfig +1 -2

@@ -1,5 +1,5 @@
 CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14

@@ -16,10 +16,13 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_MACH_SOCFPGA_CYCLONE5=y

Quoted 8 lines

arch/arm/configs/socfpga_defconfig CONFIG_MODULE_UNLOAD=y · line 23
Quoted 6 lines
arch/arm/configs/socfpga_defconfig +3 -1
-CONFIG_ARM_THUMBEE=y
+# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_ARM_ARCH_TIMER=y
You're an A9, right? You don't have arch timers.

Yes, will remove in v3.

Quoted 4 lines

arch/arm/configs/socfpga_defconfig CONFIG_MODULE_UNLOAD=y · line 24
Quoted 2 lines
arch/arm/configs/socfpga_defconfig +1 -0
+CONFIG_HIGHMEM=y
How much RAM? You need more than 2GB with CONFIG_VMSPLIT_2G.

1G for RAM only, so will remove in v3.

Thanks,
Dinh

Quoted 7 lines

Quoted 5 lines
arch/arm/configs/socfpga_defconfig +1 -0
+CONFIG_HIGHPTE=y
 CONFIG_VMSPLIT_2G=y
 CONFIG_NR_CPUS=2
 CONFIG_AEABI=y

Rob Herring

2012-10-25 15:41 UTC #6 lore raw

PATCH v2 1/1 arm:socfpga: Enable SMP for socfpga

Quoted 30 lines · Dinh Nguyen

Hi Rob,
Quoted 18 lines · Rob Herring
Quoted 12 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
Enable SMP for the SOCFPGA platform.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>
---
v2:
(quoted diff) +0 -4
-Remove pen_release code
-Remove code that was already done by v7_setup
-Add bindings document for reset and system manager
-Move socfpga_sysmgr_init from platsmp.c to socfpga.c, because
Quoted 2 lines
we will need to use the reset and system manager for more than SMP. -Move core.h to mach-socfpga from mach-socfpga/include/mach
Just some lingering comments on the defconfig. Otherwise,
Quoted 8 lines
Reviewed-by Rob Herring <[email protected]>
arch/arm/configs/socfpga_defconfig
Quoted 4 lines
arch/arm/configs/socfpga_defconfig +0 -0
index 0ac1293..349ac22 100644
I'm still not clear why multi_v7 config does not work for you?

Quoted 2 lines

multi_v7 works fine for me. But I need +#CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set

Why? I don't think those should break other versions of A9. If they do, we need to fix that. In general, we should turn on all errata for multi-platform builds, so we need to make sure they are done in a compatible way and can be bypassed if they have performance impacts. That may ultimately require some runtime patching though.

Rob

Quoted 46 lines

in order for SMP to work correctly on our platform.
Quoted 13 lines
Quoted 13 lines
arch/arm/configs/socfpga_defconfig +1 -2
@@ -1,5 +1,5 @@
 CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -16,10 +16,13 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_MACH_SOCFPGA_CYCLONE5=y
Quoted 8 lines
arch/arm/configs/socfpga_defconfig CONFIG_MODULE_UNLOAD=y · line 23
Quoted 6 lines
arch/arm/configs/socfpga_defconfig +3 -1
-CONFIG_ARM_THUMBEE=y
+# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_ARM_ARCH_TIMER=y
You're an A9, right? You don't have arch timers.
Yes, will remove in v3.
Quoted 4 lines
arch/arm/configs/socfpga_defconfig CONFIG_MODULE_UNLOAD=y · line 24
Quoted 2 lines
arch/arm/configs/socfpga_defconfig +1 -0
+CONFIG_HIGHMEM=y
How much RAM? You need more than 2GB with CONFIG_VMSPLIT_2G.
1G for RAM only, so will remove in v3.
Thanks,
Dinh
Quoted 7 lines
Quoted 5 lines
arch/arm/configs/socfpga_defconfig +1 -0
+CONFIG_HIGHPTE=y
 CONFIG_VMSPLIT_2G=y
 CONFIG_NR_CPUS=2
 CONFIG_AEABI=y

Dinh Nguyen

author

2012-10-25 17:49 UTC #7 lore raw

PATCH v2 1/1 arm:socfpga: Enable SMP for socfpga

HI Rob,

Quoted 32 lines · Rob Herring

Quoted 30 lines · Dinh Nguyen
Hi Rob,
Quoted 26 lines · Rob Herring
Quoted 12 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
Enable SMP for the SOCFPGA platform.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>
---
v2:
(quoted diff) +0 -4
-Remove pen_release code
-Remove code that was already done by v7_setup
-Add bindings document for reset and system manager
-Move socfpga_sysmgr_init from platsmp.c to socfpga.c, because
Quoted 2 lines
we will need to use the reset and system manager for more than SMP. -Move core.h to mach-socfpga from mach-socfpga/include/mach
Just some lingering comments on the defconfig. Otherwise,
Reviewed-by Rob Herring <[email protected]>
arch/arm/configs/socfpga_defconfig
Quoted 4 lines
arch/arm/configs/socfpga_defconfig +0 -0
index 0ac1293..349ac22 100644
I'm still not clear why multi_v7 config does not work for you?

Quoted 8 lines

Quoted 2 lines
multi_v7 works fine for me. But I need +#CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
Why? I don't think those should break other versions of A9. If they do, we need to fix that. In general, we should turn on all errata for multi-platform builds, so we need to make sure they are done in a compatible way and can be bypassed if they have performance impacts. That may ultimately require some runtime patching though.

Our virtual platform is having a problem with CONFIG_ARM_ERRATA_751472. It could be that our virtual platform is not simulating this correctly.

Dinh

Quoted 50 lines

Rob
Quoted 46 lines
in order for SMP to work correctly on our platform.
Quoted 13 lines
Quoted 13 lines
arch/arm/configs/socfpga_defconfig +1 -2
@@ -1,5 +1,5 @@
 CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -16,10 +16,13 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_MACH_SOCFPGA_CYCLONE5=y
Quoted 8 lines
arch/arm/configs/socfpga_defconfig CONFIG_MODULE_UNLOAD=y · line 23
Quoted 6 lines
arch/arm/configs/socfpga_defconfig +3 -1
-CONFIG_ARM_THUMBEE=y
+# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_ARM_ARCH_TIMER=y
You're an A9, right? You don't have arch timers.
Yes, will remove in v3.
Quoted 4 lines
arch/arm/configs/socfpga_defconfig CONFIG_MODULE_UNLOAD=y · line 24
Quoted 2 lines
arch/arm/configs/socfpga_defconfig +1 -0
+CONFIG_HIGHMEM=y
How much RAM? You need more than 2GB with CONFIG_VMSPLIT_2G.
1G for RAM only, so will remove in v3.
Thanks,
Dinh
Quoted 7 lines
Quoted 5 lines
arch/arm/configs/socfpga_defconfig +1 -0
+CONFIG_HIGHPTE=y
 CONFIG_VMSPLIT_2G=y
 CONFIG_NR_CPUS=2
 CONFIG_AEABI=y

Pavel Machek

2012-10-27 11:43 UTC #8 lore raw

ERRATA_751472 was Re: [PATCHv2] arm:socfpga: Enable SMP for socfpga

Hi!

Quoted 9 lines

Quoted 8 lines
Quoted 2 lines
multi_v7 works fine for me. But I need +#CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
Why? I don't think those should break other versions of A9. If they do, we need to fix that. In general, we should turn on all errata for multi-platform builds, so we need to make sure they are done in a compatible way and can be bypassed if they have performance impacts. That may ultimately require some runtime patching though.

Quoted 3 lines

Our virtual platform is having a problem with CONFIG_ARM_ERRATA_751472. It could be that our virtual platform is not simulating this correctly.

proc-v7.S:

#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
        ALT_SMP(cmp r6, #0x30)                  @ present prior to r3p0
        ALT_UP_B(1f)
	mrclt   p15, 0, r10, c15, c0, 1         @ read diagnostic register
        orrlt   r10, r10, #1 << 11              @ set bit #11
        mcrlt   p15, 0, r10, c15, c0, 1         @ write diagnostic register

1:
#endif

Is ALT_SMP()/ALT_UP available this early during boot?

If it is, do we need the && defined(CONFIG_SMP)? ALT_UP_... should do the right thing. (Okk, I guess the ifdef saves cca 16 bytes in the image...)

Pavel

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Arnd Bergmann

Applied

2012-10-25 13:56 UTC #9 lore raw

PATCH v2 1/1 arm:socfpga: Enable SMP for socfpga

In reply to dinguyen at altera.com

Quoted 6 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>
Enable SMP for the SOCFPGA platform.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>

Applied to new next/smp branch in arm-soc, but please reply to the comment from Thomas, and send a follow-on patch if necessary.

Thanks,

Arnd

Dinh Nguyen

author

2012-10-25 16:29 UTC #10 lore raw

PATCH v2 1/1 arm:socfpga: Enable SMP for socfpga

Hi Arnd,

Quoted 10 lines · Arnd Bergmann

Quoted 6 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
Enable SMP for the SOCFPGA platform.
Signed-off-by Pavel Machek <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>
Applied to new next/smp branch in arm-soc, but please reply to the comment from Thomas, and send a follow-on patch if necessary.

Thanks, I will be sending a v3 in short while.

Dinh

Quoted 5 lines

Thanks,
Arnd