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clk: ux500: Add clock lookups for u8500

PATCH New Ulf Hansson 4 participants 11 messages Oct 22, 2012 – Nov 12, 2012

Subsystems (2)
Common clk Ux500 clock drivers
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Ulf Hansson

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#0 lore raw

cover clk: ux500: Add clock lookups for u8500

From: Ulf Hansson <[email protected]>

Step by step, clock lookups for u8500 are being added in this set of patches.

These patches will require additional patches for sound/soc/ux500/ driver as well as drivers/i2c/busses/i2c-nomadik driver to prevent the boot for ux500 from break. Those patches are being merged through separate trees.

Ulf Hansson (5):
clk: ux500: Register i2c clock lookups for u8500
clk: ux500: Register ssp clock lookups for u8500
clk: ux500: Register msp clock lookups for u8500
clk: ux500: Update rtc clock lookup for u8500
clk: ux500: Register slimbus clock lookups for u8500

 drivers/clk/ux500/u8500_clk.c |   50 +++++++++++++++++++++++++++++++++++++----
 1 file changed, 46 insertions(+), 4 deletions(-)
Signature · 1 line
1.7.10
author
#1 lore raw

PATCH 1/5 clk: ux500: Register i2c clock lookups for u8500

From: Ulf Hansson <[email protected]>

Cc Ben Dooks <[email protected]>
Cc Wolfram Sang <[email protected]>
Cc Linus Walleij <[email protected]>
Signed-off-by Ulf Hansson <[email protected]>
---
 drivers/clk/ux500/u8500_clk.c |   19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)
drivers/clk/ux500/u8500_clk.c +18 -1
index ca4a25e..7ad01aa 100644
@@ -228,6 +228,8 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE,
 				BIT(2), 0);
+	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
+
 	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE,
 				BIT(3), 0);
 	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE,

@@ -239,6 +241,7 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE,
 				BIT(6), 0);
+	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
 
 	clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE,
 				BIT(7), 0);

@@ -255,11 +258,14 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE,
 				BIT(10), 0);
+	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
+
 	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE,
 				BIT(11), 0);
 
 	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE,
 				BIT(0), 0);
+	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
 
 	clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE,
 				BIT(1), 0);

@@ -284,7 +290,6 @@ void u8500_clk_init(void)
 				BIT(6), 0);
 	clk_register_clkdev(clk, "apb_pclk", "sdi1");
 
-
 	clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE,
 				BIT(7), 0);
 	clk_register_clkdev(clk, "apb_pclk", "sdi3");

@@ -318,8 +323,10 @@ void u8500_clk_init(void)
 				BIT(1), 0);
 	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE,
 				BIT(2), 0);
+
 	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE,
 				BIT(3), 0);
+	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
 
 	clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE,
 				BIT(4), 0);

@@ -401,6 +408,8 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
 			U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "nmk-i2c.1");
+
 	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
 			U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
 	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",

@@ -412,17 +421,23 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
 			U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "nmk-i2c.2");
+
 	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
 			U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
 	/* FIXME: Redefinition of BIT(3). */
+
 	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
 			U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "nmk-i2c.4");
+
 	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
 			U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE);
 
 	/* Periph2 */
 	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
 			U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "nmk-i2c.3");
 
 	clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
 			U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE);

@@ -452,8 +467,10 @@ void u8500_clk_init(void)
 			U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE);
 	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
 			U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE);
+
 	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
 			U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "nmk-i2c.0");
 
 	clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
 			U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE);
Signature · 1 line
1.7.10
author
#2 lore raw

PATCH 2/5 clk: ux500: Register ssp clock lookups for u8500

In reply to Ulf Hansson

From: Ulf Hansson <[email protected]>

Signed-off-by Ulf Hansson <[email protected]>
---
 drivers/clk/ux500/u8500_clk.c |    6 ++++++
 1 file changed, 6 insertions(+)
drivers/clk/ux500/u8500_clk.c +6 -0
index 7ad01aa..36ef41d 100644
@@ -321,8 +321,11 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,
 				BIT(1), 0);
+	clk_register_clkdev(clk, "apb_pclk", "ssp0");
+
 	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE,
 				BIT(2), 0);
+	clk_register_clkdev(clk, "apb_pclk", "ssp1");
 
 	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE,
 				BIT(3), 0);

@@ -465,8 +468,11 @@ void u8500_clk_init(void)
 	/* Periph3 */
 	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
 			U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "ssp0");
+
 	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
 			U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "ssp1");
 
 	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
 			U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE);
Signature · 1 line
1.7.10
author
#3 lore raw

PATCH 3/5 clk: ux500: Register msp clock lookups for u8500

In reply to Ulf Hansson

From: Ulf Hansson <[email protected]>

Cc Mark Brown <[email protected]>
Signed-off-by Ulf Hansson <[email protected]>
---
 drivers/clk/ux500/u8500_clk.c |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
drivers/clk/ux500/u8500_clk.c +18 -0
index 36ef41d..be843ba 100644
@@ -232,8 +232,13 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE,
 				BIT(3), 0);
+	clk_register_clkdev(clk, "apb_pclk", "msp0");
+	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0");
+
 	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE,
 				BIT(4), 0);
+	clk_register_clkdev(clk, "apb_pclk", "msp1");
+	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1");
 
 	clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE,
 				BIT(5), 0);

@@ -262,6 +267,8 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE,
 				BIT(11), 0);
+	clk_register_clkdev(clk, "apb_pclk", "msp3");
+	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3");
 
 	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE,
 				BIT(0), 0);

@@ -285,6 +292,8 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE,
 				BIT(5), 0);
+	clk_register_clkdev(clk, "apb_pclk", "msp2");
+	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2");
 
 	clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE,
 				BIT(6), 0);

@@ -415,8 +424,13 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
 			U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "msp0");
+	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0");
+
 	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
 			U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "msp1");
+	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1");
 
 	clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
 			U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE);

@@ -436,6 +450,8 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
 			U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "msp3");
+	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3");
 
 	/* Periph2 */
 	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",

@@ -448,6 +464,8 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
 			U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "msp2");
+	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2");
 
 	clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
 			U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE);
Signature · 1 line
1.7.10
author
#4 lore raw

PATCH 4/5 clk: ux500: Update rtc clock lookup for u8500

In reply to Ulf Hansson

From: Ulf Hansson <[email protected]>

Signed-off-by Ulf Hansson <[email protected]>
---
 drivers/clk/ux500/u8500_clk.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/ux500/u8500_clk.c +1 -1
index be843ba..0aae929 100644
@@ -40,7 +40,7 @@ void u8500_clk_init(void)
 				CLK_IS_ROOT|CLK_IGNORE_UNUSED,
 				32768);
 	clk_register_clkdev(clk, "clk32k", NULL);
-	clk_register_clkdev(clk, NULL, "rtc-pl031");
+	clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");
 
 	/* PRCMU clocks */
 	fw_version = prcmu_get_fw_version();
Signature · 1 line
1.7.10
author
#5 lore raw

PATCH 5/5 clk: ux500: Register slimbus clock lookups for u8500

In reply to Ulf Hansson

From: Ulf Hansson <[email protected]>

At the same time the prcc bit for the kclk is corrected to bit 8 instead of 3.

Signed-off-by Ulf Hansson <[email protected]>
---
 drivers/clk/ux500/u8500_clk.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
drivers/clk/ux500/u8500_clk.c +3 -2
index 0aae929..e2c17d1 100644
@@ -254,6 +254,7 @@ void u8500_clk_init(void)
 
 	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,
 				BIT(8), 0);
+	clk_register_clkdev(clk, "apb_pclk", "slimbus0");
 
 	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,
 				BIT(9), 0);

@@ -441,8 +442,8 @@ void u8500_clk_init(void)
 	clk_register_clkdev(clk, NULL, "nmk-i2c.2");
 
 	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
-			U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
-	/* FIXME: Redefinition of BIT(3). */
+			U8500_CLKRST1_BASE, BIT(8), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "slimbus0");
 
 	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
 			U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);
Signature · 1 line
1.7.10
#6 lore raw

cover clk: ux500: Add clock lookups for u8500

In reply to Ulf Hansson
Quoted 9 lines · Ulf Hansson

From: Ulf Hansson <[email protected]>

Step by step, clock lookups for u8500 are being added in this set of patches.

These patches will require additional patches for sound/soc/ux500/ driver as well as drivers/i2c/busses/i2c-nomadik driver to prevent the boot for ux500 from break. Those patches are being merged through separate trees.

All of these look good to me.

Acked-by Linus Walleij <[email protected]> for all.

Yours,
Linus Walleij

#7 lore raw

cover clk: ux500: Add clock lookups for u8500

In reply to Ulf Hansson
Quoted 10 lines · Ulf Hansson

From: Ulf Hansson <[email protected]>

Step by step, clock lookups for u8500 are being added in this set of patches.

These patches will require additional patches for sound/soc/ux500/ driver as well as drivers/i2c/busses/i2c-nomadik driver to prevent the boot for ux500 from break. Those patches are being merged through separate trees.

Quoted 6 lines

Ulf Hansson (5):
clk: ux500: Register i2c clock lookups for u8500
clk: ux500: Register ssp clock lookups for u8500
clk: ux500: Register msp clock lookups for u8500
clk: ux500: Update rtc clock lookup for u8500
clk: ux500: Register slimbus clock lookups for u8500

Acked-by Lee Jones <[email protected]>

Can I also mention that these need to go into the -rcs at the earliest opportunity please, as it is preventing ~50% of the devices from functioning on all of the ST-Ericsson development boards.

This is a massive blocker for us!

Signature · 4 lines
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
#8 lore raw

cover clk: ux500: Add clock lookups for u8500

Quoting Lee Jones (2012-10-25 00:51:38)

Quoted 19 lines · Ulf Hansson
Quoted 11 lines

From: Ulf Hansson <[email protected]>

Step by step, clock lookups for u8500 are being added in this set of patches.

These patches will require additional patches for sound/soc/ux500/ driver as well as drivers/i2c/busses/i2c-nomadik driver to prevent the boot for ux500 from break. Those patches are being merged through separate trees.

Quoted 6 lines

Ulf Hansson (5):
clk: ux500: Register i2c clock lookups for u8500
clk: ux500: Register ssp clock lookups for u8500
clk: ux500: Register msp clock lookups for u8500
clk: ux500: Update rtc clock lookup for u8500
clk: ux500: Register slimbus clock lookups for u8500

Quoted 9 lines
Acked-by Lee Jones <[email protected]>

Can I also mention that these need to go into the -rcs at the earliest opportunity please, as it is preventing ~50% of the devices from functioning on all of the ST-Ericsson development boards.

This is a massive blocker for us!

I've taken these patches into clk-next. Do you need them in as a late fix in the 3.7 cycle or is your urgent need only for 3.8 development?

Regards,
Mike

Quoted 5 lines
Signature · 4 lines
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
#9 lore raw

cover clk: ux500: Add clock lookups for u8500

Quoted 27 lines · Mike Turquette

Quoting Lee Jones (2012-10-25 00:51:38)

Quoted 26 lines · Ulf Hansson
Quoted 11 lines

From: Ulf Hansson <[email protected]>

Step by step, clock lookups for u8500 are being added in this set of patches.

These patches will require additional patches for sound/soc/ux500/ driver as well as drivers/i2c/busses/i2c-nomadik driver to prevent the boot for ux500 from break. Those patches are being merged through separate trees.

Quoted 6 lines

Ulf Hansson (5):
clk: ux500: Register i2c clock lookups for u8500
clk: ux500: Register ssp clock lookups for u8500
clk: ux500: Register msp clock lookups for u8500
clk: ux500: Update rtc clock lookup for u8500
clk: ux500: Register slimbus clock lookups for u8500

Acked-by Lee Jones <[email protected]>

Can I also mention that these need to go into the -rcs at the earliest opportunity please, as it is preventing ~50% of the devices from functioning on all of the ST-Ericsson development boards.

Quoted 5 lines
Quoted 2 lines

This is a massive blocker for us!

I've taken these patches into clk-next. Do you need them in as a late fix in the 3.7 cycle or is your urgent need only for 3.8 development?

It is regressing the above drivers (i2c, ssp, etc) so they need to go into v3.7-rc:s...

Yours,
Linus Walleij

#10 lore raw

cover clk: ux500: Add clock lookups for u8500

Quoting Linus Walleij (2012-11-11 10:42:59)

Quoted 28 lines · Mike Turquette
Quoted 27 lines

Quoting Lee Jones (2012-10-25 00:51:38)

Quoted 26 lines · Ulf Hansson
Quoted 11 lines

From: Ulf Hansson <[email protected]>

Step by step, clock lookups for u8500 are being added in this set of patches.

These patches will require additional patches for sound/soc/ux500/ driver as well as drivers/i2c/busses/i2c-nomadik driver to prevent the boot for ux500 from break. Those patches are being merged through separate trees.

Quoted 6 lines

Ulf Hansson (5):
clk: ux500: Register i2c clock lookups for u8500
clk: ux500: Register ssp clock lookups for u8500
clk: ux500: Register msp clock lookups for u8500
clk: ux500: Update rtc clock lookup for u8500
clk: ux500: Register slimbus clock lookups for u8500

Acked-by Lee Jones <[email protected]>

Can I also mention that these need to go into the -rcs at the earliest opportunity please, as it is preventing ~50% of the devices from functioning on all of the ST-Ericsson development boards.

Quoted 9 lines
Quoted 5 lines
Quoted 2 lines

This is a massive blocker for us!

I've taken these patches into clk-next. Do you need them in as a late fix in the 3.7 cycle or is your urgent need only for 3.8 development?

It is regressing the above drivers (i2c, ssp, etc) so they need to go into v3.7-rc:s...

Pull request sent for the fixes. I'll remove these from clk-next once they are merged into 3.7-rc6.

Regards,
Mike

Quoted 2 lines

Yours,
Linus Walleij