Enable mvebu pinctrl/gpio for Dove and Kirkwood
Subsystems (6)
Andrew Lunn
maintainercover Enable mvebu pinctrl/gpio for Dove and Kirkwood
This is the first step in converting Dove and Kirkwood boards to use pinctrl. Allow the MVEBU pinctrl driver and GPIO driver to be used by these two SoC families.
Andrew Lunn (2):
ARM: Kirkwood: Allow use of pinctrl
ARM: Kirkwood: Allow use of MVEBU GPIO driver.
Sebastian Hesselbarth (3):
pinctrl: dove: fix iomem and pdma clock
ARM: Dove: Make use of pinctrl driver
ARM: Dove: Make use of MVEBU GPIO driver
arch/arm/Kconfig | 6 ++++++ arch/arm/boot/dts/dove.dtsi | 19 ++++++++++++++++--- arch/arm/boot/dts/kirkwood.dtsi | 11 +++++++++-- arch/arm/plat-orion/irq.c | 5 +---- drivers/gpio/Kconfig | 2 +- drivers/pinctrl/Kconfig | 2 +- drivers/pinctrl/pinctrl-dove.c | 20 +++++++++++++------- 7 files changed, 47 insertions(+), 18 deletions(-)
Signature · 1 line
1.7.10.4
Andrew Lunn
maintainerPATCH 1/5 ARM: Kirkwood: Allow use of pinctrl
We now have a pinctrl driver for arch-mvebu. It supports kirkwood out of the box. Allow ARCH_KIRKWOOD to select it, and make ARCH_KIRKWOOD select it. This then allows the convertion of board-*.c files away from MPP to pinctrl in DT, before they get moved over into mach-mvebu.
--- arch/arm/Kconfig | 2 ++ drivers/pinctrl/Kconfig | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-)
arch/arm/Kconfig +2 -0
@@ -548,6 +548,8 @@ config ARCH_KIRKWOOD select GENERIC_CLOCKEVENTS select PCI select PLAT_ORION_LEGACY + select PINCTRL + select PINCTRL_KIRKWOOD help Support for the following Marvell Kirkwood series SoCs: 88F6180, 88F6192 and 88F6281.
drivers/pinctrl/Kconfig +1 -1
@@ -188,7 +188,7 @@ config PINCTRL_EXYNOS4 config PINCTRL_MVEBU bool - depends on ARCH_MVEBU + depends on ARCH_MVEBU || ARCH_KIRKWOOD select PINMUX select PINCONF
Signature · 1 line
1.7.10.4
PATCH 1/5 ARM: Kirkwood: Allow use of pinctrl
Quoted 16 lines · Andrew Lunn
We now have a pinctrl driver for arch-mvebu. It supports kirkwood out of the box. Allow
ARCH_KIRKWOODto select it, and makeARCH_KIRKWOODselect it. This then allows the convertion of board-*.c files away from MPP to pinctrl in DT, before they get moved over into mach-mvebu.Signed-off-by Andrew Lunn <[email protected]>--- arch/arm/Kconfig | 2 ++ drivers/pinctrl/Kconfig | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-)arch/arm/Kconfig +0
-0
arch/arm/Kconfig config ARCH_KIRKWOOD · line 552
Quoted 5 lines
arch/arm/Kconfig +2
-0@@ -548,6 +548,8 @@ config ARCH_KIRKWOOD select GENERIC_CLOCKEVENTS select PCI select PLAT_ORION_LEGACY + select PINCTRL + select PINCTRL_KIRKWOOD
Russell just spent the end of the release cycle sorting all of these in alphanumeric order, so keep to that. (Move above PLAT*)
Once they look OK I'd like to get ACKs from one of the ARM SoC maintainers so I can merge this set through the pinctrl tree.
Yours,
Linus Walleij
PATCH 1/5 ARM: Kirkwood: Allow use of pinctrl
In reply to Andrew LunnDear Andrew Lunn,
drivers/pinctrl/Kconfig config PINCTRL_EXYNOS4 · line 193
Quoted 11 lines · Andrew Lunn
index 7bf914d..5682c96 100644
drivers/pinctrl/Kconfig +1
-1@@ -188,7 +188,7 @@ config PINCTRL_EXYNOS4 config PINCTRL_MVEBU bool - depends on ARCH_MVEBU + depends on ARCH_MVEBU || ARCH_KIRKWOOD select PINMUX select PINCONF
Linus Walleij has accepted a patch I have sent yesterday evening that makes PINCTRL_MVEBU available for all PLAT_ORION platforms, so this chunk is no longer needed.
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Andrew Lunn
maintainerPATCH 2/5 ARM: Kirkwood: Allow use of MVEBU GPIO driver.
In reply to Andrew LunnThis GPIO driver is generic to all Marvel Orion/XP/370 SoCs. Allow Kirkwood to enable and use it. Fix the kirkwood DT to pass the expected properties and remove the old gpio probing code.
--- arch/arm/Kconfig | 1 + arch/arm/boot/dts/kirkwood.dtsi | 11 +++++++++-- arch/arm/plat-orion/irq.c | 5 +---- drivers/gpio/Kconfig | 2 +- 4 files changed, 12 insertions(+), 7 deletions(-)
arch/arm/Kconfig +1 -0
@@ -544,6 +544,7 @@ config ARCH_DOVE config ARCH_KIRKWOOD bool "Marvell Kirkwood" select ARCH_REQUIRE_GPIOLIB + select ARCH_WANT_OPTIONAL_GPIOLIB select CPU_FEROCEON select GENERIC_CLOCKEVENTS select PCI
arch/arm/boot/dts/kirkwood.dtsi +9 -2
@@ -4,6 +4,11 @@ compatible = "marvell,kirkwood"; interrupt-parent = <&intc>; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + intc: interrupt-controller { compatible = "marvell,orion-intc", "marvell,intc"; interrupt-controller;
@@ -24,7 +29,8 @@ #gpio-cells = <2>; gpio-controller; reg = <0x10100 0x40>; - ngpio = <32>; + ngpios = <32>; + interrupt-controller; interrupts = <35>, <36>, <37>, <38>; };
@@ -33,7 +39,8 @@ #gpio-cells = <2>; gpio-controller; reg = <0x10140 0x40>; - ngpio = <18>; + ngpios = <18>; + interrupt-controller; interrupts = <39>, <40>, <41>; };
arch/arm/plat-orion/irq.c +1 -4
@@ -41,7 +41,7 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)static int __init orion_add_irq_domain (struct device_node *np,struct device_node *interrupt_parent) { -int i =0 , irq_gpio; +int i =0 ;void __iomem *base; do {
@@ -55,9 +55,6 @@ static int __init orion_add_irq_domain(struct device_node *np,irq_domain_add_legacy (np, i *32 ,0 ,0 , &irq_domain_simple_ops,NULL ); - irq_gpio = i *32 ; -orion_gpio_of_init (irq_gpio); -return 0 ; }
drivers/gpio/Kconfig +1 -1
@@ -152,7 +152,7 @@ config GPIO_MSM_V2 config GPIO_MVEBU def_bool y - depends on ARCH_MVEBU + depends on ARCH_MVEBU || ARCH_KIRKWOOD select GPIO_GENERIC select GENERIC_IRQ_CHIP
Signature · 1 line
1.7.10.4
PATCH 2/5 ARM: Kirkwood: Allow use of MVEBU GPIO driver.
Dear Andrew Lunn,
drivers/gpio/Kconfig config GPIO_MSM_V2 · line 157
Quoted 6 lines · Andrew Lunn
config
GPIO_MVEBUdrivers/gpio/Kconfig +1
-1def_bool y - depends on ARCH_MVEBU + depends on ARCH_MVEBU || ARCH_KIRKWOOD select GPIO_GENERIC select GENERIC_IRQ_CHIP
Should we turn the depends on ARCH_MVEBU into a depends on PLAT_ORION, like I did for the pinctrl driver (patch accepted by Linus Walleij yesterday) ? I think the dependency on ARCH_MVEBU was making too much of a shortcut, by assuming that we would very quickly move everybody into mach-mvebu. As we rather decided to move gradually mach-{kirkwood,dove,orion5x,mv78xx0} to those infrastructure while keeping them in their respective directories, I think a dependency on PLAT_ORION is more appropriate here.
Best regards,
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Andrew Lunn
maintainerPATCH 3/5 pinctrl: dove: fix iomem and pdma clock
In reply to Andrew LunnFrom: Sebastian Hesselbarth <[email protected]>
Since 3.7 readl/writel require register addresses to be const void* instead of unsigned int. The register addresses are converted using IOMEM() and offsets are added instead of OR'ed.
Also a workaround for the pdma clock is added, that is required as there is still no DT clock provider available on Dove.
--- drivers/pinctrl/pinctrl-dove.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-)
drivers/pinctrl/pinctrl-dove.c +13 -7
@@ -22,22 +22,22 @@#include "pinctrl-mvebu.h" -#define DOVE_SB_REGS_VIRT_BASE 0xfde00000 -#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) +#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) +#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)#define DOVE_AU0_AC97_SEL BIT(16) -#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C) +#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)#define DOVE_TWSI_ENABLE_OPTION1 BIT(7) -#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030) +#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)#define DOVE_TWSI_ENABLE_OPTION2 BIT(20)#define DOVE_TWSI_ENABLE_OPTION3 BIT(21)#define DOVE_TWSI_OPTION3_GPIO BIT(22) -#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034) +#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)#define DOVE_SSP_ON_AU1 BIT(0) -#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) +#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)#define DOVE_AU1_SPDIFO_GPIO_EN BIT(1)#define DOVE_NAND_GPIO_EN BIT(0) -#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) +#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)#define DOVE_SPI_GPIO_SEL BIT(5)#define DOVE_UART1_GPIO_SEL BIT(4)
@@ -587,6 +587,12 @@ static int __devinit dove_pinctrl_probe(struct platform_device *pdev)* grab clk to make sure it is ticking. */ clk =devm_clk_get (&pdev->dev,NULL ); + +/* Currently there is no DT clock provider for pdma clock, +this fallback ensures pdma clock is ticking */ +if (IS_ERR (clk)) + clk =clk_get_sys ("dove-pdma" ,NULL ); +if (!IS_ERR (clk))clk_prepare_enable (clk);
Signature · 1 line
1.7.10.4
PATCH 3/5 pinctrl: dove: fix iomem and pdma clock
Quoted 5 lines · Andrew Lunn
Since 3.7 readl/writel require register addresses to be const void* instead of unsigned int. The register addresses are converted using
IOMEM()and offsets are added instead of OR'ed.
Also a workaround for the pdma clock is added, that is required as there is still no DT clock provider available on Dove.
So essentially two unrelated patches squashed into one, and I would apply the first one right off but now the clock change makes me hesitate.
drivers/pinctrl/pinctrl-dove.c static int __devinit dove_pinctrl_probe(struct platform_device *pdev) · line 592
Quoted 4 lines
clk = devm_clk_get(&pdev->dev, NULL);drivers/pinctrl/pinctrl-dove.c +3
-0+ +/* Currently there is no DT clock provider for pdma clock, +this fallback ensures pdma clock is ticking */
/*
* I prefer comment style like so because it's easier to read.
* Maybe it's a bit pedantic but bear with me.
*/
drivers/pinctrl/pinctrl-dove.c static int __devinit dove_pinctrl_probe(struct platform_device *pdev) · line 595
Quoted 3 lines
drivers/pinctrl/pinctrl-dove.c +3
-0+if (IS_ERR (clk)) + clk =clk_get_sys ("dove-pdma" ,NULL ); +
This is a horrible hack. But if the Marvell people agree about it I will live with it.
Yours,
Linus Walleij
Sebastian Hesselbarth
maintainerPATCH 3/5 pinctrl: dove: fix iomem and pdma clock
Quoted 22 lines · Linus Walleij
Quoted 5 lines · Andrew Lunn
Since 3.7 readl/writel require register addresses to be const void* instead of unsigned int. The register addresses are converted using
IOMEM()and offsets are added instead of OR'ed.
Also a workaround for the pdma clock is added, that is required as there is still no DT clock provider available on Dove.So essentially two unrelated patches squashed into one, and I would apply the first one right off but now the clock change makes me hesitate.
drivers/pinctrl/pinctrl-dove.c static int __devinit dove_pinctrl_probe(struct platform_device *pdev) · line 592
Quoted 4 lines
clk = devm_clk_get(&pdev->dev, NULL);drivers/pinctrl/pinctrl-dove.c +3
-0+ +/* Currently there is no DT clock provider for pdma clock, +this fallback ensures pdma clock is ticking */ /*
* I prefer comment style like so because it's easier to read.
* Maybe it's a bit pedantic but bear with me.
*/
Quoted 6 lines
drivers/pinctrl/pinctrl-dove.c static int __devinit dove_pinctrl_probe(struct platform_device *pdev) · line 595
Quoted 3 lines
drivers/pinctrl/pinctrl-dove.c +3
-0+if (IS_ERR (clk)) + clk =clk_get_sys ("dove-pdma" ,NULL ); +This is a horrible hack. But if the Marvell people agree about it I will live with it.
Unfortunately, it is. This is an chicken-egg-problem here, no DT clk-provider, no clocks properties..
While writing pinctrl-dove I was planing to enable it after the clock provider but with Andrew pushing forward - for a good reason - there comes the trouble ;)
I don't like the hack either but the clk-gate is there and if I don't enable it pinctrl-dove will hang the SoC.
I have a clk-dove DT clk-provider in my pocket somewhere but didn't find the time to prepare it for posting..
Sebastian
PATCH 3/5 pinctrl: dove: fix iomem and pdma clock
Quoted 37 lines · Sebastian Hesselbarth
Quoted 22 lines · Linus Walleij
Quoted 5 lines · Andrew Lunn
Since 3.7 readl/writel require register addresses to be const void* instead of unsigned int. The register addresses are converted using
IOMEM()and offsets are added instead of OR'ed.
Also a workaround for the pdma clock is added, that is required as there is still no DT clock provider available on Dove.So essentially two unrelated patches squashed into one, and I would apply the first one right off but now the clock change makes me hesitate.
drivers/pinctrl/pinctrl-dove.c static int __devinit dove_pinctrl_probe(struct platform_device *pdev) · line 592
Quoted 4 lines
clk = devm_clk_get(&pdev->dev, NULL);drivers/pinctrl/pinctrl-dove.c +3
-0+ +/* Currently there is no DT clock provider for pdma clock, +this fallback ensures pdma clock is ticking */ /*
* I prefer comment style like so because it's easier to read.
* Maybe it's a bit pedantic but bear with me.
*/Quoted 6 lines
drivers/pinctrl/pinctrl-dove.c static int __devinit dove_pinctrl_probe(struct platform_device *pdev) · line 595
Quoted 3 lines
drivers/pinctrl/pinctrl-dove.c +3
-0+if (IS_ERR (clk)) + clk =clk_get_sys ("dove-pdma" ,NULL ); +This is a horrible hack. But if the Marvell people agree about it I will live with it.
Unfortunately, it is. This is an chicken-egg-problem here, no DT clk-provider, no clocks properties..
While writing pinctrl-dove I was planing to enable it after the clock provider but with Andrew pushing forward - for a good reason - there comes the trouble ;)
Quoted 5 lines
I don't like the hack either but the clk-gate is there and if I don't enable it pinctrl-dove will hang the SoC.
I have a clk-dove DT clk-provider in my pocket somewhere but didn't find the time to prepare it for posting..
Then let's split out the dove-pinctrl patches until you have that series ready.
thx,
Jason.
Andrew Lunn
maintainerPATCH 4/5 ARM: Dove: Make use of pinctrl driver
In reply to Andrew LunnFrom: Sebastian Hesselbarth <[email protected]>
Allow ARCH_DOVE to select pinctrl-mvebu with support for Dove SoC. With the now enabled pinctrl driver also add the corresponding DT node to Dove DT.
--- arch/arm/Kconfig | 2 ++ arch/arm/boot/dts/dove.dtsi | 5 +++++ drivers/pinctrl/Kconfig | 2 +- 3 files changed, 8 insertions(+), 1 deletion(-)
arch/arm/Kconfig +2 -0
@@ -537,6 +537,8 @@ config ARCH_DOVE select GENERIC_CLOCKEVENTS select MIGHT_HAVE_PCI select PLAT_ORION_LEGACY + select PINCTRL + select PINCTRL_DOVE select USB_ARCH_HAS_EHCI help Support for the Marvell Dove SoC 88AP510
arch/arm/boot/dts/dove.dtsi +5 -0
@@ -67,6 +67,11 @@ status = "disabled"; }; + pinctrl: pinctrl at d0200 { + compatible = "marvell,dove-pinctrl"; + reg = <0xd0200 0x20>; + }; + gpio0: gpio at d0400 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>;
drivers/pinctrl/Kconfig +1 -1
@@ -188,7 +188,7 @@ config PINCTRL_EXYNOS4 config PINCTRL_MVEBU bool - depends on ARCH_MVEBU || ARCH_KIRKWOOD + depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_DOVE select PINMUX select PINCONF
Signature · 1 line
1.7.10.4
PATCH 4/5 ARM: Dove: Make use of pinctrl driver
arch/arm/Kconfig config ARCH_DOVE · line 541
Quoted 3 lines · Andrew Lunn
select
PLAT_ORION_LEGACYarch/arm/Kconfig +2
-0+ select PINCTRL + select PINCTRL_DOVE
Sort alphanumeric.
Yours,
Linus Walleij
Andrew Lunn
maintainerPATCH 5/5 ARM: Dove: Make use of MVEBU GPIO driver
In reply to Andrew LunnFrom: Sebastian Hesselbarth <[email protected]>
The MVEBU driver is generic to all Marvell Orion/XP/370 SoCs. Allow Dove DT to enable and use it. Also fix dove DT to pass the expected properties and add gpio aliases.
--- arch/arm/Kconfig | 1 + arch/arm/boot/dts/dove.dtsi | 14 +++++++++++--- drivers/gpio/Kconfig | 2 +- 3 files changed, 13 insertions(+), 4 deletions(-)
arch/arm/Kconfig +1 -0
@@ -533,6 +533,7 @@ config ARCH_IXP4XX config ARCH_DOVE bool "Marvell Dove" select ARCH_REQUIRE_GPIOLIB + select ARCH_WANT_OPTIONAL_GPIOLIB select CPU_V7 select GENERIC_CLOCKEVENTS select MIGHT_HAVE_PCI
arch/arm/boot/dts/dove.dtsi +11 -3
@@ -4,6 +4,12 @@ compatible = "marvell,dove"; model = "Marvell Armada 88AP510 SoC"; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + soc at f1000000 { compatible = "simple-bus"; #address-cells = <1>;
@@ -77,7 +83,8 @@ #gpio-cells = <2>; gpio-controller; reg = <0xd0400 0x20>; - ngpio = <32>; + ngpios = <32>; + interrupt-controller; interrupts = <12>, <13>, <14>, <60>; };
@@ -86,7 +93,8 @@ #gpio-cells = <2>; gpio-controller; reg = <0xd0420 0x20>; - ngpio = <32>; + ngpios = <32>; + interrupt-controller; interrupts = <61>; };
@@ -95,7 +103,7 @@ #gpio-cells = <2>; gpio-controller; reg = <0xe8400 0x0c>; - ngpio = <8>; + ngpios = <8>; }; spi0: spi at 10600 {
drivers/gpio/Kconfig +1 -1
@@ -152,7 +152,7 @@ config GPIO_MSM_V2 config GPIO_MVEBU def_bool y - depends on ARCH_MVEBU || ARCH_KIRKWOOD + depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_DOVE select GPIO_GENERIC select GENERIC_IRQ_CHIP
Signature · 1 line
1.7.10.4