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Initial Calxeda ECX-2000 support

PATCH New Rob Herring 2 participants 8 messages Oct 26, 2012

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#0 lore raw

cover Initial Calxeda ECX-2000 support

From: Rob Herring <[email protected]>

This series adds initial support for Calxeda A15 based ECX-2000 SOC. Most of the changes are shuffling of dts files to share common parts between highbank (ECX-1000) and ECX-2000 and abstracting out or removing SCU accesses as the A15 has no SCU registers.

Although the highbank name really refers to 1st gen SOC, the highbank name in the kernel is now referring to both SOCs.

Rob

Rob Herring (6):
ARM: highbank: disable unused sdhci and gpio in dts
ARM: highbank: enable coherent DMA for xgmac in dts
ARM: dts: Add Calxeda ECX-2000 support
ARM: smp_twd: don't warn on no DT node
ARM: highbank: abstract out SCU usage
ARM: highbank: Add initial ECX-2000 support

 Documentation/devicetree/bindings/arm/calxeda.txt |   13 +-
 arch/arm/boot/dts/Makefile                        |    3 +-
 arch/arm/boot/dts/ecx-2000.dts                    |  104 +++++++++
 arch/arm/boot/dts/ecx-common.dtsi                 |  237 +++++++++++++++++++++
 arch/arm/boot/dts/highbank.dts                    |  212 +-----------------
 arch/arm/kernel/smp_twd.c                         |    6 +-
 arch/arm/mach-highbank/Kconfig                    |    2 +-
 arch/arm/mach-highbank/highbank.c                 |   27 +--
 arch/arm/mach-highbank/hotplug.c                  |    6 +-
 arch/arm/mach-highbank/platsmp.c                  |    7 +-
 arch/arm/mach-highbank/pm.c                       |    3 -
 arch/arm/mach-highbank/sysregs.h                  |   19 ++
 arch/arm/mach-highbank/system.c                   |    2 -
 13 files changed, 394 insertions(+), 247 deletions(-)
 create mode 100644 arch/arm/boot/dts/ecx-2000.dts
 create mode 100644 arch/arm/boot/dts/ecx-common.dtsi
Signature · 1 line
1.7.10.4
#1 lore raw

PATCH 1/6 ARM: highbank: disable unused sdhci and gpio in dts

From: Rob Herring <[email protected]>

These peripherals are not enabled in current systems, so turn them off.

---
 arch/arm/boot/dts/highbank.dts |    5 +++++
 1 file changed, 5 insertions(+)
arch/arm/boot/dts/highbank.dts +5 -0
index 0c6fc34..28d5872 100644
@@ -132,6 +132,7 @@
 			reg = <0xffe0e000 0x1000>;
 			interrupts = <0 90 4>;
 			clocks = <&eclk>;
+			status = "disabled";
 		};
 
 		memory-controller at fff00000 {
@@ -156,6 +157,7 @@
 			interrupts = <0 14 4>;
 			clocks = <&pclk>;
 			clock-names = "apb_pclk";
+			status = "disabled";
 		};
 
 		gpiof: gpio at fff31000 {
@@ -166,6 +168,7 @@
 			interrupts = <0 15 4>;
 			clocks = <&pclk>;
 			clock-names = "apb_pclk";
+			status = "disabled";
 		};
 
 		gpiog: gpio at fff32000 {
@@ -176,6 +179,7 @@
 			interrupts = <0 16 4>;
 			clocks = <&pclk>;
 			clock-names = "apb_pclk";
+			status = "disabled";
 		};
 
 		gpioh: gpio at fff33000 {
@@ -186,6 +190,7 @@
 			interrupts = <0 17 4>;
 			clocks = <&pclk>;
 			clock-names = "apb_pclk";
+			status = "disabled";
 		};
 
 		timer {
Signature · 1 line
1.7.10.4
#2 lore raw

PATCH 2/6 ARM: highbank: enable coherent DMA for xgmac in dts

In reply to Rob Herring

From: Rob Herring <[email protected]>

Enable the xgmac to use the coherent DMA path in highbank.dts

---
 arch/arm/boot/dts/highbank.dts |    2 ++
 1 file changed, 2 insertions(+)
arch/arm/boot/dts/highbank.dts +2 -0
index 28d5872..e39a79a 100644
@@ -308,12 +308,14 @@
 			compatible = "calxeda,hb-xgmac";
 			reg = <0xfff50000 0x1000>;
 			interrupts = <0 77 4  0 78 4  0 79 4>;
+			dma-coherent;
 		};
 
 		ethernet at fff51000 {
 			compatible = "calxeda,hb-xgmac";
 			reg = <0xfff51000 0x1000>;
 			interrupts = <0 80 4  0 81 4  0 82 4>;
+			dma-coherent;
 		};
 
 		combophy0: combo-phy at fff58000 {
Signature · 1 line
1.7.10.4
#3 lore raw

PATCH 3/6 ARM: dts: Add Calxeda ECX-2000 support

In reply to Rob Herring

From: Rob Herring <[email protected]>

Separate out common dts pieces from highbank dts and add support for Calxeda ECX-2000 (Midway) SOC.

---
 Documentation/devicetree/bindings/arm/calxeda.txt |   13 +-
 arch/arm/boot/dts/Makefile                        |    3 +-
 arch/arm/boot/dts/ecx-2000.dts                    |  104 +++++++++
 arch/arm/boot/dts/ecx-common.dtsi                 |  237 +++++++++++++++++++++
 arch/arm/boot/dts/highbank.dts                    |  219 +------------------
 5 files changed, 356 insertions(+), 220 deletions(-)
 create mode 100644 arch/arm/boot/dts/ecx-2000.dts
 create mode 100644 arch/arm/boot/dts/ecx-common.dtsi
Documentation/devicetree/bindings/arm/calxeda.txt +10 -3
index 4755caa..25fcf96 100644
@@ -1,8 +1,15 @@
-Calxeda Highbank Platforms Device Tree Bindings
+Calxeda Platforms Device Tree Bindings
 -----------------------------------------------
 
-Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
-properties.
+Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the
+following properties.
 
 Required root node properties:
     - compatible = "calxeda,highbank";
+
+
+Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following
+properties.
+
+Required root node properties:
+    - compatible = "calxeda,ecx-2000";
arch/arm/boot/dts/Makefile +2 -1
index f37cf9f..5cc9566 100644
@@ -24,7 +24,8 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
 	exynos4210-smdkv310.dtb \
 	exynos4210-trats.dtb \
 	exynos5250-smdk5250.dtb
-dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
+dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
+	ecx-2000.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
 	integratorcp.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
arch/arm/boot/dts/ecx-2000.dts new file +104 -0

104 lines not on this page · raw message

arch/arm/boot/dts/ecx-common.dtsi new file +237 -0

237 lines not on this page · raw message

arch/arm/boot/dts/highbank.dts +3 -216

237 lines not on this page · raw message

Signature · 1 line
1.7.10.4
#4 lore raw

PATCH 4/6 ARM: smp_twd: don't warn on no DT node

In reply to Rob Herring

From: Rob Herring <[email protected]>

Not having a TWD is valid if we have multiple platforms with different cores, so remove the warning message.

---
 arch/arm/kernel/smp_twd.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)
arch/arm/kernel/smp_twd.c +2 -4
index e1f9069..e52e80a 100644
@@ -366,10 +366,8 @@ void __init twd_local_timer_of_register(void)
 	int err;
 
 	np = of_find_matching_node(NULL, twd_of_match);
-	if (!np) {
-		err = -ENODEV;
-		goto out;
-	}
+	if (!np)
+		return -ENODEV;
 
 	twd_ppi = irq_of_parse_and_map(np, 0);
 	if (!twd_ppi) {
Signature · 1 line
1.7.10.4
#5 lore raw

PATCH 5/6 ARM: highbank: abstract out SCU usage

In reply to Rob Herring

From: Rob Herring <[email protected]>

In preparation for A15 support on ECX-2000, the direct calls to SCU registers must be conditional. The SCU power mode register is replaced by a custom register on ECX-2000.

Rather than read the number of cores from the SCU, just hardcode it to 4. This removes one use of SCU and removes the need for the SCU to be statically mapped. The cpu initialization will ultimately come from DT.

---
 arch/arm/mach-highbank/highbank.c |   21 +++++----------------
 arch/arm/mach-highbank/hotplug.c  |    6 ++----
 arch/arm/mach-highbank/platsmp.c  |    7 +++----
 arch/arm/mach-highbank/pm.c       |    3 ---
 arch/arm/mach-highbank/sysregs.h  |   19 +++++++++++++++++++
 arch/arm/mach-highbank/system.c   |    2 --
 6 files changed, 29 insertions(+), 29 deletions(-)
arch/arm/mach-highbank/highbank.c +5 -16
index 40e36a5..3da921a 100644
@@ -28,30 +28,19 @@
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
-#include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
 #include "core.h"
 #include "sysregs.h"
 
 void __iomem *sregs_base;
-
-#define HB_SCU_VIRT_BASE	0xfee00000
-void __iomem *scu_base_addr = ((void __iomem *)(HB_SCU_VIRT_BASE));
-
-static struct map_desc scu_io_desc __initdata = {
-	.virtual	= HB_SCU_VIRT_BASE,
-	.pfn		= 0, /* run-time */
-	.length		= SZ_4K,
-	.type		= MT_DEVICE,
-};
+void __iomem *scu_base_addr;
 
 static void __init highbank_scu_map_io(void)
 {
@@ -60,13 +49,11 @@ static void __init highbank_scu_map_io(void)
 	/* Get SCU base */
 	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
 
-	scu_io_desc.pfn = __phys_to_pfn(base);
-	iotable_init(&scu_io_desc, 1);
+	scu_base_addr = ioremap(base, SZ_4K);
 }
 
 static void __init highbank_map_io(void)
 {
-	highbank_scu_map_io();
 	highbank_lluart_map_io();
 }
 
@@ -99,6 +86,9 @@ static void __init highbank_init_irq(void)
 {
 	of_irq_init(irq_match);
 
+	if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
+		highbank_scu_map_io();
+
 #ifdef CONFIG_CACHE_L2X0
 	/* Enable PL310 L2 Cache controller */
 	highbank_smc1(0x102, 0x1);
@@ -145,7 +135,6 @@ static struct sys_timer highbank_timer = {
 static void highbank_power_off(void)
 {
 	hignbank_set_pwr_shutdown();
-	scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
 
 	while (1)
 		cpu_do_idle();
arch/arm/mach-highbank/hotplug.c +2 -4
index 2c1b8c3..7b60fac 100644
@@ -14,13 +14,11 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
 
-#include <asm/smp_scu.h>
 #include <asm/cacheflush.h>
 
 #include "core.h"
+#include "sysregs.h"
 
 extern void secondary_startup(void);
 
@@ -33,7 +31,7 @@ void __ref highbank_cpu_die(unsigned int cpu)
 	flush_cache_all();
 
 	highbank_set_cpu_jump(cpu, secondary_startup);
-	scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
+	highbank_set_core_pwr();
 
 	cpu_do_idle();
 
arch/arm/mach-highbank/platsmp.c +3 -4
index fa9560e..1129957 100644
@@ -42,9 +42,7 @@ static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struc
  */
 static void __init highbank_smp_init_cpus(void)
 {
-	unsigned int i, ncores;
-
-	ncores = scu_get_core_count(scu_base_addr);
+	unsigned int i, ncores = 4;
 
 	/* sanity check */
 	if (ncores > NR_CPUS) {
@@ -65,7 +63,8 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
 {
 	int i;
 
-	scu_enable(scu_base_addr);
+	if (scu_base_addr)
+		scu_enable(scu_base_addr);
 
 	/*
 	 * Write the address of secondary startup into the jump table
arch/arm/mach-highbank/pm.c +0 -3
index de866f2..74aa135 100644
@@ -19,7 +19,6 @@
 #include <linux/suspend.h>
 
 #include <asm/proc-fns.h>
-#include <asm/smp_scu.h>
 #include <asm/suspend.h>
 
 #include "core.h"
@@ -35,8 +34,6 @@ static int highbank_pm_enter(suspend_state_t state)
 {
 	hignbank_set_pwr_suspend();
 	highbank_set_cpu_jump(0, cpu_resume);
-
-	scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
 	cpu_suspend(0, highbank_suspend_finish);
 
 	return 0;
arch/arm/mach-highbank/sysregs.h +19 -0
index 0e91338..e13e8ea 100644
@@ -17,6 +17,10 @@
 #define _MACH_HIGHBANK__SYSREGS_H_
 
 #include <linux/io.h>
+#include <linux/smp.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+#include "core.h"
 
 extern void __iomem *sregs_base;
 
@@ -29,24 +33,39 @@ extern void __iomem *sregs_base;
 #define HB_PWR_HARD_RESET		2
 #define HB_PWR_SHUTDOWN			3
 
+#define SREG_CPU_PWR_CTRL(c)		(0x200 + ((c) * 4))
+
+static inline void highbank_set_core_pwr(void)
+{
+	int cpu = cpu_logical_map(smp_processor_id());
+	if (scu_base_addr)
+		scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
+	else
+		writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
+}
+
 static inline void hignbank_set_pwr_suspend(void)
 {
 	writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
+	highbank_set_core_pwr();
 }
 
 static inline void hignbank_set_pwr_shutdown(void)
 {
 	writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
+	highbank_set_core_pwr();
 }
 
 static inline void hignbank_set_pwr_soft_reset(void)
 {
 	writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
+	highbank_set_core_pwr();
 }
 
 static inline void hignbank_set_pwr_hard_reset(void)
 {
 	writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
+	highbank_set_core_pwr();
 }
 
 #endif
arch/arm/mach-highbank/system.c +0 -2
index 82c2723..194a5bb 100644
@@ -14,7 +14,6 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/io.h>
-#include <asm/smp_scu.h>
 #include <asm/proc-fns.h>
 
 #include "core.h"
@@ -27,7 +26,6 @@ void highbank_restart(char mode, const char *cmd)
 	else
 		hignbank_set_pwr_soft_reset();
 
-	scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
 	cpu_do_idle();
 }
 
Signature · 1 line
1.7.10.4
#6 lore raw

PATCH 6/6 ARM: highbank: Add initial ECX-2000 support

In reply to Rob Herring

From: Rob Herring <[email protected]>

And initial Calxeda ECX-2000 SOC support. This adds Cortex-A15 peripherals and machine DT match name.

---
 arch/arm/mach-highbank/Kconfig    |    2 +-
 arch/arm/mach-highbank/highbank.c |    6 ++++++
 2 files changed, 7 insertions(+), 1 deletion(-)
arch/arm/mach-highbank/Kconfig +1 -1
index 0e1d0a4..551c97e 100644
@@ -1,5 +1,5 @@
 config ARCH_HIGHBANK
-	bool "Calxeda ECX-1000 (Highbank)" if ARCH_MULTI_V7
+	bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_AMBA
 	select ARM_GIC
arch/arm/mach-highbank/highbank.c +6 -0
index 3da921a..3e60e57 100644
@@ -26,6 +26,7 @@
 #include <linux/smp.h>
 #include <linux/amba/bus.h>
 
+#include <asm/arch_timer.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_twd.h>
@@ -70,6 +71,7 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
 }
 
 const static struct of_device_id irq_match[] = {
+	{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 	{}
 };
@@ -126,6 +128,9 @@ static void __init highbank_timer_init(void)
 	sp804_clockevents_init(timer_base, irq, "timer0");
 
 	twd_local_timer_of_register();
+
+	arch_timer_of_register();
+	arch_timer_sched_clock_init();
 }
 
 static struct sys_timer highbank_timer = {
@@ -200,6 +205,7 @@ static void __init highbank_init(void)
 
 static const char *highbank_match[] __initconst = {
 	"calxeda,highbank",
+	"calxeda,ecx-2000",
 	NULL,
 };
 
Signature · 1 line
1.7.10.4
maintainer
#7 lore raw

cover Initial Calxeda ECX-2000 support

In reply to Rob Herring
Quoted 9 lines · Rob Herring

From: Rob Herring <[email protected]>

This series adds initial support for Calxeda A15 based ECX-2000 SOC. Most of the changes are shuffling of dts files to share common parts between highbank (ECX-1000) and ECX-2000 and abstracting out or removing SCU accesses as the A15 has no SCU registers.

Although the highbank name really refers to 1st gen SOC, the highbank name in the kernel is now referring to both SOCs.

The patches all look good to me,