Add clock framework for armada 370/XP
Subsystems (6)
v2 cover Add clock framework for armada 370/XP
Hello Mike,
My first version didn't get many attention, so I guess it's too late for 3.7! ;) I should have ping you earlier about this series. This time was not lost, by using the cpu clock with SMP I found a bug and fixed it. And I also improved the spelling and removed unnecessary small piece of code thanks to the feed back of Andrew Lunn.
The purpose of this patch set is to add support for clock framework for Armada 370 and Armada XP SoCs. All the support is done under the directory drivers/clk/mvebu/ as the support for other mvebu SoCs was in mind during the writing of the code.
Two kinds of clocks are added:
- The CPU clocks are only for Armada XP (which si multi-core)
- The core clocks are clocks which have their rate fixed during reset.
This patch set is based on the clk-3.7 branch of Mike Turquette as it use the patch "clk: add of_clk_src_onecell_get() support" from Shawn Guo.
Many thanks to Thomas Petazzoni and Sebastian Hesselbarth for their review and feedback. The device tree bindings were really improved with the advices of Sebastian.
Changelog:
V1 -> V2:
- Improved the spelling and the wording of the documentation and the 1st commit log
- Removed the "end_of_list" name which are unused here.
- Fix the cpu clock by using of_clk_src_onecell_get in the same way it was used for the core clocks
Regards,
Gregory CLEMENT (3):
clk: mvebu: add armada-370-xp specific clocks
clk: armada-370-xp: add support for clock framework
clocksource: time-armada-370-xp converted to clk framework
.../devicetree/bindings/clock/mvebu-core-clock.txt | 40 +++ .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 21 ++ arch/arm/boot/dts/armada-370-db.dts | 4 - arch/arm/boot/dts/armada-370-xp.dtsi | 1 + arch/arm/boot/dts/armada-370.dtsi | 12 + arch/arm/boot/dts/armada-xp.dtsi | 48 +++ arch/arm/mach-mvebu/Kconfig | 5 + arch/arm/mach-mvebu/armada-370-xp.c | 8 +- arch/arm/mach-mvebu/common.h | 1 + drivers/clk/Makefile | 1 + drivers/clk/mvebu/Makefile | 2 + drivers/clk/mvebu/clk-core.c | 312 ++++++++++++++++++++ drivers/clk/mvebu/clk-core.h | 19 ++ drivers/clk/mvebu/clk-cpu.c | 155 ++++++++++ drivers/clk/mvebu/clk-cpu.h | 19 ++ drivers/clk/mvebu/clk.c | 36 +++ drivers/clocksource/time-armada-370-xp.c | 11 +- 17 files changed, 685 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt create mode 100644 drivers/clk/mvebu/Makefile create mode 100644 drivers/clk/mvebu/clk-core.c create mode 100644 drivers/clk/mvebu/clk-core.h create mode 100644 drivers/clk/mvebu/clk-cpu.c create mode 100644 drivers/clk/mvebu/clk-cpu.h create mode 100644 drivers/clk/mvebu/clk.c
Signature · 1 line
1.7.9.5
PATCH v2 1/3 clk: mvebu: add armada-370-xp specific clocks
Add Armada 370/XP specific clocks: core clocks and CPU clocks.
The CPU clocks are only for Armada XP for the SMP mode.
The core clocks are clocks which have their rate set during reset. The code was written with the other SoCs of the mvebu family in mind. Adding them should be pretty straight forward. For a new SoC, only 3 binding have to be added:
- one to provide the tclk frequency
- one to provde the pclk frequency
- and one to provide the ratio between the pclk and the children clocks
--- .../devicetree/bindings/clock/mvebu-core-clock.txt | 40 +++ .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 21 ++ drivers/clk/Makefile | 1 + drivers/clk/mvebu/Makefile | 2 + drivers/clk/mvebu/clk-core.c | 312 ++++++++++++++++++++ drivers/clk/mvebu/clk-core.h | 19 ++ drivers/clk/mvebu/clk-cpu.c | 155 ++++++++++ drivers/clk/mvebu/clk-cpu.h | 19 ++ drivers/clk/mvebu/clk.c | 36 +++ 9 files changed, 605 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt create mode 100644 drivers/clk/mvebu/Makefile create mode 100644 drivers/clk/mvebu/clk-core.c create mode 100644 drivers/clk/mvebu/clk-core.h create mode 100644 drivers/clk/mvebu/clk-cpu.c create mode 100644 drivers/clk/mvebu/clk-cpu.h create mode 100644 drivers/clk/mvebu/clk.c
Documentation/devicetree/bindings/clock/mvebu-core-clock.txt new file +40 -0
@@ -0,0 +1,40 @@ +Device Tree Clock bindings for core clock of Marvell EBU platforms + +This is the binding for the "core" clock of the mvebu SoCs, the rate +of this clocks are fixed during reset. Their value or ratio are taken +from the Sample at Reset(SAR) register. + +Required properties: +- compatible : shall be one of the following: + "marvell,armada-370-core-clockctrl" - core clock for Armada 370 + "marvell,armada-xp-core-clockctrl" - core clock for Armada XP +- reg : Address and length of the SAR register set +- #clock-cells : should be set to 1. +- clock-output-names: A list of clock output names that mvebu core + clocks provides. The full list of all valid clock names, IDs and + description are below. + Name ID Description + tclk 0 Peripheral clock + pclk 1 CPU clock + nbclk 2 L2 clock + hclk 3 DRAM control clock + dramclk 4 DDR clock + +coreclk: mvebu-sar at d0018230 { + #clock-cells = <1>; + reg = <0xd0018230 0x08>; + compatible = "marvell,armada-370-core-clockctrl"; + clock-output-names = + "tclk", /* 0 */ + "pclk", /* 1 */ + "nbclk", /* 2 */ + "hclk", /* 3 */ + "dramclk", /* 4 */ +}; + +timer at d0020300 { + compatible = "marvell,armada-370-xp-timer"; + reg = <0xd0020300 0x30>; + interrupts = <37>, <38>, <39>, <40>; + clocks = <&coreclk 0>; +};
Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt new file +21 -0
@@ -0,0 +1,21 @@ +Device Tree Clock bindings for cpu clock of Marvell EBU platforms + +Required properties: +- compatible : shall be one of the following: + "marvell,armada-xp-cpu-clockctrl" - cpu clocks for Armada XP +- reg : Address and length of the clock complex register set +- #clock-cells : should be set to 1. +- clocks : shall be the input parent clock phandle for the clock. + +cpuclk: clock-complex at d0018700 { + #clock-cells = <1>; + compatible = "marvell,armada-xp-cpu-clockctrl"; + reg = <0xd0018700 0xA0>; + clocks = <&coreclk 1>; +} + +cpu at 0 { + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; +};
drivers/clk/Makefile +1 -0
@@ -11,6 +11,7 @@ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o +obj-$(CONFIG_ARCH_MVEBU) += mvebu/ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endif
drivers/clk/mvebu/Makefile new file +2 -0
@@ -0,0 +1,2 @@ +obj-y += clk.o clk-core.o +obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
drivers/clk/mvebu/clk-core.c new file +312 -0
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drivers/clk/mvebu/clk-core.h new file +19 -0
@@ -0,0 +1,19 @@ +/* +* * Marvell EBU clock core handling defined at reset +* +* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/ + +#ifndef __MVEBU_CLK_CORE_H +#define __MVEBU_CLK_CORE_H + +void __init of_core_clk_setup (struct device_node *node); +void __init mvebu_core_clocks_init (void ); + +#endif
drivers/clk/mvebu/clk-cpu.c new file +155 -0
155 lines not on this page · raw message
drivers/clk/mvebu/clk-cpu.h new file +19 -0
@@ -0,0 +1,19 @@ +/* +* Marvell MVEBU CPU clock handling. +* +* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/ + +#ifndef __MVEBU_CLK_CPU_H +#define __MVEBU_CLK_CPU_H + +void __init of_cpu_clk_setup (struct device_node *node); +void __init mvebu_cpu_clocks_init (void ); + +#endif
drivers/clk/mvebu/clk.c new file +36 -0
@@ -0,0 +1,36 @@ +/* +* Marvell EBU SoC clock handling. +* +* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/ +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/of.h> +#include "clk-cpu.h" +#include "clk-core.h" + +static const __initconst struct of_device_id clk_match[] = { +#ifdef CONFIG_MVEBU_CLK_CPU + { + .compatible ="marvell,armada-xp-cpu-clockctrl" , + .data = of_cpu_clk_setup, + }, +#endif + { +/* sentinel */ + } +}; + +void __init mvebu_clocks_init (void ) +{ +mvebu_core_clocks_init (); +of_clk_init (clk_match); +}
Signature · 1 line
1.7.9.5
PATCH v2 1/3 clk: mvebu: add armada-370-xp specific clocks
Quoting Gregory CLEMENT (2012-10-01 14:12:04)
Quoted 13 lines
Add Armada 370/XP specific clocks: core clocks and CPU clocks.
The CPU clocks are only for Armada XP for the SMP mode.
The core clocks are clocks which have their rate set during reset. The code was written with the other SoCs of the mvebu family in mind. Adding them should be pretty straight forward. For a new SoC, only 3 binding have to be added:
- one to provide the tclk frequency
- one to provde the pclk frequency
- and one to provide the ratio between the pclk and the children clocks
Quoted 1 line
Signed-off-by Gregory CLEMENT <[email protected]>
Thanks for sending v2 Gregory. Functionally this series looks good but unfortunately there are a few style and white space nitpicks below.
Quoted 14 lines
Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt new file +8
-0@@ -0,0 +1,21 @@ +Device Tree Clock bindings for cpu clock of Marvell EBU platforms + +Required properties: +- compatible : shall be one of the following: + "marvell,armada-xp-cpu-clockctrl" - cpu clocks for Armada XP +- reg : Address and length of the clock complex register set +- #clock-cells : should be set to 1. +- clocks : shall be the input parent clock phandle for the clock.
Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt line 18
Quoted 10 lines
Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt new file +10
-0+ +cpuclk: clock-complex at d0018700 { + #clock-cells = <1>; + compatible = "marvell,armada-xp-cpu-clockctrl"; + reg = <0xd0018700 0xA0>; + clocks = <&coreclk 1>; +} + +cpu at 0 { + compatible = "marvell,sheeva-v7";
Unnecessary white space before the tab in the line above.
Quoted 17 lines
drivers/clk/mvebu/clk-core.c new file +11
-0@@ -0,0 +1,312 @@ +/* +* Marvell EBU clock core handling defined at reset +* +* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/
drivers/clk/mvebu/clk-core.c line 21
Quoted 10 lines
drivers/clk/mvebu/clk-core.c new file +10
-0+#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/io.h> +#include <linux/of.h> + +/* Sample At Reset is a 64 bit bitfiled split in two register of 32 +* bits*/
Can you make this proper comment block style per CodingStyle convention?
Quoted 25 lines
drivers/clk/mvebu/clk-core.c new file +25
-0+ +#define SARL 0/* Low part [0:31] */ +#define SARL_AXP_PCLK_FREQ_OPT 21 +#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7 +#define SARL_A370_PCLK_FREQ_OPT 11 +#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF +#define SARL_AXP_FAB_FREQ_OPT 24 +#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF +#define SARL_A370_FAB_FREQ_OPT 15 +#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F +#define SARL_A370_TCLK_FREQ_OPT 20 +#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1 +#define SARH 4/* High part [32:63] */ +#define SARH_AXP_PCLK_FREQ_OPT (52-32) +#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1 +#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3 +#define SARH_AXP_FAB_FREQ_OPT (51-32) +#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1 +#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4 + +u32 *sar_reg; +int sar_reg_size; + +enum core_clk { + tclk, pclk, nbclk, hclk, dramclk, clk_max
drivers/clk/mvebu/clk-core.c line 56
Quoted 10 lines
drivers/clk/mvebu/clk-core.c new file +10
-0+}; + +struct core_clk_fn { +u32 (*get_tclk_freq) (void ); +u32 (*get_pck_freq) (void ); +const int *(*get_fab_freq_opt) (void ); +}; + +/* Ratio between VCO and each of the member in the following order: +CPU clock, L2 clock, DRAM controler clock, DDR clcok */
ditto
Quoted 74 lines
drivers/clk/mvebu/clk-core.c new file +74
-0+static const int reset_core_ratio[32 ][4 ] = { + [0x01 ] = {1 ,2 ,2 ,2 }, + [0x02 ] = {2 ,2 ,6 ,3 }, + [0x03 ] = {2 ,2 ,3 ,3 }, + [0x04 ] = {1 ,2 ,3 ,3 }, + [0x05 ] = {1 ,2 ,4 ,2 }, + [0x06 ] = {1 ,1 ,2 ,2 }, + [0x07 ] = {2 ,3 ,6 ,6 }, + [0x09 ] = {1 ,2 ,6 ,3 }, + [0x0A ] = {2 ,4 ,10 ,5 }, + [0x0C ] = {1 ,2 ,4 ,4 }, + [0x0F ] = {2 ,2 ,5 ,5 }, + [0x13 ] = {1 ,1 ,2 ,1 }, + [0x14 ] = {2 ,3 ,6 ,3 }, + [0x1B ] = {1 ,1 ,1 ,1 }, +}; + +static struct clk *clks[clk_max]; + +static struct clk_onecell_data clk_data; + +/* Frequency in MHz*/ +static u32 armada_370_pclk[] = {400 ,533 ,667 ,800 ,1000 ,1067 ,1200 }; + +static u32 armada_xp_pclk[] = {1000 ,1066 ,1200 ,1333 ,1500 ,1666 , +1800 ,2000 ,667 ,0 ,800 ,1600 +}; + +static u32 armada_370_tclk[] = {166 ,200 }; + +static const int *__init armada_370_get_fab_freq_opt (void ) +{ +u8 fab_freq_opt =0 ; + + fab_freq_opt = ((sar_reg[0 ] >>SARL_A370_FAB_FREQ_OPT ) & +SARL_A370_FAB_FREQ_OPT_MASK ); + +if (reset_core_ratio[fab_freq_opt][0 ] ==0 ) +return NULL ; +else +return reset_core_ratio[fab_freq_opt]; +} + +static u32 __init armada_370_get_pck_freq (void ) +{ +u32 cpu_freq; +u8 cpu_freq_select =0 ; + + cpu_freq_select = ((sar_reg[0 ] >>SARL_A370_PCLK_FREQ_OPT ) & +SARL_A370_PCLK_FREQ_OPT_MASK ); +if (cpu_freq_select >ARRAY_SIZE (armada_370_pclk)) { +pr_err ("CPU freq select unsuported %d\n" , cpu_freq_select); + cpu_freq =0 ; + }else + cpu_freq = armada_370_pclk[cpu_freq_select]; + +return cpu_freq *1000 *1000 ; +} + +static u32 __init armada_370_get_tclk_freq (void ) +{ +u32 tclk_freq; +u8 tclk_freq_select =0 ; + + tclk_freq_select = ((sar_reg[0 ] >>SARL_A370_TCLK_FREQ_OPT ) & +SARL_A370_TCLK_FREQ_OPT_MASK ); +if (tclk_freq_select >ARRAY_SIZE (armada_370_tclk)) { +pr_err ("TCLK freq select unsuported %d\n" , tclk_freq_select); + tclk_freq =0 ; + }else + tclk_freq = armada_370_tclk[tclk_freq_select]; + +return tclk_freq *1000 *1000 ; +}
drivers/clk/mvebu/clk-core.c line 140
Quoted 10 lines
drivers/clk/mvebu/clk-core.c new file +10
-0+ +static const int *__init armada_xp_get_fab_freq_opt (void ) +{ +u8 fab_freq_opt =0 ; + + fab_freq_opt = ((sar_reg[0 ] >>SARL_AXP_FAB_FREQ_OPT ) & +SARL_AXP_FAB_FREQ_OPT_MASK ); +/* The upper bit is not contiguous to the other ones +* and located in the high part of the SAR +* registers */
ditto
Quoted 10 lines
drivers/clk/mvebu/clk-core.c new file +10
-0+ fab_freq_opt |= (((sar_reg[1 ] >>SARH_AXP_FAB_FREQ_OPT ) & +SARH_AXP_FAB_FREQ_OPT_MASK ) + <<SARH_AXP_FAB_FREQ_OPT_SHIFT ); + +if (reset_core_ratio[fab_freq_opt][0 ] ==0 ) +return NULL ; +else +return reset_core_ratio[fab_freq_opt]; +} +
drivers/clk/mvebu/clk-core.c line 160
Quoted 10 lines
drivers/clk/mvebu/clk-core.c new file +10
-0+static u32 __init armada_xp_get_pck_freq (void ) +{ +u32 cpu_freq; +u8 cpu_freq_select =0 ; + + cpu_freq_select = ((sar_reg[0 ] >>SARL_AXP_PCLK_FREQ_OPT ) & +SARL_AXP_PCLK_FREQ_OPT_MASK ); +/* The upper bit is not contiguous to the other ones +* and located in the high part of the SAR +* registers */
ditto
Quoted 49 lines
drivers/clk/mvebu/clk-core.c new file +49
-0+ cpu_freq_select |= (((sar_reg[1 ] >>SARH_AXP_PCLK_FREQ_OPT ) & +SARH_AXP_PCLK_FREQ_OPT_MASK ) + <<SARH_AXP_PCLK_FREQ_OPT_SHIFT ); +if (cpu_freq_select >ARRAY_SIZE (armada_xp_pclk)) { +pr_err ("CPU freq select unsuported: %d\n" , cpu_freq_select); + cpu_freq =0 ; + }else + cpu_freq = armada_xp_pclk[cpu_freq_select]; + +return cpu_freq *1000 *1000 ; +} + +/* For Armada XP TCLK frequency is fix: 250MHz */ +static u32 __init armada_xp_get_tclk_freq (void ) +{ +return 250 *1000 *1000 ; +} + +void __init of_core_clk_setup (struct device_node *node, +struct core_clk_fn clk_fn) +{ +struct clk *clk; +unsigned long rate; +const char *clk_name; +int i; + +/* clock 0 is tclk */ +of_property_read_string_index (node,"clock-output-names" , tclk, + &clk_name); + rate = clk_fn.get_tclk_freq (); +if (rate !=0 ) + clk =clk_register_fixed_rate (NULL , clk_name,NULL , +CLK_IS_ROOT , rate); +else { +pr_err ("Invalid freq for %s\n" , clk_name); +return ; + } + +if (WARN_ON (IS_ERR (clk))) +return ; + clks[tclk] = clk; + +/* clock 1 is pclk */ +of_property_read_string_index (node,"clock-output-names" , pclk, + &clk_name); + rate = clk_fn.get_pck_freq (); +if (rate !=0 ) + clk =clk_register_fixed_rate (NULL , clk_name,NULL , +CLK_IS_ROOT , rate);
drivers/clk/mvebu/clk-core.c line 219
Quoted 10 lines
drivers/clk/mvebu/clk-core.c new file +10
-0+else { +pr_err ("Invalid freq for %s\n" , clk_name); +return ; + } +if (WARN_ON (IS_ERR (clk))) +return ; + clks[pclk] = clk; + +/* the clocks 2 to 4 are nbclk, hclk and dramclk and are all +* derivated from the clock 1: pclk */
ditto
Quoted 36 lines
drivers/clk/mvebu/clk-core.c new file +36
-0+ +for (i = nbclk; i <= dramclk; i++) { +const int *ratio = clk_fn.get_fab_freq_opt (); +const char *parent_clk_name; + +of_property_read_string_index (node,"clock-output-names" , + i, &clk_name); +of_property_read_string_index (node,"clock-output-names" , + pclk, &parent_clk_name); + +if (ratio !=NULL ) + clk =clk_register_fixed_factor (NULL , clk_name, + parent_clk_name,0 , + ratio[0 ], + ratio[i - nbclk +1 ]); +else { +pr_err ("Invalid clk ratio for %s\n" , clk_name); +return ; + } + +if (WARN_ON (IS_ERR (clk))) +return ; + clks[i] = clk; + } + clk_data.clk_num =ARRAY_SIZE (clks); + clk_data.clks = clks; +of_clk_add_provider (node, of_clk_src_onecell_get, &clk_data); +} + +static struct core_clk_fn armada_370_clk_fn = { + .get_tclk_freq = armada_370_get_tclk_freq, + .get_pck_freq = armada_370_get_pck_freq, + .get_fab_freq_opt = armada_370_get_fab_freq_opt, +}; + +static struct core_clk_fn armada_xp_clk_fn = {
drivers/clk/mvebu/clk-core.c line 265
Quoted 10 lines
drivers/clk/mvebu/clk-core.c new file +10
-0+ .get_tclk_freq = armada_xp_get_tclk_freq, + .get_pck_freq = armada_xp_get_pck_freq, + .get_fab_freq_opt = armada_xp_get_fab_freq_opt, +}; + +static const __initconst struct of_device_id clk_match[] = { + { + .compatible ="marvell,armada-370-core-clockctrl" , + .data = &armada_370_clk_fn, + },
Indention is a bit weird here. The members are just indented with one space and there is an extra white space in front of the closing bracket. Can you re-align?
drivers/clk/mvebu/clk-core.c line 270
Quoted 5 lines
drivers/clk/mvebu/clk-core.c new file +5
-0+ + { + .compatible = "marvell,armada-xp-core-clockctrl", + .data = &armada_xp_clk_fn, + },
ditto
drivers/clk/mvebu/clk-core.c line 273
Quoted 3 lines
drivers/clk/mvebu/clk-core.c new file +3
-0+ { +/* sentinel */ + }
ditto
Quoted 73 lines
drivers/clk/mvebu/clk-core.c new file +39
-0+}; + +void __init mvebu_core_clocks_init (void ) +{ +struct device_node *np; +struct resource res; +void __iomem *sar_base; +int i; + + np =of_find_node_by_name (NULL ,"mvebu-sar" ); + +if (!np) + goto err; + +if (of_address_to_resource (np,0 , &res)) + goto err; + + sar_reg_size =resource_size (&res); + sar_reg =kmalloc (sar_reg_size,GFP_KERNEL ); + + sar_base =ioremap (res.start, sar_reg_size); +if (sar_base ==NULL ) + goto err; +for (i =0 ; i < sar_reg_size; i +=sizeof (*sar_reg)) + sar_reg[i] =readl (sar_base + i); + +iounmap (sar_base); + +for_each_matching_node (np, clk_match) { +const struct of_device_id *match =of_match_node (clk_match, np); +struct core_clk_fn *clk_fn = match->data; +of_core_clk_setup (np, *clk_fn); + } + +return ; +err: +pr_err ("%s:SAR base adresse not set in DT\n" , __func__); +return ; +}drivers/clk/mvebu/clk-core.h new file +19
-0@@ -0,0 +1,19 @@ +/* +* * Marvell EBU clock core handling defined at reset +* +* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/ + +#ifndef __MVEBU_CLK_CORE_H +#define __MVEBU_CLK_CORE_H + +void __init of_core_clk_setup (struct device_node *node); +void __init mvebu_core_clocks_init (void ); + +#endif drivers/clk/mvebu/clk-cpu.c new file +3
-0@@ -0,0 +1,155 @@ +/* +* Marvell MVEBU CPU clock handling. +*
drivers/clk/mvebu/clk-cpu.c line 13
Quoted 10 lines
drivers/clk/mvebu/clk-cpu.c new file +10
-0+* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/ +#include <linux/kernel.h> +#include <linux/clk.h>
clk-provider.h includes clk.h, so this is redundant.
Regards,
Mike
PATCH v2 1/3 clk: mvebu: add armada-370-xp specific clocks
Quoted 14 lines · Mike Turquette
Quoting Gregory CLEMENT (2012-10-01 14:12:04)
Quoted 13 lines
Add Armada 370/XP specific clocks: core clocks and CPU clocks.
The CPU clocks are only for Armada XP for the SMP mode.
The core clocks are clocks which have their rate set during reset. The code was written with the other SoCs of the mvebu family in mind. Adding them should be pretty straight forward. For a new SoC, only 3 binding have to be added:
- one to provide the tclk frequency
- one to provde the pclk frequency
- and one to provide the ratio between the pclk and the children clocks
Quoted 4 lines
Quoted 1 line
Signed-off-by Gregory CLEMENT <[email protected]>Thanks for sending v2 Gregory. Functionally this series looks good but unfortunately there are a few style and white space nitpicks below.
Hi Mike,
You don't review the last version: I have sent a third version tow weeks ago (October th 15th). But all your comment should applied for this last version.
The changelog was
V2 -> V3:
- Rebased on top of v3.7-rc1
- Fixed a typo in device trees
- Fixed warning from checkpatch
Thanks for your review, I will send a new version in few hours.
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Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt new file +8
-0@@ -0,0 +1,21 @@ +Device Tree Clock bindings for cpu clock of Marvell EBU platforms + +Required properties: +- compatible : shall be one of the following: + "marvell,armada-xp-cpu-clockctrl" - cpu clocks for Armada XP +- reg : Address and length of the clock complex register set +- #clock-cells : should be set to 1. +- clocks : shall be the input parent clock phandle for the clock.Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt line 18
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Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt new file +10
-0+ +cpuclk: clock-complex at d0018700 { + #clock-cells = <1>; + compatible = "marvell,armada-xp-cpu-clockctrl"; + reg = <0xd0018700 0xA0>; + clocks = <&coreclk 1>; +} + +cpu at 0 { + compatible = "marvell,sheeva-v7";Unnecessary white space before the tab in the line above.
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drivers/clk/mvebu/clk-core.c new file +11
-0@@ -0,0 +1,312 @@ +/* +* Marvell EBU clock core handling defined at reset +* +* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/ drivers/clk/mvebu/clk-core.c line 21
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drivers/clk/mvebu/clk-core.c new file +10
-0+#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/io.h> +#include <linux/of.h> + +/* Sample At Reset is a 64 bit bitfiled split in two register of 32 +* bits*/ Can you make this proper comment block style per CodingStyle convention?
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drivers/clk/mvebu/clk-core.c new file +25
-0+ +#define SARL 0/* Low part [0:31] */ +#define SARL_AXP_PCLK_FREQ_OPT 21 +#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7 +#define SARL_A370_PCLK_FREQ_OPT 11 +#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF +#define SARL_AXP_FAB_FREQ_OPT 24 +#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF +#define SARL_A370_FAB_FREQ_OPT 15 +#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F +#define SARL_A370_TCLK_FREQ_OPT 20 +#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1 +#define SARH 4/* High part [32:63] */ +#define SARH_AXP_PCLK_FREQ_OPT (52-32) +#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1 +#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3 +#define SARH_AXP_FAB_FREQ_OPT (51-32) +#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1 +#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4 + +u32 *sar_reg; +int sar_reg_size; + +enum core_clk { + tclk, pclk, nbclk, hclk, dramclk, clk_maxdrivers/clk/mvebu/clk-core.c line 56
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drivers/clk/mvebu/clk-core.c new file +10
-0+}; + +struct core_clk_fn { +u32 (*get_tclk_freq) (void ); +u32 (*get_pck_freq) (void ); +const int *(*get_fab_freq_opt) (void ); +}; + +/* Ratio between VCO and each of the member in the following order: +CPU clock, L2 clock, DRAM controler clock, DDR clcok */ ditto
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drivers/clk/mvebu/clk-core.c new file +74
-0+static const int reset_core_ratio[32 ][4 ] = { + [0x01 ] = {1 ,2 ,2 ,2 }, + [0x02 ] = {2 ,2 ,6 ,3 }, + [0x03 ] = {2 ,2 ,3 ,3 }, + [0x04 ] = {1 ,2 ,3 ,3 }, + [0x05 ] = {1 ,2 ,4 ,2 }, + [0x06 ] = {1 ,1 ,2 ,2 }, + [0x07 ] = {2 ,3 ,6 ,6 }, + [0x09 ] = {1 ,2 ,6 ,3 }, + [0x0A ] = {2 ,4 ,10 ,5 }, + [0x0C ] = {1 ,2 ,4 ,4 }, + [0x0F ] = {2 ,2 ,5 ,5 }, + [0x13 ] = {1 ,1 ,2 ,1 }, + [0x14 ] = {2 ,3 ,6 ,3 }, + [0x1B ] = {1 ,1 ,1 ,1 }, +}; + +static struct clk *clks[clk_max]; + +static struct clk_onecell_data clk_data; + +/* Frequency in MHz*/ +static u32 armada_370_pclk[] = {400 ,533 ,667 ,800 ,1000 ,1067 ,1200 }; + +static u32 armada_xp_pclk[] = {1000 ,1066 ,1200 ,1333 ,1500 ,1666 , +1800 ,2000 ,667 ,0 ,800 ,1600 +}; + +static u32 armada_370_tclk[] = {166 ,200 }; + +static const int *__init armada_370_get_fab_freq_opt (void ) +{ +u8 fab_freq_opt =0 ; + + fab_freq_opt = ((sar_reg[0 ] >>SARL_A370_FAB_FREQ_OPT ) & +SARL_A370_FAB_FREQ_OPT_MASK ); + +if (reset_core_ratio[fab_freq_opt][0 ] ==0 ) +return NULL ; +else +return reset_core_ratio[fab_freq_opt]; +} + +static u32 __init armada_370_get_pck_freq (void ) +{ +u32 cpu_freq; +u8 cpu_freq_select =0 ; + + cpu_freq_select = ((sar_reg[0 ] >>SARL_A370_PCLK_FREQ_OPT ) & +SARL_A370_PCLK_FREQ_OPT_MASK ); +if (cpu_freq_select >ARRAY_SIZE (armada_370_pclk)) { +pr_err ("CPU freq select unsuported %d\n" , cpu_freq_select); + cpu_freq =0 ; + }else + cpu_freq = armada_370_pclk[cpu_freq_select]; + +return cpu_freq *1000 *1000 ; +} + +static u32 __init armada_370_get_tclk_freq (void ) +{ +u32 tclk_freq; +u8 tclk_freq_select =0 ; + + tclk_freq_select = ((sar_reg[0 ] >>SARL_A370_TCLK_FREQ_OPT ) & +SARL_A370_TCLK_FREQ_OPT_MASK ); +if (tclk_freq_select >ARRAY_SIZE (armada_370_tclk)) { +pr_err ("TCLK freq select unsuported %d\n" , tclk_freq_select); + tclk_freq =0 ; + }else + tclk_freq = armada_370_tclk[tclk_freq_select]; + +return tclk_freq *1000 *1000 ; +}drivers/clk/mvebu/clk-core.c line 140
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drivers/clk/mvebu/clk-core.c new file +10
-0+ +static const int *__init armada_xp_get_fab_freq_opt (void ) +{ +u8 fab_freq_opt =0 ; + + fab_freq_opt = ((sar_reg[0 ] >>SARL_AXP_FAB_FREQ_OPT ) & +SARL_AXP_FAB_FREQ_OPT_MASK ); +/* The upper bit is not contiguous to the other ones +* and located in the high part of the SAR +* registers */ ditto
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drivers/clk/mvebu/clk-core.c new file +10
-0+ fab_freq_opt |= (((sar_reg[1 ] >>SARH_AXP_FAB_FREQ_OPT ) & +SARH_AXP_FAB_FREQ_OPT_MASK ) + <<SARH_AXP_FAB_FREQ_OPT_SHIFT ); + +if (reset_core_ratio[fab_freq_opt][0 ] ==0 ) +return NULL ; +else +return reset_core_ratio[fab_freq_opt]; +} +drivers/clk/mvebu/clk-core.c line 160
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drivers/clk/mvebu/clk-core.c new file +10
-0+static u32 __init armada_xp_get_pck_freq (void ) +{ +u32 cpu_freq; +u8 cpu_freq_select =0 ; + + cpu_freq_select = ((sar_reg[0 ] >>SARL_AXP_PCLK_FREQ_OPT ) & +SARL_AXP_PCLK_FREQ_OPT_MASK ); +/* The upper bit is not contiguous to the other ones +* and located in the high part of the SAR +* registers */ ditto
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drivers/clk/mvebu/clk-core.c new file +49
-0+ cpu_freq_select |= (((sar_reg[1 ] >>SARH_AXP_PCLK_FREQ_OPT ) & +SARH_AXP_PCLK_FREQ_OPT_MASK ) + <<SARH_AXP_PCLK_FREQ_OPT_SHIFT ); +if (cpu_freq_select >ARRAY_SIZE (armada_xp_pclk)) { +pr_err ("CPU freq select unsuported: %d\n" , cpu_freq_select); + cpu_freq =0 ; + }else + cpu_freq = armada_xp_pclk[cpu_freq_select]; + +return cpu_freq *1000 *1000 ; +} + +/* For Armada XP TCLK frequency is fix: 250MHz */ +static u32 __init armada_xp_get_tclk_freq (void ) +{ +return 250 *1000 *1000 ; +} + +void __init of_core_clk_setup (struct device_node *node, +struct core_clk_fn clk_fn) +{ +struct clk *clk; +unsigned long rate; +const char *clk_name; +int i; + +/* clock 0 is tclk */ +of_property_read_string_index (node,"clock-output-names" , tclk, + &clk_name); + rate = clk_fn.get_tclk_freq (); +if (rate !=0 ) + clk =clk_register_fixed_rate (NULL , clk_name,NULL , +CLK_IS_ROOT , rate); +else { +pr_err ("Invalid freq for %s\n" , clk_name); +return ; + } + +if (WARN_ON (IS_ERR (clk))) +return ; + clks[tclk] = clk; + +/* clock 1 is pclk */ +of_property_read_string_index (node,"clock-output-names" , pclk, + &clk_name); + rate = clk_fn.get_pck_freq (); +if (rate !=0 ) + clk =clk_register_fixed_rate (NULL , clk_name,NULL , +CLK_IS_ROOT , rate);drivers/clk/mvebu/clk-core.c line 219
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drivers/clk/mvebu/clk-core.c new file +10
-0+else { +pr_err ("Invalid freq for %s\n" , clk_name); +return ; + } +if (WARN_ON (IS_ERR (clk))) +return ; + clks[pclk] = clk; + +/* the clocks 2 to 4 are nbclk, hclk and dramclk and are all +* derivated from the clock 1: pclk */ ditto
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drivers/clk/mvebu/clk-core.c new file +36
-0+ +for (i = nbclk; i <= dramclk; i++) { +const int *ratio = clk_fn.get_fab_freq_opt (); +const char *parent_clk_name; + +of_property_read_string_index (node,"clock-output-names" , + i, &clk_name); +of_property_read_string_index (node,"clock-output-names" , + pclk, &parent_clk_name); + +if (ratio !=NULL ) + clk =clk_register_fixed_factor (NULL , clk_name, + parent_clk_name,0 , + ratio[0 ], + ratio[i - nbclk +1 ]); +else { +pr_err ("Invalid clk ratio for %s\n" , clk_name); +return ; + } + +if (WARN_ON (IS_ERR (clk))) +return ; + clks[i] = clk; + } + clk_data.clk_num =ARRAY_SIZE (clks); + clk_data.clks = clks; +of_clk_add_provider (node, of_clk_src_onecell_get, &clk_data); +} + +static struct core_clk_fn armada_370_clk_fn = { + .get_tclk_freq = armada_370_get_tclk_freq, + .get_pck_freq = armada_370_get_pck_freq, + .get_fab_freq_opt = armada_370_get_fab_freq_opt, +}; + +static struct core_clk_fn armada_xp_clk_fn = {drivers/clk/mvebu/clk-core.c line 265
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drivers/clk/mvebu/clk-core.c new file +10
-0+ .get_tclk_freq = armada_xp_get_tclk_freq, + .get_pck_freq = armada_xp_get_pck_freq, + .get_fab_freq_opt = armada_xp_get_fab_freq_opt, +}; + +static const __initconst struct of_device_id clk_match[] = { + { + .compatible ="marvell,armada-370-core-clockctrl" , + .data = &armada_370_clk_fn, + },Indention is a bit weird here. The members are just indented with one space and there is an extra white space in front of the closing bracket. Can you re-align?
drivers/clk/mvebu/clk-core.c line 270
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drivers/clk/mvebu/clk-core.c new file +5
-0+ + { + .compatible = "marvell,armada-xp-core-clockctrl", + .data = &armada_xp_clk_fn, + },ditto
drivers/clk/mvebu/clk-core.c line 273
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drivers/clk/mvebu/clk-core.c new file +3
-0+ { +/* sentinel */ + }ditto
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drivers/clk/mvebu/clk-core.c new file +39
-0+}; + +void __init mvebu_core_clocks_init (void ) +{ +struct device_node *np; +struct resource res; +void __iomem *sar_base; +int i; + + np =of_find_node_by_name (NULL ,"mvebu-sar" ); + +if (!np) + goto err; + +if (of_address_to_resource (np,0 , &res)) + goto err; + + sar_reg_size =resource_size (&res); + sar_reg =kmalloc (sar_reg_size,GFP_KERNEL ); + + sar_base =ioremap (res.start, sar_reg_size); +if (sar_base ==NULL ) + goto err; +for (i =0 ; i < sar_reg_size; i +=sizeof (*sar_reg)) + sar_reg[i] =readl (sar_base + i); + +iounmap (sar_base); + +for_each_matching_node (np, clk_match) { +const struct of_device_id *match =of_match_node (clk_match, np); +struct core_clk_fn *clk_fn = match->data; +of_core_clk_setup (np, *clk_fn); + } + +return ; +err: +pr_err ("%s:SAR base adresse not set in DT\n" , __func__); +return ; +}drivers/clk/mvebu/clk-core.h new file +19
-0@@ -0,0 +1,19 @@ +/* +* * Marvell EBU clock core handling defined at reset +* +* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/ + +#ifndef __MVEBU_CLK_CORE_H +#define __MVEBU_CLK_CORE_H + +void __init of_core_clk_setup (struct device_node *node); +void __init mvebu_core_clocks_init (void ); + +#endif drivers/clk/mvebu/clk-cpu.c new file +3
-0@@ -0,0 +1,155 @@ +/* +* Marvell MVEBU CPU clock handling. +* drivers/clk/mvebu/clk-cpu.c line 13
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drivers/clk/mvebu/clk-cpu.c new file +10
-0+* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/ +#include <linux/kernel.h> +#include <linux/clk.h>
clk-provider.hincludesclk.h, so this is redundant.Regards,
Mike
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
PATCH v2 2/3 clk: armada-370-xp: add support for clock framework
In reply to Gregory CLEMENT--- arch/arm/boot/dts/armada-370.dtsi | 12 +++++++++ arch/arm/boot/dts/armada-xp.dtsi | 48 +++++++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/Kconfig | 5 ++++ arch/arm/mach-mvebu/armada-370-xp.c | 8 +++++- arch/arm/mach-mvebu/common.h | 1 + 5 files changed, 73 insertions(+), 1 deletion(-)
arch/arm/boot/dts/armada-370.dtsi +12 -0
@@ -31,5 +31,17 @@ compatible = "marvell,armada-370-xp-system-controller"; reg = <0xd0018200 0x100>; }; + coreclk: mvebu-sar at d0018230 { + #clock-cells = <1>; + reg = <0xd0018230 0x08>; + compatible = "marvell,armada-370-core-clockctrl"; + clock-output-names = + "tclk", /* 0 */ + "pclk", /* 1 */ + "nbclk", /* 2 */ + "hclk", /* 3 */ + "dramclk", /* 4 */ + }; + }; };
arch/arm/boot/dts/armada-xp.dtsi +48 -0
60 lines not on this page · raw message
arch/arm/mach-mvebu/Kconfig +5 -0
@@ -2,10 +2,15 @@ if ARCH_MVEBU menu "Marvell SOC with device tree" +config MVEBU_CLK_CPU + bool + config MACH_ARMADA_370_XP bool "Marvell Armada 370 and Aramada XP boards" select ARMADA_370_XP_TIMER select CPU_V7 + select CLKDEV_LOOKUP + select MVEBU_CLK_CPU help Say 'Y' here if you want your kernel to support boards based on
arch/arm/mach-mvebu/armada-370-xp.c +7 -1
@@ -37,8 +37,14 @@ void __init armada_370_xp_map_io(void)iotable_init (armada_370_xp_io_desc,ARRAY_SIZE (armada_370_xp_io_desc)); } +void __init armada_370_xp_timer_and_clk_init (void ) +{ +mvebu_clocks_init (); +armada_370_xp_timer_init (); +} +struct sys_timer armada_370_xp_timer = { - .init = armada_370_xp_timer_init, + .init = armada_370_xp_timer_and_clk_init, };static void __init armada_370_xp_dt_init (void )
arch/arm/mach-mvebu/common.h +1 -0
@@ -16,6 +16,7 @@#define __ARCH_MVEBU_COMMON_Hvoid mvebu_restart (char mode,const char *cmd); +void mvebu_clocks_init (void );void armada_370_xp_init_irq (void );void armada_370_xp_handle_irq (struct pt_regs *regs);
Signature · 1 line
1.7.9.5
PATCH v2 2/3 clk: armada-370-xp: add support for clock framework
Quoting Gregory CLEMENT (2012-10-01 14:12:05)
Quoted 1 line
Signed-off-by Gregory CLEMENT <[email protected]>
This didn't apply cleanly to -rc3. Can you rebase this along with the respin of patch #1 in the series?
<snip>
Quoted 5 lines
arch/arm/boot/dts/armada-xp.dtsi +0
-0
arch/arm/boot/dts/armada-xp.dtsi line 35
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arch/arm/boot/dts/armada-xp.dtsi +6
-0@@ -27,6 +27,35 @@ <0xd0021870 0x58>; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + compatible = "marvell,sheeva-v7";
Extra white space in front of compatible. Should be tabs.
Regards,
Mike
PATCH v2 3/3 clocksource: time-armada-370-xp converted to clk framework
In reply to Gregory CLEMENT--- arch/arm/boot/dts/armada-370-db.dts | 4 ---- arch/arm/boot/dts/armada-370-xp.dtsi | 1 + drivers/clocksource/time-armada-370-xp.c | 11 ++++++----- 3 files changed, 7 insertions(+), 9 deletions(-)
arch/arm/boot/dts/armada-370-db.dts +0 -4
@@ -34,9 +34,5 @@ clock-frequency = <200000000>; status = "okay"; }; - timer at d0020300 { - clock-frequency = <600000000>; - status = "okay"; - }; }; };
arch/arm/boot/dts/armada-370-xp.dtsi +1 -0
@@ -62,6 +62,7 @@ compatible = "marvell,armada-370-xp-timer"; reg = <0xd0020300 0x30>; interrupts = <37>, <38>, <39>, <40>; + clocks = <&coreclk 2>; }; }; };
drivers/clocksource/time-armada-370-xp.c +6 -5
@@ -18,6 +18,7 @@#include <linux/init.h> #include <linux/platform_device.h> #include <linux/kernel.h> +#include <linux/clk.h> #include <linux/timer.h> #include <linux/clockchips.h> #include <linux/interrupt.h>
@@ -167,7 +168,6 @@ void __init armada_370_xp_timer_init(void)u32 u;struct device_node *np;unsigned int timer_clk; -int ret; np =of_find_compatible_node (NULL ,NULL ,"marvell,armada-370-xp-timer" ); timer_base =of_iomap (np,0 );WARN_ON (!timer_base);
@@ -179,13 +179,14 @@ void __init armada_370_xp_timer_init(void) timer_base + TIMER_CTRL_OFF); timer_clk =25000000 ; }else { -u32 clk =0 ; - ret =of_property_read_u32 (np,"clock-frequency" , &clk); -WARN_ON (!clk || ret <0 ); +unsigned long rate =0 ; +struct clk *clk =of_clk_get (np,0 ); +WARN_ON (IS_ERR (clk)); + rate =clk_get_rate (clk); u =readl (timer_base +TIMER_CTRL_OFF );writel (u & ~(TIMER0_25MHZ |TIMER1_25MHZ ), timer_base +TIMER_CTRL_OFF ); - timer_clk = clk /TIMER_DIVIDER ; + timer_clk = rate /TIMER_DIVIDER ; }/* We use timer 0 as clocksource, and timer 1 for
Signature · 1 line
1.7.9.5
PATCH v2 3/3 clocksource: time-armada-370-xp converted to clk framework
Quoting Gregory CLEMENT (2012-10-01 14:12:06)
Quoted 1 line
Signed-off-by Gregory CLEMENT <[email protected]>
I'm not sure this patch should go through me. Perhaps John Stultz?
Regards,
Mike
PATCH v2 3/3 clocksource: time-armada-370-xp converted to clk framework
Quoted 3 lines · Mike Turquette
Quoting Gregory CLEMENT (2012-10-01 14:12:06)
Quoted 1 line
Signed-off-by Gregory CLEMENT <[email protected]>I'm not sure this patch should go through me. Perhaps John Stultz?
I can apply it to my tree, but really none of it is generic, so in the future I'd almost rather someone who could reasonably audit the changes for correctness merge it instead (although I always appreciate being Cc'ed into the loop).
thanks
-john
v2 cover Add clock framework for armada 370/XP
In reply to Gregory CLEMENTQuoting Gregory CLEMENT (2012-10-01 14:12:03)
Quoted 8 lines
Hello Mike,
My first version didn't get many attention, so I guess it's too late for 3.7! ;) I should have ping you earlier about this series. This time was not lost, by using the cpu clock with SMP I found a bug and fixed it. And I also improved the spelling and removed unnecessary small piece of code thanks to the feed back of Andrew Lunn.
My apologies for letting this one slip through the cracks. I'm glad you fixed the bug though!
I'll give this a review once the -rc1 merge window is closed.
Regards,
Mike
Quoted 65 lines
The purpose of this patch set is to add support for clock framework for Armada 370 and Armada XP SoCs. All the support is done under the directory
drivers/clk/mvebu/as the support for other mvebu SoCs was in mind during the writing of the code.Two kinds of clocks are added:
- The CPU clocks are only for Armada XP (which si multi-core)
- The core clocks are clocks which have their rate fixed during reset.
This patch set is based on the clk-3.7 branch of Mike Turquette as it use the patch "clk: add
of_clk_src_onecell_get()support" from Shawn Guo.Many thanks to Thomas Petazzoni and Sebastian Hesselbarth for their review and feedback. The device tree bindings were really improved with the advices of Sebastian.
Changelog:
V1 -> V2:- Improved the spelling and the wording of the documentation and the 1st commit log
- Removed the "end_of_list" name which are unused here.
- Fix the cpu clock by usingof_clk_src_onecell_getin the same way it was used for the core clocksRegards,
Gregory CLEMENT (3):
clk: mvebu: add armada-370-xp specific clocks
clk: armada-370-xp: add support for clock framework
clocksource: time-armada-370-xp converted to clk framework.../devicetree/bindings/clock/mvebu-core-clock.txt | 40 +++ .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 21 ++ arch/arm/boot/dts/armada-370-db.dts | 4 - arch/arm/boot/dts/armada-370-xp.dtsi | 1 + arch/arm/boot/dts/armada-370.dtsi | 12 + arch/arm/boot/dts/armada-xp.dtsi | 48 +++ arch/arm/mach-mvebu/Kconfig | 5 + arch/arm/mach-mvebu/armada-370-xp.c | 8 +- arch/arm/mach-mvebu/common.h | 1 + drivers/clk/Makefile | 1 + drivers/clk/mvebu/Makefile | 2 + drivers/clk/mvebu/clk-core.c | 312 ++++++++++++++++++++ drivers/clk/mvebu/clk-core.h | 19 ++ drivers/clk/mvebu/clk-cpu.c | 155 ++++++++++ drivers/clk/mvebu/clk-cpu.h | 19 ++ drivers/clk/mvebu/clk.c | 36 +++ drivers/clocksource/time-armada-370-xp.c | 11 +- 17 files changed, 685 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt create mode 100644 drivers/clk/mvebu/Makefile create mode 100644 drivers/clk/mvebu/clk-core.c create mode 100644 drivers/clk/mvebu/clk-core.h create mode 100644 drivers/clk/mvebu/clk-cpu.c create mode 100644 drivers/clk/mvebu/clk-cpu.h create mode 100644 drivers/clk/mvebu/clk.cSignature · 1 line
1.7.9.5
v2 cover Add clock framework for armada 370/XP
Quoted 10 lines · Mike Turquette
Quoting Gregory CLEMENT (2012-10-01 14:12:03)
Quoted 8 lines
Hello Mike,
My first version didn't get many attention, so I guess it's too late for 3.7! ;) I should have ping you earlier about this series. This time was not lost, by using the cpu clock with SMP I found a bug and fixed it. And I also improved the spelling and removed unnecessary small piece of code thanks to the feed back of Andrew Lunn.
Quoted 4 lines
My apologies for letting this one slip through the cracks. I'm glad you fixed the bug though!
I'll give this a review once the -rc1 merge window is closed.
This time I will remind you as soon as -rc1 will be released ;)
I have an other patch set which will depend on this one. So I hope this one will be merged early enough in your clk-3.8 branch.
Regards,
Gregory
Quoted 75 lines
Regards,
MikeQuoted 54 lines
The purpose of this patch set is to add support for clock framework for Armada 370 and Armada XP SoCs. All the support is done under the directory
drivers/clk/mvebu/as the support for other mvebu SoCs was in mind during the writing of the code.Two kinds of clocks are added:
- The CPU clocks are only for Armada XP (which si multi-core)
- The core clocks are clocks which have their rate fixed during reset.
This patch set is based on the clk-3.7 branch of Mike Turquette as it use the patch "clk: add
of_clk_src_onecell_get()support" from Shawn Guo.Many thanks to Thomas Petazzoni and Sebastian Hesselbarth for their review and feedback. The device tree bindings were really improved with the advices of Sebastian.
Changelog:
V1 -> V2:- Improved the spelling and the wording of the documentation and the 1st commit log
- Removed the "end_of_list" name which are unused here.
- Fix the cpu clock by usingof_clk_src_onecell_getin the same way it was used for the core clocksRegards,
Gregory CLEMENT (3):
clk: mvebu: add armada-370-xp specific clocks
clk: armada-370-xp: add support for clock framework
clocksource: time-armada-370-xp converted to clk framework.../devicetree/bindings/clock/mvebu-core-clock.txt | 40 +++ .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 21 ++ arch/arm/boot/dts/armada-370-db.dts | 4 - arch/arm/boot/dts/armada-370-xp.dtsi | 1 + arch/arm/boot/dts/armada-370.dtsi | 12 + arch/arm/boot/dts/armada-xp.dtsi | 48 +++ arch/arm/mach-mvebu/Kconfig | 5 + arch/arm/mach-mvebu/armada-370-xp.c | 8 +- arch/arm/mach-mvebu/common.h | 1 + drivers/clk/Makefile | 1 + drivers/clk/mvebu/Makefile | 2 + drivers/clk/mvebu/clk-core.c | 312 ++++++++++++++++++++ drivers/clk/mvebu/clk-core.h | 19 ++ drivers/clk/mvebu/clk-cpu.c | 155 ++++++++++ drivers/clk/mvebu/clk-cpu.h | 19 ++ drivers/clk/mvebu/clk.c | 36 +++ drivers/clocksource/time-armada-370-xp.c | 11 +- 17 files changed, 685 insertions(+), 10 deletions(-)Quoted 11 lines
create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt create mode 100644 drivers/clk/mvebu/Makefile create mode 100644 drivers/clk/mvebu/clk-core.c create mode 100644 drivers/clk/mvebu/clk-core.h create mode 100644 drivers/clk/mvebu/clk-cpu.c create mode 100644 drivers/clk/mvebu/clk-cpu.h create mode 100644 drivers/clk/mvebu/clk.cSignature · 1 line
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Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com