q35 patches for pci tree

From: Isaku Yamahata <[email protected]>

Factor out smram/pam logic for later use.
Which will be used by q35 too.

[[email protected]: changes for updated memory API]

Signed-off-by Isaku Yamahata <[email protected]>

Signed-off-by Jason Baron <[email protected]>

---
 hw/i386/Makefile.objs |    1 +
 hw/pam.c              |   87 ++++++++++++++++++++++++++++++++++++++++++++
 hw/pam.h              |   97 +++++++++++++++++++++++++++++++++++++++++++++++++
 hw/piix_pci.c         |   68 ++++++++---------------------------
 4 files changed, 200 insertions(+), 53 deletions(-)
 create mode 100644 hw/pam.c
 create mode 100644 hw/pam.h

hw/i386/Makefile.objs +1 -0

index d400d1a..693bd18 100644
@@ -6,6 +6,7 @@ obj-y += pci-hotplug.o smbios.o wdt_ib700.o
 obj-y += debugcon.o multiboot.o
 obj-y += pc_piix.o
 obj-y += pc_sysfw.o
+obj-y += pam.o
 obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o
 obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o
 obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o

hw/pam.c new file +87 -0

new file mode 100644
index 0000000..a95e2cf
@@ -0,0 +1,87 @@
+/*
+ * QEMU i440FX/PIIX3 PCI Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
+ *                    VA Linux Systems Japan K.K.
+ * Copyright (c) 2012 Jason Baron <[email protected]>
+ *
+ * Split out from piix_pci.c
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "sysemu.h"
+#include "pam.h"
+
+void smram_update(MemoryRegion *smram_region, uint8_t smram,
+                  uint8_t smm_enabled)
+{
+    bool smram_enabled;
+
+    smram_enabled = ((smm_enabled && (smram & SMRAM_G_SMRAME)) ||
+                        (smram & SMRAM_D_OPEN));
+    memory_region_set_enabled(smram_region, !smram_enabled);
+}
+
+void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
+                   MemoryRegion *smram_region)
+{
+    uint8_t smm_enabled = (smm != 0);
+    if (*host_smm_enabled != smm_enabled) {
+        *host_smm_enabled = smm_enabled;
+        smram_update(smram_region, smram, *host_smm_enabled);
+    }
+}
+
+void init_pam(MemoryRegion *ram_memory, MemoryRegion *system_memory,
+              MemoryRegion *pci_address_space, PAMMemoryRegion *mem,
+              uint32_t start, uint32_t size)
+{
+    int i;
+
+    /* RAM */
+    memory_region_init_alias(&mem->alias[3], "pam-ram", ram_memory,
+                             start, size);
+    /* ROM (XXX: not quite correct) */
+    memory_region_init_alias(&mem->alias[1], "pam-rom", ram_memory,
+                             start, size);
+    memory_region_set_readonly(&mem->alias[1], true);
+
+    /* XXX: should distinguish read/write cases */
+    memory_region_init_alias(&mem->alias[0], "pam-pci", pci_address_space,
+                             start, size);
+    memory_region_init_alias(&mem->alias[2], "pam-pci", pci_address_space,
+                             start, size);
+
+    for (i = 0; i < 4; ++i) {
+        memory_region_set_enabled(&mem->alias[i], false);
+        memory_region_add_subregion_overlap(system_memory, start,
+                                            &mem->alias[i], 1);
+    }
+    mem->current = 0;
+}
+
+void pam_update(PAMMemoryRegion *pam, int idx, uint8_t val)
+{
+    assert(0 <= idx && idx <= 12);
+
+    memory_region_set_enabled(&pam->alias[pam->current], false);
+    pam->current = (val >> ((!(idx & 1)) * 4)) & PAM_ATTR_MASK;
+    memory_region_set_enabled(&pam->alias[pam->current], true);
+}

hw/pam.h new file +97 -0

new file mode 100644
index 0000000..2d77ebe
@@ -0,0 +1,97 @@
+#ifndef QEMU_PAM_H
+#define QEMU_PAM_H
+
+/*
+ * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
+ *               VA Linux Systems Japan K.K.
+ * Copyright (c) 2012 Jason Baron <[email protected]>
+ *
+ * Split out from piix_pci.c
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/*
+ * SMRAM memory area and PAM memory area in Legacy address range for PC.
+ * PAM: Programmable Attribute Map registers
+ *
+ * 0xa0000 - 0xbffff compatible SMRAM
+ *
+ * 0xc0000 - 0xc3fff Expansion area memory segments
+ * 0xc4000 - 0xc7fff
+ * 0xc8000 - 0xcbfff
+ * 0xcc000 - 0xcffff
+ * 0xd0000 - 0xd3fff
+ * 0xd4000 - 0xd7fff
+ * 0xd8000 - 0xdbfff
+ * 0xdc000 - 0xdffff
+ * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
+ * 0xe4000 - 0xe7fff
+ * 0xe8000 - 0xebfff
+ * 0xec000 - 0xeffff
+ *
+ * 0xf0000 - 0xfffff System BIOS Area Memory Segments
+ */
+
+#include "qemu-common.h"
+#include "memory.h"
+
+#define SMRAM_C_BASE    0xa0000
+#define SMRAM_C_END     0xc0000
+#define SMRAM_C_SIZE    0x20000
+
+#define PAM_EXPAN_BASE  0xc0000
+#define PAM_EXPAN_SIZE  0x04000
+
+#define PAM_EXBIOS_BASE 0xe0000
+#define PAM_EXBIOS_SIZE 0x04000
+
+#define PAM_BIOS_BASE   0xf0000
+#define PAM_BIOS_END    0xfffff
+/* 64KB: Intel 3 series express chipset family p. 58*/
+#define PAM_BIOS_SIZE   0x10000
+
+/* PAM registers: log nibble and high nibble*/
+#define PAM_ATTR_WE     ((uint8_t)2)
+#define PAM_ATTR_RE     ((uint8_t)1)
+#define PAM_ATTR_MASK   ((uint8_t)3)
+
+/* SMRAM register */
+#define SMRAM_D_OPEN           ((uint8_t)(1 << 6))
+#define SMRAM_D_CLS            ((uint8_t)(1 << 5))
+#define SMRAM_D_LCK            ((uint8_t)(1 << 4))
+#define SMRAM_G_SMRAME         ((uint8_t)(1 << 3))
+#define SMRAM_C_BASE_SEG_MASK  ((uint8_t)0x7)
+#define SMRAM_C_BASE_SEG       ((uint8_t)0x2)  /* hardwired to b010 */
+
+typedef struct PAMMemoryRegion {
+    MemoryRegion alias[4];  /* index = PAM value */
+    unsigned current;
+} PAMMemoryRegion;
+
+void smram_update(MemoryRegion *smram_region, uint8_t smram,
+                  uint8_t smm_enabled);
+void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
+                   MemoryRegion *smram_region);
+void init_pam(MemoryRegion *ram, MemoryRegion *system, MemoryRegion *pci,
+              PAMMemoryRegion *mem, uint32_t start, uint32_t size);
+void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val);
+
+#endif /* QEMU_PAM_H */

hw/piix_pci.c +15 -53

index 9af5847..ba1b3de 100644
@@ -30,6 +30,7 @@
 #include "sysbus.h"
 #include "range.h"
 #include "xen.h"
+#include "pam.h"
 
 /*
  * I440FX chipset data sheet.

@@ -68,11 +69,6 @@ typedef struct PIIX3State {
     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
 } PIIX3State;
 
-typedef struct PAMMemoryRegion {
-    MemoryRegion alias[4];  /* index = PAM value */
-    unsigned current;
-} PAMMemoryRegion;
-
 struct PCII440FXState {
     PCIDevice dev;
     MemoryRegion *system_memory;

@@ -105,52 +101,16 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
     return (pci_intx + slot_addend) & 3;
 }
 
-static void init_pam(PCII440FXState *d, PAMMemoryRegion *mem,
-                     uint32_t start, uint32_t size)
-{
-    int i;
-
-    /* RAM */
-    memory_region_init_alias(&mem->alias[3], "pam-ram", d->ram_memory, start, size);
-    /* ROM (XXX: not quite correct) */
-    memory_region_init_alias(&mem->alias[1], "pam-rom", d->ram_memory, start, size);
-    memory_region_set_readonly(&mem->alias[1], true);
-
-    /* XXX: should distinguish read/write cases */
-    memory_region_init_alias(&mem->alias[0], "pam-pci", d->pci_address_space,
-                             start, size);
-    memory_region_init_alias(&mem->alias[2], "pam-pci", d->pci_address_space,
-                             start, size);
-
-    for (i = 0; i < 4; ++i) {
-        memory_region_set_enabled(&mem->alias[i], false);
-        memory_region_add_subregion_overlap(d->system_memory, start, &mem->alias[i], 1);
-    }
-    mem->current = 0;
-}
-
-static void update_pam(PAMMemoryRegion *pam, unsigned r)
-{
-    memory_region_set_enabled(&pam->alias[pam->current], false);
-    pam->current = r;
-    memory_region_set_enabled(&pam->alias[pam->current], true);
-}
-
 static void i440fx_update_memory_mappings(PCII440FXState *d)
 {
-    int i, r;
-    uint32_t smram;
-    bool smram_enabled;
+    int i;
 
     memory_region_transaction_begin();
-    update_pam(&d->pam_regions[0], (d->dev.config[I440FX_PAM] >> 4) & 3);
-    for(i = 0; i < 12; i++) {
-        r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
-        update_pam(&d->pam_regions[i+1], r);
+    for (i = 0; i < 13; i++) {
+        pam_update(&d->pam_regions[i], i,
+                   d->dev.config[I440FX_PAM + ((i + 1) / 2)]);
     }
-    smram = d->dev.config[I440FX_SMRAM];
-    smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40);
-    memory_region_set_enabled(&d->smram_region, !smram_enabled);
+    smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
     memory_region_transaction_commit();
 }
 

@@ -158,11 +118,10 @@ static void i440fx_set_smm(int val, void *arg)
 {
     PCII440FXState *d = arg;
 
-    val = (val != 0);
-    if (d->smm_enabled != val) {
-        d->smm_enabled = val;
-        i440fx_update_memory_mappings(d);
-    }
+    memory_region_transaction_begin();
+    smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
+                  &d->smram_region);
+    memory_region_transaction_commit();
 }
 
 

@@ -300,9 +259,12 @@ static PCIBus *i440fx_common_init(const char *device_name,
     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
                                         &f->smram_region, 1);
     memory_region_set_enabled(&f->smram_region, false);
-    init_pam(f, &f->pam_regions[0], 0xf0000, 0x10000);
+    init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
+             &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
     for (i = 0; i < 12; ++i) {
-        init_pam(f, &f->pam_regions[i+1], 0xc0000 + i * 0x4000, 0x4000);
+        init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
+                 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
+                 PAM_EXPAN_SIZE);
     }
 
     /* Xen supports additional interrupt routes from the PCI devices to

Signature · 1 line

1.7.1

Quoted 8 lines · Jason Baron

From: Isaku Yamahata <[email protected]>

Factor out smram/pam logic for later use.
Which will be used by q35 too.

[[email protected]: changes for updated memory API]

Signed-off-by Isaku Yamahata <[email protected]>

Signed-off-by Jason Baron <[email protected]>

This is really not the right approach to solving this problem.

"pam" is not a device.

Instead, the common bits here are essentially the northbridge logic. That's what we should model here.

It's pretty simple actually. Just throw this all into a device where the memory regions are owned by the device. But also make the device own creation of all RAM (not just the areas controlled by PAM).

Then embed the northbridge into the i440fx and q35.

From: Jason Baron <[email protected]>

As pointed out by Andreas Färber this is covered by dec_pci.c.

Signed-off-by Jason Baron <[email protected]>

---
 hw/Makefile.objs |    2 +-
 hw/i21154.c      |  113 ------------------------------------------------------
 hw/i21154.h      |    9 ----
 3 files changed, 1 insertions(+), 123 deletions(-)
 delete mode 100644 hw/i21154.c
 delete mode 100644 hw/i21154.h

hw/Makefile.objs +1 -1

index e951eba..a816e7e 100644
@@ -9,7 +9,7 @@ common-obj-$(CONFIG_PCI) += shpc.o
 common-obj-$(CONFIG_PCI) += slotid_cap.o
 common-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
 common-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
-common-obj-$(CONFIG_PCI) += i82801b11.o i21154.o
+common-obj-$(CONFIG_PCI) += i82801b11.o
 common-obj-y += watchdog.o
 common-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o
 common-obj-$(CONFIG_ECC) += ecc.o

hw/i21154.c deleted +0 -113

deleted file mode 100644
index 93faa59..0000000
@@ -1,113 +0,0 @@
-/*
- * Copyright (c) 2006 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-/*
- * QEMU i21154 PCI Bridge Emulation
- *
- *  Copyright (c) 2009, 2010, 2011
- *                Isaku Yamahata <yamahata at valinux co jp>
- *                VA Linux Systems Japan K.K.
- *  Copyright (C) 2012 Jason Baron <[email protected]>
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>
- */
-
-#include "i21154.h"
-#include "pci_ids.h"
-#include "pci.h"
-#include "pci_bridge.h"
-#include "pci_internals.h"
-
-/* i21154 pci bridge*/
-
-typedef struct I21154Bridge {
-    PCIBridge br;
-} I21154Bridge;
-
-static int i21154_bridge_initfn(PCIDevice *d)
-{
-    int rc;
-
-    rc = pci_bridge_initfn(d);
-    if (rc < 0) {
-        return rc;
-    }
-
-    return 0;
-}
-
-#define I21154_REV            0x05
-#define I21154_PI             0x00
-
-static void i21154_bridge_class_init(ObjectClass *klass, void *data)
-{
-    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
-    k->is_bridge = 1;
-    k->vendor_id = PCI_VENDOR_ID_DEC;
-    k->device_id = PCI_DEVICE_ID_DEC_21154;
-    k->revision = I21154_REV;
-    k->init = i21154_bridge_initfn;
-}
-
-static const TypeInfo i21154_bridge_info = {
-    .name          = "i21154-bridge",
-    .parent        = TYPE_PCI_DEVICE,
-    .instance_size = sizeof(I21154Bridge),
-    .class_init    = i21154_bridge_class_init,
-};
-
-PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
-                              bool multifunction)
-{
-    PCIDevice *d;
-    PCIBridge *br;
-    DeviceState *qdev;
-
-    d = pci_create_multifunction(bus, devfn, multifunction, "i21154-bridge");
-    if (!d) {
-        return NULL;
-    }
-    br = DO_UPCAST(PCIBridge, dev, d);
-    qdev = &br->dev.qdev;
-
-    pci_bridge_map_irq(br, bus_name, pci_swizzle_map_irq_fn);
-    qdev_init_nofail(qdev);
-
-    return br;
-}
-
-static void i21154_register(void)
-{
-    type_register_static(&i21154_bridge_info);
-}
-type_init(i21154_register);

hw/i21154.h deleted +0 -9

deleted file mode 100644
index 0cf8753..0000000
@@ -1,9 +0,0 @@
-#ifndef QEMU_I21154_H
-#define QEMU_I21154_H
-
-#include "pci.h"
-
-PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
-                              bool multifunction);
-
-#endif /* QEMU_I21154_H */

Signature · 1 line

1.7.1

From: Jason Baron <[email protected]>

The current QEMUMachine definition has a 'use_scsi' field to indicate if a machine type should use scsi by default. However, Q35 wants to use ahci by default. Thus, introdue a new field in the QEMUMachine defintion, default_drive_if.

Please use 'static inline int get_default_drive_if(int default_drive_if)', when accesssing the new default_drive_if field. The field should be initialized by the machine type to the default interface type which it wants to use (IF_SCSI, IF_AHCI, etc.). If no default_drive_if is specified, we assume IF_IDE. In the future, we should go through all of the machines types and explicitly define their desired default interface, thus eliminating the need for get_default_drive_if() interface.

Reviewed-by Paolo Bonzini <[email protected]>

Signed-off-by Jason Baron <[email protected]>

---
 blockdev.c          |    4 ++--
 blockdev.h          |   20 ++++++++++++++++++++
 hw/boards.h         |    2 +-
 hw/device-hotplug.c |    2 +-
 hw/highbank.c       |    2 +-
 hw/leon3.c          |    1 -
 hw/mips_jazz.c      |    4 ++--
 hw/pc_sysfw.c       |    2 +-
 hw/puv3.c           |    1 -
 hw/realview.c       |    6 +++---
 hw/spapr.c          |    2 +-
 hw/sun4m.c          |   24 ++++++++++++------------
 hw/versatilepb.c    |    4 ++--
 hw/vexpress.c       |    4 ++--
 hw/xilinx_zynq.c    |    2 +-
 vl.c                |   20 +++++++++++---------
 16 files changed, 60 insertions(+), 40 deletions(-)

blockdev.c +2 -2

index 99828ad..2977e2f 100644
@@ -275,7 +275,7 @@ static bool do_check_io_limits(BlockIOLimit *io_limits)
     return true;
 }
 
-DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
+DriveInfo *drive_init(QemuOpts *opts, BlockInterfaceType default_drive_if)
 {
     const char *buf;
     const char *file = NULL;

@@ -325,7 +325,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
             return NULL;
 	}
     } else {
-        type = default_to_scsi ? IF_SCSI : IF_IDE;
+        type = get_default_drive_if(default_drive_if);
     }
 
     max_devs = if_max_devs[type];

blockdev.h +20 -0

index 5f27b64..658380d 100644
@@ -40,6 +40,26 @@ struct DriveInfo {
     int refcount;
 };
 
+/*
+ * Each qemu machine type defines a default_drive_if field for its default
+ * interface type. When accessing the default_drive_if field, please make use
+ * of get_default_drive_if(). If default_drive_if is unspecified, we set it to
+ * IF_IDE.
+ *
+ * Left as a 'todo': We should convert those that are unspecified to their
+ * proper default values, thus eliminating the need for get_default_drive_if().
+ */
+static inline int get_default_drive_if(int default_drive_if)
+{
+    assert(default_drive_if < IF_COUNT);
+    assert(default_drive_if >= IF_NONE);
+
+    if (default_drive_if == 0) {
+        return IF_IDE;
+    }
+    return default_drive_if;
+}
+
 DriveInfo *drive_get(BlockInterfaceType type, int bus, int unit);
 DriveInfo *drive_get_by_index(BlockInterfaceType type, int index);
 int drive_get_max_bus(BlockInterfaceType type);

hw/boards.h +1 -1

index 813d0e5..cd3f79f 100644
@@ -24,7 +24,7 @@ typedef struct QEMUMachine {
     const char *desc;
     QEMUMachineInitFunc *init;
     QEMUMachineResetFunc *reset;
-    int use_scsi;
+    int default_drive_if;
     int max_cpus;
     unsigned int no_serial:1,
         no_parallel:1,

hw/device-hotplug.c +1 -1

index eec0fe3..53ee6c3 100644
@@ -39,7 +39,7 @@ DriveInfo *add_init_drive(const char *optstr)
     if (!opts)
         return NULL;
 
-    dinfo = drive_init(opts, current_machine->use_scsi);
+    dinfo = drive_init(opts, current_machine->default_drive_if);
     if (!dinfo) {
         qemu_opts_del(opts);
         return NULL;

hw/highbank.c +1 -1

index afbb005..03ae3d8 100644
@@ -326,7 +326,7 @@ static QEMUMachine highbank_machine = {
     .name = "highbank",
     .desc = "Calxeda Highbank (ECX-1000)",
     .init = highbank_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
     .max_cpus = 4,
 };
 

hw/leon3.c +0 -1

index 7742738..ef83dff 100644
@@ -212,7 +212,6 @@ static QEMUMachine leon3_generic_machine = {
     .name     = "leon3_generic",
     .desc     = "Leon-3 generic",
     .init     = leon3_generic_hw_init,
-    .use_scsi = 0,
 };
 
 static void leon3_machine_init(void)

hw/mips_jazz.c +2 -2

index 0847427..f72358c 100644
@@ -324,14 +324,14 @@ static QEMUMachine mips_magnum_machine = {
     .name = "magnum",
     .desc = "MIPS Magnum",
     .init = mips_magnum_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
 };
 
 static QEMUMachine mips_pica61_machine = {
     .name = "pica61",
     .desc = "Acer Pica 61",
     .init = mips_pica61_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
 };
 
 static void mips_jazz_machine_init(void)

hw/pc_sysfw.c +1 -1

index 9d7c5f4..b294f91 100644
@@ -98,7 +98,7 @@ static void pc_fw_add_pflash_drv(void)
       return;
     }
 
-    drive_init(opts, machine->use_scsi);
+    drive_init(opts, machine->default_drive_if);
 }
 
 static void pc_system_flash_init(MemoryRegion *rom_memory,

hw/puv3.c +0 -1

index 764799c..3d77349 100644
@@ -122,7 +122,6 @@ static QEMUMachine puv3_machine = {
     .desc = "PKUnity Version-3 based on UniCore32",
     .init = puv3_init,
     .is_default = 1,
-    .use_scsi = 0,
 };
 
 static void puv3_machine_init(void)

hw/realview.c +3 -3

index b5cb08c..129c181 100644
@@ -394,14 +394,14 @@ static QEMUMachine realview_eb_machine = {
     .name = "realview-eb",
     .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
     .init = realview_eb_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
 };
 
 static QEMUMachine realview_eb_mpcore_machine = {
     .name = "realview-eb-mpcore",
     .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
     .init = realview_eb_mpcore_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
     .max_cpus = 4,
 };
 

@@ -415,7 +415,7 @@ static QEMUMachine realview_pbx_a9_machine = {
     .name = "realview-pbx-a9",
     .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
     .init = realview_pbx_a9_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
     .max_cpus = 4,
 };
 

hw/spapr.c +1 -1

index 8d0ad3c..ee5346b 100644
@@ -924,7 +924,7 @@ static QEMUMachine spapr_machine = {
     .reset = ppc_spapr_reset,
     .max_cpus = MAX_CPUS,
     .no_parallel = 1,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
 };
 
 static void spapr_machine_init(void)

hw/sun4m.c +12 -12

index 02673b2..dc2a7c1 100644
@@ -1426,7 +1426,7 @@ static QEMUMachine ss5_machine = {
     .name = "SS-5",
     .desc = "Sun4m platform, SPARCstation 5",
     .init = ss5_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
     .is_default = 1,
 };
 

@@ -1434,7 +1434,7 @@ static QEMUMachine ss10_machine = {
     .name = "SS-10",
     .desc = "Sun4m platform, SPARCstation 10",
     .init = ss10_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
     .max_cpus = 4,
 };
 

@@ -1442,7 +1442,7 @@ static QEMUMachine ss600mp_machine = {
     .name = "SS-600MP",
     .desc = "Sun4m platform, SPARCserver 600MP",
     .init = ss600mp_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
     .max_cpus = 4,
 };
 

@@ -1450,7 +1450,7 @@ static QEMUMachine ss20_machine = {
     .name = "SS-20",
     .desc = "Sun4m platform, SPARCstation 20",
     .init = ss20_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
     .max_cpus = 4,
 };
 

@@ -1458,35 +1458,35 @@ static QEMUMachine voyager_machine = {
     .name = "Voyager",
     .desc = "Sun4m platform, SPARCstation Voyager",
     .init = vger_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
 };
 
 static QEMUMachine ss_lx_machine = {
     .name = "LX",
     .desc = "Sun4m platform, SPARCstation LX",
     .init = ss_lx_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
 };
 
 static QEMUMachine ss4_machine = {
     .name = "SS-4",
     .desc = "Sun4m platform, SPARCstation 4",
     .init = ss4_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
 };
 
 static QEMUMachine scls_machine = {
     .name = "SPARCClassic",
     .desc = "Sun4m platform, SPARCClassic",
     .init = scls_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
 };
 
 static QEMUMachine sbook_machine = {
     .name = "SPARCbook",
     .desc = "Sun4m platform, SPARCbook",
     .init = sbook_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
 };
 
 static const struct sun4d_hwdef sun4d_hwdefs[] = {

@@ -1709,7 +1709,7 @@ static QEMUMachine ss1000_machine = {
     .name = "SS-1000",
     .desc = "Sun4d platform, SPARCserver 1000",
     .init = ss1000_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
     .max_cpus = 8,
 };
 

@@ -1717,7 +1717,7 @@ static QEMUMachine ss2000_machine = {
     .name = "SS-2000",
     .desc = "Sun4d platform, SPARCcenter 2000",
     .init = ss2000_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
     .max_cpus = 20,
 };
 

@@ -1896,7 +1896,7 @@ static QEMUMachine ss2_machine = {
     .name = "SS-2",
     .desc = "Sun4c platform, SPARCstation 2",
     .init = ss2_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
 };
 
 static void sun4m_register_types(void)

hw/versatilepb.c +2 -2

index e85f982..86c18aa 100644
@@ -380,14 +380,14 @@ static QEMUMachine versatilepb_machine = {
     .name = "versatilepb",
     .desc = "ARM Versatile/PB (ARM926EJ-S)",
     .init = vpb_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
 };
 
 static QEMUMachine versatileab_machine = {
     .name = "versatileab",
     .desc = "ARM Versatile/AB (ARM926EJ-S)",
     .init = vab_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
 };
 
 static void versatile_machine_init(void)

hw/vexpress.c +2 -2

index 3f7cb66..8fb9905 100644
@@ -497,7 +497,7 @@ static QEMUMachine vexpress_a9_machine = {
     .name = "vexpress-a9",
     .desc = "ARM Versatile Express for Cortex-A9",
     .init = vexpress_a9_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
     .max_cpus = 4,
 };
 

@@ -505,7 +505,7 @@ static QEMUMachine vexpress_a15_machine = {
     .name = "vexpress-a15",
     .desc = "ARM Versatile Express for Cortex-A15",
     .init = vexpress_a15_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
     .max_cpus = 4,
 };
 

hw/xilinx_zynq.c +1 -1

index c55dafb..a4f2c1b 100644
@@ -181,7 +181,7 @@ static QEMUMachine zynq_machine = {
     .name = "xilinx-zynq-a9",
     .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
     .init = zynq_init,
-    .use_scsi = 1,
+    .default_drive_if = IF_SCSI,
     .max_cpus = 1,
     .no_sdcard = 1
 };

vl.c +11 -9

index 6dd767c..824d8ae 100644
@@ -812,9 +812,9 @@ bool usb_enabled(bool default_usb)
 
 static int drive_init_func(QemuOpts *opts, void *opaque)
 {
-    int *use_scsi = opaque;
+    int *default_drive_if = opaque;
 
-    return drive_init(opts, *use_scsi) == NULL;
+    return drive_init(opts, *default_drive_if) == NULL;
 }
 
 static int drive_enable_snapshot(QemuOpts *opts, void *opaque)

@@ -825,14 +825,14 @@ static int drive_enable_snapshot(QemuOpts *opts, void *opaque)
     return 0;
 }
 
-static void default_drive(int enable, int snapshot, int use_scsi,
+static void default_drive(int enable, int snapshot, int default_drive_if,
                           BlockInterfaceType type, int index,
                           const char *optstr)
 {
     QemuOpts *opts;
 
     if (type == IF_DEFAULT) {
-        type = use_scsi ? IF_SCSI : IF_IDE;
+        type = get_default_drive_if(default_drive_if);
     }
 
     if (!enable || drive_get_by_index(type, index)) {

@@ -843,7 +843,7 @@ static void default_drive(int enable, int snapshot, int use_scsi,
     if (snapshot) {
         drive_enable_snapshot(opts, NULL);
     }
-    if (!drive_init(opts, use_scsi)) {
+    if (!drive_init(opts, default_drive_if)) {
         exit(1);
     }
 }

@@ -3565,14 +3565,16 @@ int main(int argc, char **argv, char **envp)
     /* open the virtual block devices */
     if (snapshot)
         qemu_opts_foreach(qemu_find_opts("drive"), drive_enable_snapshot, NULL, 0);
-    if (qemu_opts_foreach(qemu_find_opts("drive"), drive_init_func, &machine->use_scsi, 1) != 0)
+    if (qemu_opts_foreach(qemu_find_opts("drive"), drive_init_func,
+                          &machine->default_drive_if, 1) != 0) {
         exit(1);
+    }
 
-    default_drive(default_cdrom, snapshot, machine->use_scsi,
+    default_drive(default_cdrom, snapshot, machine->default_drive_if,
                   IF_DEFAULT, 2, CDROM_OPTS);
-    default_drive(default_floppy, snapshot, machine->use_scsi,
+    default_drive(default_floppy, snapshot, machine->default_drive_if,
                   IF_FLOPPY, 0, FD_OPTS);
-    default_drive(default_sdcard, snapshot, machine->use_scsi,
+    default_drive(default_sdcard, snapshot, machine->default_drive_if,
                   IF_SD, 0, SD_OPTS);
 
     register_savevm_live(NULL, "ram", 0, 4, &savevm_ram_handlers, NULL);

Signature · 1 line

1.7.1

From: Isaku Yamahata <[email protected]>

Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code duplication of q35 pc initialization.

Reviewed-by Paolo Bonzini <[email protected]>

Signed-off-by Isaku Yamahata <[email protected]>

Signed-off-by Jason Baron <[email protected]>

---
 hw/pc.c      |   15 +++++++++++++++
 hw/pc.h      |    1 +
 hw/pc_piix.c |    9 +--------
 3 files changed, 17 insertions(+), 8 deletions(-)

hw/pc.c +15 -0

index a02b397..cb7fa68 100644
@@ -1104,6 +1104,21 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
     *floppy = fdctrl_init_isa(isa_bus, fd);
 }
 
+void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
+{
+    int i;
+
+    for (i = 0; i < nb_nics; i++) {
+        NICInfo *nd = &nd_table[i];
+
+        if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
+            pc_init_ne2k_isa(isa_bus, nd);
+        } else {
+            pci_nic_init_nofail(nd, "e1000", NULL);
+        }
+    }
+}
+
 void pc_pci_device_init(PCIBus *pci_bus)
 {
     int max_bus;

hw/pc.h +1 -0

index e7993ca..d6639a6 100644
@@ -98,6 +98,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
                   const char *boot_device,
                   ISADevice *floppy, BusState *ide0, BusState *ide1,
                   ISADevice *s);
+void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
 void pc_pci_device_init(PCIBus *pci_bus);
 
 typedef void (*cpu_set_smm_t)(int smm, void *arg);

hw/pc_piix.c +1 -8

index 85529b2..acb1e92 100644
@@ -234,14 +234,7 @@ static void pc_init1(MemoryRegion *system_memory,
     /* init basic PC hardware */
     pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, xen_enabled());
 
-    for(i = 0; i < nb_nics; i++) {
-        NICInfo *nd = &nd_table[i];
-
-        if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
-            pc_init_ne2k_isa(isa_bus, nd);
-        else
-            pci_nic_init_nofail(nd, "e1000", NULL);
-    }
+    pc_nic_init(isa_bus, pci_bus);
 
     ide_drive_get(hd, MAX_IDE_BUS);
     if (pci_enabled) {

Signature · 1 line

1.7.1

From: Isaku Yamahata <[email protected]>

Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code duplication of q35 pc initialization.

Reviewed-by Paolo Bonzini <[email protected]>

Signed-off-by Isaku Yamahata <[email protected]>

Signed-off-by Jason Baron <[email protected]>

---
 hw/pc.c      |   15 +++++++++++++++
 hw/pc.h      |    1 +
 hw/pc_piix.c |    9 +--------
 3 files changed, 17 insertions(+), 8 deletions(-)

hw/pc.c +15 -0

index a02b397..cb7fa68 100644
@@ -1104,6 +1104,21 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
     *floppy = fdctrl_init_isa(isa_bus, fd);
 }
 
+void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
+{
+    int i;
+
+    for (i = 0; i < nb_nics; i++) {
+        NICInfo *nd = &nd_table[i];
+
+        if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
+            pc_init_ne2k_isa(isa_bus, nd);
+        } else {
+            pci_nic_init_nofail(nd, "e1000", NULL);
+        }
+    }
+}
+
 void pc_pci_device_init(PCIBus *pci_bus)
 {
     int max_bus;

hw/pc.h +1 -0

index e7993ca..d6639a6 100644
@@ -98,6 +98,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
                   const char *boot_device,
                   ISADevice *floppy, BusState *ide0, BusState *ide1,
                   ISADevice *s);
+void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
 void pc_pci_device_init(PCIBus *pci_bus);
 
 typedef void (*cpu_set_smm_t)(int smm, void *arg);

hw/pc_piix.c +1 -8

index 85529b2..acb1e92 100644
@@ -234,14 +234,7 @@ static void pc_init1(MemoryRegion *system_memory,
     /* init basic PC hardware */
     pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, xen_enabled());
 
-    for(i = 0; i < nb_nics; i++) {
-        NICInfo *nd = &nd_table[i];
-
-        if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
-            pc_init_ne2k_isa(isa_bus, nd);
-        else
-            pci_nic_init_nofail(nd, "e1000", NULL);
-    }
+    pc_nic_init(isa_bus, pci_bus);
 
     ide_drive_get(hd, MAX_IDE_BUS);
     if (pci_enabled) {

Signature · 1 line

1.7.1

From: Jason Baron <[email protected]>

Move ioapic_init from pc_piix.c to pc.c, to make it a common function. Rename ioapic_init -> ioapic_init_gsi.

Reviewed-by Paolo Bonzini <[email protected]>

Signed-off-by Jason Baron <[email protected]>

---
 hw/pc.c      |   24 ++++++++++++++++++++++++
 hw/pc.h      |    2 ++
 hw/pc_piix.c |   25 +------------------------
 3 files changed, 27 insertions(+), 24 deletions(-)

hw/pc.c +24 -0

index cb7fa68..af1a076 100644
@@ -1129,3 +1129,27 @@ void pc_pci_device_init(PCIBus *pci_bus)
         pci_create_simple(pci_bus, -1, "lsi53c895a");
     }
 }
+
+void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
+{
+    DeviceState *dev;
+    SysBusDevice *d;
+    unsigned int i;
+
+    if (kvm_irqchip_in_kernel()) {
+        dev = qdev_create(NULL, "kvm-ioapic");
+    } else {
+        dev = qdev_create(NULL, "ioapic");
+    }
+    if (parent_name) {
+        object_property_add_child(object_resolve_path(parent_name, NULL),
+                                  "ioapic", OBJECT(dev), NULL);
+    }
+    qdev_init_nofail(dev);
+    d = sysbus_from_qdev(dev);
+    sysbus_mmio_map(d, 0, 0xfec00000);
+
+    for (i = 0; i < IOAPIC_NUM_PINS; i++) {
+        gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
+    }
+}

hw/pc.h +2 -0

index d6639a6..2237e86 100644
@@ -104,6 +104,8 @@ void pc_pci_device_init(PCIBus *pci_bus);
 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 void cpu_smm_register(cpu_set_smm_t callback, void *arg);
 
+void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
+
 /* acpi.c */
 extern int acpi_enabled;
 extern char *acpi_tables;

hw/pc_piix.c +1 -24

index acb1e92..7bcac87 100644
@@ -95,29 +95,6 @@ static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
     }
 }
 
-static void ioapic_init(GSIState *gsi_state)
-{
-    DeviceState *dev;
-    SysBusDevice *d;
-    unsigned int i;
-
-    if (kvm_irqchip_in_kernel()) {
-        dev = qdev_create(NULL, "kvm-ioapic");
-    } else {
-        dev = qdev_create(NULL, "ioapic");
-    }
-    /* FIXME: this should be under the piix3.  */
-    object_property_add_child(object_resolve_path("i440fx", NULL),
-                              "ioapic", OBJECT(dev), NULL);
-    qdev_init_nofail(dev);
-    d = sysbus_from_qdev(dev);
-    sysbus_mmio_map(d, 0, 0xfec00000);
-
-    for (i = 0; i < IOAPIC_NUM_PINS; i++) {
-        gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
-    }
-}
-
 /* PC hardware initialisation */
 static void pc_init1(MemoryRegion *system_memory,
                      MemoryRegion *system_io,

@@ -221,7 +198,7 @@ static void pc_init1(MemoryRegion *system_memory,
         gsi_state->i8259_irq[i] = i8259[i];
     }
     if (pci_enabled) {
-        ioapic_init(gsi_state);
+        ioapic_init_gsi(gsi_state, "i440fx");
     }
 
     pc_register_ferr_irq(gsi[13]);

Signature · 1 line

1.7.1

From: Isaku Yamahata <[email protected]>

pc q35 based chipset emulator to support pci express natively. Based on Anthony Liguori's suggestion, the machine name is 'q35-next', with an alias of 'q35'. At this point, there are no compatibility guarantees. When the chipset stabilizes more, we will begin to version the machine names.

Major features which still need to be added:

(quoted diff) +0 -3

-Migration support (mostly around ahci)
-ACPI hotplug support (pcie hotplug support is working)
-Passthrough support

Signed-off-by Isaku Yamahata <[email protected]>

Signed-off-by Jason Baron <[email protected]>

---
 hw/i386/Makefile.objs |    2 +-
 hw/pc.h               |    2 +
 hw/pc_piix.c          |    4 +-
 hw/pc_q35.c           |  326 +++++++++++++++++++++++++++++++++++++++++++++++++
 hw/pci_ids.h          |    2 +
 hw/q35.c              |  315 +++++++++++++++++++++++++++++++++++++++++++++++
 hw/q35.h              |  161 ++++++++++++++++++++++++
 7 files changed, 809 insertions(+), 3 deletions(-)
 create mode 100644 hw/pc_q35.c
 create mode 100644 hw/q35.c
 create mode 100644 hw/q35.h

hw/i386/Makefile.objs +0 -0

index 693bd18..469b127 100644

hw/pc.h +0 -0

 /* Global System Interrupts */
 

hw/pc_piix.c +2 -2

index 7bcac87..26565a1 100644
@@ -54,7 +54,7 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
 static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
 static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
 
-static void kvm_piix3_setup_irq_routing(bool pci_enabled)
+void kvm_piix3_setup_irq_routing(bool pci_enabled)
 {
 #ifdef CONFIG_KVM
     KVMState *s = kvm_state;

@@ -83,7 +83,7 @@ static void kvm_piix3_setup_irq_routing(bool pci_enabled)
 #endif /* CONFIG_KVM */
 }
 
-static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
+void kvm_piix3_gsi_handler(void *opaque, int n, int level)
 {
     GSIState *s = opaque;
 

hw/pc_q35.c new file +28 -0

new file mode 100644
index 0000000..cf0d361
@@ -0,0 +1,326 @@
+/*
+ * Q35 chipset based pc system emulator
+ *
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ * Copyright (c) 2009, 2010
+ *               Isaku Yamahata <yamahata at valinux co jp>
+ *               VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <[email protected]>
+ *
+ * This is based on pc.c, but heavily modified.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.

hw/pc_q35.c new file +12 -0

+#include "block.h"
+#include "blockdev.h"
+#include "sysemu.h"
+#include "audio/audio.h"
+#include "net.h"
+#include "smbus.h"
+#include "boards.h"
+#include "monitor.h"
+#include "fw_cfg.h"
+#include "hpet_emul.h"
+#include "watchdog.h"
+#include "smbios.h"

hw/pc_q35.c new file +24 -0

+
+/* ICH9 AHCI has 6 ports */
+#define MAX_SATA_PORTS     6
+
+static void pc_q35_init_early(qemu_irq *gsi, GSIState *gsi_state,
+                              DeviceState **gmch_host_p,
+                              PCIBus **host_bus_p,
+                              PCIDevice **lpc_p, ISABus **isa_bus,
+                              MemoryRegion *system_memory,
+                              MemoryRegion *pci_address_space,
+                              MemoryRegion *address_space_io,
+                              MemoryRegion *ram_memory,
+                              ram_addr_t below_4g_mem_size,
+                              ram_addr_t above_4g_mem_size)
+{
+    int i;
+    hwaddr pci_hole64_size;
+    DeviceState *gmch_host;
+    PCIBus *host_bus;
+
+    PCIDevice *gmch_state;
+    PCIDevice *lpc;
+    GMCHPCIState *gmps;
+    ICH9LPCState *ich9_lpc;

hw/pc_q35.c new file +127 -0

+    ich9_lpc = ICH9_LPC_DEVICE(lpc);
+    ich9_lpc->pic = gsi;
+    ich9_lpc->ioapic = gsi_state->ioapic_irq;
+    pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
+                 ICH9_LPC_NB_PIRQS);
+
+    gmps->ram_memory = ram_memory;
+    gmps->pci_address_space = pci_address_space;
+    gmps->system_memory = system_memory;
+    /* pci */
+    memory_region_init_alias(&gmps->pci_hole, "pci-hole",
+                             gmps->pci_address_space,
+                             below_4g_mem_size,
+                             0x100000000ULL - below_4g_mem_size);
+    memory_region_add_subregion(gmps->system_memory, below_4g_mem_size,
+                                &gmps->pci_hole);
+    pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 :
+                                            ((uint64_t)1 << 62));
+    memory_region_init_alias(&gmps->pci_hole_64bit, "pci-hole64",
+                             gmps->pci_address_space,
+                             0x100000000ULL + above_4g_mem_size,
+                             pci_hole64_size);
+    if (pci_hole64_size) {
+        memory_region_add_subregion(gmps->system_memory,
+                                    0x100000000ULL + above_4g_mem_size,
+                                    &gmps->pci_hole_64bit);
+    }
+
+    /* smram */
+    memory_region_init_alias(&gmps->smram_region, "smram-region",
+                             pci_address_space, 0xa0000, 0x20000);
+    memory_region_add_subregion_overlap(system_memory, 0xa0000,
+                                        &gmps->smram_region, 1);
+    memory_region_set_enabled(&gmps->smram_region, false);
+    init_pam(gmps->ram_memory, gmps->system_memory, gmps->pci_address_space,
+             &gmps->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
+    for (i = 0; i < 12; ++i) {
+        init_pam(gmps->ram_memory, gmps->system_memory, gmps->pci_address_space,
+                 &gmps->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
+                 PAM_EXPAN_SIZE);
+    }
+
+    *gmch_host_p = gmch_host;
+    *host_bus_p = host_bus;
+    *lpc_p = lpc;
+    *isa_bus = ich9_lpc->isa_bus;
+}
+
+
+/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
+ *    BIOS will read it and start S3 resume at POST Entry */
+static void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
+{
+    ISADevice *s = opaque;
+
+    if (level) {
+        rtc_set_memory(s, 0xF, 0xFE);
+    }
+}
+
+static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
+                             DeviceState *gmch_host, PCIBus *host_bus,
+                             PCIDevice *lpc)
+{
+    qemu_irq *cmos_s3;
+    PCIDevice *ahci;
+    DriveInfo **hd;
+    struct AHCIPCIState *ahci_state;
+    int ports, max_unit, max_bus;
+
+    /* connect pm stuff to lpc */
+    cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
+    ich9_lpc_pm_init(lpc, *cmos_s3);
+
+    /* ahci and SATA device, for q35 1 ahci controller is built-in */
+    ahci = pci_create_simple_multifunction(host_bus,
+                                           PCI_DEVFN(ICH9_SATA1_DEV,
+                                                     ICH9_SATA1_FUNC),
+                                           true, "ich9-ahci");
+    ahci_state = DO_UPCAST(struct AHCIPCIState, card, ahci);
+    ports = ahci_state->ahci.ports;
+    max_unit = drive_get_max_unit(IF_AHCI);
+    if (max_unit >= ports) {
+        fprintf(stderr, "%d ports are available on the host ahci controller.\n"
+                        "Ignoring extra assignments.\n", ports);
+    }
+    max_bus = drive_get_max_bus(IF_AHCI);
+    if (max_bus > 0) {
+        fprintf(stderr, "1 bus is available on the host ahci controller.\n"
+                        "Ignoring extra assignments.\n");
+    }
+    hd = g_malloc(ports * sizeof(DriveInfo *));
+    ahci_drive_get(hd, 0, ports);
+    pci_ahci_create_devs(ahci, hd, ports);
+    idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
+    idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
+
+    if (usb_enabled(false)) {
+        /* Should we create 6 UHCI according to ich9 spec? */
+        pci_create_simple_multifunction(
+            host_bus, PCI_DEVFN(ICH9_USB_UHCI1_DEV, ICH9_USB_UHCI1_FUNC),
+            true, "ich9-usb-uhci1");
+        /* XXX: EHCI */
+    }
+
+    /* TODO: Populate SPD eeprom data.  */
+    smbus_eeprom_init(ich9_smb_init(host_bus,
+                                    PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
+                                    0xb100),
+                      8, NULL, 0);
+}
+
+/* PC hardware initialisation */
+static void pc_q35_init(QEMUMachineInitArgs *args)
+{
+    ram_addr_t ram_size = args->ram_size;
+    const char *cpu_model = args->cpu_model;
+    const char *kernel_filename = args->kernel_filename;
+    const char *kernel_cmdline = args->kernel_cmdline;
+    const char *initrd_filename = args->initrd_filename;
+    const char *boot_device = args->boot_device;
+    ram_addr_t below_4g_mem_size, above_4g_mem_size;
+    DeviceState *gmch_host;
+    PCIBus *host_bus;
+    PCIDevice *lpc;
+    BusState *idebus[MAX_SATA_PORTS];
+    ISADevice *rtc_state;

hw/pc_q35.c new file +95 -0

+    int i;
+
+    pc_cpus_init(cpu_model);
+
+    if (ram_size >= 0xb0000000) {
+        above_4g_mem_size = ram_size - 0xb0000000;
+        below_4g_mem_size = 0xb0000000;
+    } else {
+        above_4g_mem_size = 0;
+        below_4g_mem_size = ram_size;
+    }
+
+    /* pci enabled */
+    if (pci_enabled) {
+        pci_memory = g_new(MemoryRegion, 1);
+        memory_region_init(pci_memory, "pci", INT64_MAX);
+        rom_memory = pci_memory;
+    } else {
+        pci_memory = NULL;
+        rom_memory = get_system_memory();
+    }
+
+    /* allocate ram and load rom/bios */
+    if (!xen_enabled()) {
+        pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
+                       initrd_filename, below_4g_mem_size, above_4g_mem_size,
+                       rom_memory, &ram_memory);
+    }
+
+    /* irq lines */
+    gsi_state = g_malloc0(sizeof(*gsi_state));
+    if (kvm_irqchip_in_kernel()) {
+        kvm_piix3_setup_irq_routing(pci_enabled);
+        gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state,
+                                 GSI_NUM_PINS);
+    } else {
+        gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
+    }
+
+    pc_q35_init_early(gsi, gsi_state,
+                      &gmch_host, &host_bus, &lpc, &isa_bus,
+                      get_system_memory(), pci_memory, get_system_io(),
+                      ram_memory, below_4g_mem_size, above_4g_mem_size);
+    isa_bus_irqs(isa_bus, gsi);
+
+    if (kvm_irqchip_in_kernel()) {
+        i8259 = kvm_i8259_init(isa_bus);
+    } else if (xen_enabled()) {
+        i8259 = xen_interrupt_controller_init();
+    } else {
+        cpu_irq = pc_allocate_cpu_irq();
+        i8259 = i8259_init(isa_bus, cpu_irq[0]);
+    }
+
+    for (i = 0; i < ISA_NUM_IRQS; i++) {
+        gsi_state->i8259_irq[i] = i8259[i];
+    }
+    if (pci_enabled) {
+        ioapic_init_gsi(gsi_state, NULL);
+    }
+
+    pc_register_ferr_irq(gsi[13]);
+
+    /* init basic PC hardware */
+    pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
+
+    pc_q35_init_late(idebus, rtc_state, gmch_host, host_bus, lpc);
+
+    pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
+                 floppy, idebus[0], idebus[1], rtc_state);
+
+    /* the rest devices to which pci devfn is automatically assigned */
+    pc_vga_init(isa_bus, host_bus);
+    audio_init(isa_bus, host_bus);
+    pc_nic_init(isa_bus, host_bus);
+    if (pci_enabled) {
+        pc_pci_device_init(host_bus);
+    }
+}
+
+static QEMUMachine pc_q35_machine = {
+    .name = "q35-next",
+    .alias = "q35",
+    .desc = "Q35 chipset PC",
+    .init = pc_q35_init,
+    .max_cpus = 255,
+    .default_drive_if = IF_AHCI,
+};
+
+static void pc_q35_machine_init(void)
+{
+    qemu_register_machine(&pc_q35_machine);
+}
+
+machine_init(pc_q35_machine_init);

hw/pci_ids.h +2 -0

index 17ae42e..ef24181 100644
@@ -137,6 +137,8 @@
 #define PCI_DEVICE_ID_INTEL_82801I_EHCI2 0x293c
 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
 
+#define PCI_DEVICE_ID_INTEL_Q35_MCH      0x29c0
+
 #define PCI_VENDOR_ID_XEN               0x5853
 #define PCI_DEVICE_ID_XEN_PLATFORM      0x0001
 

hw/q35.c new file +62 -0

new file mode 100644
index 0000000..1fd8802
@@ -0,0 +1,315 @@
+/*
+ * QEMU GMCH/ICH9 PCI Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2009, 2010, 2011
+ *               Isaku Yamahata <yamahata at valinux co jp>
+ *               VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <[email protected]>
+ *
+ * This is based on piix_pci.c, but heavily modified.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "range.h"
+#include "isa.h"
+#include "sysbus.h"
+#include "pc.h"
+#include "apm.h"
+#include "apic.h"
+#include "pci.h"
+#include "pcie_host.h"
+#include "pci_bridge.h"
+#include "q35.h"
+#include "acpi.h"
+#include "acpi_ich9.h"
+#include "pam.h"
+#include "pci_internals.h"
+#include "exec-memory.h"
+#include "isa.h"
+#include "qemu-common.h"
+#include "ich9.h"
+
+
+
+/****************************************************************************
+ * GMCH PCI host
+ */
+
+static int gmch_pcihost_initfn(SysBusDevice *dev)
+{
+    PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
+    GMCHPCIHost *s = GMCH_HOST_DEVICE(&dev->qdev);
+
+    memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci,
+                          "pci-conf-idx", 4);

hw/q35.c new file +9 -0

+    }
+
+    return 0;
+}
+
+static Property gmch_props[] = {
+    DEFINE_PROP_UINT64("MCFG", GMCHPCIHost, host.base_addr,
+                        GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
+    DEFINE_PROP_END_OF_LIST(),

hw/q35.c new file +194 -0

+}
+
+static const TypeInfo gmch_pcihost_info = {
+    .name       = TYPE_GMCH_HOST_DEVICE,
+    .parent     = TYPE_PCIE_HOST_BRIDGE,
+    .instance_size = sizeof(GMCHPCIHost),
+    .class_init = gmch_pcihost_class_init,
+};
+
+/* host bridge */
+PCIBus *gmch_host_init(DeviceState **gmch_hostp,
+                       MemoryRegion *pci_address_space,
+                       MemoryRegion *address_space_io)
+{
+    DeviceState *dev;
+    GMCHPCIHost *s;
+    PCIBus *b;
+
+    dev = qdev_create(NULL, TYPE_GMCH_HOST_DEVICE);
+    s = GMCH_HOST_DEVICE(dev);
+    b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0", pci_address_space,
+                    address_space_io, 0);
+    s->host.pci.bus = b;
+    qdev_init_nofail(dev);
+    *gmch_hostp = dev;
+    return b;
+}
+
+
+/****************************************************************************
+ * GMCH D0:F0
+ */
+
+/* PCIE MMCFG */
+static void gmch_update_pciexbar(GMCHPCIState *gs)
+{
+    PCIDevice *pci_dev = &gs->d;
+    BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
+    DeviceState *qdev = bus->parent;
+    GMCHPCIHost *s = GMCH_HOST_DEVICE(qdev);
+
+    uint64_t pciexbar;
+    int enable;
+    uint64_t addr;
+    uint64_t addr_mask;
+    uint32_t length;
+
+    pciexbar = pci_get_quad(pci_dev->config + GMCH_HOST_BRIDGE_PCIEXBAR);
+    enable = pciexbar & GMCH_HOST_BRIDGE_PCIEXBAREN;
+
+    addr_mask = GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
+    switch (pciexbar & GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
+    case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
+        length = 256 * 1024 * 1024;
+        break;
+    case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
+        length = 128 * 1024 * 1024;
+        addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
+            GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
+        break;
+    case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
+        length = 64 * 1024 * 1024;
+        addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
+        break;
+    case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
+    default:
+        enable = 0;
+        length = 0;
+        abort();
+        break;
+    }
+    addr = pciexbar & addr_mask;
+
+    pcie_host_mmcfg_update(&s->host, enable, addr, length);
+}
+
+/* PAM */
+static void gmch_update_pam(GMCHPCIState *gs)
+{
+    int i;
+
+    memory_region_transaction_begin();
+    for (i = 0; i < 13; i++) {
+        pam_update(&gs->pam_regions[i], i,
+                   gs->d.config[GMCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
+    }
+    memory_region_transaction_commit();
+}
+
+/* SMRAM */
+static void gmch_update_smram(GMCHPCIState *gs)
+{
+    memory_region_transaction_begin();
+    smram_update(&gs->smram_region, gs->d.config[GMCH_HOST_BRDIGE_SMRAM],
+                    gs->smm_enabled);
+    memory_region_transaction_commit();
+}
+
+static void gmch_set_smm(int smm, void *arg)
+{
+    GMCHPCIState *gs = arg;
+
+    memory_region_transaction_begin();
+    smram_set_smm(&gs->smm_enabled, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM],
+                    &gs->smram_region);
+    memory_region_transaction_commit();
+}
+
+static void gmch_write_config(PCIDevice *d,
+                              uint32_t address, uint32_t val, int len)
+{
+    GMCHPCIState *gs = GMCH_PCI_DEVICE(d);
+
+    /* XXX: implement SMRAM.D_LOCK */
+    pci_default_write_config(d, address, val, len);
+
+    if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PAM0,
+                       GMCH_HOST_BRIDGE_PAM_SIZE)) {
+        gmch_update_pam(gs);
+    }
+
+    if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PCIEXBAR,
+                       GMCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
+        gmch_update_pciexbar(gs);
+    }
+
+    if (ranges_overlap(address, len, GMCH_HOST_BRDIGE_SMRAM,
+                       GMCH_HOST_BRDIGE_SMRAM_SIZE)) {
+        gmch_update_smram(gs);
+    }
+}
+
+static void gmch_update(GMCHPCIState *gs)
+{
+    gmch_update_pciexbar(gs);
+    gmch_update_pam(gs);
+    gmch_update_smram(gs);
+}
+
+static int gmch_post_load(void *opaque, int version_id)
+{
+    GMCHPCIState *gs = opaque;
+    gmch_update(gs);
+    return 0;
+}
+
+static const VMStateDescription vmstate_gmch = {
+    .name = "gmch",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .post_load = gmch_post_load,
+    .fields = (VMStateField []) {
+        VMSTATE_PCI_DEVICE(d, GMCHPCIState),
+        VMSTATE_UINT8(smm_enabled, GMCHPCIState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void gmch_reset(DeviceState *qdev)
+{
+    PCIDevice *d = PCI_DEVICE(qdev);
+    GMCHPCIState *gs = GMCH_PCI_DEVICE(d);
+
+    pci_set_quad(d->config + GMCH_HOST_BRIDGE_PCIEXBAR,
+                 GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
+
+    d->config[GMCH_HOST_BRDIGE_SMRAM] = GMCH_HOST_BRIDGE_SMRAM_DEFAULT;
+
+    gmch_update(gs);
+}
+
+static int pci_gmch_initfn(PCIDevice *d)
+{
+    GMCHPCIState *gs = GMCH_PCI_DEVICE(d);
+
+    cpu_smm_register(&gmch_set_smm, gs);
+
+    return 0;
+}
+
+static void pci_gmch_class_init(ObjectClass *klass, void *data)
+{
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    k->init = pci_gmch_initfn;
+    k->config_write = gmch_write_config;
+    dc->reset = gmch_reset;
+    dc->desc = "Host bridge";
+    dc->vmsd = &vmstate_gmch;
+    dc->no_user = 1;
+    k->vendor_id = PCI_VENDOR_ID_INTEL;
+    k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;

hw/q35.c new file +20 -0

+
+/* host bridge */
+PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
+{
+    GMCHPCIHost *s = GMCH_HOST_DEVICE(gmch_host);
+    PCIDevice *d;
+
+    d = pci_create_simple_multifunction(b, 0, false, TYPE_GMCH_PCI_DEVICE);
+    s->dev = d;
+
+    return d;
+}
+
+static void q35_register(void)
+{
+    type_register_static(&pci_gmch_info);
+    type_register_static(&gmch_pcihost_info);
+}
+
+type_init(q35_register);

hw/q35.h new file +69 -0

new file mode 100644
index 0000000..0b66da7
@@ -0,0 +1,161 @@
+/*
+ * q35.h
+ *
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ *                    VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#ifndef HW_Q35_H
+#define HW_Q35_H
+
+#include "hw.h"
+#include "range.h"
+#include "isa.h"
+#include "sysbus.h"
+#include "pc.h"
+#include "apm.h"
+#include "apic.h"
+#include "pci.h"
+#include "pcie_host.h"
+#include "pci_bridge.h"
+#include "q35.h"
+#include "acpi.h"
+#include "acpi_ich9.h"
+#include "pam.h"
+#include "pci_internals.h"
+
+
+#define TYPE_GMCH_HOST_DEVICE "gmch-pcihost"
+#define GMCH_HOST_DEVICE(obj) \
+     OBJECT_CHECK(GMCHPCIHost, (obj), TYPE_GMCH_HOST_DEVICE)
+
+#define TYPE_GMCH_PCI_DEVICE "gmch"
+#define GMCH_PCI_DEVICE(obj) \
+     OBJECT_CHECK(GMCHPCIState, (obj), TYPE_GMCH_PCI_DEVICE)
+
+typedef struct GMCHPCIHost {
+    PCIExpressHost      host;
+    PCIDevice    *dev;
+} GMCHPCIHost;
+
+typedef struct GMCHPCIState {
+    PCIDevice   d;
+    /*
+     * GMCH_PCIHost   *gmch_host;
+     * In order to get GMCH_PCIHost
+     *  PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
+     */
+    MemoryRegion *ram_memory;
+    MemoryRegion *pci_address_space;
+    MemoryRegion *system_memory;
+    PAMMemoryRegion pam_regions[13];
+    MemoryRegion smram_region;
+    MemoryRegion pci_hole;
+    MemoryRegion pci_hole_64bit;
+    uint8_t smm_enabled;

hw/q35.h new file +16 -0

+
+/*
+ * gmch part
+ */
+
+/* PCI configuration */
+#define GMCH_HOST_BRIDGE                        "GMCH"
+
+#define GMCH_HOST_BRIDGE_CONFIG_ADDR            0xcf8
+#define GMCH_HOST_BRIDGE_CONFIG_DATA            0xcfc
+
+/* D0:F0 configuration space */
+#define GMCH_HOST_BRIDGE_REVISION_DEFUALT       0x0
+
+#define GMCH_HOST_BRIDGE_PCIEXBAR               0x60    /* 64bit register */
+#define GMCH_HOST_BRIDGE_PCIEXBAR_SIZE          8       /* 64bit register */

hw/q35.h new file +57 -0

+
+#define GMCH_HOST_BRIDGE_PAM_NB                 7
+#define GMCH_HOST_BRIDGE_PAM_SIZE               7
+#define GMCH_HOST_BRIDGE_PAM0                   0x90
+#define GMCH_HOST_BRIDGE_PAM_BIOS_AREA          0xf0000
+#define GMCH_HOST_BRIDGE_PAM_AREA_SIZE          0x10000 /* 16KB */
+#define GMCH_HOST_BRIDGE_PAM1                   0x91
+#define GMCH_HOST_BRIDGE_PAM_EXPAN_AREA         0xc0000
+#define GMCH_HOST_BRIDGE_PAM_EXPAN_SIZE         0x04000
+#define GMCH_HOST_BRIDGE_PAM2                   0x92
+#define GMCH_HOST_BRIDGE_PAM3                   0x93
+#define GMCH_HOST_BRIDGE_PAM4                   0x94
+#define GMCH_HOST_BRIDGE_PAM_EXBIOS_AREA        0xe0000
+#define GMCH_HOST_BRIDGE_PAM_EXBIOS_SIZE        0x04000
+#define GMCH_HOST_BRIDGE_PAM5                   0x95
+#define GMCH_HOST_BRIDGE_PAM6                   0x96
+#define GMCH_HOST_BRIDGE_PAM_WE_HI              ((uint8_t)(0x2 << 4))
+#define GMCH_HOST_BRIDGE_PAM_RE_HI              ((uint8_t)(0x1 << 4))
+#define GMCH_HOST_BRIDGE_PAM_HI_MASK            ((uint8_t)(0x3 << 4))
+#define GMCH_HOST_BRIDGE_PAM_WE_LO              ((uint8_t)0x2)
+#define GMCH_HOST_BRIDGE_PAM_RE_LO              ((uint8_t)0x1)
+#define GMCH_HOST_BRIDGE_PAM_LO_MASK            ((uint8_t)0x3)
+#define GMCH_HOST_BRIDGE_PAM_WE                 ((uint8_t)0x2)
+#define GMCH_HOST_BRIDGE_PAM_RE                 ((uint8_t)0x1)
+#define GMCH_HOST_BRIDGE_PAM_MASK               ((uint8_t)0x3)
+
+#define GMCH_HOST_BRDIGE_SMRAM                  0x9d
+#define GMCH_HOST_BRDIGE_SMRAM_SIZE             1
+#define GMCH_HOST_BRIDGE_SMRAM_DEFAULT          ((uint8_t)0x2)
+#define GMCH_HOST_BRIDGE_SMRAM_D_OPEN           ((uint8_t)(1 << 6))
+#define GMCH_HOST_BRIDGE_SMRAM_D_CLS            ((uint8_t)(1 << 5))
+#define GMCH_HOST_BRIDGE_SMRAM_D_LCK            ((uint8_t)(1 << 4))
+#define GMCH_HOST_BRIDGE_SMRAM_G_SMRAME         ((uint8_t)(1 << 3))
+#define GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK  ((uint8_t)0x7)
+#define GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG       ((uint8_t)0x2)  /* hardwired to b010 */
+#define GMCH_HOST_BRIDGE_SMRAM_C_BASE           0xa0000
+#define GMCH_HOST_BRIDGE_SMRAM_C_END            0xc0000
+#define GMCH_HOST_BRIDGE_SMRAM_C_SIZE           0x20000
+#define GMCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END  0x100000
+
+#define GMCH_HOST_BRIDGE_ESMRAMC                0x9e
+#define GMCH_HOST_BRDIGE_ESMRAMC_H_SMRAME       ((uint8_t)(1 << 6))
+#define GMCH_HOST_BRDIGE_ESMRAMC_E_SMERR        ((uint8_t)(1 << 5))
+#define GMCH_HOST_BRDIGE_ESMRAMC_SM_CACHE       ((uint8_t)(1 << 4))
+#define GMCH_HOST_BRDIGE_ESMRAMC_SM_L1          ((uint8_t)(1 << 3))
+#define GMCH_HOST_BRDIGE_ESMRAMC_SM_L2          ((uint8_t)(1 << 2))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK   ((uint8_t)(0x3 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB    ((uint8_t)(0x0 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB    ((uint8_t)(0x1 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB    ((uint8_t)(0x2 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_T_EN           ((uint8_t)1)
+
+/* D1:F0 PCIE* port*/
+#define GMCH_PCIE_DEV                           1
+#define GMCH_PCIE_FUNC                          0
+
+#endif /* HW_Q35_H */

Signature · 1 line

1.7.1

Quoted 33 lines · Jason Baron

From: Isaku Yamahata <[email protected]>

pc q35 based chipset emulator to support pci express natively. Based on Anthony Liguori's suggestion, the machine name is 'q35-next', with an alias of 'q35'. At this point, there are no compatibility guarantees. When the chipset stabilizes more, we will begin to version the machine names.

Major features which still need to be added:

(quoted diff) +0 -3

-Migration support (mostly around ahci)
-ACPI hotplug support (pcie hotplug support is working)
-Passthrough support

Signed-off-by Isaku Yamahata <[email protected]>

Signed-off-by Jason Baron <[email protected]>

---
 hw/i386/Makefile.objs |    2 +-
 hw/pc.h               |    2 +
 hw/pc_piix.c          |    4 +-
 hw/pc_q35.c           |  326 +++++++++++++++++++++++++++++++++++++++++++++++++
 hw/pci_ids.h          |    2 +
 hw/q35.c              |  315 +++++++++++++++++++++++++++++++++++++++++++++++
 hw/q35.h              |  161 ++++++++++++++++++++++++
 7 files changed, 809 insertions(+), 3 deletions(-)
 create mode 100644 hw/pc_q35.c
 create mode 100644 hw/q35.c
 create mode 100644 hw/q35.h

hw/i386/Makefile.objs +0 -0

index 693bd18..469b127 100644

hw/i386/Makefile.objs obj-y += debugcon.o multiboot.o · line 10

Quoted 5 lines

hw/i386/Makefile.objs +1 -1

@@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o
 obj-y += pc_piix.o
 obj-y += pc_sysfw.o
 obj-y += pam.o
-obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o
+obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o q35.o pc_q35.o

This shouldn't be here. It should be in hw/Makefile.objs.

This is not target specific code.

Quoted 43 lines · Anthony Liguori

Quoted 33 lines · Jason Baron

From: Isaku Yamahata <[email protected]>

pc q35 based chipset emulator to support pci express natively. Based on Anthony Liguori's suggestion, the machine name is 'q35-next', with an alias of 'q35'. At this point, there are no compatibility guarantees. When the chipset stabilizes more, we will begin to version the machine names.

Major features which still need to be added:

(quoted diff) +0 -3

-Migration support (mostly around ahci)
-ACPI hotplug support (pcie hotplug support is working)
-Passthrough support

Signed-off-by Isaku Yamahata <[email protected]>

Signed-off-by Jason Baron <[email protected]>

---
 hw/i386/Makefile.objs |    2 +-
 hw/pc.h               |    2 +
 hw/pc_piix.c          |    4 +-
 hw/pc_q35.c           |  326 +++++++++++++++++++++++++++++++++++++++++++++++++
 hw/pci_ids.h          |    2 +
 hw/q35.c              |  315 +++++++++++++++++++++++++++++++++++++++++++++++
 hw/q35.h              |  161 ++++++++++++++++++++++++
 7 files changed, 809 insertions(+), 3 deletions(-)
 create mode 100644 hw/pc_q35.c
 create mode 100644 hw/q35.c
 create mode 100644 hw/q35.h

hw/i386/Makefile.objs +0 -0

index 693bd18..469b127 100644

hw/i386/Makefile.objs obj-y += debugcon.o multiboot.o · line 10

Quoted 5 lines

hw/i386/Makefile.objs +1 -1

@@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o
 obj-y += pc_piix.o
 obj-y += pc_sysfw.o
 obj-y += pam.o
-obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o
+obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o q35.o pc_q35.o

This shouldn't be here. It should be in hw/Makefile.objs.

Quoted 1 line

This is not target specific code.

What about acpi_ich9.o lpc_ich9.o smbus_ich9.o? Should it move to Makefile.objs too?

How is this different from pc_piix?

Signature · 2 lines

-- 
MST

+ uhci_devname[sizeof(uhci_devname) - 2] = ((char)'1') + i;

+ qdev_prop_set_string(usb_qdev, "masterbus", "ich9-usb-bus.0");

Hi,

Quoted 1 line

+ uhci_devname[sizeof(uhci_devname) - 2] = ((char)'1') + i;

snprintf(devname, sizeof(devname), "...%d", i) is more readable.

Quoted 2 lines

+ qdev_prop_set_string(usb_qdev, "masterbus", "ich9-usb-bus.0");

Any reason why you rename the usb bus?

Quoted 5 lines · Gerd Hoffmann

Hi,

Quoted 1 line

+ uhci_devname[sizeof(uhci_devname) - 2] = ((char)'1') + i;

snprintf(devname, sizeof(devname), "...%d", i) is more readable.

ok.

Quoted 3 lines

Quoted 2 lines

+ qdev_prop_set_string(usb_qdev, "masterbus", "ich9-usb-bus.0");

Quoted 2 lines

Any reason why you rename the usb bus?

I wasn't sure if the user created usb devices on the command-line via -device if that would break naming here. Thus, I added a 'private' name. If the naming is stable, that works. It would be 'usb-bus.0', in that case?

Quoted 12 lines · Jason Baron

Quoted 5 lines · Gerd Hoffmann

Hi,

Quoted 1 line

+ uhci_devname[sizeof(uhci_devname) - 2] = ((char)'1') + i;

snprintf(devname, sizeof(devname), "...%d", i) is more readable.

ok.

Quoted 3 lines

Quoted 2 lines

+ qdev_prop_set_string(usb_qdev, "masterbus", "ich9-usb-bus.0");

Quoted 7 lines

Quoted 2 lines

Any reason why you rename the usb bus?

I wasn't sure if the user created usb devices on the command-line via -device if that would break naming here. Thus, I added a 'private' name. If the naming is stable, that works. It would be 'usb-bus.0', in that case?

"usb.0" would be the default name, but you don't need to know it, you can just look up what qdev created. See here:

http://www.kraxel.org/cgit/qemu/commit/?h=rebase/usb-next&id=70b9867011c4793787c5acee3d2005a6bc951f59

[ This is part of the "usb patch queue" patch series posted today,
depending on how the qom discussions go and how fast it goes in you might just call the function the patch provides. Or do something simliar in pc_q35.c and I'll drop the patch. ]

-usb for -M pc creates a "usb.0" bus too, so I don't expect trouble.