arm: zynq: add system level control register manager
Subsystems (3)
PATCH 1/1 arm: zynq: add system level control register manager
This patch for the Xilinx Zynq ARM architecture adds management of system level control register. The code is taken from the Xilinx-internal Linux Git tree and cleaned up a bit for mainline integration. Besides others, this patch is needed in order to integrate further drivers for Zynq such as the Zynq xemacps networking device driver. The patch is aganst the latest arm-soc tree.
--- arch/arm/mach-zynq/Makefile | 2 +- arch/arm/mach-zynq/include/mach/slcr.h | 27 + arch/arm/mach-zynq/slcr.c | 2166 ++++++++++++++++++++++++++++++++ 3 files changed, 2194 insertions(+), 1 deletions(-)
arch/arm/mach-zynq/Makefile +1 -1
@@ -3,4 +3,4 @@ # # Common support -obj-y := common.o timer.o +obj-y := common.o timer.o slcr.o
arch/arm/mach-zynq/include/mach/slcr.h new file +27 -0
@@ -0,0 +1,27 @@ +/* +* arch/arm/mach-zynq/include/mach/slcr.h +* +* Copyright (C) 2012 Xilinx +* +* This software is licensed under the terms of the GNU General Public +* License version 2, as published by the Free Software Foundation, and +* may be copied, distributed, and modified under those terms. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef __MACH_SLCR_H__ +#define __MACH_SLCR_H__ + +extern void xslcr_write (u32 offset,u32 val); +extern u32 xslcr_read (u32 offset); + +extern void xslcr_system_reset (void ); + +extern void xslcr_init_preload_fpga (void ); +extern void xslcr_init_postload_fpga (void ); + +#endif /* __MACH_SLCR_H__ */
arch/arm/mach-zynq/slcr.c new file +2166 -0
2,166 lines not on this page · raw message
PATCH 1/1 arm: zynq: add system level control register manager
Quoted 7 lines · Daniel Borkmann
This patch for the Xilinx Zynq ARM architecture adds management of system level control register. The code is taken from the Xilinx-internal Linux Git tree and cleaned up a bit for mainline integration. Besides others, this patch is needed in order to integrate further drivers for Zynq such as the Zynq xemacps networking device driver. The patch is aganst the latest arm-soc tree.
Quoted 5 lines
Signed-off-by Daniel Borkmann <[email protected]>Cc Michal Simek <[email protected]>Cc John Linn <[email protected]>Cc Arnd Bergmann <[email protected]>---
Hey Daniel-
These changes will conflict with my pending clk patchset [1], as I'm introducing bindings for the SLCR (and its clk interfaces).
It seems like a hefty chunk of the out-of-tree slcr driver is related to configuring MIO. I think it would be really nice if this driver was reworked to use the pinctrl subsystem, and also to provide suitable device tree bindings.
But, at an even higher level, it would be nice to have a coordinated plan for getting better Zynq support upstream. My implicit plan (so far) has been:
1. Initial cleanup [get the thing booting] (done)
2. Figure out clk drivers and bindings (pending)
3. Figure out MIO pinctrl support and bindings (?)
4. Adapting out-of-tree peripheral drivers according to 2 & 3 (?)
5. Add support for SMP (?)
Step 4 has a dependency on 2 and 3, of course, the point being that we get those into a state where we are happy with them before moving all of the peripherals over. I believe step 5 can be done in parallel to the others.
Arnd-
At a high level, does this sound like a suitable plan of action? Is there something else you would like to see from those of us working on Zynq support?
Thanks,
Josh
1: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-October/129295.html
PATCH 1/1 arm: zynq: add system level control register manager
Quoted 8 lines · Josh Cartwright
Quoted 7 lines · Daniel Borkmann
This patch for the Xilinx Zynq ARM architecture adds management of system level control register. The code is taken from the Xilinx-internal Linux Git tree and cleaned up a bit for mainline integration. Besides others, this patch is needed in order to integrate further drivers for Zynq such as the Zynq xemacps networking device driver. The patch is aganst the latest arm-soc tree.
Quoted 8 lines
Quoted 5 lines
Signed-off-by Daniel Borkmann <[email protected]>Cc Michal Simek <[email protected]>Cc John Linn <[email protected]>Cc Arnd Bergmann <[email protected]>---
These changes will conflict with my pending clk patchset [1], as I'm introducing bindings for the SLCR (and its clk interfaces).
Oops, okay. Then your's has priority, of course.
Quoted 4 lines
It seems like a hefty chunk of the out-of-tree slcr driver is related to configuring MIO. I think it would be really nice if this driver was reworked to use the pinctrl subsystem, and also to provide suitable device tree bindings.
Agreed. If there's a chance to help with further Zynq integration and to develop this driver with testing on Qemu for ARM Zynq, I'd like to give it a try. (The board is a bit expensive as a hobby only.)
Quoted 30 lines
But, at an even higher level, it would be nice to have a coordinated plan for getting better Zynq support upstream. My implicit plan (so far) has been:
1. Initial cleanup [get the thing booting] (done)
2. Figure out clk drivers and bindings (pending)
3. Figure out MIO pinctrl support and bindings (?)
4. Adapting out-of-tree peripheral drivers according to 2 & 3 (?)
5. Add support for SMP (?)Step 4 has a dependency on 2 and 3, of course, the point being that we get those into a state where we are happy with them before moving all of the peripherals over. I believe step 5 can be done in parallel to the others.
Arnd-
At a high level, does this sound like a suitable plan of action? Is there something else you would like to see from those of us working on Zynq support?
Thanks,
Josh1: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-October/129295.html
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PATCH 1/1 arm: zynq: add system level control register manager
Quoted 15 lines · Daniel Borkmann
Quoted 14 lines · Josh Cartwright
Quoted 12 lines · Daniel Borkmann
This patch for the Xilinx Zynq ARM architecture adds management of system level control register. The code is taken from the Xilinx-internal Linux Git tree and cleaned up a bit for mainline integration. Besides others, this patch is needed in order to integrate further drivers for Zynq such as the Zynq xemacps networking device driver. The patch is aganst the latest arm-soc tree.
Signed-off-by Daniel Borkmann <[email protected]>Cc Michal Simek <[email protected]>Cc John Linn <[email protected]>Cc Arnd Bergmann <[email protected]>---
Quoted 4 lines
Quoted 2 lines
These changes will conflict with my pending clk patchset [1], as I'm introducing bindings for the SLCR (and its clk interfaces).
Oops, okay. Then your's has priority, of course.
I did not mean to discourage. I just meant to say that we should work out how this work can be done on top of the clk changes.
Quoted 8 lines
Quoted 4 lines
It seems like a hefty chunk of the out-of-tree slcr driver is related to configuring MIO. I think it would be really nice if this driver was reworked to use the pinctrl subsystem, and also to provide suitable device tree bindings.
Agreed. If there's a chance to help with further Zynq integration and to develop this driver with testing on Qemu for ARM Zynq, I'd like to give it a try. (The board is a bit expensive as a hobby only.)
My concern is that, especially regarding the configuration of MIO, being able to do adequate testing will require real hardware. It isn't clear to me what the state of qemu's slcr/mio model is.
Josh
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PATCH 1/1 arm: zynq: add system level control register manager
Quoted 29 lines · Josh Cartwright
Quoted 15 lines · Daniel Borkmann
Quoted 14 lines · Josh Cartwright
Quoted 12 lines · Daniel Borkmann
This patch for the Xilinx Zynq ARM architecture adds management of system level control register. The code is taken from the Xilinx-internal Linux Git tree and cleaned up a bit for mainline integration. Besides others, this patch is needed in order to integrate further drivers for Zynq such as the Zynq xemacps networking device driver. The patch is aganst the latest arm-soc tree.
Signed-off-by Daniel Borkmann <[email protected]>Cc Michal Simek <[email protected]>Cc John Linn <[email protected]>Cc Arnd Bergmann <[email protected]>---
Quoted 4 lines
Quoted 2 lines
These changes will conflict with my pending clk patchset [1], as I'm introducing bindings for the SLCR (and its clk interfaces).
Oops, okay. Then your's has priority, of course.
I did not mean to discourage. I just meant to say that we should work out how this work can be done on top of the clk changes.
Quoted 5 lines
Quoted 4 lines
It seems like a hefty chunk of the out-of-tree slcr driver is related to configuring MIO. I think it would be really nice if this driver was reworked to use the pinctrl subsystem, and also to provide suitable device tree bindings.
Quoted 7 lines
Quoted 3 lines
Agreed. If there's a chance to help with further Zynq integration and to develop this driver with testing on Qemu for ARM Zynq, I'd like to give it a try. (The board is a bit expensive as a hobby only.)
My concern is that, especially regarding the configuration of MIO, being able to do adequate testing will require real hardware. It isn't clear to me what the state of qemu's slcr/mio model is.
I added Peter Crosthwaite into CC, since he could provide an answer to that (I've been told).
PATCH 1/1 arm: zynq: add system level control register manager
Quoted 59 lines
-----Original Message-----
From: Daniel Borkmann [mailto:danborkmann at iogearbox.net]
Sent: Wednesday, November 14, 2012 5:25 AM
To: Josh Cartwright
Cc: Josh Cartwright; Arnd Bergmann; Michal Simek; John Linn; linux-arm- kernel at lists.infradead.org; Peter Crosthwaite
Subject: Re: [PATCH] arm: zynq: add system level control register managerQuoted 2 lines · Josh Cartwright
Quoted 1 line · Daniel Borkmann
On Thu, Nov 8, 2012 at 5:01 PM, Josh Cartwright <[email protected]>
Quoted 2 lines · wrote:
Quoted 2 lines
Quoted 2 lines · Daniel Borkmann
Quoted 1 line
This patch for the Xilinx Zynq ARM architecture adds management
of system
Quoted 1 line
Quoted 1 line
Quoted 1 line
Quoted 1 line
level control register. The code is taken from the Xilinx-
internal Linux
Quoted 1 line
Quoted 1 line
Quoted 1 line
Quoted 1 line
Git tree and cleaned up a bit for mainline integration. Besides
others,
Quoted 1 line
Quoted 1 line
Quoted 1 line
Quoted 1 line
this patch is needed in order to integrate further drivers for
Zynq such as
Quoted 1 line
Quoted 1 line
Quoted 1 line
Quoted 1 line
the Zynq xemacps networking device driver. The patch is aganst
the latest
Quoted 9 lines
Quoted 9 lines
Quoted 9 lines
Quoted 7 lines
arm-soc tree.
Signed-off-by Daniel Borkmann <[email protected]>Cc Michal Simek <[email protected]>Cc John Linn <[email protected]>Cc Arnd Bergmann <[email protected]>---
These changes will conflict with my pending clk patchset [1], as
I'm
Quoted 5 lines
Quoted 3 lines
Quoted 1 line
introducing bindings for the SLCR (and its clk interfaces).
Oops, okay. Then your's has priority, of course.
I did not mean to discourage. I just meant to say that we should
work
Quoted 3 lines
out how this work can be done on top of the clk changes.
Quoted 1 line
Quoted 1 line
It seems like a hefty chunk of the out-of-tree slcr driver is
related to
Quoted 1 line
Quoted 1 line
Quoted 1 line
configuring MIO. I think it would be really nice if this driver
was
Quoted 1 line
Quoted 1 line
Quoted 1 line
reworked to use the pinctrl subsystem, and also to provide
suitable
Quoted 3 lines
Quoted 3 lines
Quoted 1 line
device tree bindings.
Agreed. If there's a chance to help with further Zynq integration
and
Quoted 1 line
Quoted 1 line
to develop this driver with testing on Qemu for ARM Zynq, I'd like
to
Quoted 2 lines
Quoted 1 line
give it a try. (The board is a bit expensive as a hobby only.)
Quoted 8 lines
Quoted 1 line
My concern is that, especially regarding the configuration of MIO,
being
Quoted 1 line
able to do adequate testing will require real hardware. It isn't
clear
Quoted 1 line
to me what the state of qemu's slcr/mio model is.
I added Peter Crosthwaite into CC, since he could provide an answer to that (I've been told).
Hi Daniel, Josh,
MIO functionality is not modeled at all in QEMU SLCR. The bounds of QEMU zynq stop before the MIO switch so all devices are always present and connected concurrently (impossible with real hw). There are dummy registers for all the MIO controls in SLCR, so your driver shouldn't crash anything, but everything will just be a NOP.
SLCR Peripheral resets and clock controls are also not modeled (the latter doesn't mean a lot anyway). SLCR doesn't really do much in the end, apart from the CPU reset and halt capabilities needed for SMP linux, and we have a few bits for the bootmode switch and the OCM remapping that are still out of tree.
Regards,
Peter
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PATCH 1/1 arm: zynq: add system level control register manager
In reply to Josh CartwrightHi guys,
first of all sorry for late answer.
Quoted 22 lines
-----Original Message-----
From: Josh Cartwright [mailto:joshc at eso.teric.us]
Sent: Thursday, November 08, 2012 5:01 PM
To: Daniel Borkmann; Arnd Bergmann
Cc: Michal Simek; linux-arm-kernel at lists.infradead.org; John Linn; Josh Cartwright
Subject: Re: [PATCH] arm: zynq: add system level control register managerQuoted 7 lines · Daniel Borkmann
This patch for the Xilinx Zynq ARM architecture adds management of system level control register. The code is taken from the Xilinx-internal Linux Git tree and cleaned up a bit for mainline integration. Besides others, this patch is needed in order to integrate further drivers for Zynq such as the Zynq xemacps networking device driver. The patch is aganst the latest arm-soc tree.
Quoted 5 lines
Signed-off-by Daniel Borkmann <[email protected]>Cc Michal Simek <[email protected]>Cc John Linn <[email protected]>Cc Arnd Bergmann <[email protected]>---
Quoted 8 lines
Hey Daniel-
These changes will conflict with my pending clk patchset [1], as I'm introducing bindings for the SLCR (and its clk interfaces).
It seems like a hefty chunk of the out-of-tree slcr driver is related to configuring MIO. I think it would be really nice if this driver was reworked to use the pinctrl subsystem, and also to provide suitable device tree bindings.
Agree with Josh.
Quoted 7 lines
But, at an even higher level, it would be nice to have a coordinated plan for getting better Zynq support upstream. My implicit plan (so
far) has been:1. Initial cleanup [get the thing booting] (done)
2. Figure out clk drivers and bindings (pending)
I will comment it today.
Quoted 1 line
3. Figure out MIO pinctrl support and bindings (?)
We will look at this topic more closely.
Quoted 1 line
4. Adapting out-of-tree peripheral drivers according to 2 & 3 (?)
This will take some time.
Quoted 1 line
5. Add support for SMP (?)
I can't see any problem why we shouldn't add this after drivers. Cleaning mach-zynq can be done in parallel.
Quoted 4 lines
Step 4 has a dependency on 2 and 3, of course, the point being that we get those into a state where we are happy with them before moving all of the peripherals over. I believe step 5 can be done in parallel to the others.
Ok. Here it is.
Thanks,
Michal
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
PATCH 1/1 arm: zynq: add system level control register manager
Quoted 3 lines · Michal Simek
Quoted 1 line
3. Figure out MIO pinctrl support and bindings (?)
We will look at this topic more closely.
For some clarification: are you (or someone at Xilinx) actively looking at this?
Thanks,
Josh
PATCH 1/1 arm: zynq: add system level control register manager
Quoted 7 lines
-----Original Message-----
From: Josh Cartwright [mailto:josh.cartwright at ni.com]
Sent: Tuesday, November 13, 2012 10:34 AM
To: Michal Simek
Cc: Josh Cartwright; Daniel Borkmann; Arnd Bergmann; linux-arm-kernel at lists.infradead.org; John Linn
Subject: Re: [PATCH] arm: zynq: add system level control register manager
Quoted 7 lines
Quoted 3 lines · Michal Simek
Quoted 1 line
3. Figure out MIO pinctrl support and bindings (?)
We will look at this topic more closely.
For some clarification: are you (or someone at Xilinx) actively looking at this?
Hi Josh,
No one is looking at it that I know of (other than maybe Michal). Our previous thinking was that this was low priority as the first stage boot loader sets up the MIO prior to the kernel running. U-boot needs the MIO setup for some set of devices also.
I don't know the use cases for dynamic MIO, or I'm just misunderstanding what the pinctrl really does. Do designers often build a board to deal with being able use the pins for multiple purposes?
Thanks
John
Quoted 3 lines
Thanks,
Josh
PATCH 1/1 arm: zynq: add system level control register manager
Quoted 22 lines · John Linn
Quoted 7 lines
-----Original Message-----
From: Josh Cartwright [mailto:josh.cartwright at ni.com]
Sent: Tuesday, November 13, 2012 10:34 AM
To: Michal Simek
Cc: Josh Cartwright; Daniel Borkmann; Arnd Bergmann; linux-arm-kernel at lists.infradead.org; John Linn
Subject: Re: [PATCH] arm: zynq: add system level control register managerQuoted 7 lines
Quoted 3 lines · Michal Simek
Quoted 1 line
3. Figure out MIO pinctrl support and bindings (?)
We will look at this topic more closely.
For some clarification: are you (or someone at Xilinx) actively looking at this?
Hi Josh,
No one is looking at it that I know of (other than maybe Michal). Our previous thinking was that this was low priority as the first stage boot loader sets up the MIO prior to the kernel running. U-boot needs the MIO setup for some set of devices also.
Quoted 4 lines
I don't know the use cases for dynamic MIO, or I'm just misunderstanding what the pinctrl really does. Do designers often build a board to deal with being able use the pins for multiple purposes?
I'm less concerned about dynamic (runtime) MIO configuration. What I would personally like to see put into place before the peripherals are moved over is for the MIO configuration to be explicitly modelled in the device tree, instead of implicitly in the u-boot/kernel handoff as you have described.
I think that also means the logic to commit whatever MIO configuration described in the device tree to hardware would be there, too.
Josh
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