Add support for Aurora L2 Cache Controller

Instead of having multiple functions belonging to outer_cache and filling this structure on the fly, use a outer_cache_fns field inside l2x0_of_data and just memcopy it into outer_cache depending of the type of the l2x0 cache. For non DT case, the former code was kept.

Signed-off-by Gregory CLEMENT <[email protected]>

Tested-and-reviewed-by Yehuda Yitschak <[email protected]>

Tested-and-reviewed-by Lior Amsalem <[email protected]>

Cc Barry Song <[email protected]>

Cc Will Deacon <[email protected]>

Cc Santosh Shilimkar <[email protected]>

Cc Rob Herring <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Olof Johansson <[email protected]>

Signed-off-by Gregory CLEMENT <[email protected]>

---
 arch/arm/mm/cache-l2x0.c |   55 +++++++++++++++++++++++++++++++++-------------
 1 file changed, 40 insertions(+), 15 deletions(-)

arch/arm/mm/cache-l2x0.c +36 -14

index 2a8e380..8b9c0ae 100644
@@ -39,8 +39,9 @@ struct l2x0_regs l2x0_saved_regs;
 struct l2x0_of_data {
 	void (*setup)(const struct device_node *, u32 *, u32 *);
 	void (*save)(void);
-	void (*resume)(void);
+	struct outer_cache_fns outer_cache;
 };
+static bool of_init = false;
 
 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
 {

@@ -376,13 +377,15 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		writel_relaxed(1, l2x0_base + L2X0_CTRL);
 	}
 
-	outer_cache.inv_range = l2x0_inv_range;
-	outer_cache.clean_range = l2x0_clean_range;
-	outer_cache.flush_range = l2x0_flush_range;
-	outer_cache.sync = l2x0_cache_sync;
-	outer_cache.flush_all = l2x0_flush_all;
-	outer_cache.inv_all = l2x0_inv_all;
-	outer_cache.disable = l2x0_disable;
+	if (!of_init) {
+		outer_cache.inv_range = l2x0_inv_range;
+		outer_cache.clean_range = l2x0_clean_range;
+		outer_cache.flush_range = l2x0_flush_range;
+		outer_cache.sync = l2x0_cache_sync;
+		outer_cache.flush_all = l2x0_flush_all;
+		outer_cache.inv_all = l2x0_inv_all;
+		outer_cache.disable = l2x0_disable;
+	}
 
 	printk(KERN_INFO "%s cache controller enabled\n", type);
 	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",

@@ -533,15 +536,34 @@ static void pl310_resume(void)
 }
 
 static const struct l2x0_of_data pl310_data = {
-	pl310_of_setup,
-	pl310_save,
-	pl310_resume,
+	.setup = pl310_of_setup,
+	.save  = pl310_save,
+	.outer_cache = {
+		.resume      = pl310_resume,
+		.inv_range   = l2x0_inv_range,
+		.clean_range = l2x0_clean_range,
+		.flush_range = l2x0_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+		.set_debug   = pl310_set_debug,
+	},
 };
 
 static const struct l2x0_of_data l2x0_data = {
-	l2x0_of_setup,
-	NULL,
-	l2x0_resume,
+	.setup = l2x0_of_setup,
+	.save  = NULL,
+	.outer_cache = {
+		.resume      = l2x0_resume,
+		.inv_range   = l2x0_inv_range,
+		.clean_range = l2x0_clean_range,
+		.flush_range = l2x0_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
 };
 
 static const struct of_device_id l2x0_ids[] __initconst = {

arch/arm/mm/cache-l2x0.c +3 -1

+	of_init = true;
 	l2x0_init(l2x0_base, aux_val, aux_mask);
 
-	outer_cache.resume = data->resume;
+	memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
+
 	return 0;
 }
 #endif

Signature · 1 line

1.7.9.5

Quoted 98 lines · Gregory CLEMENT

Instead of having multiple functions belonging to outer_cache and filling this structure on the fly, use a outer_cache_fns field inside l2x0_of_data and just memcopy it into outer_cache depending of the type of the l2x0 cache. For non DT case, the former code was kept.

Signed-off-by Gregory CLEMENT <[email protected]>

Tested-and-reviewed-by Yehuda Yitschak <[email protected]>

Tested-and-reviewed-by Lior Amsalem <[email protected]>

Cc Barry Song <[email protected]>

Cc Will Deacon <[email protected]>

Cc Santosh Shilimkar <[email protected]>

Cc Rob Herring <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Olof Johansson <[email protected]>

Signed-off-by Gregory CLEMENT <[email protected]>

---
 arch/arm/mm/cache-l2x0.c |   55 +++++++++++++++++++++++++++++++++-------------
 1 file changed, 40 insertions(+), 15 deletions(-)

arch/arm/mm/cache-l2x0.c +36 -14

index 2a8e380..8b9c0ae 100644
@@ -39,8 +39,9 @@ struct l2x0_regs l2x0_saved_regs;
 struct l2x0_of_data {
 	void (*setup)(const struct device_node *, u32 *, u32 *);
 	void (*save)(void);
-	void (*resume)(void);
+	struct outer_cache_fns outer_cache;
 };
+static bool of_init = false;
 
 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
 {

@@ -376,13 +377,15 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		writel_relaxed(1, l2x0_base + L2X0_CTRL);
 	}
 
-	outer_cache.inv_range = l2x0_inv_range;
-	outer_cache.clean_range = l2x0_clean_range;
-	outer_cache.flush_range = l2x0_flush_range;
-	outer_cache.sync = l2x0_cache_sync;
-	outer_cache.flush_all = l2x0_flush_all;
-	outer_cache.inv_all = l2x0_inv_all;
-	outer_cache.disable = l2x0_disable;
+	if (!of_init) {
+		outer_cache.inv_range = l2x0_inv_range;
+		outer_cache.clean_range = l2x0_clean_range;
+		outer_cache.flush_range = l2x0_flush_range;
+		outer_cache.sync = l2x0_cache_sync;
+		outer_cache.flush_all = l2x0_flush_all;
+		outer_cache.inv_all = l2x0_inv_all;
+		outer_cache.disable = l2x0_disable;
+	}
 
 	printk(KERN_INFO "%s cache controller enabled\n", type);
 	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",

@@ -533,15 +536,34 @@ static void pl310_resume(void)
 }
 
 static const struct l2x0_of_data pl310_data = {
-	pl310_of_setup,
-	pl310_save,
-	pl310_resume,
+	.setup = pl310_of_setup,
+	.save  = pl310_save,
+	.outer_cache = {
+		.resume      = pl310_resume,
+		.inv_range   = l2x0_inv_range,
+		.clean_range = l2x0_clean_range,
+		.flush_range = l2x0_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+		.set_debug   = pl310_set_debug,
+	},
 };
 
 static const struct l2x0_of_data l2x0_data = {
-	l2x0_of_setup,
-	NULL,
-	l2x0_resume,
+	.setup = l2x0_of_setup,
+	.save  = NULL,
+	.outer_cache = {
+		.resume      = l2x0_resume,
+		.inv_range   = l2x0_inv_range,
+		.clean_range = l2x0_clean_range,
+		.flush_range = l2x0_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
 };
 

arch/arm/mm/cache-l2x0.c int __init l2x0_of_init(u32 aux_val, u32 aux_mask) · line 606

Quoted 6 lines

arch/arm/mm/cache-l2x0.c +1 -0

 static const struct of_device_id l2x0_ids[] __initconst = {

@@ -581,9 +603,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	if (data->save)
 		data->save();
 
+	/* */

Was there a comment here?

arch/arm/mm/cache-l2x0.c static void l2x0_flush_range(unsigned long start, unsigned long end) · line 321

Quoted 8 lines · <[email protected]> wrote:

arch/arm/mm/cache-l2x0.c +8 -0

+static void aurora_pa_range(unsigned long start, unsigned long end,
+                       unsigned long offset)
+{
+       unsigned long flags;
+
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
+       writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+       writel(end, l2x0_base + offset);

Just use writel_relaxed() here for consistency and possible deadlock avoidance.

Aurora Cache Controller was designed to be compatible with the ARM L2 Cache Controller. It comes with some difference or improvement such as:
- no cache id part number available through hardware (need to get it

by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line.

Quoted 4 lines · Gregory CLEMENT

Aurora Cache Controller was designed to be compatible with the ARM L2 Cache Controller. It comes with some difference or improvement such as:
- no cache id part number available through hardware (need to get it

Quoted 8 lines

by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line.

This adds new build warnings:

arch/arm/mm/cache-l2x0.c:328:13: warning: 'aurora_inv_range' defined but not used arch/arm/mm/cache-l2x0.c:347:13: warning: 'aurora_clean_range' defined but not used arch/arm/mm/cache-l2x0.c:365:13: warning: 'aurora_flush_range' defined but not used

to the realview build (non-DT). Please investigate, thanks.

Quoted 20 lines · Russell King - ARM Linux

Quoted 4 lines · Gregory CLEMENT

Aurora Cache Controller was designed to be compatible with the ARM L2 Cache Controller. It comes with some difference or improvement such as:
- no cache id part number available through hardware (need to get it

Quoted 8 lines

by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line.

This adds new build warnings:

arch/arm/mm/cache-l2x0.c:328:13: warning: 'aurora_inv_range' defined but not used arch/arm/mm/cache-l2x0.c:347:13: warning: 'aurora_clean_range' defined but not used arch/arm/mm/cache-l2x0.c:365:13: warning: 'aurora_flush_range' defined but not used

Quoted 1 line

to the realview build (non-DT). Please investigate, thanks.

OK I found the problem: aurora cache support is new so it is only enable with device tree support. I moved all this functions in the under OF_CONFIG (see the patch below). Do you want I submit it on the patch system, or can you get it directly from this email?

Quoted 23 lines · Gregory CLEMENT

Quoted 21 lines · Russell King - ARM Linux

Quoted 4 lines · Gregory CLEMENT

Aurora Cache Controller was designed to be compatible with the ARM L2 Cache Controller. It comes with some difference or improvement such as:
- no cache id part number available through hardware (need to get it

Quoted 8 lines

by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line.

This adds new build warnings:

arch/arm/mm/cache-l2x0.c:328:13: warning: 'aurora_inv_range' defined but not used arch/arm/mm/cache-l2x0.c:347:13: warning: 'aurora_clean_range' defined but not used arch/arm/mm/cache-l2x0.c:365:13: warning: 'aurora_flush_range' defined but not used

to the realview build (non-DT). Please investigate, thanks.

Quoted 4 lines

OK I found the problem: aurora cache support is new so it is only enable with device tree support. I moved all this functions in the under OF_CONFIG (see the patch below). Do you want I submit it on the patch system, or can you get it directly from this email?

Easier by the patch system, and much less likely to get buried and lost between now and when I do the update, thanks.

Quoted 29 lines · Russell King - ARM Linux

Quoted 27 lines · Gregory CLEMENT

Quoted 14 lines · Russell King - ARM Linux

Quoted 4 lines · Gregory CLEMENT

Aurora Cache Controller was designed to be compatible with the ARM L2 Cache Controller. It comes with some difference or improvement such as:
- no cache id part number available through hardware (need to get it

Quoted 8 lines

by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line.

Quoted 7 lines

This adds new build warnings:

arch/arm/mm/cache-l2x0.c:328:13: warning: 'aurora_inv_range' defined but not used arch/arm/mm/cache-l2x0.c:347:13: warning: 'aurora_clean_range' defined but not used arch/arm/mm/cache-l2x0.c:365:13: warning: 'aurora_flush_range' defined but not used

to the realview build (non-DT). Please investigate, thanks.

OK I found the problem: aurora cache support is new so it is only enable with device tree support. I moved all this functions in the under OF_CONFIG (see the patch below). Do you want I submit it on the patch system, or can you get it directly from this email?

Quoted 3 lines

Easier by the patch system, and much less likely to get buried and lost between now and when I do the update, thanks.

OK, the initial patch 7547/1 was superseded by the patch 7547/2 that I have just pushed in the patch system. I hope I have done it right.

Quoted 30 lines · Gregory CLEMENT

Quoted 29 lines · Russell King - ARM Linux

Quoted 27 lines · Gregory CLEMENT

Quoted 14 lines · Russell King - ARM Linux

Quoted 4 lines · Gregory CLEMENT

Aurora Cache Controller was designed to be compatible with the ARM L2 Cache Controller. It comes with some difference or improvement such as:
- no cache id part number available through hardware (need to get it

Quoted 8 lines

by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line.

Quoted 7 lines

This adds new build warnings:

arch/arm/mm/cache-l2x0.c:328:13: warning: 'aurora_inv_range' defined but not used arch/arm/mm/cache-l2x0.c:347:13: warning: 'aurora_clean_range' defined but not used arch/arm/mm/cache-l2x0.c:365:13: warning: 'aurora_flush_range' defined but not used

to the realview build (non-DT). Please investigate, thanks.

OK I found the problem: aurora cache support is new so it is only enable with device tree support. I moved all this functions in the under OF_CONFIG (see the patch below). Do you want I submit it on the patch system, or can you get it directly from this email?

Quoted 5 lines

Quoted 3 lines

Easier by the patch system, and much less likely to get buried and lost between now and when I do the update, thanks.

OK, the initial patch 7547/1 was superseded by the patch 7547/2 that I have just pushed in the patch system. I hope I have done it right.

I know it's been a while, but it looks like it's still producing a warning.

arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used

This seems to be used only by the aurora code, which is wholely contained within a CONFIG_OF block, and this is outside of said block...

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

The initial patch 7547/2 was superseded by the patch 7547/3 that I have just pushed in the patch system. Last time first I fixed the code then I used the versatile_defconfig configuration to test the compilation and didn't realize that it did set CONFIG_OF by default.

Quoted 4 lines · Gregory CLEMENT

The initial patch 7547/2 was superseded by the patch 7547/3 that I have just pushed in the patch system. Last time first I fixed the code then I used the versatile_defconfig configuration to test the compilation and didn't realize that it did set CONFIG_OF by default.

Are you sure you put the right patch in there?

diff -u <(pdb getpatch 7547/2) <(pdb getpatch 7547/3)

dev/fd/62 renamed from dev/fd/63 +5 -1

@@ -1,5 +1,5 @@
 ===============================================================================
-Patch: 7547/2: cache-l2x0: add support for Aurora L2 cache ctrl
+Patch: 7547/3: cache-l2x0: add support for Aurora L2 cache ctrl
 From: Gregory CLEMENT
 Email: gregory.clement at free-electrons.com
 Status: 3.7-rc1

@@ -10,6 +10,8 @@
  arch/arm/mm/cache-l2x0.c                   |  222 +++++++++++++++++++++++++++--
  3 files changed, 268 insertions(+), 13 deletions(-)
 -------------------------------------------------------------------------------
+diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
+index 5f2c7b4..3b2c40b 100644
 --- a/arch/arm/include/asm/hardware/cache-l2x0.h
 +++ b/arch/arm/include/asm/hardware/cache-l2x0.h
 @@ -102,6 +102,10 @@

@@ -443,3 +445,5 @@
 
  	if (data->save)
 
+
+

Looks mostly idential to me...

The newly introduced l2_wt_override should be in the same #ifdef as the code using it, otherwise we get:

arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used

Quoted 4 lines · Arnd Bergmann

The newly introduced l2_wt_override should be in the same #ifdef as the code using it, otherwise we get:

arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used

This should already be fixed. I think your patch pre-dates 7547/4.

Signed-off-by Gregory CLEMENT <[email protected]>

Tested-and-reviewed-by Yehuda Yitschak <[email protected]>

Tested-and-reviewed-by Lior Amsalem <[email protected]>

Acked-by Arnd Bergmann <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Olof Johansson <[email protected]>

---
 arch/arm/mach-mvebu/Kconfig             |    1 +
 arch/arm/mach-mvebu/irq-armada-370-xp.c |    4 ++++
 2 files changed, 5 insertions(+)

arch/arm/mach-mvebu/Kconfig +1 -0

index caa2c5e..e20c5e9 100644
@@ -6,6 +6,7 @@ config MACH_ARMADA_370_XP
 	bool "Marvell Armada 370 and Aramada XP boards"
 	select ARMADA_370_XP_TIMER
 	select CPU_V7
+	select CACHE_L2X0
 	help
 
 	  Say 'Y' here if you want your kernel to support boards based on

arch/arm/mach-mvebu/irq-armada-370-xp.c +1 -0

index 5f5f939..570be84 100644
@@ -24,6 +24,7 @@
 #include <linux/irqdomain.h>
 #include <asm/mach/arch.h>
 #include <asm/exception.h>
+#include <asm/hardware/cache-l2x0.h>
 
 /* Interrupt Controller Registers Map */
 #define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)

Changelog:
V4 -> V5:
- Rebased L2 pach set onto v3.6-rc7.
- The header file cache-aurora-l2.h was co-located with its only user:
moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
- Removed additional unnecessary blank lines in cache-l2x0.c.

The git branch aurora-L2-cache-ctrl is visible at
https://github.com/MISL-EBU-System-SW/mainline-public.git

Quoted 7 lines

Changelog:
V4 -> V5:
- Rebased L2 pach set onto v3.6-rc7.
- The header file cache-aurora-l2.h was co-located with its only user:
moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
- Removed additional unnecessary blank lines in cache-l2x0.c.

Russell,

will you take the all series from the git repository ? As the last patches have been already acked-by Arnd and were initially pulled by Jason Cooper, I think there should be no problem to get the whole series.

Now if you only want to take the first three patches, will you pull them from the git repository or do you prefer that I submit them through your patch system?

Quoted 9 lines · Gregory CLEMENT

Quoted 7 lines

Changelog:
V4 -> V5:
- Rebased L2 pach set onto v3.6-rc7.
- The header file cache-aurora-l2.h was co-located with its only user:
moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
- Removed additional unnecessary blank lines in cache-l2x0.c.

Russell,

Quoted 8 lines

will you take the all series from the git repository ? As the last patches have been already acked-by Arnd and were initially pulled by Jason Cooper, I think there should be no problem to get the whole series.

Now if you only want to take the first three patches, will you pull them from the git repository or do you prefer that I submit them through your patch system?

Russell,

If you're ok with it, I can take the whole series (incl 1,2,3) through my tree. Or, split it up as we did before (arch/arm/mm changes through you, all else through us).

Gregory,

I'm inclined to make this v3.8 material, especially if pushing it through two different trees. Do you have any objection?

thx,

Jason.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Quoted 25 lines · Jason Cooper

Quoted 9 lines · Gregory CLEMENT

Quoted 7 lines

Changelog:
V4 -> V5:
- Rebased L2 pach set onto v3.6-rc7.
- The header file cache-aurora-l2.h was co-located with its only user:
moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
- Removed additional unnecessary blank lines in cache-l2x0.c.

Russell,

Quoted 8 lines

will you take the all series from the git repository ? As the last patches have been already acked-by Arnd and were initially pulled by Jason Cooper, I think there should be no problem to get the whole series.

Now if you only want to take the first three patches, will you pull them from the git repository or do you prefer that I submit them through your patch system?

Russell,

If you're ok with it, I can take the whole series (incl 1,2,3) through my tree. Or, split it up as we did before (arch/arm/mm changes through you, all else through us).

Quoted 4 lines

Gregory,

I'm inclined to make this v3.8 material, especially if pushing it through two different trees. Do you have any objection?

Well I have pushed this series a long time ago and I have hopped it would have been part of the v3.7.

Quoted 26 lines · Gregory CLEMENT

Quoted 25 lines · Jason Cooper

Quoted 9 lines · Gregory CLEMENT

Quoted 7 lines

Changelog:
V4 -> V5:
- Rebased L2 pach set onto v3.6-rc7.
- The header file cache-aurora-l2.h was co-located with its only user:
moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
- Removed additional unnecessary blank lines in cache-l2x0.c.

Russell,

Quoted 8 lines

will you take the all series from the git repository ? As the last patches have been already acked-by Arnd and were initially pulled by Jason Cooper, I think there should be no problem to get the whole series.

Now if you only want to take the first three patches, will you pull them from the git repository or do you prefer that I submit them through your patch system?

Russell,

If you're ok with it, I can take the whole series (incl 1,2,3) through my tree. Or, split it up as we did before (arch/arm/mm changes through you, all else through us).

Quoted 7 lines

Quoted 4 lines

Gregory,

I'm inclined to make this v3.8 material, especially if pushing it through two different trees. Do you have any objection?

Well I have pushed this series a long time ago and I have hopped it would have been part of the v3.7.

It really hinges on if Russell is ok with keeping the series together. I'd really prefer not to cause the dependency headache this late in the release cycle.

So, if Russell is ok with me taking the whole series, v3.7. If not, v3.8. Fair enough?

thx,

Jason.

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Hello,

This a the 5th version of the patch set (the sixth if we include the RFC). This last series add the ultimate change asked by Russell after his review. See the end of this email for the changelog.

The purpose of this patch set is to add support for Aurora L2 Cache Controller used by Armada 370 and Armada XP SoCs. As it was initially designed by Marvell engineer to be compatible with the ARM L2 Cache Controller, we chose to reuse the existing code and to just extend it to support the differences and improvements brought by the Aurora controller.The diffstat looks like:

 Documentation/devicetree/bindings/arm/l2cc.txt |    9 +
 arch/arm/boot/dts/armada-370.dtsi              |    6 +
 arch/arm/boot/dts/armada-xp.dtsi               |    7 +
 arch/arm/include/asm/hardware/cache-l2x0.h     |    5 +
 arch/arm/mach-mvebu/Kconfig                    |    1 +
 arch/arm/mach-mvebu/irq-armada-370-xp.c        |    4 +
 arch/arm/mm/cache-aurora-l2.h                  |   55 +++++
 arch/arm/mm/cache-l2x0.c                       |  277 +++++++++++++++++++++---
 8 files changed, 336 insertions(+), 28 deletions(-)

The main differences and improvements are:

- no cache id part number available through hardware (need to get it by the DT).
- always write through mode available.
- two flavors of the controller 'outer cache' and 'system cache' (the last one meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line.
- during resume the controller need to restore the ctrl register.

The first patch adds some modifications in the driver infrastructure. As most of the outer cache functions can use the Aurora improvements, we had to introduce new functions. So we thought it was better to use a outer_cache_fns field inside l2x0_of_data and just memcopy it into outer_cache depending of the type of the l2x0 cache.

Changelog:
V4 -> V5:
- Rebased L2 pach set onto v3.6-rc7.
- The header file cache-aurora-l2.h was co-located with its only user:
moved from arch/arm/include/asm/hardware/ to arch/arm/mm/.
- Removed additional unnecessary blank lines in cache-l2x0.c.

V3 -> V4:
- Rebased L2 pach set onto v3.6-rc6.
- The assignment of outer_cache in l2x0_init, don't depend of CONFIG_OF but of variable. The value of this boolean variable is changed in l2x0_of_init. Then, if a system enable CONFIG_OF don't supply a DT file, relying on the old way to initialize the L2 cache, the assignment won't be disable.
- Removed unnecessary check in calc_range_end(). The alignment tested was already made before calling this function.

V2 -> V3:
- Use define instead of literal value for AURORA_CTRL_FW, AURORA_WAY_SIZE_SHIFT, L2X0_WAY_SIZE_SHIFT and L2X0_CTRL_EN.
- Used ALIGN, IS_ALUGNED and PAGE_ALIGN macro instead of bitwise operation.
- Calculate the number of way for Aurora instead of using a switch case.
- removed inaccurate BUG() call and replaced them by a pr_warn if needed.
- In aurora_inv_range round the start and end addresses to cache line size. The initial code was supposed to invalidate partial line cache but actually invalidate the full line, so there was no point to do it outside the aurora_pa_range call.
- Removed the dsb call in the aurora_*_range function: the cache_sync() call inside aurora_pa_range() is enough.
- And as usual tested on Armada 370 and Armada XP boards and ran benchmark without seeing any regression. Results are updated on the wiki page.

V1 -> V2:
- Rebased L2 pach set onto v3.6-rc4.
- Changed the compatible names to be more explicit, from aurora-cache-with-outer to aurora-outer-cache , and from aurora-cache-without-outer to aurora-system-cache.
- Add an isb() after the call to mcr in aurora_broadcast_l2_commands().
- Added the tested and reviewed-by from Lior Amsalem and Yehuda Yitschak.
- Tested on Armada 370 and Armada XP boards and ran benchmark without seeing any regression.

RFC -> V1:
- Rebased the series on to V3.6-rc3
- Added missing Signed-off-by
- Corrected a compilation warning that I have missed
- Ran benchmarks without seeing any regression

Benchmarks results are visible here:
https://github.com/MISL-EBU-System-SW/mainline-public/wiki/Non-official-cache-bench-results-on-the-mainline-Linux-port-%28-kernels-3.6-rcX%29-of-Armada-XP-and-Armada-370

The git branch aurora-L2-cache-ctrl is visible at
https://github.com/MISL-EBU-System-SW/mainline-public.git

Regards,

Gregory

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