Move OMAP2+ over to common clk framework

PATCH Superseded Mike Turquette 8 participants 67 messages Nov 8, 2012 – Nov 15, 2012 3 messages not in the archive Page 2 of 2

Subsystems (7)

Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP power management support +3 more subsystems

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Mike Turquette

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2012-11-08 01:13 UTC #29 lore raw

PATCH v2 26/26 ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts

In reply to Mike Turquette

Clean all #ifdef's added to common clock code. This code is no longer needed due to migration to the common clock framework.

Signed-off-by Mike Turquette <[email protected]>

---
 arch/arm/mach-omap2/clkt_clksel.c       |  238 ----------
 arch/arm/mach-omap2/clkt_dpll.c         |   50 --
 arch/arm/mach-omap2/clkt_iclk.c         |   42 --
 arch/arm/mach-omap2/clock.c             |  778 -------------------------------
 arch/arm/mach-omap2/clock.h             |  221 +--------
 arch/arm/mach-omap2/clock_common_data.c |   20 +-
 6 files changed, 2 insertions(+), 1347 deletions(-)

arch/arm/mach-omap2/clkt_clksel.c +0 ~~-238~~

index 03ceb2e..0ec9f6f 100644
@@ -41,11 +41,7 @@
 
 #include <linux/kernel.h>
 #include <linux/errno.h>
-#ifdef CONFIG_COMMON_CLK
 #include <linux/clk-provider.h>
-#else
-#include <linux/clk.h>
-#endif
 #include <linux/io.h>
 #include <linux/bug.h>

@@ -62,11 +58,7 @@
  * the element associated with the supplied parent clock address.
  * Returns a pointer to the struct clksel on success or NULL on error.
  */
-#ifdef CONFIG_COMMON_CLK
 static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk,
-#else
-static const struct clksel *_get_clksel_by_parent(struct clk *clk,
-#endif
 						  struct clk *src_clk)
 {
 	const struct clksel *clks;

@@ -81,11 +73,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
 	if (!clks->parent) {
 		/* This indicates a data problem */
 		WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
-#ifdef CONFIG_COMMON_CLK
 		     __clk_get_name(clk->hw.clk), __clk_get_name(src_clk));
-#else
-		     __clk_get_name(clk), __clk_get_name(src_clk));
-#endif
 		return NULL;
 	}

@@ -93,66 +81,6 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
 }
 
 /**
- * _get_div_and_fieldval() - find the new clksel divisor and field value to use
- * @src_clk: planned new parent struct clk *
- * @clk: struct clk * that is being reparented
- * @field_val: pointer to a u32 to contain the register data for the divisor
- *
- * Given an intended new parent struct clk * @src_clk, and the struct
- * clk * @clk to the clock that is being reparented, find the
- * appropriate rate divisor for the new clock (returned as the return
- * value), and the corresponding register bitfield data to program to
- * reach that divisor (returned in the u32 pointed to by @field_val).
- * Returns 0 on error, or returns the newly-selected divisor upon
- * success (in this latter case, the corresponding register bitfield
- * value is passed back in the variable pointed to by @field_val)
- */
-#ifndef CONFIG_COMMON_CLK
-static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
-				u32 *field_val)
-{
-	const struct clksel *clks;
-	const struct clksel_rate *clkr, *max_clkr = NULL;
-	u8 max_div = 0;
-
-	clks = _get_clksel_by_parent(clk, src_clk);
-	if (!clks)
-		return 0;
-
-	/*
-	 * Find the highest divisor (e.g., the one resulting in the
-	 * lowest rate) to use as the default.  This should avoid
-	 * clock rates that are too high for the device.  XXX A better
-	 * solution here would be to try to determine if there is a
-	 * divisor matching the original clock rate before the parent
-	 * switch, and if it cannot be found, to fall back to the
-	 * highest divisor.
-	 */
-	for (clkr = clks->rates; clkr->div; clkr++) {
-		if (!(clkr->flags & cpu_mask))
-			continue;
-
-		if (clkr->div > max_div) {
-			max_div = clkr->div;
-			max_clkr = clkr;
-		}
-	}
-
-	if (max_div == 0) {
-		/* This indicates an error in the clksel data */
-		WARN(1, "clock: %s: could not find divisor for parent %s\n",
-		     __clk_get_name(clk),
-		     __clk_get_name(__clk_get_parent(src_clk)));
-		return 0;
-	}
-
-	*field_val = max_clkr->val;
-
-	return max_div;
-}
-#endif
-
-/**
  * _write_clksel_reg() - program a clock's clksel register in hardware
  * @clk: struct clk * to program
  * @v: clksel bitfield value to program (with LSB at bit 0)

@@ -165,11 +93,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
  * take into account any time the hardware might take to switch the
  * clock source.
  */
-#ifdef CONFIG_COMMON_CLK
 static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
-#else
-static void _write_clksel_reg(struct clk *clk, u32 field_val)
-#endif
 {
 	u32 v;

@@ -192,21 +116,13 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val)
  * before calling.  Returns 0 on error or returns the actual integer divisor
  * upon success.
  */
-#ifdef CONFIG_COMMON_CLK
 static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val)
-#else
-static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
-#endif
 {
 	const struct clksel *clks;
 	const struct clksel_rate *clkr;
 	struct clk *parent;
 
-#ifdef CONFIG_COMMON_CLK
 	parent = __clk_get_parent(clk->hw.clk);
-#else
-	parent = __clk_get_parent(clk);
-#endif
 
 	clks = _get_clksel_by_parent(clk, parent);
 	if (!clks)

@@ -223,12 +139,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 	if (!clkr->div) {
 		/* This indicates a data error */
 		WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
-#ifdef CONFIG_COMMON_CLK
 		     __clk_get_name(clk->hw.clk), field_val,
 		     __clk_get_name(parent));
-#else
-		     __clk_get_name(clk), field_val, __clk_get_name(parent));
-#endif
 		return 0;
 	}

@@ -245,11 +157,7 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
  * register field value _before_ left-shifting (i.e., LSB is at bit
  * 0); or returns 0xFFFFFFFF (~0) upon error.
  */
-#ifdef CONFIG_COMMON_CLK
 static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div)
-#else
-static u32 _divisor_to_clksel(struct clk *clk, u32 div)
-#endif
 {
 	const struct clksel *clks;
 	const struct clksel_rate *clkr;

@@ -258,11 +166,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 	/* should never happen */
 	WARN_ON(div == 0);
 
-#ifdef CONFIG_COMMON_CLK
 	parent = __clk_get_parent(clk->hw.clk);
-#else
-	parent = __clk_get_parent(clk);
-#endif
 	clks = _get_clksel_by_parent(clk, parent);
 	if (!clks)
 		return ~0;

@@ -277,12 +181,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 
 	if (!clkr->div) {
 		pr_err("clock: %s: could not find divisor %d for parent %s\n",
-#ifdef CONFIG_COMMON_CLK
 		       __clk_get_name(clk->hw.clk), div,
 		       __clk_get_name(parent));
-#else
-		       __clk_get_name(clk), div, __clk_get_name(parent));
-#endif
 		return ~0;
 	}

@@ -297,11 +197,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
  * into the hardware, convert it into the actual divisor value, and
  * return it; or return 0 on error.
  */
-#ifdef CONFIG_COMMON_CLK
 static u32 _read_divisor(struct clk_hw_omap *clk)
-#else
-static u32 _read_divisor(struct clk *clk)
-#endif
 {
 	u32 v;

@@ -329,12 +225,8 @@ static u32 _read_divisor(struct clk *clk)
  *
  * Returns the rounded clock rate or returns 0xffffffff on error.
  */
-#ifdef CONFIG_COMMON_CLK
 u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
 						 unsigned long target_rate,
-#else
-u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
-#endif
 				u32 *new_div)
 {
 	unsigned long test_rate;

@@ -345,13 +237,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 	unsigned long parent_rate;
 	const char *clk_name;
 
-#ifdef CONFIG_COMMON_CLK
 	parent = __clk_get_parent(clk->hw.clk);
 	clk_name = __clk_get_name(clk->hw.clk);
-#else
-	parent = __clk_get_parent(clk);
-	clk_name = __clk_get_name(clk);
-#endif
 	parent_rate = __clk_get_rate(parent);
 
 	if (!clk->clksel || !clk->clksel_mask)

@@ -402,7 +289,6 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
  * (i.e., those used in struct clk field function pointers, etc.)
  */
 
-#ifdef CONFIG_COMMON_CLK
 /**
  * omap2_clksel_find_parent_index() - return the array index of the current
  * hardware parent of @hw

@@ -457,62 +343,6 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
 	return ret;
 }
 
-#else
-
-/**
- * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
- * @clk: OMAP clock struct ptr to use
- *
- * Given a pointer @clk to a source-selectable struct clk, read the
- * hardware register and determine what its parent is currently set
- * to.  Update @clk's .parent field with the appropriate clk ptr.  No
- * return value.
- */
-void omap2_init_clksel_parent(struct clk *clk)
-{
-	const struct clksel *clks;
-	const struct clksel_rate *clkr;
-	u32 r, found = 0;
-	struct clk *parent;
-	const char *clk_name;
-
-	if (!clk->clksel || !clk->clksel_mask)
-		return;
-
-	parent = __clk_get_parent(clk);
-	clk_name = __clk_get_name(clk);
-
-	r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
-	r >>= __ffs(clk->clksel_mask);
-
-	for (clks = clk->clksel; clks->parent && !found; clks++) {
-		for (clkr = clks->rates; clkr->div && !found; clkr++) {
-			if (!(clkr->flags & cpu_mask))
-				continue;
-
-			if (clkr->val == r) {
-				if (parent != clks->parent) {
-					pr_debug("clock: %s: inited parent to %s (was %s)\n",
-						 clk_name,
-						 __clk_get_name(clks->parent),
-						 ((parent) ?
-						  __clk_get_name(parent) :
-						 "NULL"));
-					clk_reparent(clk, clks->parent);
-				}
-				found = 1;
-			}
-		}
-	}
-
-	/* This indicates a data error */
-	WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
-	     clk_name, r);
-
-	return;
-}
-
-#endif
 
 /**
  * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field

@@ -523,7 +353,6 @@ void omap2_init_clksel_parent(struct clk *clk)
  * function.  Returns the clock's current rate, based on its parent's rate
  * and its current divisor setting in the hardware.
  */
-#ifdef CONFIG_COMMON_CLK
 unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate)
 {
 	unsigned long rate;

@@ -544,26 +373,6 @@ unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate)
 
 	return rate;
 }
-#else
-unsigned long omap2_clksel_recalc(struct clk *clk)
-{
-	unsigned long rate;
-	u32 div = 0;
-	struct clk *parent;
-
-	div = _read_divisor(clk);
-	if (div == 0)
-		return __clk_get_rate(clk);
-
-	parent = __clk_get_parent(clk);
-	rate = __clk_get_rate(parent) / div;
-
-	pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
-		 __clk_get_name(clk), rate, div);
-
-	return rate;
-}
-#endif
 
 /**
  * omap2_clksel_round_rate() - find rounded rate for the given clock and rate

@@ -576,15 +385,10 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
  *
  * Returns the rounded clock rate or returns 0xffffffff on error.
  */
-#ifdef CONFIG_COMMON_CLK
 long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
 			unsigned long *parent_rate)
 {
 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-#else
-long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
-{
-#endif
 	u32 new_div;
 
 	return omap2_clksel_round_rate_div(clk, target_rate, &new_div);

@@ -605,15 +409,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
  * is changed, they will all be affected without any notification.
  * Returns -EINVAL upon error, or 0 upon success.
  */
-#ifdef CONFIG_COMMON_CLK
 int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
 				unsigned long parent_rate)
 {
 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-#else
-int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
-{
-#endif
 	u32 field_val, validrate, new_div = 0;
 
 	if (!clk->clksel || !clk->clksel_mask)

@@ -629,15 +428,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 
 	_write_clksel_reg(clk, field_val);
 
-#ifdef CONFIG_COMMON_CLK
 	pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk),
 		 __clk_get_rate(hw->clk));
-#else
-	pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
-		 __clk_get_rate(clk));
-
-	clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
-#endif
 
 	return 0;
 }

@@ -662,7 +454,6 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
  * affected without any notification.  Returns -EINVAL upon error, or
  * 0 upon success.
  */
-#ifdef CONFIG_COMMON_CLK
 int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val)
 {
 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);

@@ -673,32 +464,3 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val)
 	_write_clksel_reg(clk, field_val);
 	return 0;
 }
-#else
-int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
-{
-	u32 field_val = 0;
-	u32 parent_div;
-
-	if (!clk->clksel || !clk->clksel_mask)
-		return -EINVAL;
-
-	parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
-	if (!parent_div)
-		return -EINVAL;
-	_write_clksel_reg(clk, field_val);
-
-	clk_reparent(clk, new_parent);
-
-	/* CLKSEL clocks follow their parents' rates, divided by a divisor */
-	clk->rate = __clk_get_rate(new_parent);
-
-	if (parent_div > 0)
-		__clk_get_rate(clk) /= parent_div;
-	pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
-		 __clk_get_name(clk),
-		 __clk_get_name(__clk_get_parent(clk)),
-		 __clk_get_rate(clk));
-
-	return 0;
-}
-#endif

arch/arm/mach-omap2/clkt_dpll.c +0 ~~-50~~

128 lines not on this page · raw message

arch/arm/mach-omap2/clkt_iclk.c +0 ~~-42~~

77 lines not on this page · raw message

arch/arm/mach-omap2/clock.c +0 ~~-778~~

855 lines not on this page · raw message

arch/arm/mach-omap2/clock.h +1 ~~-220~~

297 lines not on this page · raw message

arch/arm/mach-omap2/clock_common_data.c +1 ~~-19~~

index c0d02a9..ef4d21b 100644
@@ -16,6 +16,7 @@
  * OMAP3xxx clock definition files.
  */
 
+#include <linux/clk-private.h>
 #include "clock.h"
 
 /* clksel_rate data common to 24xx/343x */

@@ -115,9 +116,6 @@ const struct clksel_rate div31_1to31_rates[] = {
 };
 
 /* Clocks shared between various OMAP SoCs */
-#ifdef CONFIG_COMMON_CLK
-
-#include <linux/clk-private.h>
 
 static struct clk_ops dummy_ck_ops = {};

@@ -126,19 +124,3 @@ struct clk dummy_ck = {
 	.ops = &dummy_ck_ops,
 	.flags = CLK_IS_BASIC,
 };
-
-#else
-
-struct clk virt_19200000_ck = {
-	.name		= "virt_19200000_ck",
-	.ops		= &clkops_null,
-	.rate		= 19200000,
-};
-
-struct clk virt_26000000_ck = {
-	.name		= "virt_26000000_ck",
-	.ops		= &clkops_null,
-	.rate		= 26000000,
-};
-
-#endif

Signature · 1 line

1.7.9.5

Mike Turquette

2012-11-08 01:31 UTC #30 lore raw

v2 cover Move OMAP2+ over to common clk framework

In reply to Mike Turquette

Doh, I got the LAKML address wrong...

Thankfully it's already up on some archives:
http://article.gmane.org/gmane.linux.ports.arm.omap/88824

For anyone interested in testing:
git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8

Regards,
Mike

Quoting Mike Turquette (2012-11-07 17:12:35)

Quoted 120 lines

From: Mike Turquette <[email protected]>
Hi all,
This series is based on top of Paul's PRM/CM clean-up work. It is a refresh of the patches Rajendra sent out a while back[1], with the addition of several fixes for PM regressions[2] across several platforms.
I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF patches (delta is zero) and also suspend/resume.
I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming appears sane. However Panda-ES never comes back from suspend/resume. This problem exists on the PRM/CM branch I based on and was not introduced by this series. I am investigating that independently of this series.
Anyone wanting to pull the work can find it at:
git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8
[1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771
[2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015
Mike Turquette (3):
ARM: OMAP4: clock: Convert to common clk
ARM: OMAP2+: clock: remove unnecessary declarations
ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts
Paul Walmsley (7):
ARM: OMAP2xxx: clock: add APLL rate recalculation functions
ARM: OMAP2+: clock: add OMAP CCF convenience macros to
mach-omap2/clock.h
ARM: AM33XX: clock: add clock data in common clock format
ARM: OMAP44xx: clock: drop obsolete clock data
ARM: OMAP3xxx: clk: drop obsolete clock data
ARM: AM33xx: clock: drop obsolete clock data
ARM: OMAP2xxx: clock: drop obsolete clock data
Rajendra Nayak (15):
ARM: OMAP: clock: Nuke plat/clock.c & reuse struct clk as clk_hw_omap
ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses
ARM: OMAP3: clock: Convert to common clk
ARM: OMAP2: clock: Convert to common clk
ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable
autoidle
ARM: OMAP: clock: Define a function to enable clocks at init
ARM: OMAP: clock: Get rid of some clkdm assocations within clks
ARM: OMAP4: clock: Add 44xx data using common struct clk
ARM: OMAP3: clock: Add 3xxx data using common struct clk
ARM: omap2: clock: Add 24xx data using common struct clk
ARM: OMAP: clock: Switch to COMMON clk
ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP4: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: omap3: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: omap2: clock: Cleanup !CONFIG_COMMON_CLK parts
Vaibhav Hiremath (1):
ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions
 arch/arm/mach-omap2/Kconfig                  |    5 +
 arch/arm/mach-omap2/Makefile                 |   10 +-
 arch/arm/mach-omap2/cclock2420_data.c        | 1959 ++++++++++++++
 arch/arm/mach-omap2/cclock2430_data.c        | 2073 +++++++++++++++
 arch/arm/mach-omap2/cclock33xx_data.c        |  961 +++++++
 arch/arm/mach-omap2/cclock3xxx_data.c        | 3595 +++++++++++++++++++++++++
 arch/arm/mach-omap2/cclock44xx_data.c        | 1991 ++++++++++++++
 arch/arm/mach-omap2/clkt2xxx_apll.c          |   66 +-
 arch/arm/mach-omap2/clkt2xxx_dpll.c          |    8 +-
 arch/arm/mach-omap2/clkt2xxx_dpllcore.c      |   12 +-
 arch/arm/mach-omap2/clkt2xxx_osc.c           |   13 +-
 arch/arm/mach-omap2/clkt2xxx_sys.c           |    7 +-
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c |   11 +-
 arch/arm/mach-omap2/clkt34xx_dpll3m2.c       |    8 +-
 arch/arm/mach-omap2/clkt_clksel.c            |  194 +-
 arch/arm/mach-omap2/clkt_dpll.c              |   28 +-
 arch/arm/mach-omap2/clkt_iclk.c              |   31 +-
 arch/arm/mach-omap2/clock.c                  |  845 ++----
 arch/arm/mach-omap2/clock.h                  |  356 ++-
 arch/arm/mach-omap2/clock2420_data.c         | 1986 --------------
 arch/arm/mach-omap2/clock2430.c              |    8 +-
 arch/arm/mach-omap2/clock2430_data.c         | 2085 ---------------
 arch/arm/mach-omap2/clock2xxx.c              |    1 +
 arch/arm/mach-omap2/clock2xxx.h              |   47 +-
 arch/arm/mach-omap2/clock33xx_data.c         | 1107 --------
 arch/arm/mach-omap2/clock34xx.c              |   51 +-
 arch/arm/mach-omap2/clock3517.c              |   24 +-
 arch/arm/mach-omap2/clock36xx.c              |   22 +-
 arch/arm/mach-omap2/clock36xx.h              |    2 +-
 arch/arm/mach-omap2/clock3xxx.c              |    6 +-
 arch/arm/mach-omap2/clock3xxx.h              |    6 +-
 arch/arm/mach-omap2/clock3xxx_data.c         | 3613 --------------------------
 arch/arm/mach-omap2/clock44xx_data.c         | 3398 ------------------------
 arch/arm/mach-omap2/clock_common_data.c      |   22 +-
 arch/arm/mach-omap2/cm-regbits-24xx.h        |    5 +
 arch/arm/mach-omap2/cm-regbits-34xx.h        |   31 +
 arch/arm/mach-omap2/cm2xxx_3xxx.h            |    1 +
 arch/arm/mach-omap2/dpll3xxx.c               |  226 +-
 arch/arm/mach-omap2/dpll44xx.c               |   21 +-
 arch/arm/mach-omap2/io.c                     |   25 +
 arch/arm/mach-omap2/omap_hwmod.c             |   63 +-
 arch/arm/mach-omap2/pm24xx.c                 |    4 +-
 arch/arm/mach-omap2/prm-regbits-24xx.h       |    2 +
 arch/arm/mach-omap2/prm-regbits-34xx.h       |    1 +
 arch/arm/mach-omap2/prm2xxx_3xxx.h           |    1 +
 arch/arm/mach-omap2/scrm44xx.h               |    2 +
 46 files changed, 11539 insertions(+), 13394 deletions(-)
 create mode 100644 arch/arm/mach-omap2/cclock2420_data.c
 create mode 100644 arch/arm/mach-omap2/cclock2430_data.c
 create mode 100644 arch/arm/mach-omap2/cclock33xx_data.c
 create mode 100644 arch/arm/mach-omap2/cclock3xxx_data.c
 create mode 100644 arch/arm/mach-omap2/cclock44xx_data.c
 delete mode 100644 arch/arm/mach-omap2/clock2420_data.c
 delete mode 100644 arch/arm/mach-omap2/clock2430_data.c
 delete mode 100644 arch/arm/mach-omap2/clock33xx_data.c
 delete mode 100644 arch/arm/mach-omap2/clock3xxx_data.c
 delete mode 100644 arch/arm/mach-omap2/clock44xx_data.c
Signature · 1 line
1.7.9.5

Tony Lindgren

maintainer

2012-11-08 01:42 UTC #31 lore raw

v2 cover Move OMAP2+ over to common clk framework

Hi,

Quoted 5 lines · Mike Turquette

Doh, I got the LAKML address wrong...
Thankfully it's already up on some archives:
http://article.gmane.org/gmane.linux.ports.arm.omap/88824

Quoted 24 lines

For anyone interested in testing:
git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8
Regards,
Mike
Quoting Mike Turquette (2012-11-07 17:12:35)
Quoted 17 lines
From: Mike Turquette <[email protected]>
Hi all,
This series is based on top of Paul's PRM/CM clean-up work. It is a refresh of the patches Rajendra sent out a while back[1], with the addition of several fixes for PM regressions[2] across several platforms.
I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF patches (delta is zero) and also suspend/resume.
I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming appears sane. However Panda-ES never comes back from suspend/resume. This problem exists on the PRM/CM branch I based on and was not introduced by this series. I am investigating that independently of this series.

Cool! Do we still have some omaps that have issues booting with these?

Regards,

Tony

Quoted 5 lines

Quoted 5 lines
Anyone wanting to pull the work can find it at:
git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8
[1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771
[2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015

Mike Turquette

author

2012-11-08 01:54 UTC #32 lore raw

v2 cover Move OMAP2+ over to common clk framework

Quoting Tony Lindgren (2012-11-07 17:42:18)

Quoted 27 lines

Hi,
Quoted 24 lines · Mike Turquette
Doh, I got the LAKML address wrong...
Thankfully it's already up on some archives:
http://article.gmane.org/gmane.linux.ports.arm.omap/88824
For anyone interested in testing:
git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8
Regards,
Mike
Quoting Mike Turquette (2012-11-07 17:12:35)
Quoted 12 lines
From: Mike Turquette <[email protected]>
Hi all,
This series is based on top of Paul's PRM/CM clean-up work. It is a refresh of the patches Rajendra sent out a while back[1], with the addition of several fixes for PM regressions[2] across several platforms.
I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF patches (delta is zero) and also suspend/resume.

Quoted 9 lines

Quoted 5 lines
Quoted 5 lines
I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming appears sane. However Panda-ES never comes back from suspend/resume. This problem exists on the PRM/CM branch I based on and was not introduced by this series. I am investigating that independently of this series.
Cool! Do we still have some omaps that have issues booting with these?

We shouldn't (fingers crossed). I've just now stolen a Beagle and a Bone to test, but I'm going to have to get bootloaders and a userspace all set up for them which will take some time.

I believe Paul is planning on putting this series through his automated test rig.

Regards,
Mike

Quoted 10 lines

Regards,
Tony
Quoted 5 lines
Quoted 5 lines
Anyone wanting to pull the work can find it at:
git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8
[1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771
[2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015

Paul Walmsley

maintainer

2012-11-08 02:50 UTC #33 lore raw

v2 cover Move OMAP2+ over to common clk framework

Quoted 2 lines · Mike Turquette

I believe Paul is planning on putting this series through his automated test rig.

Indeed and this is underway now.

- Paul

Rajendra Nayak

2012-11-08 05:03 UTC #34 lore raw

In reply to Mike Turquette

Quoted 5 lines · Mike Turquette

I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming appears sane. However Panda-ES never comes back from suspend/resume. This problem exists on the PRM/CM branch I based on and was not introduced by this series. I am investigating that independently of this series.

Don't bother. Its been a know issue for a long time now.
http://www.mail-archive.com/[email protected]/msg72056.html

Mike Turquette

author

2012-11-08 05:19 UTC #35 lore raw

Quoting Rajendra Nayak (2012-11-07 21:02:59)

Quoted 9 lines · Mike Turquette

Quoted 5 lines
I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming appears sane. However Panda-ES never comes back from suspend/resume. This problem exists on the PRM/CM branch I based on and was not introduced by this series. I am investigating that independently of this series.
Don't bother. Its been a know issue for a long time now.
http://www.mail-archive.com/[email protected]/msg72056.html

Thanks. I realized that after posting! I think there are fixes posted to the list so I will re-test with those fixes tomorrow.

Regards,
Mike

Kevin Hilman

2012-11-08 19:20 UTC #36 lore raw

Quoted 8 lines · Mike Turquette

Quoting Rajendra Nayak (2012-11-07 21:02:59)
Quoted 7 lines · Mike Turquette
Quoted 5 lines
I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming appears sane. However Panda-ES never comes back from suspend/resume. This problem exists on the PRM/CM branch I based on and was not introduced by this series. I am investigating that independently of this series.

Quoted 5 lines

Quoted 2 lines
Don't bother. Its been a know issue for a long time now.
http://www.mail-archive.com/[email protected]/msg72056.html
Thanks. I realized that after posting! I think there are fixes posted to the list so I will re-test with those fixes tomorrow.

I recently sent a pull request for these:

http://marc.info/?l=linux-omap&m=135224963505956&w=2

With that, suspend/resume is working fine on 4460/Panda-ES.

Kevin

A message that is not in the archive (sent off-list or not yet received): [email protected]

Paul Walmsley

maintainer

2012-11-08 18:08 UTC #38 lore raw

PATCH v2 14/26 ARM: OMAP3: clock: Add 3xxx data using common struct clk

Quoted 6 lines · Mike Turquette

From: Rajendra Nayak <[email protected]>
The patch is the output from a python script which converts from the old OMAP clk format to COMMON clk format using a JSON parser in between which was developed by Paul Walmsley.

Quoted 7 lines

Signed-off-by Rajendra Nayak <[email protected]>
[paul at pwsan.com: AM3517/05: dropped bogus hsotgusb "ick" and "fck"
clkdev aliases; added hsotgusb_fck alias; added emac_ick and emac_fck aliases; replace omap2_init_clksel_parent() with omap2_clksel_find_parent_index(); reflow macros and parent name lists; add clkdm_name argument to DEFINE_STRUCT_CLK_HW_OMAP macros]
Signed-off-by Mike Turquette <[email protected]>

Am seeing warnings during the disable-unused-clocks phase of the boot on the OMAP3 test boards here. Log is included at the bottom of this E-mail, with some debugging added for extra context. The problem appears to be that the clock code is disabling clocks that are active in the hardware, but for which the clockdomain use count is 0, since they've never been enabled.

Ideally there would be some way for the core CCF code to indicate to the underlying clock hardware implementation that the disable-unused-clock process is a 'force disable'. The OMAP clock hardware implementation code could then also put the clockdomain to sleep (and skip the warning) in such a circumstance.

- Paul

[    2.685943] disabling sys_clkout1: ec = 0
[    2.690277] disabling wdt1_ick: ec = 0
[    2.694366] disabling cam_mclk: ec = 0
[    2.698333] ------------[ cut here ]------------
[    2.703216] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 _clkdm_clk_hwmod_disable+0xc4/0xd8()
[    2.712646] Modules linked in:
[    2.715911] [<c001c38c>] (unwind_backtrace+0x0/0xf0) from [<c0043cd8>] (warn_slowpath_common+0x4c/0x64)
[    2.725799] [<c0043cd8>] (warn_slowpath_common+0x4c/0x64) from [<c0043d0c>] (warn_slowpath_null+0x1c/0x24)
[    2.735961] [<c0043d0c>] (warn_slowpath_null+0x1c/0x24) from [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8)
[    2.746520] [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) from [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc)
[    2.757781] [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc) from [<c0437b40>] (clk_disable_unused_subtree+0x20/0xbc)
[    2.769226] ---[ end trace ebefd5468131571a ]---
[    2.774261] disabling mspro_fck: ec = 0
[    2.778320] disabling ssi_ssr_fck_3430es2: ec = 0
[    2.783355] disabling pka_ick: ec = 0
[    2.787231] disabling sad2d_ick: ec = 0
[    2.791259] ------------[ cut here ]------------
[    2.796142] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 _clkdm_clk_hwmod_disable+0xc4/0xd8()
[    2.805572] Modules linked in:
[    2.808807] [<c001c38c>] (unwind_backtrace+0x0/0xf0) from [<c0043cd8>] (warn_slowpath_common+0x4c/0x64)
[    2.818695] [<c0043cd8>] (warn_slowpath_common+0x4c/0x64) from [<c0043d0c>] (warn_slowpath_null+0x1c/0x24)
[    2.828857] [<c0043d0c>] (warn_slowpath_null+0x1c/0x24) from [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8)
[    2.839416] [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) from [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc)
[    2.850677] [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc) from [<c0437b40>] (clk_disable_unused_subtree+0x20/0xbc)
[    2.862121] ---[ end trace ebefd5468131571b ]---
[    2.867065] disabling wdt3_ick: ec = 0
[    2.871032] disabling des1_ick: ec = 0
[    2.875030] disabling sha11_ick: ec = 0
[    2.879089] disabling rng_ick: ec = 0
[    2.882995] disabling aes1_ick: ec = 0
[    2.886932] disabling ssi_ick_3430es2: ec = 0
[    2.891601] disabling mspro_ick: ec = 0
[    2.895660] disabling des2_ick: ec = 0
[    2.899658] disabling sha12_ick: ec = 0
[    2.903686] disabling aes2_ick: ec = 0
[    2.907684] disabling icr_ick: ec = 0
[    2.911621] disabling wdt3_fck: ec = 0

Mike Turquette

author

2012-11-08 21:52 UTC #39 lore raw

PATCH v2 14/26 ARM: OMAP3: clock: Add 3xxx data using common struct clk

Quoting Paul Walmsley (2012-11-08 10:08:16)

Quoted 16 lines · Mike Turquette

Quoted 7 lines
From: Rajendra Nayak <[email protected]>
The patch is the output from a python script which converts from the old OMAP clk format to COMMON clk format using a JSON parser in between which was developed by Paul Walmsley.
Quoted 7 lines
Signed-off-by Rajendra Nayak <[email protected]>
[paul at pwsan.com: AM3517/05: dropped bogus hsotgusb "ick" and "fck"
clkdev aliases; added hsotgusb_fck alias; added emac_ick and emac_fck aliases; replace omap2_init_clksel_parent() with omap2_clksel_find_parent_index(); reflow macros and parent name lists; add clkdm_name argument to DEFINE_STRUCT_CLK_HW_OMAP macros]
Signed-off-by Mike Turquette <[email protected]>

Quoted 7 lines

Am seeing warnings during the disable-unused-clocks phase of the boot on the OMAP3 test boards here. Log is included at the bottom of this E-mail, with some debugging added for extra context. The problem appears to be that the clock code is disabling clocks that are active in the hardware, but for which the clockdomain use count is 0, since they've never been enabled.

Right. The old omap2_disabled_unused_clocks code used to call omap2_clk_enable before calling omap2_clk_disable. That approach is sort of "cooking the books" and the generic implementation in drivers/clk/clk.c simply disables the clocks (without first enabling), which is why these WARNs are new.

Quoted 6 lines

Ideally there would be some way for the core CCF code to indicate to the underlying clock hardware implementation that the disable-unused-clock process is a 'force disable'. The OMAP clock hardware implementation code could then also put the clockdomain to sleep (and skip the warning) in such a circumstance.

I'm looking at a few different ways to do that now.

Regards,
Mike

Quoted 40 lines

- Paul

[    2.685943] disabling sys_clkout1: ec = 0
[    2.690277] disabling wdt1_ick: ec = 0
[    2.694366] disabling cam_mclk: ec = 0
[    2.698333] ------------[ cut here ]------------
[    2.703216] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 _clkdm_clk_hwmod_disable+0xc4/0xd8()
[    2.712646] Modules linked in:
[    2.715911] [<c001c38c>] (unwind_backtrace+0x0/0xf0) from [<c0043cd8>] (warn_slowpath_common+0x4c/0x64)
[    2.725799] [<c0043cd8>] (warn_slowpath_common+0x4c/0x64) from [<c0043d0c>] (warn_slowpath_null+0x1c/0x24)
[    2.735961] [<c0043d0c>] (warn_slowpath_null+0x1c/0x24) from [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8)
[    2.746520] [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) from [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc)
[    2.757781] [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc) from [<c0437b40>] (clk_disable_unused_subtree+0x20/0xbc)
[    2.769226] ---[ end trace ebefd5468131571a ]---
[    2.774261] disabling mspro_fck: ec = 0
[    2.778320] disabling ssi_ssr_fck_3430es2: ec = 0
[    2.783355] disabling pka_ick: ec = 0
[    2.787231] disabling sad2d_ick: ec = 0
[    2.791259] ------------[ cut here ]------------
[    2.796142] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 _clkdm_clk_hwmod_disable+0xc4/0xd8()
[    2.805572] Modules linked in:
[    2.808807] [<c001c38c>] (unwind_backtrace+0x0/0xf0) from [<c0043cd8>] (warn_slowpath_common+0x4c/0x64)
[    2.818695] [<c0043cd8>] (warn_slowpath_common+0x4c/0x64) from [<c0043d0c>] (warn_slowpath_null+0x1c/0x24)
[    2.828857] [<c0043d0c>] (warn_slowpath_null+0x1c/0x24) from [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8)
[    2.839416] [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) from [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc)
[    2.850677] [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc) from [<c0437b40>] (clk_disable_unused_subtree+0x20/0xbc)
[    2.862121] ---[ end trace ebefd5468131571b ]---
[    2.867065] disabling wdt3_ick: ec = 0
[    2.871032] disabling des1_ick: ec = 0
[    2.875030] disabling sha11_ick: ec = 0
[    2.879089] disabling rng_ick: ec = 0
[    2.882995] disabling aes1_ick: ec = 0
[    2.886932] disabling ssi_ick_3430es2: ec = 0
[    2.891601] disabling mspro_ick: ec = 0
[    2.895660] disabling des2_ick: ec = 0
[    2.899658] disabling sha12_ick: ec = 0
[    2.903686] disabling aes2_ick: ec = 0
[    2.907684] disabling icr_ick: ec = 0
[    2.911621] disabling wdt3_fck: ec = 0

Paul Walmsley

maintainer

2012-11-08 22:01 UTC #40 lore raw

PATCH v2 14/26 ARM: OMAP3: clock: Add 3xxx data using common struct clk

In reply to Paul Walmsley

Quoted 2 lines · Paul Walmsley

Am seeing warnings during the disable-unused-clocks phase of the boot on the OMAP3 test boards here.

Similar problems during system suspend on 3530ES3 Beagle. Not sure what's causing these yet. At this point the clockdomain usecounts should be accurate.

- Paul

root at beagleboard:~# echo mem > /sys/power/state

[   36.488800] PM: Syncing filesystems ... done.
[   37.037841] Freezing user space processes ... (elapsed 0.01 seconds) done.
[   37.059600] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
[   37.082885] Suspending console(s) (use no_console_suspend to debug)
[   37.222747] PM: suspend of devices complete after 129.791 msecs
[   37.228057] PM: late suspend of devices complete after 5.310 msecs
[   37.235412] ------------[ cut here ]------------
[   37.235473] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 _clkdm_clk_hwmod_disable+0xc4/0xd8()
[   37.235504] Modules linked in:
[   37.235565] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c00435f8>] (warn_slowpath_common+0x4c/0x64)
[   37.235565] [<c00435f8>] (warn_slowpath_common+0x4c/0x64) from [<c004362c>] (warn_slowpath_null+0x1c/0x24)
[   37.235595] [<c004362c>] (warn_slowpath_null+0x1c/0x24) from [<c003697c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8)
[   37.235626] [<c003697c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) from [<c0437d1c>] (__clk_disable+0x70/0xa8)
[   37.235656] [<c0437d1c>] (__clk_disable+0x70/0xa8) from [<c0437d74>] (clk_disable+0x20/0x34)
[   37.235687] [<c0437d74>] (clk_disable+0x20/0x34) from [<c002a330>] (_disable_clocks+0x18/0x68)
[   37.235717] [<c002a330>] (_disable_clocks+0x18/0x68) from [<c002b09c>] (_idle+0xf8/0x1b4)
[   37.235717] [<c002b09c>] (_idle+0xf8/0x1b4) from [<c002bf08>] (omap_hwmod_idle+0x24/0x40)
[   37.235748] [<c002bf08>] (omap_hwmod_idle+0x24/0x40) from [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c)
[   37.235778] [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c) from [<c002d024>] (_omap_device_deactivate+0x9c/0x138)
[   37.235778] [<c002d024>] (_omap_device_deactivate+0x9c/0x138) from [<c002d984>] (omap_device_idle+0x28/0x54)
[   37.235809] [<c002d984>] (omap_device_idle+0x28/0x54) from [<c002da48>] (_od_suspend_noirq+0x74/0x7c)
[   37.235839] [<c002da48>] (_od_suspend_noirq+0x74/0x7c) from [<c034cbec>] (dpm_run_callback.clone.9+0x30/0xb4)
[   37.235870] [<c034cbec>] (dpm_run_callback.clone.9+0x30/0xb4) from [<c034d440>] (dpm_suspend_end+0x364/0x554)
[   37.235870] [<c034d440>] (dpm_suspend_end+0x364/0x554) from [<c0084ec0>] (suspend_devices_and_enter+0xbc/0x2d0)
[   37.235900] [<c0084ec0>] (suspend_devices_and_enter+0xbc/0x2d0) from [<c0085260>] (pm_suspend+0x18c/0x208)
[   37.235931] [<c0085260>] (pm_suspend+0x18c/0x208) from [<c00844f4>] (state_store+0x120/0x134)
[   37.235961] [<c00844f4>] (state_store+0x120/0x134) from [<c02d29b8>] (kobj_attr_store+0x14/0x20)
[   37.235992] [<c02d29b8>] (kobj_attr_store+0x14/0x20) from [<c017a630>] (sysfs_write_file+0x100/0x184)
[   37.236022] [<c017a630>] (sysfs_write_file+0x100/0x184) from [<c0116630>] (vfs_write+0xb4/0x148)
[   37.236022] [<c0116630>] (vfs_write+0xb4/0x148) from [<c01168b4>] (sys_write+0x40/0x6c)
[   37.236053] [<c01168b4>] (sys_write+0x40/0x6c) from [<c0013ee0>] (ret_fast_syscall+0x0/0x3c)
[   37.236083] ---[ end trace 86835b3ee8ec9dde ]---
[   37.236083] ------------[ cut here ]------------
[   37.236114] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 _clkdm_clk_hwmod_disable+0xc4/0xd8()
[   37.236145] Modules linked in:
[   37.236175] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c00435f8>] (warn_slowpath_common+0x4c/0x64)
[   37.236175] [<c00435f8>] (warn_slowpath_common+0x4c/0x64) from [<c004362c>] (warn_slowpath_null+0x1c/0x24)
[   37.236206] [<c004362c>] (warn_slowpath_null+0x1c/0x24) from [<c003697c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8)
[   37.236236] [<c003697c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) from [<c0437d1c>] (__clk_disable+0x70/0xa8)
[   37.236267] [<c0437d1c>] (__clk_disable+0x70/0xa8) from [<c0437d74>] (clk_disable+0x20/0x34)
[   37.236267] [<c0437d74>] (clk_disable+0x20/0x34) from [<c002a330>] (_disable_clocks+0x18/0x68)
[   37.236297] [<c002a330>] (_disable_clocks+0x18/0x68) from [<c002b09c>] (_idle+0xf8/0x1b4)
[   37.236328] [<c002b09c>] (_idle+0xf8/0x1b4) from [<c002bf08>] (omap_hwmod_idle+0x24/0x40)
[   37.236328] [<c002bf08>] (omap_hwmod_idle+0x24/0x40) from [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c)
[   37.236358] [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c) from [<c002d024>] (_omap_device_deactivate+0x9c/0x138)
[   37.236389] [<c002d024>] (_omap_device_deactivate+0x9c/0x138) from [<c002d984>] (omap_device_idle+0x28/0x54)
[   37.236389] [<c002d984>] (omap_device_idle+0x28/0x54) from [<c002da48>] (_od_suspend_noirq+0x74/0x7c)
[   37.236419] [<c002da48>] (_od_suspend_noirq+0x74/0x7c) from [<c034cbec>] (dpm_run_callback.clone.9+0x30/0xb4)
[   37.236450] [<c034cbec>] (dpm_run_callback.clone.9+0x30/0xb4) from [<c034d440>] (dpm_suspend_end+0x364/0x554)
[   37.236450] [<c034d440>] (dpm_suspend_end+0x364/0x554) from [<c0084ec0>] (suspend_devices_and_enter+0xbc/0x2d0)
[   37.236480] [<c0084ec0>] (suspend_devices_and_enter+0xbc/0x2d0) from [<c0085260>] (pm_suspend+0x18c/0x208)
[   37.236511] [<c0085260>] (pm_suspend+0x18c/0x208) from [<c00844f4>] (state_store+0x120/0x134)
[   37.236541] [<c00844f4>] (state_store+0x120/0x134) from [<c02d29b8>] (kobj_attr_store+0x14/0x20)
[   37.236541] [<c02d29b8>] (kobj_attr_store+0x14/0x20) from [<c017a630>] (sysfs_write_file+0x100/0x184)
[   37.236572] [<c017a630>] (sysfs_write_file+0x100/0x184) from [<c0116630>] (vfs_write+0xb4/0x148)
[   37.236602] [<c0116630>] (vfs_write+0xb4/0x148) from [<c01168b4>] (sys_write+0x40/0x6c)
[   37.236602] [<c01168b4>] (sys_write+0x40/0x6c) from [<c0013ee0>] (ret_fast_syscall+0x0/0x3c)
[   37.236633] ---[ end trace 86835b3ee8ec9ddf ]---
[   37.237213] PM: noirq suspend of devices complete after 9.124 msecs
[   37.237304] Disabling non-boot CPUs ...
[   37.237792] Successfully put all powerdomains to target state
[   37.242034] PM: noirq resume of devices complete after 3.967 msecs
[   37.247161] PM: early resume of devices complete after 3.570 msecs
[   37.536956] PM: resume of devices complete after 289.550 msecs
[   37.815185] Restarting tasks ... done.

root at beagleboard:~#

Paul Walmsley

maintainer

2012-11-09 00:11 UTC #41 lore raw

PATCH v2 14/26 ARM: OMAP3: clock: Add 3xxx data using common struct clk

Quoted 8 lines · Paul Walmsley

Quoted 2 lines · Paul Walmsley
Am seeing warnings during the disable-unused-clocks phase of the boot on the OMAP3 test boards here.
Similar problems during system suspend on 3530ES3 Beagle. Not sure what's causing these yet. At this point the clockdomain usecounts should be accurate.

Here's a redacted debugging log for these cases. The suspend events start around the 30 second mark.

One observation is that dpll4_m5x2_ck and dpll4_m6x2_ck are never enabled. The tracebacks occur when something in the suspend path tries to disable those clocks.

- Paul

[    0.135528] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck
[    0.135559] clockdomain: dpll4_clkdm: enabled
[    0.135589] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[    0.135681] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck
[    0.135681] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck
[    0.135711] clockdomain: dpll4_clkdm: disabled
[    0.135772] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck
[    0.135803] clockdomain: dpll4_clkdm: enabled
[    0.135833] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[    0.135894] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck
[    0.135925] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck
[    0.135955] clockdomain: dpll4_clkdm: disabled
[    0.135986] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck
[    0.136016] clockdomain: dpll4_clkdm: enabled
[    0.136047] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[    0.136138] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck
[    0.136169] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck
[    0.136169] clockdomain: dpll4_clkdm: disabled
[    0.136260] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck
[    0.136291] clockdomain: dpll4_clkdm: enabled
[    0.136322] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[    0.140594] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck
[    0.140686] enabling clkdm dpll4_clkdm during enable of clk dpll4_m3x2_ck
[    0.140838] disabling clkdm dpll4_clkdm during disable of clk dpll4_m3x2_ck
[    0.140930] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck
[    0.141479] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck
[    0.141571] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck
[    0.141601] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck
[    0.141662] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck
[    0.141693] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck
[    0.141784] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck
[    0.141815] enabling clkdm dpll4_clkdm during enable of clk dpll4_m3x2_ck
[    0.141876] disabling clkdm dpll4_clkdm during disable of clk dpll4_m3x2_ck
[    3.399200] disabling clkdm dpll4_clkdm during disable of clk dpll4_m6x2_ck
[    3.417694] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[    3.445251] ---[ end trace 72e2d7bdcf98ea8b ]---
[    3.450134] disabling clkdm dpll4_clkdm during disable of clk dpll4_m5x2_ck
[    3.453918] clockdomain: dpll4_clkdm: disabled
[    3.477569] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[    3.505096] ---[ end trace 72e2d7bdcf98ea8c ]---
[    3.531280] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[    3.558807] ---[ end trace 72e2d7bdcf98ea8d ]---
[   38.999145] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck
[   38.999267] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[   38.999816] ---[ end trace 72e2d7bdcf98ea8e ]---
[   38.999816] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck
[   38.999908] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[   39.000366] ---[ end trace 72e2d7bdcf98ea8f ]---
[   42.169647] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck
[   42.169647] clockdomain: dpll4_clkdm: enabled
[   42.169677] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[   45.730346] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[   45.795654] ---[ end trace 72e2d7bdcf98ea90 ]---

Paul Walmsley

maintainer

2012-11-09 00:33 UTC #42 lore raw

PATCH v2 14/26 ARM: OMAP3: clock: Add 3xxx data using common struct clk

Quoted 3 lines · Paul Walmsley

One observation is that dpll4_m5x2_ck and dpll4_m6x2_ck are never enabled. The tracebacks occur when something in the suspend path tries to disable those clocks.

Sorry, this part is inaccurate - I misread the trace. The suspend path errors are coming from a disable of dpll4_m2x2_ck which is probably caused by the disable of i2c1_fck. Here's the unredacted trace of this section.

The enables and disables of dpll4_m2x2_ck from the entire log appear to be balanced:

[    0.135589] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[    0.135681] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck
[    0.135833] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[    0.135894] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck
[    0.136047] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[    0.136138] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck
[    0.136322] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[   38.999145] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck

- Paul

[   38.986267] PM: suspend of devices complete after 129.760 msecs
[   38.991668] PM: late suspend of devices complete after 5.340 msecs
[   38.996459] disabling clkdm core_l4_clkdm during disable of clk mmchs1_fck
[   38.998718] disabling clkdm per_clkdm during disable of clk uart3_fck
[   38.998840] disabling clkdm core_l4_clkdm during disable of clk uart2_fck
[   38.998931] disabling clkdm core_l4_clkdm during disable of clk uart1_fck
[   38.999114] disabling clkdm core_l4_clkdm during disable of clk i2c1_fck
[   38.999145] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck
[   38.999145] ------------[ cut here ]------------
[   38.999206] WARNING: at arch/arm/mach-omap2/clockdomain.c:962 _clkdm_clk_hwmod_disable+0xa4/0xf8()
[   38.999206] Modules linked in:
[   38.999267] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[   38.999298] [<c0043680>] (warn_slowpath_common+0x4c/0x64) from [<c00436b4>] (warn_slowpath_null+0x1c/0x24)
[   38.999328] [<c00436b4>] (warn_slowpath_null+0x1c/0x24) from [<c003695c>] (_clkdm_clk_hwmod_disable+0xa4/0xf8)
[   38.999359] [<c003695c>] (_clkdm_clk_hwmod_disable+0xa4/0xf8) from [<c0437d38>] (__clk_disable+0x70/0xac)
[   38.999389] [<c0437d38>] (__clk_disable+0x70/0xac) from [<c0437d94>] (clk_disable+0x20/0x34)
[   38.999420] [<c0437d94>] (clk_disable+0x20/0x34) from [<c002a330>] (_disable_clocks+0x18/0x68)
[   38.999420] [<c002a330>] (_disable_clocks+0x18/0x68) from [<c002b09c>] (_idle+0xf8/0x1b4)
[   38.999450] [<c002b09c>] (_idle+0xf8/0x1b4) from [<c002bf08>] (omap_hwmod_idle+0x24/0x40)
[   38.999481] [<c002bf08>] (omap_hwmod_idle+0x24/0x40) from [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c)
[   38.999511] [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c) from [<c002d024>] (_omap_device_deactivate+0x9c/0x138)
[   38.999511] [<c002d024>] (_omap_device_deactivate+0x9c/0x138) from [<c002d984>] (omap_device_idle+0x28/0x54)
[   38.999542] [<c002d984>] (omap_device_idle+0x28/0x54) from [<c002da48>] (_od_suspend_noirq+0x74/0x7c)
[   38.999572] [<c002da48>] (_od_suspend_noirq+0x74/0x7c) from [<c034cc6c>] (dpm_run_callback.clone.9+0x30/0xb4)
[   38.999603] [<c034cc6c>] (dpm_run_callback.clone.9+0x30/0xb4) from [<c034d4c0>] (dpm_suspend_end+0x364/0x554)
[   38.999603] [<c034d4c0>] (dpm_suspend_end+0x364/0x554) from [<c0084f48>] (suspend_devices_and_enter+0xbc/0x2d0)
[   38.999633] [<c0084f48>] (suspend_devices_and_enter+0xbc/0x2d0) from [<c00852e8>] (pm_suspend+0x18c/0x208)
[   38.999664] [<c00852e8>] (pm_suspend+0x18c/0x208) from [<c008457c>] (state_store+0x120/0x134)
[   38.999694] [<c008457c>] (state_store+0x120/0x134) from [<c02d2a38>] (kobj_attr_store+0x14/0x20)
[   38.999725] [<c02d2a38>] (kobj_attr_store+0x14/0x20) from [<c017a6b8>] (sysfs_write_file+0x100/0x184)
[   38.999755] [<c017a6b8>] (sysfs_write_file+0x100/0x184) from [<c01166b8>] (vfs_write+0xb4/0x148)
[   38.999755] [<c01166b8>] (vfs_write+0xb4/0x148) from [<c011693c>] (sys_write+0x40/0x6c)
[   38.999786] [<c011693c>] (sys_write+0x40/0x6c) from [<c0013ee0>] (ret_fast_syscall+0x0/0x3c)
[   38.999816] ---[ end trace 72e2d7bdcf98ea8e ]---
[   38.999816] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck
[   38.999847] ------------[ cut here ]------------
[   38.999847] WARNING: at arch/arm/mach-omap2/clockdomain.c:962 _clkdm_clk_hwmod_disable+0xa4/0xf8()
[   38.999877] Modules linked in:
[   38.999908] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[   38.999938] [<c0043680>] (warn_slowpath_common+0x4c/0x64) from [<c00436b4>] (warn_slowpath_null+0x1c/0x24)
[   38.999938] [<c00436b4>] (warn_slowpath_null+0x1c/0x24) from [<c003695c>] (_clkdm_clk_hwmod_disable+0xa4/0xf8)
[   38.999969] [<c003695c>] (_clkdm_clk_hwmod_disable+0xa4/0xf8) from [<c0437d38>] (__clk_disable+0x70/0xac)
[   38.999999] [<c0437d38>] (__clk_disable+0x70/0xac) from [<c0437d94>] (clk_disable+0x20/0x34)
[   38.999999] [<c0437d94>] (clk_disable+0x20/0x34) from [<c002a330>] (_disable_clocks+0x18/0x68)
[   39.000030] [<c002a330>] (_disable_clocks+0x18/0x68) from [<c002b09c>] (_idle+0xf8/0x1b4)
[   39.000061] [<c002b09c>] (_idle+0xf8/0x1b4) from [<c002bf08>] (omap_hwmod_idle+0x24/0x40)
[   39.000061] [<c002bf08>] (omap_hwmod_idle+0x24/0x40) from [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c)
[   39.000091] [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c) from [<c002d024>] (_omap_device_deactivate+0x9c/0x138)
[   39.000122] [<c002d024>] (_omap_device_deactivate+0x9c/0x138) from [<c002d984>] (omap_device_idle+0x28/0x54)
[   39.000152] [<c002d984>] (omap_device_idle+0x28/0x54) from [<c002da48>] (_od_suspend_noirq+0x74/0x7c)
[   39.000152] [<c002da48>] (_od_suspend_noirq+0x74/0x7c) from [<c034cc6c>] (dpm_run_callback.clone.9+0x30/0xb4)
[   39.000183] [<c034cc6c>] (dpm_run_callback.clone.9+0x30/0xb4) from [<c034d4c0>] (dpm_suspend_end+0x364/0x554)
[   39.000213] [<c034d4c0>] (dpm_suspend_end+0x364/0x554) from [<c0084f48>] (suspend_devices_and_enter+0xbc/0x2d0)
[   39.000213] [<c0084f48>] (suspend_devices_and_enter+0xbc/0x2d0) from [<c00852e8>] (pm_suspend+0x18c/0x208)
[   39.000244] [<c00852e8>] (pm_suspend+0x18c/0x208) from [<c008457c>] (state_store+0x120/0x134)
[   39.000274] [<c008457c>] (state_store+0x120/0x134) from [<c02d2a38>] (kobj_attr_store+0x14/0x20)
[   39.000274] [<c02d2a38>] (kobj_attr_store+0x14/0x20) from [<c017a6b8>] (sysfs_write_file+0x100/0x184)
[   39.000305] [<c017a6b8>] (sysfs_write_file+0x100/0x184) from [<c01166b8>] (vfs_write+0xb4/0x148)
[   39.000335] [<c01166b8>] (vfs_write+0xb4/0x148) from [<c011693c>] (sys_write+0x40/0x6c)
[   39.000366] [<c011693c>] (sys_write+0x40/0x6c) from [<c0013ee0>] (ret_fast_syscall+0x0/0x3c)
[   39.000366] ---[ end trace 72e2d7bdcf98ea8f ]---
[   39.000823] disabling clkdm wkup_clkdm during disable of clk gpio1_ick
[   39.000976] PM: noirq suspend of devices complete after 9.307 msecs
[   39.001068] Disabling non-boot CPUs ...

Paul Walmsley

maintainer

2012-11-09 00:49 UTC #43 lore raw

PATCH v2 14/26 ARM: OMAP3: clock: Add 3xxx data using common struct clk

Quoted 1 line · Paul Walmsley

The enables and disables of dpll4_m2x2_ck from the entire log appear to be balanced:

Looks like this is an artifact of the disable-unused-clocks problem. The disable of dpll4_m6x2_ck during that phase removes the usecount that was previously added by the enable of dpll4_m2x2_ck. So fixing that problem should clean this one up.

- Paul

Mike Turquette

author

2012-11-09 00:57 UTC #44 lore raw

PATCH v2 14/26 ARM: OMAP3: clock: Add 3xxx data using common struct clk

In reply to Paul Walmsley

Quoting Paul Walmsley (2012-11-08 16:11:12)

Quoted 11 lines · Paul Walmsley

Quoted 9 lines · Paul Walmsley
Quoted 3 lines
Am seeing warnings during the disable-unused-clocks phase of the boot on the OMAP3 test boards here.
Similar problems during system suspend on 3530ES3 Beagle. Not sure what's causing these yet. At this point the clockdomain usecounts should be accurate.

Quoted 6 lines

Here's a redacted debugging log for these cases. The suspend events start around the 30 second mark.
One observation is that dpll4_m5x2_ck and dpll4_m6x2_ck are never enabled. The tracebacks occur when something in the suspend path tries to disable those clocks.

Hi Paul,

My instrumentation shows that dpll4_ck & dpll4_m2x2_ck are triggering the WARNs:

[   25.214599] _clkdm_clk_hwmod_disable: dpll4_m2x2_ck
[   25.214599] ------------[ cut here ]------------
[   25.214660] WARNING: at arch/arm/mach-omap2/clockdomain.c:967
_clkdm_clk_hwmod_disable+0xd0/0x118()
...
[   25.215209] _clkdm_clk_hwmod_disable: dpll4_ck
[   25.215209] ------------[ cut here ]------------
[   25.215240] WARNING: at arch/arm/mach-omap2/clockdomain.c:967

_clkdm_clk_hwmod_disable+0xd0/0x118()

Patch that give that information:

arch/arm/mach-omap2/clockdomain.c +7 -3

index 64e5046..a9d5965 100644
@@ -947,7 +947,8 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
 	return 0;
 }
 
-static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
+static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm,
+		struct clk *clk)
 {
 	unsigned long flags;

@@ -957,6 +958,9 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
 	spin_lock_irqsave(&clkdm->lock, flags);
 
 	if (atomic_read(&clkdm->usecount) == 0) {
+		if (clk)
+			pr_err("%s: %s\n", __func__, __clk_get_name(clk));
+
 		spin_unlock_irqrestore(&clkdm->lock, flags);
 		WARN_ON(1); /* underflow */
 		return -ERANGE;

@@ -1026,7 +1030,7 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
 	if (!clk)
 		return -EINVAL;
 
-	return _clkdm_clk_hwmod_disable(clkdm);
+	return _clkdm_clk_hwmod_disable(clkdm, clk);
 }
 
 /**

@@ -1089,6 +1093,6 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
 	if (!oh)
 		return -EINVAL;
 
-	return _clkdm_clk_hwmod_disable(clkdm);
+	return _clkdm_clk_hwmod_disable(clkdm, NULL);
 }

Regards,
Mike

Quoted 57 lines

- Paul

[    0.135528] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck
[    0.135559] clockdomain: dpll4_clkdm: enabled
[    0.135589] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[    0.135681] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck
[    0.135681] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck
[    0.135711] clockdomain: dpll4_clkdm: disabled
[    0.135772] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck
[    0.135803] clockdomain: dpll4_clkdm: enabled
[    0.135833] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[    0.135894] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck
[    0.135925] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck
[    0.135955] clockdomain: dpll4_clkdm: disabled
[    0.135986] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck
[    0.136016] clockdomain: dpll4_clkdm: enabled
[    0.136047] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[    0.136138] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck
[    0.136169] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck
[    0.136169] clockdomain: dpll4_clkdm: disabled
[    0.136260] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck
[    0.136291] clockdomain: dpll4_clkdm: enabled
[    0.136322] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[    0.140594] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck
[    0.140686] enabling clkdm dpll4_clkdm during enable of clk dpll4_m3x2_ck
[    0.140838] disabling clkdm dpll4_clkdm during disable of clk dpll4_m3x2_ck
[    0.140930] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck
[    0.141479] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck
[    0.141571] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck
[    0.141601] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck
[    0.141662] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck
[    0.141693] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck
[    0.141784] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck
[    0.141815] enabling clkdm dpll4_clkdm during enable of clk dpll4_m3x2_ck
[    0.141876] disabling clkdm dpll4_clkdm during disable of clk dpll4_m3x2_ck
[    3.399200] disabling clkdm dpll4_clkdm during disable of clk dpll4_m6x2_ck
[    3.417694] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[    3.445251] ---[ end trace 72e2d7bdcf98ea8b ]---
[    3.450134] disabling clkdm dpll4_clkdm during disable of clk dpll4_m5x2_ck
[    3.453918] clockdomain: dpll4_clkdm: disabled
[    3.477569] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[    3.505096] ---[ end trace 72e2d7bdcf98ea8c ]---
[    3.531280] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[    3.558807] ---[ end trace 72e2d7bdcf98ea8d ]---
[   38.999145] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck
[   38.999267] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[   38.999816] ---[ end trace 72e2d7bdcf98ea8e ]---
[   38.999816] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck
[   38.999908] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[   39.000366] ---[ end trace 72e2d7bdcf98ea8f ]---
[   42.169647] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck
[   42.169647] clockdomain: dpll4_clkdm: enabled
[   42.169677] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck
[   45.730346] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64)
[   45.795654] ---[ end trace 72e2d7bdcf98ea90 ]---

Mike Turquette

author

2012-11-08 23:31 UTC #45 lore raw

PATCH 1/1 ARM: OMAP2+: clockdomain: disabling unused clks

In reply to Paul Walmsley

The OMAP port to the common clk framework[1] resulted in spurious WARNs while disable unused clocks. This is due to _clkdm_clk_hwmod_disable catching clkdm->usecount's with a value of zero. Even less desirable it would not allow the clkdm_clk_disable function pointer to get called due to an early return of -ERANGE.

This patch adds a check for such a corner case by skipping the WARN and early return in the event that clkdm->usecount and clk->enable_usecount are both zero. Presumably this could only happen during the check for unused clocks at boot-time.

[1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824

Signed-off-by Mike Turquette <[email protected]>

---
 arch/arm/mach-omap2/clockdomain.c |   14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

arch/arm/mach-omap2/clockdomain.c +10 -4

index 64e5046..b0c0ce6 100644
@@ -947,16 +947,22 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
 	return 0;
 }
 
-static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
+static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm,
+		struct clk *clk)
 {
 	unsigned long flags;
+	int clk_enable_count = 1;
 
 	if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
 		return -EINVAL;
 
 	spin_lock_irqsave(&clkdm->lock, flags);
 
-	if (atomic_read(&clkdm->usecount) == 0) {
+	/* corner case: disabling unused clocks */
+	if (clk)
+		clk_enable_count = __clk_get_enable_count(clk);
+
+	if (atomic_read(&clkdm->usecount) == 0 && clk_enable_count) {
 		spin_unlock_irqrestore(&clkdm->lock, flags);
 		WARN_ON(1); /* underflow */
 		return -ERANGE;

@@ -1026,7 +1032,7 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
 	if (!clk)
 		return -EINVAL;
 
-	return _clkdm_clk_hwmod_disable(clkdm);
+	return _clkdm_clk_hwmod_disable(clkdm, clk);
 }
 
 /**

@@ -1089,6 +1095,6 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
 	if (!oh)
 		return -EINVAL;
 
-	return _clkdm_clk_hwmod_disable(clkdm);
+	return _clkdm_clk_hwmod_disable(clkdm, NULL);
 }

Signature · 1 line

1.7.9.5

Paul Walmsley

maintainer

2012-11-09 00:58 UTC #46 lore raw

PATCH 1/1 ARM: OMAP2+: clockdomain: disabling unused clks

Quoted 6 lines · Mike Turquette

The OMAP port to the common clk framework[1] resulted in spurious WARNs while disable unused clocks. This is due to _clkdm_clk_hwmod_disable catching clkdm->usecount's with a value of zero. Even less desirable it would not allow the clkdm_clk_disable function pointer to get called due to an early return of -ERANGE.

Quoted 8 lines

This patch adds a check for such a corner case by skipping the WARN and early return in the event that clkdm->usecount and clk->enable_usecount are both zero. Presumably this could only happen during the check for unused clocks at boot-time.
[1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824
Signed-off-by Mike Turquette <[email protected]>

I don't think this is going to work, as it currently stands. The code will just bypass the warning and the error return. The clockdomain usecount still will be decremented, which is going to cause problems since the usecount will be inaccurate.

- Paul

Mike Turquette

author

2012-11-09 01:17 UTC #47 lore raw

PATCH 1/1 ARM: OMAP2+: clockdomain: disabling unused clks

Quoting Paul Walmsley (2012-11-08 16:58:21)

Quoted 13 lines · Mike Turquette

Quoted 12 lines
The OMAP port to the common clk framework[1] resulted in spurious WARNs while disable unused clocks. This is due to _clkdm_clk_hwmod_disable catching clkdm->usecount's with a value of zero. Even less desirable it would not allow the clkdm_clk_disable function pointer to get called due to an early return of -ERANGE.
This patch adds a check for such a corner case by skipping the WARN and early return in the event that clkdm->usecount and clk->enable_usecount are both zero. Presumably this could only happen during the check for unused clocks at boot-time.

Quoted 9 lines

Quoted 3 lines
[1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824
Signed-off-by Mike Turquette <[email protected]>
I don't think this is going to work, as it currently stands. The code will just bypass the warning and the error return. The clockdomain usecount still will be decremented, which is going to cause problems since the usecount will be inaccurate.

You're right. In my rush I glossed over the clkdm decrement part. In light of the suspend/resume issues I'm not sure this approach is really valid. I think getting to the bottom of those issues will give the final word.

Regards,
Mike

Quoted 2 lines

- Paul

Paul Walmsley

maintainer

2012-11-09 19:06 UTC #48 lore raw

PATCH 1/1 ARM: OMAP2+: clockdomain: disabling unused clks

Quoted 4 lines · Mike Turquette

You're right. In my rush I glossed over the clkdm decrement part. In light of the suspend/resume issues I'm not sure this approach is really valid. I think getting to the bottom of those issues will give the final word.

What do you think about something like this? It's still under test and review here, but seems to avoid the warnings on 3530ES3 Beagle at least.

The usage of __clk_get_enable_count() in this code still seems like a hack to me. It would be better for the CCF to call a different clk_hw_ops function pointer for the disable-unused-clocks case. But if you agree, and plan to fix this, or have some other cleaner fix in mind for the near future, then something like this seems reasonable for the short term to me. What do you think?

- Paul

Paul Walmsley

maintainer

2012-11-09 19:08 UTC #49 lore raw

PATCH 1/1 ARM: OMAP2+: clockdomain: disabling unused clks

Quoted 10 lines · Paul Walmsley

Quoted 4 lines · Mike Turquette
You're right. In my rush I glossed over the clkdm decrement part. In light of the suspend/resume issues I'm not sure this approach is really valid. I think getting to the bottom of those issues will give the final word.
What do you think about something like this? It's still under test and review here, but seems to avoid the warnings on 3530ES3 Beagle at least.

Quoted 6 lines

The usage of __clk_get_enable_count() in this code still seems like a hack to me. It would be better for the CCF to call a different clk_hw_ops function pointer for the disable-unused-clocks case. But if you agree, and plan to fix this, or have some other cleaner fix in mind for the near future, then something like this seems reasonable for the short term to me. What do you think?

Here's the patch. The changes to clkdm_clk_disable() are the important ones, the rest can be ignored for the purposes of this review.

- Paul

From: Mike Turquette <[email protected]>
Date: Fri, 9 Nov 2012 11:28:42 -0700
Subject: [PATCH] ARM: OMAP2+: clockdomain: bypass clockdomain handling when
disabling unused clks

[1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824

Signed-off-by Mike Turquette <[email protected]>

[paul at pwsan.com: split the hwmod and clock disable cases; modified the
code to skip the clockdomain handling during the disable-unused-clocks phase]

---
 arch/arm/mach-omap2/clockdomain.c |   91 ++++++++++++++++++++++---------------
 1 file changed, 54 insertions(+), 37 deletions(-)

arch/arm/mach-omap2/clockdomain.c +54 ~~-37~~

index 64e5046..1bd0ff0 100644
@@ -22,6 +22,7 @@
 #include <linux/clk.h>
 #include <linux/limits.h>
 #include <linux/err.h>
+#include <linux/clk-private.h>
 
 #include <linux/io.h>

@@ -947,35 +948,6 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
 	return 0;
 }
 
-static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
-{
-	unsigned long flags;
-
-	if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
-		return -EINVAL;
-
-	spin_lock_irqsave(&clkdm->lock, flags);
-
-	if (atomic_read(&clkdm->usecount) == 0) {
-		spin_unlock_irqrestore(&clkdm->lock, flags);
-		WARN_ON(1); /* underflow */
-		return -ERANGE;
-	}
-
-	if (atomic_dec_return(&clkdm->usecount) > 0) {
-		spin_unlock_irqrestore(&clkdm->lock, flags);
-		return 0;
-	}
-
-	arch_clkdm->clkdm_clk_disable(clkdm);
-	pwrdm_state_switch(clkdm->pwrdm.ptr);
-	spin_unlock_irqrestore(&clkdm->lock, flags);
-
-	pr_debug("clockdomain: %s: disabled\n", clkdm->name);
-
-	return 0;
-}
-
 /**
  * clkdm_clk_enable - add an enabled downstream clock to this clkdm
  * @clkdm: struct clockdomain *

@@ -1018,15 +990,39 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
  */
 int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
 {
-	/*
-	 * XXX Rewrite this code to maintain a list of enabled
-	 * downstream clocks for debugging purposes?
-	 */
+	unsigned long flags;
+	int force_disable = 0;
 
-	if (!clk)
+	if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
 		return -EINVAL;
 
-	return _clkdm_clk_hwmod_disable(clkdm);
+	spin_lock_irqsave(&clkdm->lock, flags);
+
+	/* corner case: disabling unused clocks */
+	force_disable = (__clk_get_enable_count(clk) == 0) ? 1 : 0;
+	if (force_disable)
+		goto ccd_exit;
+
+	if (atomic_read(&clkdm->usecount) == 0) {
+		spin_unlock_irqrestore(&clkdm->lock, flags);
+		WARN_ON(1); /* underflow */
+		return -ERANGE;
+	}
+
+	if (atomic_dec_return(&clkdm->usecount) > 0) {
+		spin_unlock_irqrestore(&clkdm->lock, flags);
+		return 0;
+	}
+
+	arch_clkdm->clkdm_clk_disable(clkdm);
+	pwrdm_state_switch(clkdm->pwrdm.ptr);
+
+	pr_debug("clockdomain: %s: disabled\n", clkdm->name);
+
+ccd_exit:
+	spin_unlock_irqrestore(&clkdm->lock, flags);
+
+	return 0;
 }
 
 /**

@@ -1077,6 +1073,8 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
  */
 int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
 {
+	unsigned long flags;
+
 	/* The clkdm attribute does not exist yet prior OMAP4 */
 	if (cpu_is_omap24xx() || cpu_is_omap34xx())
 		return 0;

@@ -1086,9 +1084,28 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
 	 * downstream hwmods for debugging purposes?
 	 */
 
-	if (!oh)
+	if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
 		return -EINVAL;
 
-	return _clkdm_clk_hwmod_disable(clkdm);
+	spin_lock_irqsave(&clkdm->lock, flags);
+
+	if (atomic_read(&clkdm->usecount) == 0) {
+		spin_unlock_irqrestore(&clkdm->lock, flags);
+		WARN_ON(1); /* underflow */
+		return -ERANGE;
+	}
+
+	if (atomic_dec_return(&clkdm->usecount) > 0) {
+		spin_unlock_irqrestore(&clkdm->lock, flags);
+		return 0;
+	}
+
+	arch_clkdm->clkdm_clk_disable(clkdm);
+	pwrdm_state_switch(clkdm->pwrdm.ptr);
+	spin_unlock_irqrestore(&clkdm->lock, flags);
+
+	pr_debug("clockdomain: %s: disabled\n", clkdm->name);
+
+	return 0;
 }

Signature · 1 line

1.7.10.4

Mike Turquette

author

2012-11-09 19:40 UTC #50 lore raw

PATCH 1/1 ARM: OMAP2+: clockdomain: disabling unused clks

Quoting Paul Walmsley (2012-11-09 11:08:00)

Quoted 12 lines · Paul Walmsley

Quoted 11 lines · Mike Turquette
Quoted 5 lines
You're right. In my rush I glossed over the clkdm decrement part. In light of the suspend/resume issues I'm not sure this approach is really valid. I think getting to the bottom of those issues will give the final word.
What do you think about something like this? It's still under test and review here, but seems to avoid the warnings on 3530ES3 Beagle at least.

Quoted 7 lines

Quoted 6 lines
The usage of __clk_get_enable_count() in this code still seems like a hack to me. It would be better for the CCF to call a different clk_hw_ops function pointer for the disable-unused-clocks case. But if you agree, and plan to fix this, or have some other cleaner fix in mind for the near future, then something like this seems reasonable for the short term to me. What do you think?

For avoiding the WARNs, this seems fine to me. And I agree that a new clk_ops function pointer is needed. Maybe something like,

void (*unused_disable)(struct clk_hw *hw);

But I'm OK with the below patch in the short term. I just have one
question: did you observe any PM regressions by skipping the clkdm programming?

Thanks,
Mike

Quoted 167 lines

Here's the patch. The changes to clkdm_clk_disable() are the important ones, the rest can be ignored for the purposes of this review.

- Paul

From: Mike Turquette <[email protected]>
Date: Fri, 9 Nov 2012 11:28:42 -0700
Subject: [PATCH] ARM: OMAP2+: clockdomain: bypass clockdomain handling when
disabling unused clks

[1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824

Signed-off-by Mike Turquette <[email protected]>

[paul at pwsan.com: split the hwmod and clock disable cases; modified the
code to skip the clockdomain handling during the disable-unused-clocks phase]

---
 arch/arm/mach-omap2/clockdomain.c |   91 ++++++++++++++++++++++---------------
 1 file changed, 54 insertions(+), 37 deletions(-)

arch/arm/mach-omap2/clockdomain.c +54 ~~-37~~

index 64e5046..1bd0ff0 100644
@@ -22,6 +22,7 @@
 #include <linux/clk.h>
 #include <linux/limits.h>
 #include <linux/err.h>
+#include <linux/clk-private.h>
 
 #include <linux/io.h>

@@ -947,35 +948,6 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
        return 0;
 }
 
-static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
-{
-       unsigned long flags;
-
-       if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
-               return -EINVAL;
-
-       spin_lock_irqsave(&clkdm->lock, flags);
-
-       if (atomic_read(&clkdm->usecount) == 0) {
-               spin_unlock_irqrestore(&clkdm->lock, flags);
-               WARN_ON(1); /* underflow */
-               return -ERANGE;
-       }
-
-       if (atomic_dec_return(&clkdm->usecount) > 0) {
-               spin_unlock_irqrestore(&clkdm->lock, flags);
-               return 0;
-       }
-
-       arch_clkdm->clkdm_clk_disable(clkdm);
-       pwrdm_state_switch(clkdm->pwrdm.ptr);
-       spin_unlock_irqrestore(&clkdm->lock, flags);
-
-       pr_debug("clockdomain: %s: disabled\n", clkdm->name);
-
-       return 0;
-}
-
 /**
  * clkdm_clk_enable - add an enabled downstream clock to this clkdm
  * @clkdm: struct clockdomain *

@@ -1018,15 +990,39 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
  */
 int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
 {
-       /*
-        * XXX Rewrite this code to maintain a list of enabled
-        * downstream clocks for debugging purposes?
-        */
+       unsigned long flags;
+       int force_disable = 0;
 
-       if (!clk)
+       if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
                return -EINVAL;
 
-       return _clkdm_clk_hwmod_disable(clkdm);
+       spin_lock_irqsave(&clkdm->lock, flags);
+
+       /* corner case: disabling unused clocks */
+       force_disable = (__clk_get_enable_count(clk) == 0) ? 1 : 0;
+       if (force_disable)
+               goto ccd_exit;
+
+       if (atomic_read(&clkdm->usecount) == 0) {
+               spin_unlock_irqrestore(&clkdm->lock, flags);
+               WARN_ON(1); /* underflow */
+               return -ERANGE;
+       }
+
+       if (atomic_dec_return(&clkdm->usecount) > 0) {
+               spin_unlock_irqrestore(&clkdm->lock, flags);
+               return 0;
+       }
+
+       arch_clkdm->clkdm_clk_disable(clkdm);
+       pwrdm_state_switch(clkdm->pwrdm.ptr);
+
+       pr_debug("clockdomain: %s: disabled\n", clkdm->name);
+
+ccd_exit:
+       spin_unlock_irqrestore(&clkdm->lock, flags);
+
+       return 0;
 }
 
 /**

@@ -1077,6 +1073,8 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
  */
 int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
 {
+       unsigned long flags;
+
        /* The clkdm attribute does not exist yet prior OMAP4 */
        if (cpu_is_omap24xx() || cpu_is_omap34xx())
                return 0;

@@ -1086,9 +1084,28 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
         * downstream hwmods for debugging purposes?
         */
 
-       if (!oh)
+       if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
                return -EINVAL;
 
-       return _clkdm_clk_hwmod_disable(clkdm);
+       spin_lock_irqsave(&clkdm->lock, flags);
+
+       if (atomic_read(&clkdm->usecount) == 0) {
+               spin_unlock_irqrestore(&clkdm->lock, flags);
+               WARN_ON(1); /* underflow */
+               return -ERANGE;
+       }
+
+       if (atomic_dec_return(&clkdm->usecount) > 0) {
+               spin_unlock_irqrestore(&clkdm->lock, flags);
+               return 0;
+       }
+
+       arch_clkdm->clkdm_clk_disable(clkdm);
+       pwrdm_state_switch(clkdm->pwrdm.ptr);
+       spin_unlock_irqrestore(&clkdm->lock, flags);
+
+       pr_debug("clockdomain: %s: disabled\n", clkdm->name);
+
+       return 0;
 }

Signature · 1 line

1.7.10.4

Paul Walmsley

maintainer

2012-11-09 19:52 UTC #51 lore raw

PATCH 1/1 ARM: OMAP2+: clockdomain: disabling unused clks

Quoted 3 lines · Mike Turquette

But I'm OK with the below patch in the short term. I just have one
question: did you observe any PM regressions by skipping the clkdm programming?

It's still under test here but 3530ES3 Beagle passed the PM tests with it, with no obvious warnings.

- Paul

Paul Walmsley

maintainer

2012-11-09 20:53 UTC #52 lore raw

PATCH 1/1 ARM: OMAP2+: clockdomain: disabling unused clks

Quoted 8 lines · Paul Walmsley

Quoted 3 lines · Mike Turquette
But I'm OK with the below patch in the short term. I just have one
question: did you observe any PM regressions by skipping the clkdm programming?
It's still under test here but 3530ES3 Beagle passed the PM tests with it, with no obvious warnings.

OK I'm satisfied with this general fix. Will have to break it up into pieces and move it earlier in the patch stack to ensure that PM doesn't break in the middle of the series, but the idea seems reasonably sound for short-term use. A clock should only be disabled during the disable-unused-clocks phase if its usecount is zero and it's enabled in the hardware. As far as I can tell, this can only happen when the clock is enabled by the bootloader/ROM code/PPA, and never touched by the kernel before the disable-unused-clocks phase. The only regression cases that come to mind at the moment are:

1. CONFIG_PM=n and a clockdomain only contains unused clocks; or

2. CONFIG_PM=y and a clockdomain only contains unused clocks and that same clockdomain does not support hardware-supervised autoidle or force-idle

In those cases, I'd assume the clockdomain would effectively get stuck on. #1 we don't really care about since CONFIG_PM=n anyway. #2 is more of a concern but it should disappear completely once hwmods are present for all of the IP blocks on the device. (The presence of the hwmods will ensure that every clock that matters from an idle-management perspective is enabled at least once when the IP block is reset.) For this reason, it's important to note that when the hwmod reset code is moved to run late in the boot process, it will have to run before the unused clocks are disabled.

One nice side-effect of this bug is that it highlighted that we're still missing OMAP3 hwmods for the camera subsystem, and that the reset code for the SAD2D module needs to be moved out of arch/arm/mach-omap2/pm34xx.c:omap3_d2d_idle() and into something that can be called from the hwmod reset code.

- Paul

Vaibhav Hiremath

2012-11-08 19:04 UTC #53 lore raw

In reply to Mike Turquette

Quoted 109 lines · Mike Turquette

From: Mike Turquette <[email protected]>
Hi all,
This series is based on top of Paul's PRM/CM clean-up work. It is a refresh of the patches Rajendra sent out a while back[1], with the addition of several fixes for PM regressions[2] across several platforms.
I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF patches (delta is zero) and also suspend/resume.
I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming appears sane. However Panda-ES never comes back from suspend/resume. This problem exists on the PRM/CM branch I based on and was not introduced by this series. I am investigating that independently of this series.
Anyone wanting to pull the work can find it at:
git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8
[1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771
[2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015
Mike Turquette (3):
ARM: OMAP4: clock: Convert to common clk
ARM: OMAP2+: clock: remove unnecessary declarations
ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts
Paul Walmsley (7):
ARM: OMAP2xxx: clock: add APLL rate recalculation functions
ARM: OMAP2+: clock: add OMAP CCF convenience macros to
mach-omap2/clock.h
ARM: AM33XX: clock: add clock data in common clock format
ARM: OMAP44xx: clock: drop obsolete clock data
ARM: OMAP3xxx: clk: drop obsolete clock data
ARM: AM33xx: clock: drop obsolete clock data
ARM: OMAP2xxx: clock: drop obsolete clock data
Rajendra Nayak (15):
ARM: OMAP: clock: Nuke plat/clock.c & reuse struct clk as clk_hw_omap
ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses
ARM: OMAP3: clock: Convert to common clk
ARM: OMAP2: clock: Convert to common clk
ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable
autoidle
ARM: OMAP: clock: Define a function to enable clocks at init
ARM: OMAP: clock: Get rid of some clkdm assocations within clks
ARM: OMAP4: clock: Add 44xx data using common struct clk
ARM: OMAP3: clock: Add 3xxx data using common struct clk
ARM: omap2: clock: Add 24xx data using common struct clk
ARM: OMAP: clock: Switch to COMMON clk
ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP4: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: omap3: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: omap2: clock: Cleanup !CONFIG_COMMON_CLK parts
Vaibhav Hiremath (1):
ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions
 arch/arm/mach-omap2/Kconfig                  |    5 +
 arch/arm/mach-omap2/Makefile                 |   10 +-
 arch/arm/mach-omap2/cclock2420_data.c        | 1959 ++++++++++++++
 arch/arm/mach-omap2/cclock2430_data.c        | 2073 +++++++++++++++
 arch/arm/mach-omap2/cclock33xx_data.c        |  961 +++++++
 arch/arm/mach-omap2/cclock3xxx_data.c        | 3595 +++++++++++++++++++++++++
 arch/arm/mach-omap2/cclock44xx_data.c        | 1991 ++++++++++++++
 arch/arm/mach-omap2/clkt2xxx_apll.c          |   66 +-
 arch/arm/mach-omap2/clkt2xxx_dpll.c          |    8 +-
 arch/arm/mach-omap2/clkt2xxx_dpllcore.c      |   12 +-
 arch/arm/mach-omap2/clkt2xxx_osc.c           |   13 +-
 arch/arm/mach-omap2/clkt2xxx_sys.c           |    7 +-
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c |   11 +-
 arch/arm/mach-omap2/clkt34xx_dpll3m2.c       |    8 +-
 arch/arm/mach-omap2/clkt_clksel.c            |  194 +-
 arch/arm/mach-omap2/clkt_dpll.c              |   28 +-
 arch/arm/mach-omap2/clkt_iclk.c              |   31 +-
 arch/arm/mach-omap2/clock.c                  |  845 ++----
 arch/arm/mach-omap2/clock.h                  |  356 ++-
 arch/arm/mach-omap2/clock2420_data.c         | 1986 --------------
 arch/arm/mach-omap2/clock2430.c              |    8 +-
 arch/arm/mach-omap2/clock2430_data.c         | 2085 ---------------
 arch/arm/mach-omap2/clock2xxx.c              |    1 +
 arch/arm/mach-omap2/clock2xxx.h              |   47 +-
 arch/arm/mach-omap2/clock33xx_data.c         | 1107 --------
 arch/arm/mach-omap2/clock34xx.c              |   51 +-
 arch/arm/mach-omap2/clock3517.c              |   24 +-
 arch/arm/mach-omap2/clock36xx.c              |   22 +-
 arch/arm/mach-omap2/clock36xx.h              |    2 +-
 arch/arm/mach-omap2/clock3xxx.c              |    6 +-
 arch/arm/mach-omap2/clock3xxx.h              |    6 +-
 arch/arm/mach-omap2/clock3xxx_data.c         | 3613 --------------------------
 arch/arm/mach-omap2/clock44xx_data.c         | 3398 ------------------------
 arch/arm/mach-omap2/clock_common_data.c      |   22 +-
 arch/arm/mach-omap2/cm-regbits-24xx.h        |    5 +
 arch/arm/mach-omap2/cm-regbits-34xx.h        |   31 +
 arch/arm/mach-omap2/cm2xxx_3xxx.h            |    1 +
 arch/arm/mach-omap2/dpll3xxx.c               |  226 +-
 arch/arm/mach-omap2/dpll44xx.c               |   21 +-
 arch/arm/mach-omap2/io.c                     |   25 +
 arch/arm/mach-omap2/omap_hwmod.c             |   63 +-
 arch/arm/mach-omap2/pm24xx.c                 |    4 +-
 arch/arm/mach-omap2/prm-regbits-24xx.h       |    2 +
 arch/arm/mach-omap2/prm-regbits-34xx.h       |    1 +
 arch/arm/mach-omap2/prm2xxx_3xxx.h           |    1 +
 arch/arm/mach-omap2/scrm44xx.h               |    2 +
 46 files changed, 11539 insertions(+), 13394 deletions(-)
 create mode 100644 arch/arm/mach-omap2/cclock2420_data.c
 create mode 100644 arch/arm/mach-omap2/cclock2430_data.c

Quoted 9 lines

 create mode 100644 arch/arm/mach-omap2/cclock33xx_data.c
 create mode 100644 arch/arm/mach-omap2/cclock3xxx_data.c
 create mode 100644 arch/arm/mach-omap2/cclock44xx_data.c
 delete mode 100644 arch/arm/mach-omap2/clock2420_data.c
 delete mode 100644 arch/arm/mach-omap2/clock2430_data.c
 delete mode 100644 arch/arm/mach-omap2/clock33xx_data.c
 delete mode 100644 arch/arm/mach-omap2/clock3xxx_data.c
 delete mode 100644 arch/arm/mach-omap2/clock44xx_data.c

Thanks Mike for the patches.
Just boot tested it on BeagleBone Platform, and it is booting up fine for me without any issues. Also I did some basic clk_rate check, and it came out well.

Anyway, I will try to review it tomorrow (if time permits).

Thanks,
Vaibhav

A message that is not in the archive (sent off-list or not yet received): [email protected]

Paul Walmsley

maintainer

2012-11-09 20:32 UTC #56 lore raw

PATCH v2 15/26 ARM: omap2: clock: Add 24xx data using common struct clk

Here's another update on this one to add the twl.fck clock alias, recently added by commit defa6be1c8216ed2d52d65db81a8a148e73be5f7 ("mfd: Fix compile for twl-core.c by removing cpu_is_omap usage").

- Paul

From: Rajendra Nayak <[email protected]>
Date: Wed, 7 Nov 2012 21:09:35 -0700
Subject: [PATCH] ARM: OMAP2: clock: Add 24xx data using common struct clk

The patch is the output from a python script which converts from the old OMAP clk format to COMMON clk format using a JSON parser in between which was developed by Paul Walmsley.

Signed-off-by Rajendra Nayak <[email protected]>

[paul at pwsan.com: replace omap2_init_clksel_parent() with
omap2_clksel_find_parent_index(); reflowed macros; dropped 243x clkdev aliases in 242x file; added recalc_rate fn ptrs to APLL clocks; fixed some checkpatch warnings]

[mturquette at ti.com: removed deprecated variables from omap24x0_clk_init]

Signed-off-by Mike Turquette <[email protected]>

[paul at pwsan.com: fixed boot crash due to missing clock init code; added twl.fck
alias]

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/cclock2420_data.c  | 1962 ++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/cclock2430_data.c  | 2076 ++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/cm-regbits-24xx.h  |    5 +
 arch/arm/mach-omap2/prm-regbits-24xx.h |    2 +
 4 files changed, 4045 insertions(+)
 create mode 100644 arch/arm/mach-omap2/cclock2420_data.c
 create mode 100644 arch/arm/mach-omap2/cclock2430_data.c

arch/arm/mach-omap2/cclock2420_data.c new file +1962 -0

new file mode 100644
index 0000000..f1ee478
@@ -0,0 +1,1962 @@
+/*
+ * OMAP2420 clock data
+ *
+ * Copyright (C) 2005-2012 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <[email protected]>
+ * Paul Walmsley
+ * Updated to COMMON clk format by Rajendra Nayak <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/list.h>
+
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm2xxx.h"
+#include "prm2xxx.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "control.h"
+
+#define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
+
+/*
+ * 2420 clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ *	many cases the parent is selectable. The set parent calls will
+ *	also switch sources.
+ *
+ *	Several sources are given initial rates which may be wrong, this will
+ *	be fixed up in the init func.
+ *
+ *	Things are broadly separated below by clock domains. It is
+ *	noteworthy that most peripherals have dependencies on multiple clock
+ *	domains. Many get their interface clocks from the L4 domain, but get
+ *	functional clocks from fixed sources or other core domain derived
+ *	clocks.
+ */
+
+DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
+
+static struct clk osc_ck;
+
+static const struct clk_ops osc_ck_ops = {
+	.recalc_rate	= &omap2_osc_clk_recalc,
+};
+
+static struct clk_hw_omap osc_ck_hw = {
+	.hw = {
+		.clk = &osc_ck,
+	},
+};
+
+static struct clk osc_ck = {
+	.name	= "osc_ck",
+	.ops	= &osc_ck_ops,
+	.hw	= &osc_ck_hw.hw,
+	.flags	= CLK_IS_ROOT,
+};
+
+DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+static struct clk sys_ck;
+
+static const char *sys_ck_parent_names[] = {
+	"osc_ck",
+};
+
+static const struct clk_ops sys_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.recalc_rate	= &omap2xxx_sys_clk_recalc,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
+
+static struct dpll_data dpll_dd = {
+	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+	.mult_mask	= OMAP24XX_DPLL_MULT_MASK,
+	.div1_mask	= OMAP24XX_DPLL_DIV_MASK,
+	.clk_bypass	= &sys_ck,
+	.clk_ref	= &sys_ck,
+	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+	.enable_mask	= OMAP24XX_EN_DPLL_MASK,
+	.max_multiplier	= 1023,
+	.min_divider	= 1,
+	.max_divider	= 16,
+};
+
+static struct clk dpll_ck;
+
+static const char *dpll_ck_parent_names[] = {
+	"sys_ck",
+};
+
+static const struct clk_ops dpll_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap2_dpllcore_recalc,
+	.round_rate	= &omap2_dpll_round_rate,
+	.set_rate	= &omap2_reprogram_dpllcore,
+};
+
+static struct clk_hw_omap dpll_ck_hw = {
+	.hw = {
+		.clk = &dpll_ck,
+	},
+	.ops		= &clkhwops_omap2xxx_dpll,
+	.dpll_data	= &dpll_dd,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
+
+static struct clk core_ck;
+
+static const char *core_ck_parent_names[] = {
+	"dpll_ck",
+};
+
+static const struct clk_ops core_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
+
+DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
+		   OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+		   OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
+		   CLK_DIVIDER_ONE_BASED, NULL);
+
+DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
+		   OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+		   OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
+		   CLK_DIVIDER_ONE_BASED, NULL);
+
+static struct clk aes_ick;
+
+static const char *aes_ick_parent_names[] = {
+	"l4_ck",
+};
+
+static const struct clk_ops aes_ick_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+static struct clk_hw_omap aes_ick_hw = {
+	.hw = {
+		.clk = &aes_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+	.enable_bit	= OMAP24XX_EN_AES_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk apll54_ck;
+
+static const struct clk_ops apll54_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_clk_apll54_enable,
+	.disable	= &omap2_clk_apll_disable,
+	.recalc_rate	= &omap2_clk_apll54_recalc,
+};
+
+static struct clk_hw_omap apll54_ck_hw = {
+	.hw = {
+		.clk = &apll54_ck,
+	},
+	.ops		= &clkhwops_apll54,
+	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+	.enable_bit	= OMAP24XX_EN_54M_PLL_SHIFT,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
+
+static struct clk apll96_ck;
+
+static const struct clk_ops apll96_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_clk_apll96_enable,
+	.disable	= &omap2_clk_apll_disable,
+	.recalc_rate	= &omap2_clk_apll96_recalc,
+};
+
+static struct clk_hw_omap apll96_ck_hw = {
+	.hw = {
+		.clk = &apll96_ck,
+	},
+	.ops		= &clkhwops_apll96,
+	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+	.enable_bit	= OMAP24XX_EN_96M_PLL_SHIFT,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
+
+static struct clk func_96m_ck;
+
+static const char *func_96m_ck_parent_names[] = {
+	"apll96_ck",
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops);
+
+static struct clk cam_fck;
+
+static const char *cam_fck_parent_names[] = {
+	"func_96m_ck",
+};
+
+static struct clk_hw_omap cam_fck_hw = {
+	.hw = {
+		.clk = &cam_fck,
+	},
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_CAM_SHIFT,
+	.clkdm_name	= "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk cam_ick;
+
+static struct clk_hw_omap cam_ick_hw = {
+	.hw = {
+		.clk = &cam_ick,
+	},
+	.ops		= &clkhwops_iclk,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_CAM_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk des_ick;
+
+static struct clk_hw_omap des_ick_hw = {
+	.hw = {
+		.clk = &des_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+	.enable_bit	= OMAP24XX_EN_DES_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate dsp_fck_core_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
+	{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
+	{ .div = 6, .val = 6, .flags = RATE_IN_242X },
+	{ .div = 8, .val = 8, .flags = RATE_IN_242X },
+	{ .div = 12, .val = 12, .flags = RATE_IN_242X },
+	{ .div = 0 }
+};
+
+static const struct clksel dsp_fck_clksel[] = {
+	{ .parent = &core_ck, .rates = dsp_fck_core_rates },
+	{ .parent = NULL },
+};
+
+static const char *dsp_fck_parent_names[] = {
+	"core_ck",
+};
+
+static const struct clk_ops dsp_fck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+	.recalc_rate	= &omap2_clksel_recalc,
+	.set_rate	= &omap2_clksel_set_rate,
+	.round_rate	= &omap2_clksel_round_rate,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
+			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+			 OMAP24XX_CLKSEL_DSP_MASK,
+			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+			 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
+			 dsp_fck_parent_names, dsp_fck_ops);
+
+static const struct clksel dsp_ick_clksel[] = {
+	{ .parent = &dsp_fck, .rates = dsp_ick_rates },
+	{ .parent = NULL },
+};
+
+static const char *dsp_ick_parent_names[] = {
+	"dsp_fck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel,
+			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+			 OMAP24XX_CLKSEL_DSP_IF_MASK,
+			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+			 OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait,
+			 dsp_ick_parent_names, dsp_fck_ops);
+
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate dss1_fck_core_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
+	{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
+	{ .div = 5, .val = 5, .flags = RATE_IN_24XX },
+	{ .div = 6, .val = 6, .flags = RATE_IN_24XX },
+	{ .div = 8, .val = 8, .flags = RATE_IN_24XX },
+	{ .div = 9, .val = 9, .flags = RATE_IN_24XX },
+	{ .div = 12, .val = 12, .flags = RATE_IN_24XX },
+	{ .div = 16, .val = 16, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel dss1_fck_clksel[] = {
+	{ .parent = &sys_ck, .rates = dss1_fck_sys_rates },
+	{ .parent = &core_ck, .rates = dss1_fck_core_rates },
+	{ .parent = NULL },
+};
+
+static const char *dss1_fck_parent_names[] = {
+	"sys_ck", "core_ck",
+};
+
+static struct clk dss1_fck;
+
+static const struct clk_ops dss1_fck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+	.recalc_rate	= &omap2_clksel_recalc,
+	.get_parent	= &omap2_clksel_find_parent_index,
+	.set_parent	= &omap2_clksel_set_parent,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+			 OMAP24XX_CLKSEL_DSS1_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_DSS1_SHIFT, NULL,
+			 dss1_fck_parent_names, dss1_fck_ops);
+
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate func_48m_apll96_rates[] = {
+	{ .div = 2, .val = 0, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate func_48m_alt_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel func_48m_clksel[] = {
+	{ .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+	{ .parent = &alt_ck, .rates = func_48m_alt_rates },
+	{ .parent = NULL },
+};
+
+static const char *func_48m_ck_parent_names[] = {
+	"apll96_ck", "alt_ck",
+};
+
+static struct clk func_48m_ck;
+
+static const struct clk_ops func_48m_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.recalc_rate	= &omap2_clksel_recalc,
+	.set_rate	= &omap2_clksel_set_rate,
+	.round_rate	= &omap2_clksel_round_rate,
+	.get_parent	= &omap2_clksel_find_parent_index,
+	.set_parent	= &omap2_clksel_set_parent,
+};
+
+static struct clk_hw_omap func_48m_ck_hw = {
+	.hw = {
+		.clk = &func_48m_ck,
+	},
+	.clksel		= func_48m_clksel,
+	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+	.clksel_mask	= OMAP24XX_48M_SOURCE_MASK,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
+
+static const struct clksel dss2_fck_clksel[] = {
+	{ .parent = &sys_ck, .rates = dss2_fck_sys_rates },
+	{ .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+	{ .parent = NULL },
+};
+
+static const char *dss2_fck_parent_names[] = {
+	"sys_ck", "func_48m_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+			 OMAP24XX_CLKSEL_DSS2_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_DSS2_SHIFT, NULL,
+			 dss2_fck_parent_names, dss1_fck_ops);
+
+static const char *func_54m_ck_parent_names[] = {
+	"apll54_ck", "alt_ck",
+};
+
+DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
+	       OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+	       OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH,
+	       0x0, NULL);
+
+static struct clk dss_54m_fck;
+
+static const char *dss_54m_fck_parent_names[] = {
+	"func_54m_ck",
+};
+
+static struct clk_hw_omap dss_54m_fck_hw = {
+	.hw = {
+		.clk = &dss_54m_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_TV_SHIFT,
+	.clkdm_name	= "dss_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
+
+static struct clk dss_ick;
+
+static struct clk_hw_omap dss_ick_hw = {
+	.hw = {
+		.clk = &dss_ick,
+	},
+	.ops		= &clkhwops_iclk,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_DSS1_SHIFT,
+	.clkdm_name	= "dss_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk eac_fck;
+
+static struct clk_hw_omap eac_fck_hw = {
+	.hw = {
+		.clk = &eac_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP2420_EN_EAC_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk eac_ick;
+
+static struct clk_hw_omap eac_ick_hw = {
+	.hw = {
+		.clk = &eac_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP2420_EN_EAC_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk emul_ck;
+
+static struct clk_hw_omap emul_ck_hw = {
+	.hw = {
+		.clk = &emul_ck,
+	},
+	.enable_reg	= OMAP2420_PRCM_CLKEMUL_CTRL,
+	.enable_bit	= OMAP24XX_EMULATION_EN_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
+
+DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
+
+static struct clk fac_fck;
+
+static const char *fac_fck_parent_names[] = {
+	"func_12m_ck",
+};
+
+static struct clk_hw_omap fac_fck_hw = {
+	.hw = {
+		.clk = &fac_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_FAC_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk fac_ick;
+
+static struct clk_hw_omap fac_ick_hw = {
+	.hw = {
+		.clk = &fac_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_FAC_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel gfx_fck_clksel[] = {
+	{ .parent = &core_l3_ck, .rates = gfx_l3_rates },
+	{ .parent = NULL },
+};
+
+static const char *gfx_2d_fck_parent_names[] = {
+	"core_l3_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
+			 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+			 OMAP_CLKSEL_GFX_MASK,
+			 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+			 OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
+			 gfx_2d_fck_parent_names, dsp_fck_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
+			 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+			 OMAP_CLKSEL_GFX_MASK,
+			 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+			 OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
+			 gfx_2d_fck_parent_names, dsp_fck_ops);
+
+static struct clk gfx_ick;
+
+static const char *gfx_ick_parent_names[] = {
+	"core_l3_ck",
+};
+
+static struct clk_hw_omap gfx_ick_hw = {
+	.hw = {
+		.clk = &gfx_ick,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP_EN_GFX_SHIFT,
+	.clkdm_name	= "gfx_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
+
+static struct clk gpios_fck;
+
+static const char *gpios_fck_parent_names[] = {
+	"func_32k_ck",
+};
+
+static struct clk_hw_omap gpios_fck_hw = {
+	.hw = {
+		.clk = &gpios_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+	.enable_bit	= OMAP24XX_EN_GPIOS_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk wu_l4_ick;
+
+DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
+DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
+
+static struct clk gpios_ick;
+
+static const char *gpios_ick_parent_names[] = {
+	"wu_l4_ick",
+};
+
+static struct clk_hw_omap gpios_ick_hw = {
+	.hw = {
+		.clk = &gpios_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP24XX_EN_GPIOS_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk gpmc_fck;
+
+static struct clk_hw_omap gpmc_fck_hw = {
+	.hw = {
+		.clk = &gpmc_fck,
+	},
+	.ops		= &clkhwops_iclk,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+	.enable_bit	= OMAP24XX_AUTO_GPMC_SHIFT,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
+
+static const struct clksel_rate gpt_alt_rates[] = {
+	{ .div = 1, .val = 2, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel omap24xx_gpt_clksel[] = {
+	{ .parent = &func_32k_ck, .rates = gpt_32k_rates },
+	{ .parent = &sys_ck, .rates = gpt_sys_rates },
+	{ .parent = &alt_ck, .rates = gpt_alt_rates },
+	{ .parent = NULL },
+};
+
+static const char *gpt10_fck_parent_names[] = {
+	"func_32k_ck", "sys_ck", "alt_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT10_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt10_ick;
+
+static struct clk_hw_omap gpt10_ick_hw = {
+	.hw = {
+		.clk = &gpt10_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT10_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT11_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt11_ick;
+
+static struct clk_hw_omap gpt11_ick_hw = {
+	.hw = {
+		.clk = &gpt11_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT11_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT12_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt12_ick;
+
+static struct clk_hw_omap gpt12_ick_hw = {
+	.hw = {
+		.clk = &gpt12_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT12_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clk_ops gpt1_fck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+	.recalc_rate	= &omap2_clksel_recalc,
+	.set_rate	= &omap2_clksel_set_rate,
+	.round_rate	= &omap2_clksel_round_rate,
+	.get_parent	= &omap2_clksel_find_parent_index,
+	.set_parent	= &omap2_clksel_set_parent,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+			 OMAP24XX_CLKSEL_GPT1_MASK,
+			 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+			 OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, gpt1_fck_ops);
+
+static struct clk gpt1_ick;
+
+static struct clk_hw_omap gpt1_ick_hw = {
+	.hw = {
+		.clk = &gpt1_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP24XX_EN_GPT1_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT2_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt2_ick;
+
+static struct clk_hw_omap gpt2_ick_hw = {
+	.hw = {
+		.clk = &gpt2_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT3_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt3_ick;
+
+static struct clk_hw_omap gpt3_ick_hw = {
+	.hw = {
+		.clk = &gpt3_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT3_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT4_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt4_ick;
+
+static struct clk_hw_omap gpt4_ick_hw = {
+	.hw = {
+		.clk = &gpt4_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT4_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT5_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt5_ick;
+
+static struct clk_hw_omap gpt5_ick_hw = {
+	.hw = {
+		.clk = &gpt5_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT5_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT6_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt6_ick;
+
+static struct clk_hw_omap gpt6_ick_hw = {
+	.hw = {
+		.clk = &gpt6_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT6_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT7_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt7_ick;
+
+static struct clk_hw_omap gpt7_ick_hw = {
+	.hw = {
+		.clk = &gpt7_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT7_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT8_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt8_ick;
+
+static struct clk_hw_omap gpt8_ick_hw = {
+	.hw = {
+		.clk = &gpt8_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT8_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT9_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt9_ick;
+
+static struct clk_hw_omap gpt9_ick_hw = {
+	.hw = {
+		.clk = &gpt9_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT9_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk hdq_fck;
+
+static struct clk_hw_omap hdq_fck_hw = {
+	.hw = {
+		.clk = &hdq_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_HDQ_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk hdq_ick;
+
+static struct clk_hw_omap hdq_ick_hw = {
+	.hw = {
+		.clk = &hdq_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_HDQ_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2c1_fck;
+
+static struct clk_hw_omap i2c1_fck_hw = {
+	.hw = {
+		.clk = &i2c1_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk i2c1_ick;
+
+static struct clk_hw_omap i2c1_ick_hw = {
+	.hw = {
+		.clk = &i2c1_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2c2_fck;
+
+static struct clk_hw_omap i2c2_fck_hw = {
+	.hw = {
+		.clk = &i2c2_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk i2c2_ick;
+
+static struct clk_hw_omap i2c2_ick_hw = {
+	.hw = {
+		.clk = &i2c2_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,
+			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+			 OMAP2420_CLKSEL_IVA_MASK,
+			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+			 OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait,
+			 dsp_fck_parent_names, dsp_fck_ops);
+
+static struct clk iva1_mpu_int_ifck;
+
+static const char *iva1_mpu_int_ifck_parent_names[] = {
+	"iva1_ifck",
+};
+
+static const struct clk_ops iva1_mpu_int_ifck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+	.recalc_rate	= &omap_fixed_divisor_recalc,
+};
+
+static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
+	.hw = {
+		.clk = &iva1_mpu_int_ifck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+	.enable_bit	= OMAP2420_EN_IVA_MPU_SHIFT,
+	.clkdm_name	= "iva1_clkdm",
+	.fixed_div	= 2,
+};
+
+DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names,
+		  iva1_mpu_int_ifck_ops);
+
+static struct clk mailboxes_ick;
+
+static struct clk_hw_omap mailboxes_ick_hw = {
+	.hw = {
+		.clk = &mailboxes_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_MAILBOXES_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel mcbsp_fck_clksel[] = {
+	{ .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
+	{ .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
+	{ .parent = NULL },
+};
+
+static const char *mcbsp1_fck_parent_names[] = {
+	"func_96m_ck", "mcbsp_clks",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+			 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+			 OMAP2_MCBSP1_CLKS_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
+			 mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp1_ick;
+
+static struct clk_hw_omap mcbsp1_ick_hw = {
+	.hw = {
+		.clk = &mcbsp1_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_MCBSP1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+			 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+			 OMAP2_MCBSP2_CLKS_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
+			 mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp2_ick;
+
+static struct clk_hw_omap mcbsp2_ick_hw = {
+	.hw = {
+		.clk = &mcbsp2_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_MCBSP2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mcspi1_fck;
+
+static const char *mcspi1_fck_parent_names[] = {
+	"func_48m_ck",
+};
+
+static struct clk_hw_omap mcspi1_fck_hw = {
+	.hw = {
+		.clk = &mcspi1_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_MCSPI1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk mcspi1_ick;
+
+static struct clk_hw_omap mcspi1_ick_hw = {
+	.hw = {
+		.clk = &mcspi1_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_MCSPI1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mcspi2_fck;
+
+static struct clk_hw_omap mcspi2_fck_hw = {
+	.hw = {
+		.clk = &mcspi2_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_MCSPI2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk mcspi2_ick;
+
+static struct clk_hw_omap mcspi2_ick_hw = {
+	.hw = {
+		.clk = &mcspi2_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_MCSPI2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mmc_fck;
+
+static struct clk_hw_omap mmc_fck_hw = {
+	.hw = {
+		.clk = &mmc_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP2420_EN_MMC_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk mmc_ick;
+
+static struct clk_hw_omap mmc_ick_hw = {
+	.hw = {
+		.clk = &mmc_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP2420_EN_MMC_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
+		   OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+		   OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
+		   CLK_DIVIDER_ONE_BASED, NULL);
+
+static struct clk mpu_wdt_fck;
+
+static struct clk_hw_omap mpu_wdt_fck_hw = {
+	.hw = {
+		.clk = &mpu_wdt_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+	.enable_bit	= OMAP24XX_EN_MPU_WDT_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk mpu_wdt_ick;
+
+static struct clk_hw_omap mpu_wdt_ick_hw = {
+	.hw = {
+		.clk = &mpu_wdt_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP24XX_EN_MPU_WDT_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk mspro_fck;
+
+static struct clk_hw_omap mspro_fck_hw = {
+	.hw = {
+		.clk = &mspro_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_MSPRO_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk mspro_ick;
+
+static struct clk_hw_omap mspro_ick_hw = {
+	.hw = {
+		.clk = &mspro_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_MSPRO_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk omapctrl_ick;
+
+static struct clk_hw_omap omapctrl_ick_hw = {
+	.hw = {
+		.clk = &omapctrl_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP24XX_EN_OMAPCTRL_SHIFT,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk pka_ick;
+
+static struct clk_hw_omap pka_ick_hw = {
+	.hw = {
+		.clk = &pka_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+	.enable_bit	= OMAP24XX_EN_PKA_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk rng_ick;
+
+static struct clk_hw_omap rng_ick_hw = {
+	.hw = {
+		.clk = &rng_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+	.enable_bit	= OMAP24XX_EN_RNG_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk sdma_fck;
+
+DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
+DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sdma_ick;
+
+static struct clk_hw_omap sdma_ick_hw = {
+	.hw = {
+		.clk = &sdma_ick,
+	},
+	.ops		= &clkhwops_iclk,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+	.enable_bit	= OMAP24XX_AUTO_SDMA_SHIFT,
+	.clkdm_name	= "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sdrc_ick;
+
+static struct clk_hw_omap sdrc_ick_hw = {
+	.hw = {
+		.clk = &sdrc_ick,
+	},
+	.ops		= &clkhwops_iclk,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+	.enable_bit	= OMAP24XX_AUTO_SDRC_SHIFT,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sha_ick;
+
+static struct clk_hw_omap sha_ick_hw = {
+	.hw = {
+		.clk = &sha_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+	.enable_bit	= OMAP24XX_EN_SHA_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk ssi_l4_ick;
+
+static struct clk_hw_omap ssi_l4_ick_hw = {
+	.hw = {
+		.clk = &ssi_l4_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+	.enable_bit	= OMAP24XX_EN_SSI_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
+	{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
+	{ .div = 6, .val = 6, .flags = RATE_IN_242X },
+	{ .div = 8, .val = 8, .flags = RATE_IN_242X },
+	{ .div = 0 }
+};
+
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+	{ .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+	{ .parent = NULL },
+};
+
+static const char *ssi_ssr_sst_fck_parent_names[] = {
+	"core_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
+			 ssi_ssr_sst_fck_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+			 OMAP24XX_CLKSEL_SSI_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+			 OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
+			 ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
+
+static struct clk sync_32k_ick;
+
+static struct clk_hw_omap sync_32k_ick_hw = {
+	.hw = {
+		.clk = &sync_32k_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP24XX_EN_32KSYNC_SHIFT,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+	{ .div = 1, .val = 2, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+	{ .div = 1, .val = 3, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel common_clkout_src_clksel[] = {
+	{ .parent = &core_ck, .rates = common_clkout_src_core_rates },
+	{ .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
+	{ .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+	{ .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+	{ .parent = NULL },
+};
+
+static const char *sys_clkout_src_parent_names[] = {
+	"core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
+			 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
+			 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
+			 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
+
+DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
+		   OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
+		   OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
+			 common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL,
+			 OMAP2420_CLKOUT2_SOURCE_MASK,
+			 OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT,
+			 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
+
+DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0,
+		   OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT,
+		   OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static struct clk uart1_fck;
+
+static struct clk_hw_omap uart1_fck_hw = {
+	.hw = {
+		.clk = &uart1_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_UART1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart1_ick;
+
+static struct clk_hw_omap uart1_ick_hw = {
+	.hw = {
+		.clk = &uart1_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_UART1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk uart2_fck;
+
+static struct clk_hw_omap uart2_fck_hw = {
+	.hw = {
+		.clk = &uart2_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_UART2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart2_ick;
+
+static struct clk_hw_omap uart2_ick_hw = {
+	.hw = {
+		.clk = &uart2_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_UART2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk uart3_fck;
+
+static struct clk_hw_omap uart3_fck_hw = {
+	.hw = {
+		.clk = &uart3_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+	.enable_bit	= OMAP24XX_EN_UART3_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart3_ick;
+
+static struct clk_hw_omap uart3_ick_hw = {
+	.hw = {
+		.clk = &uart3_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+	.enable_bit	= OMAP24XX_EN_UART3_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk usb_fck;
+
+static struct clk_hw_omap usb_fck_hw = {
+	.hw = {
+		.clk = &usb_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+	.enable_bit	= OMAP24XX_EN_USB_SHIFT,
+	.clkdm_name	= "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel usb_l4_ick_clksel[] = {
+	{ .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+	{ .parent = NULL },
+};
+
+static const char *usb_l4_ick_parent_names[] = {
+	"core_l3_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+			 OMAP24XX_CLKSEL_USB_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+			 OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
+			 usb_l4_ick_parent_names, dsp_fck_ops);
+
+static struct clk virt_prcm_set;
+
+static const char *virt_prcm_set_parent_names[] = {
+	"mpu_ck",
+};
+
+static const struct clk_ops virt_prcm_set_ops = {
+	.recalc_rate	= &omap2_table_mpu_recalc,
+	.set_rate	= &omap2_select_table_rate,
+	.round_rate	= &omap2_round_to_table_rate,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
+DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
+
+static const struct clksel_rate vlynq_fck_96m_rates[] = {
+	{ .div = 1, .val = 0, .flags = RATE_IN_242X },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate vlynq_fck_core_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_242X },
+	{ .div = 2, .val = 2, .flags = RATE_IN_242X },
+	{ .div = 3, .val = 3, .flags = RATE_IN_242X },
+	{ .div = 4, .val = 4, .flags = RATE_IN_242X },
+	{ .div = 6, .val = 6, .flags = RATE_IN_242X },
+	{ .div = 8, .val = 8, .flags = RATE_IN_242X },
+	{ .div = 9, .val = 9, .flags = RATE_IN_242X },
+	{ .div = 12, .val = 12, .flags = RATE_IN_242X },
+	{ .div = 16, .val = 16, .flags = RATE_IN_242X },
+	{ .div = 18, .val = 18, .flags = RATE_IN_242X },
+	{ .div = 0 }
+};
+
+static const struct clksel vlynq_fck_clksel[] = {
+	{ .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
+	{ .parent = &core_ck, .rates = vlynq_fck_core_rates },
+	{ .parent = NULL },
+};
+
+static const char *vlynq_fck_parent_names[] = {
+	"func_96m_ck", "core_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+			 OMAP2420_CLKSEL_VLYNQ_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait,
+			 vlynq_fck_parent_names, dss1_fck_ops);
+
+static struct clk vlynq_ick;
+
+static struct clk_hw_omap vlynq_ick_hw = {
+	.hw = {
+		.clk = &vlynq_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP2420_EN_VLYNQ_SHIFT,
+	.clkdm_name	= "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt1_ick;
+
+static struct clk_hw_omap wdt1_ick_hw = {
+	.hw = {
+		.clk = &wdt1_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP24XX_EN_WDT1_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt1_osc_ck;
+
+static const struct clk_ops wdt1_osc_ck_ops = {};
+
+DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
+DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
+
+static struct clk wdt3_fck;
+
+static struct clk_hw_omap wdt3_fck_hw = {
+	.hw = {
+		.clk = &wdt3_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP2420_EN_WDT3_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk wdt3_ick;
+
+static struct clk_hw_omap wdt3_ick_hw = {
+	.hw = {
+		.clk = &wdt3_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP2420_EN_WDT3_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt4_fck;
+
+static struct clk_hw_omap wdt4_fck_hw = {
+	.hw = {
+		.clk = &wdt4_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_WDT4_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk wdt4_ick;
+
+static struct clk_hw_omap wdt4_ick_hw = {
+	.hw = {
+		.clk = &wdt4_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_WDT4_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
+
+/*
+ * clkdev integration
+ */
+
+static struct omap_clk omap2420_clks[] = {
+	/* external root sources */
+	CLK(NULL,	"func_32k_ck",	&func_32k_ck,	CK_242X),
+	CLK(NULL,	"secure_32k_ck", &secure_32k_ck, CK_242X),
+	CLK(NULL,	"osc_ck",	&osc_ck,	CK_242X),
+	CLK(NULL,	"sys_ck",	&sys_ck,	CK_242X),
+	CLK(NULL,	"alt_ck",	&alt_ck,	CK_242X),
+	CLK(NULL,	"mcbsp_clks",	&mcbsp_clks,	CK_242X),
+	/* internal analog sources */
+	CLK(NULL,	"dpll_ck",	&dpll_ck,	CK_242X),
+	CLK(NULL,	"apll96_ck",	&apll96_ck,	CK_242X),
+	CLK(NULL,	"apll54_ck",	&apll54_ck,	CK_242X),
+	/* internal prcm root sources */
+	CLK(NULL,	"func_54m_ck",	&func_54m_ck,	CK_242X),
+	CLK(NULL,	"core_ck",	&core_ck,	CK_242X),
+	CLK(NULL,	"func_96m_ck",	&func_96m_ck,	CK_242X),
+	CLK(NULL,	"func_48m_ck",	&func_48m_ck,	CK_242X),
+	CLK(NULL,	"func_12m_ck",	&func_12m_ck,	CK_242X),
+	CLK(NULL,	"ck_wdt1_osc",	&wdt1_osc_ck,	CK_242X),
+	CLK(NULL,	"sys_clkout_src", &sys_clkout_src, CK_242X),
+	CLK(NULL,	"sys_clkout",	&sys_clkout,	CK_242X),
+	CLK(NULL,	"sys_clkout2_src", &sys_clkout2_src, CK_242X),
+	CLK(NULL,	"sys_clkout2",	&sys_clkout2,	CK_242X),
+	CLK(NULL,	"emul_ck",	&emul_ck,	CK_242X),
+	/* mpu domain clocks */
+	CLK(NULL,	"mpu_ck",	&mpu_ck,	CK_242X),
+	/* dsp domain clocks */
+	CLK(NULL,	"dsp_fck",	&dsp_fck,	CK_242X),
+	CLK(NULL,	"dsp_ick",	&dsp_ick,	CK_242X),
+	CLK(NULL,	"iva1_ifck",	&iva1_ifck,	CK_242X),
+	CLK(NULL,	"iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+	/* GFX domain clocks */
+	CLK(NULL,	"gfx_3d_fck",	&gfx_3d_fck,	CK_242X),
+	CLK(NULL,	"gfx_2d_fck",	&gfx_2d_fck,	CK_242X),
+	CLK(NULL,	"gfx_ick",	&gfx_ick,	CK_242X),
+	/* DSS domain clocks */
+	CLK("omapdss_dss",	"ick",		&dss_ick,	CK_242X),
+	CLK(NULL,	"dss_ick",		&dss_ick,	CK_242X),
+	CLK(NULL,	"dss1_fck",		&dss1_fck,	CK_242X),
+	CLK(NULL,	"dss2_fck",	&dss2_fck,	CK_242X),
+	CLK(NULL,	"dss_54m_fck",	&dss_54m_fck,	CK_242X),
+	/* L3 domain clocks */
+	CLK(NULL,	"core_l3_ck",	&core_l3_ck,	CK_242X),
+	CLK(NULL,	"ssi_fck",	&ssi_ssr_sst_fck, CK_242X),
+	CLK(NULL,	"usb_l4_ick",	&usb_l4_ick,	CK_242X),
+	/* L4 domain clocks */
+	CLK(NULL,	"l4_ck",	&l4_ck,		CK_242X),
+	CLK(NULL,	"ssi_l4_ick",	&ssi_l4_ick,	CK_242X),
+	CLK(NULL,	"wu_l4_ick",	&wu_l4_ick,	CK_242X),
+	/* virtual meta-group clock */
+	CLK(NULL,	"virt_prcm_set", &virt_prcm_set, CK_242X),
+	/* general l4 interface ck, multi-parent functional clk */
+	CLK(NULL,	"gpt1_ick",	&gpt1_ick,	CK_242X),
+	CLK(NULL,	"gpt1_fck",	&gpt1_fck,	CK_242X),
+	CLK(NULL,	"gpt2_ick",	&gpt2_ick,	CK_242X),
+	CLK(NULL,	"gpt2_fck",	&gpt2_fck,	CK_242X),
+	CLK(NULL,	"gpt3_ick",	&gpt3_ick,	CK_242X),
+	CLK(NULL,	"gpt3_fck",	&gpt3_fck,	CK_242X),
+	CLK(NULL,	"gpt4_ick",	&gpt4_ick,	CK_242X),
+	CLK(NULL,	"gpt4_fck",	&gpt4_fck,	CK_242X),
+	CLK(NULL,	"gpt5_ick",	&gpt5_ick,	CK_242X),
+	CLK(NULL,	"gpt5_fck",	&gpt5_fck,	CK_242X),
+	CLK(NULL,	"gpt6_ick",	&gpt6_ick,	CK_242X),
+	CLK(NULL,	"gpt6_fck",	&gpt6_fck,	CK_242X),
+	CLK(NULL,	"gpt7_ick",	&gpt7_ick,	CK_242X),
+	CLK(NULL,	"gpt7_fck",	&gpt7_fck,	CK_242X),
+	CLK(NULL,	"gpt8_ick",	&gpt8_ick,	CK_242X),
+	CLK(NULL,	"gpt8_fck",	&gpt8_fck,	CK_242X),
+	CLK(NULL,	"gpt9_ick",	&gpt9_ick,	CK_242X),
+	CLK(NULL,	"gpt9_fck",	&gpt9_fck,	CK_242X),
+	CLK(NULL,	"gpt10_ick",	&gpt10_ick,	CK_242X),
+	CLK(NULL,	"gpt10_fck",	&gpt10_fck,	CK_242X),
+	CLK(NULL,	"gpt11_ick",	&gpt11_ick,	CK_242X),
+	CLK(NULL,	"gpt11_fck",	&gpt11_fck,	CK_242X),
+	CLK(NULL,	"gpt12_ick",	&gpt12_ick,	CK_242X),
+	CLK(NULL,	"gpt12_fck",	&gpt12_fck,	CK_242X),
+	CLK("omap-mcbsp.1", "ick",	&mcbsp1_ick,	CK_242X),
+	CLK(NULL,	"mcbsp1_ick",	&mcbsp1_ick,	CK_242X),
+	CLK(NULL,	"mcbsp1_fck",	&mcbsp1_fck,	CK_242X),
+	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_242X),
+	CLK(NULL,	"mcbsp2_ick",	&mcbsp2_ick,	CK_242X),
+	CLK(NULL,	"mcbsp2_fck",	&mcbsp2_fck,	CK_242X),
+	CLK("omap2_mcspi.1", "ick",	&mcspi1_ick,	CK_242X),
+	CLK(NULL,	"mcspi1_ick",	&mcspi1_ick,	CK_242X),
+	CLK(NULL,	"mcspi1_fck",	&mcspi1_fck,	CK_242X),
+	CLK("omap2_mcspi.2", "ick",	&mcspi2_ick,	CK_242X),
+	CLK(NULL,	"mcspi2_ick",	&mcspi2_ick,	CK_242X),
+	CLK(NULL,	"mcspi2_fck",	&mcspi2_fck,	CK_242X),
+	CLK(NULL,	"uart1_ick",	&uart1_ick,	CK_242X),
+	CLK(NULL,	"uart1_fck",	&uart1_fck,	CK_242X),
+	CLK(NULL,	"uart2_ick",	&uart2_ick,	CK_242X),
+	CLK(NULL,	"uart2_fck",	&uart2_fck,	CK_242X),
+	CLK(NULL,	"uart3_ick",	&uart3_ick,	CK_242X),
+	CLK(NULL,	"uart3_fck",	&uart3_fck,	CK_242X),
+	CLK(NULL,	"gpios_ick",	&gpios_ick,	CK_242X),
+	CLK(NULL,	"gpios_fck",	&gpios_fck,	CK_242X),
+	CLK("omap_wdt",	"ick",		&mpu_wdt_ick,	CK_242X),
+	CLK(NULL,	"mpu_wdt_ick",		&mpu_wdt_ick,	CK_242X),
+	CLK(NULL,	"mpu_wdt_fck",	&mpu_wdt_fck,	CK_242X),
+	CLK(NULL,	"sync_32k_ick",	&sync_32k_ick,	CK_242X),
+	CLK(NULL,	"wdt1_ick",	&wdt1_ick,	CK_242X),
+	CLK(NULL,	"omapctrl_ick",	&omapctrl_ick,	CK_242X),
+	CLK("omap24xxcam", "fck",	&cam_fck,	CK_242X),
+	CLK(NULL,	"cam_fck",	&cam_fck,	CK_242X),
+	CLK("omap24xxcam", "ick",	&cam_ick,	CK_242X),
+	CLK(NULL,	"cam_ick",	&cam_ick,	CK_242X),
+	CLK(NULL,	"mailboxes_ick", &mailboxes_ick,	CK_242X),
+	CLK(NULL,	"wdt4_ick",	&wdt4_ick,	CK_242X),
+	CLK(NULL,	"wdt4_fck",	&wdt4_fck,	CK_242X),
+	CLK(NULL,	"wdt3_ick",	&wdt3_ick,	CK_242X),
+	CLK(NULL,	"wdt3_fck",	&wdt3_fck,	CK_242X),
+	CLK(NULL,	"mspro_ick",	&mspro_ick,	CK_242X),
+	CLK(NULL,	"mspro_fck",	&mspro_fck,	CK_242X),
+	CLK("mmci-omap.0", "ick",	&mmc_ick,	CK_242X),
+	CLK(NULL,	"mmc_ick",	&mmc_ick,	CK_242X),
+	CLK("mmci-omap.0", "fck",	&mmc_fck,	CK_242X),
+	CLK(NULL,	"mmc_fck",	&mmc_fck,	CK_242X),
+	CLK(NULL,	"fac_ick",	&fac_ick,	CK_242X),
+	CLK(NULL,	"fac_fck",	&fac_fck,	CK_242X),
+	CLK(NULL,	"eac_ick",	&eac_ick,	CK_242X),
+	CLK(NULL,	"eac_fck",	&eac_fck,	CK_242X),
+	CLK("omap_hdq.0", "ick",	&hdq_ick,	CK_242X),
+	CLK(NULL,	"hdq_ick",	&hdq_ick,	CK_242X),
+	CLK("omap_hdq.0", "fck",	&hdq_fck,	CK_242X),
+	CLK(NULL,	"hdq_fck",	&hdq_fck,	CK_242X),
+	CLK("omap_i2c.1", "ick",	&i2c1_ick,	CK_242X),
+	CLK(NULL,	"i2c1_ick",	&i2c1_ick,	CK_242X),
+	CLK(NULL,	"i2c1_fck",	&i2c1_fck,	CK_242X),
+	CLK("omap_i2c.2", "ick",	&i2c2_ick,	CK_242X),
+	CLK(NULL,	"i2c2_ick",	&i2c2_ick,	CK_242X),
+	CLK(NULL,	"i2c2_fck",	&i2c2_fck,	CK_242X),
+	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_242X),
+	CLK(NULL,	"sdma_fck",	&sdma_fck,	CK_242X),
+	CLK(NULL,	"sdma_ick",	&sdma_ick,	CK_242X),
+	CLK(NULL,	"sdrc_ick",	&sdrc_ick,	CK_242X),
+	CLK(NULL,	"vlynq_ick",	&vlynq_ick,	CK_242X),
+	CLK(NULL,	"vlynq_fck",	&vlynq_fck,	CK_242X),
+	CLK(NULL,	"des_ick",	&des_ick,	CK_242X),
+	CLK("omap-sham",	"ick",	&sha_ick,	CK_242X),
+	CLK(NULL,	"sha_ick",	&sha_ick,	CK_242X),
+	CLK("omap_rng",	"ick",		&rng_ick,	CK_242X),
+	CLK(NULL,	"rng_ick",		&rng_ick,	CK_242X),
+	CLK("omap-aes",	"ick",	&aes_ick,	CK_242X),
+	CLK(NULL,	"aes_ick",	&aes_ick,	CK_242X),
+	CLK(NULL,	"pka_ick",	&pka_ick,	CK_242X),
+	CLK(NULL,	"usb_fck",	&usb_fck,	CK_242X),
+	CLK("musb-hdrc",	"fck",	&osc_ck,	CK_242X),
+	CLK(NULL,	"timer_32k_ck",	&func_32k_ck,	CK_242X),
+	CLK(NULL,	"timer_sys_ck",	&sys_ck,	CK_242X),
+	CLK(NULL,	"timer_ext_ck",	&alt_ck,	CK_242X),
+	CLK(NULL,	"cpufreq_ck",	&virt_prcm_set,	CK_242X),
+};
+
+
+static const char *enable_init_clks[] = {
+	"apll96_ck",
+	"apll54_ck",
+	"sync_32k_ick",
+	"omapctrl_ick",
+	"gpmc_fck",
+	"sdrc_ick",
+};
+
+/*
+ * init code
+ */
+
+int __init omap2420_clk_init(void)
+{
+	const struct prcm_config *prcm;
+	struct omap_clk *c;
+	unsigned long clkrate;
+
+	prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
+	cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
+	cpu_mask = RATE_IN_242X;
+	rate_table = omap2420_rate_table;
+
+	/* Check the MPU rate set by bootloader */
+	clkrate = omap2xxx_clk_get_core_rate(&dpll_ck_hw);
+	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+		if (!(prcm->flags & cpu_mask))
+			continue;
+		if (prcm->xtal_speed != sys_ck.rate)
+			continue;
+		if (prcm->dpll_speed <= clkrate)
+			break;
+	}
+
+	curr_prcm_set = prcm;
+
+	for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
+	     c++) {
+		clkdev_add(&c->lk);
+		if (!__clk_init(NULL, c->lk.clk))
+			omap2_init_clk_hw_omap_clocks(c->lk.clk);
+	}
+
+	omap2_clk_disable_autoidle_all();
+
+	omap2_clk_enable_init_clocks(enable_init_clks,
+				     ARRAY_SIZE(enable_init_clks));
+
+	pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
+		(clk_get_rate(&sys_ck) / 1000000),
+		(clk_get_rate(&sys_ck) / 100000) % 10,
+		(clk_get_rate(&dpll_ck) / 1000000),
+		(clk_get_rate(&mpu_ck) / 1000000));
+
+	return 0;
+}

arch/arm/mach-omap2/cclock2430_data.c new file +2076 -0

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arch/arm/mach-omap2/cm-regbits-24xx.h +5 -0

index 6862904..f3fcba2 100644

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arch/arm/mach-omap2/prm-regbits-24xx.h +2 -0

index 638da6d..91aa510 100644

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Signature · 1 line

1.7.10.4

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Mike Turquette

author

2012-11-09 21:05 UTC #57 lore raw

PATCH v2 15/26 ARM: omap2: clock: Add 24xx data using common struct clk

Quoting Paul Walmsley (2012-11-09 12:32:59)

Quoted 4 lines

Here's another update on this one to add the twl.fck clock alias, recently added by commit defa6be1c8216ed2d52d65db81a8a148e73be5f7 ("mfd: Fix compile for twl-core.c by removing cpu_is_omap usage").

I'll post a new series to the list with these fixes rolled in. Do you want me to squash the clkdm_clk_disable/usecount patch into another patch in the series or keep it separate? Separate might be good since we're going to replace that solution with some force-disable thing in the future.

Regards,
Mike

Quoted 4,135 lines

- Paul

From: Rajendra Nayak <[email protected]>
Date: Wed, 7 Nov 2012 21:09:35 -0700
Subject: [PATCH] ARM: OMAP2: clock: Add 24xx data using common struct clk

The patch is the output from a python script which converts from the old OMAP clk format to COMMON clk format using a JSON parser in between which was developed by Paul Walmsley.

Signed-off-by Rajendra Nayak <[email protected]>

[mturquette at ti.com: removed deprecated variables from omap24x0_clk_init]

Signed-off-by Mike Turquette <[email protected]>

[paul at pwsan.com: fixed boot crash due to missing clock init code; added twl.fck
alias]

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/cclock2420_data.c  | 1962 ++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/cclock2430_data.c  | 2076 ++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/cm-regbits-24xx.h  |    5 +
 arch/arm/mach-omap2/prm-regbits-24xx.h |    2 +
 4 files changed, 4045 insertions(+)
 create mode 100644 arch/arm/mach-omap2/cclock2420_data.c
 create mode 100644 arch/arm/mach-omap2/cclock2430_data.c

arch/arm/mach-omap2/cclock2420_data.c new file +1962 -0

new file mode 100644
index 0000000..f1ee478
@@ -0,0 +1,1962 @@
+/*
+ * OMAP2420 clock data
+ *
+ * Copyright (C) 2005-2012 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <[email protected]>
+ * Paul Walmsley
+ * Updated to COMMON clk format by Rajendra Nayak <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/list.h>
+
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm2xxx.h"
+#include "prm2xxx.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "control.h"
+
+#define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
+
+/*
+ * 2420 clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ *     many cases the parent is selectable. The set parent calls will
+ *     also switch sources.
+ *
+ *     Several sources are given initial rates which may be wrong, this will
+ *     be fixed up in the init func.
+ *
+ *     Things are broadly separated below by clock domains. It is
+ *     noteworthy that most peripherals have dependencies on multiple clock
+ *     domains. Many get their interface clocks from the L4 domain, but get
+ *     functional clocks from fixed sources or other core domain derived
+ *     clocks.
+ */
+
+DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
+
+static struct clk osc_ck;
+
+static const struct clk_ops osc_ck_ops = {
+       .recalc_rate    = &omap2_osc_clk_recalc,
+};
+
+static struct clk_hw_omap osc_ck_hw = {
+       .hw = {
+               .clk = &osc_ck,
+       },
+};
+
+static struct clk osc_ck = {
+       .name   = "osc_ck",
+       .ops    = &osc_ck_ops,
+       .hw     = &osc_ck_hw.hw,
+       .flags  = CLK_IS_ROOT,
+};
+
+DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+static struct clk sys_ck;
+
+static const char *sys_ck_parent_names[] = {
+       "osc_ck",
+};
+
+static const struct clk_ops sys_ck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .recalc_rate    = &omap2xxx_sys_clk_recalc,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
+
+static struct dpll_data dpll_dd = {
+       .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .mult_mask      = OMAP24XX_DPLL_MULT_MASK,
+       .div1_mask      = OMAP24XX_DPLL_DIV_MASK,
+       .clk_bypass     = &sys_ck,
+       .clk_ref        = &sys_ck,
+       .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_mask    = OMAP24XX_EN_DPLL_MASK,
+       .max_multiplier = 1023,
+       .min_divider    = 1,
+       .max_divider    = 16,
+};
+
+static struct clk dpll_ck;
+
+static const char *dpll_ck_parent_names[] = {
+       "sys_ck",
+};
+
+static const struct clk_ops dpll_ck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .get_parent     = &omap2_init_dpll_parent,
+       .recalc_rate    = &omap2_dpllcore_recalc,
+       .round_rate     = &omap2_dpll_round_rate,
+       .set_rate       = &omap2_reprogram_dpllcore,
+};
+
+static struct clk_hw_omap dpll_ck_hw = {
+       .hw = {
+               .clk = &dpll_ck,
+       },
+       .ops            = &clkhwops_omap2xxx_dpll,
+       .dpll_data      = &dpll_dd,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
+
+static struct clk core_ck;
+
+static const char *core_ck_parent_names[] = {
+       "dpll_ck",
+};
+
+static const struct clk_ops core_ck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
+
+DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
+                  OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                  OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
+                  CLK_DIVIDER_ONE_BASED, NULL);
+
+DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
+                  OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                  OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
+                  CLK_DIVIDER_ONE_BASED, NULL);
+
+static struct clk aes_ick;
+
+static const char *aes_ick_parent_names[] = {
+       "l4_ck",
+};
+
+static const struct clk_ops aes_ick_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_dflt_clk_enable,
+       .disable        = &omap2_dflt_clk_disable,
+       .is_enabled     = &omap2_dflt_clk_is_enabled,
+};
+
+static struct clk_hw_omap aes_ick_hw = {
+       .hw = {
+               .clk = &aes_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+       .enable_bit     = OMAP24XX_EN_AES_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk apll54_ck;
+
+static const struct clk_ops apll54_ck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_clk_apll54_enable,
+       .disable        = &omap2_clk_apll_disable,
+       .recalc_rate    = &omap2_clk_apll54_recalc,
+};
+
+static struct clk_hw_omap apll54_ck_hw = {
+       .hw = {
+               .clk = &apll54_ck,
+       },
+       .ops            = &clkhwops_apll54,
+       .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
+       .flags          = ENABLE_ON_INIT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
+
+static struct clk apll96_ck;
+
+static const struct clk_ops apll96_ck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_clk_apll96_enable,
+       .disable        = &omap2_clk_apll_disable,
+       .recalc_rate    = &omap2_clk_apll96_recalc,
+};
+
+static struct clk_hw_omap apll96_ck_hw = {
+       .hw = {
+               .clk = &apll96_ck,
+       },
+       .ops            = &clkhwops_apll96,
+       .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
+       .flags          = ENABLE_ON_INIT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
+
+static struct clk func_96m_ck;
+
+static const char *func_96m_ck_parent_names[] = {
+       "apll96_ck",
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops);
+
+static struct clk cam_fck;
+
+static const char *cam_fck_parent_names[] = {
+       "func_96m_ck",
+};
+
+static struct clk_hw_omap cam_fck_hw = {
+       .hw = {
+               .clk = &cam_fck,
+       },
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+       .clkdm_name     = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk cam_ick;
+
+static struct clk_hw_omap cam_ick_hw = {
+       .hw = {
+               .clk = &cam_ick,
+       },
+       .ops            = &clkhwops_iclk,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk des_ick;
+
+static struct clk_hw_omap des_ick_hw = {
+       .hw = {
+               .clk = &des_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+       .enable_bit     = OMAP24XX_EN_DES_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate dsp_fck_core_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+       { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+       { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+       { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+       { .div = 6, .val = 6, .flags = RATE_IN_242X },
+       { .div = 8, .val = 8, .flags = RATE_IN_242X },
+       { .div = 12, .val = 12, .flags = RATE_IN_242X },
+       { .div = 0 }
+};
+
+static const struct clksel dsp_fck_clksel[] = {
+       { .parent = &core_ck, .rates = dsp_fck_core_rates },
+       { .parent = NULL },
+};
+
+static const char *dsp_fck_parent_names[] = {
+       "core_ck",
+};
+
+static const struct clk_ops dsp_fck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_dflt_clk_enable,
+       .disable        = &omap2_dflt_clk_disable,
+       .is_enabled     = &omap2_dflt_clk_is_enabled,
+       .recalc_rate    = &omap2_clksel_recalc,
+       .set_rate       = &omap2_clksel_set_rate,
+       .round_rate     = &omap2_clksel_round_rate,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
+                        OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+                        OMAP24XX_CLKSEL_DSP_MASK,
+                        OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+                        OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
+                        dsp_fck_parent_names, dsp_fck_ops);
+
+static const struct clksel dsp_ick_clksel[] = {
+       { .parent = &dsp_fck, .rates = dsp_ick_rates },
+       { .parent = NULL },
+};
+
+static const char *dsp_ick_parent_names[] = {
+       "dsp_fck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel,
+                        OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+                        OMAP24XX_CLKSEL_DSP_IF_MASK,
+                        OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+                        OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait,
+                        dsp_ick_parent_names, dsp_fck_ops);
+
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+       { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel_rate dss1_fck_core_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+       { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+       { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+       { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+       { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+       { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+       { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+       { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+       { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+       { .div = 16, .val = 16, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel dss1_fck_clksel[] = {
+       { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
+       { .parent = &core_ck, .rates = dss1_fck_core_rates },
+       { .parent = NULL },
+};
+
+static const char *dss1_fck_parent_names[] = {
+       "sys_ck", "core_ck",
+};
+
+static struct clk dss1_fck;
+
+static const struct clk_ops dss1_fck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_dflt_clk_enable,
+       .disable        = &omap2_dflt_clk_disable,
+       .is_enabled     = &omap2_dflt_clk_is_enabled,
+       .recalc_rate    = &omap2_clksel_recalc,
+       .get_parent     = &omap2_clksel_find_parent_index,
+       .set_parent     = &omap2_clksel_set_parent,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                        OMAP24XX_CLKSEL_DSS1_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_DSS1_SHIFT, NULL,
+                        dss1_fck_parent_names, dss1_fck_ops);
+
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+       { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel_rate func_48m_apll96_rates[] = {
+       { .div = 2, .val = 0, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel_rate func_48m_alt_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel func_48m_clksel[] = {
+       { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+       { .parent = &alt_ck, .rates = func_48m_alt_rates },
+       { .parent = NULL },
+};
+
+static const char *func_48m_ck_parent_names[] = {
+       "apll96_ck", "alt_ck",
+};
+
+static struct clk func_48m_ck;
+
+static const struct clk_ops func_48m_ck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .recalc_rate    = &omap2_clksel_recalc,
+       .set_rate       = &omap2_clksel_set_rate,
+       .round_rate     = &omap2_clksel_round_rate,
+       .get_parent     = &omap2_clksel_find_parent_index,
+       .set_parent     = &omap2_clksel_set_parent,
+};
+
+static struct clk_hw_omap func_48m_ck_hw = {
+       .hw = {
+               .clk = &func_48m_ck,
+       },
+       .clksel         = func_48m_clksel,
+       .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
+
+static const struct clksel dss2_fck_clksel[] = {
+       { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
+       { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+       { .parent = NULL },
+};
+
+static const char *dss2_fck_parent_names[] = {
+       "sys_ck", "func_48m_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                        OMAP24XX_CLKSEL_DSS2_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_DSS2_SHIFT, NULL,
+                        dss2_fck_parent_names, dss1_fck_ops);
+
+static const char *func_54m_ck_parent_names[] = {
+       "apll54_ck", "alt_ck",
+};
+
+DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
+              OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+              OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH,
+              0x0, NULL);
+
+static struct clk dss_54m_fck;
+
+static const char *dss_54m_fck_parent_names[] = {
+       "func_54m_ck",
+};
+
+static struct clk_hw_omap dss_54m_fck_hw = {
+       .hw = {
+               .clk = &dss_54m_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_TV_SHIFT,
+       .clkdm_name     = "dss_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
+
+static struct clk dss_ick;
+
+static struct clk_hw_omap dss_ick_hw = {
+       .hw = {
+               .clk = &dss_ick,
+       },
+       .ops            = &clkhwops_iclk,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+       .clkdm_name     = "dss_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk eac_fck;
+
+static struct clk_hw_omap eac_fck_hw = {
+       .hw = {
+               .clk = &eac_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP2420_EN_EAC_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk eac_ick;
+
+static struct clk_hw_omap eac_ick_hw = {
+       .hw = {
+               .clk = &eac_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP2420_EN_EAC_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk emul_ck;
+
+static struct clk_hw_omap emul_ck_hw = {
+       .hw = {
+               .clk = &emul_ck,
+       },
+       .enable_reg     = OMAP2420_PRCM_CLKEMUL_CTRL,
+       .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
+
+DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
+
+static struct clk fac_fck;
+
+static const char *fac_fck_parent_names[] = {
+       "func_12m_ck",
+};
+
+static struct clk_hw_omap fac_fck_hw = {
+       .hw = {
+               .clk = &fac_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk fac_ick;
+
+static struct clk_hw_omap fac_ick_hw = {
+       .hw = {
+               .clk = &fac_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel gfx_fck_clksel[] = {
+       { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+       { .parent = NULL },
+};
+
+static const char *gfx_2d_fck_parent_names[] = {
+       "core_l3_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
+                        OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+                        OMAP_CLKSEL_GFX_MASK,
+                        OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+                        OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
+                        gfx_2d_fck_parent_names, dsp_fck_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
+                        OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+                        OMAP_CLKSEL_GFX_MASK,
+                        OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+                        OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
+                        gfx_2d_fck_parent_names, dsp_fck_ops);
+
+static struct clk gfx_ick;
+
+static const char *gfx_ick_parent_names[] = {
+       "core_l3_ck",
+};
+
+static struct clk_hw_omap gfx_ick_hw = {
+       .hw = {
+               .clk = &gfx_ick,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+       .enable_bit     = OMAP_EN_GFX_SHIFT,
+       .clkdm_name     = "gfx_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
+
+static struct clk gpios_fck;
+
+static const char *gpios_fck_parent_names[] = {
+       "func_32k_ck",
+};
+
+static struct clk_hw_omap gpios_fck_hw = {
+       .hw = {
+               .clk = &gpios_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk wu_l4_ick;
+
+DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
+DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
+
+static struct clk gpios_ick;
+
+static const char *gpios_ick_parent_names[] = {
+       "wu_l4_ick",
+};
+
+static struct clk_hw_omap gpios_ick_hw = {
+       .hw = {
+               .clk = &gpios_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk gpmc_fck;
+
+static struct clk_hw_omap gpmc_fck_hw = {
+       .hw = {
+               .clk = &gpmc_fck,
+       },
+       .ops            = &clkhwops_iclk,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+       .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
+       .flags          = ENABLE_ON_INIT,
+       .clkdm_name     = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
+
+static const struct clksel_rate gpt_alt_rates[] = {
+       { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel omap24xx_gpt_clksel[] = {
+       { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+       { .parent = &sys_ck, .rates = gpt_sys_rates },
+       { .parent = &alt_ck, .rates = gpt_alt_rates },
+       { .parent = NULL },
+};
+
+static const char *gpt10_fck_parent_names[] = {
+       "func_32k_ck", "sys_ck", "alt_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT10_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt10_ick;
+
+static struct clk_hw_omap gpt10_ick_hw = {
+       .hw = {
+               .clk = &gpt10_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT11_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt11_ick;
+
+static struct clk_hw_omap gpt11_ick_hw = {
+       .hw = {
+               .clk = &gpt11_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT12_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt12_ick;
+
+static struct clk_hw_omap gpt12_ick_hw = {
+       .hw = {
+               .clk = &gpt12_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clk_ops gpt1_fck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_dflt_clk_enable,
+       .disable        = &omap2_dflt_clk_disable,
+       .is_enabled     = &omap2_dflt_clk_is_enabled,
+       .recalc_rate    = &omap2_clksel_recalc,
+       .set_rate       = &omap2_clksel_set_rate,
+       .round_rate     = &omap2_clksel_round_rate,
+       .get_parent     = &omap2_clksel_find_parent_index,
+       .set_parent     = &omap2_clksel_set_parent,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+                        OMAP24XX_CLKSEL_GPT1_MASK,
+                        OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+                        OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, gpt1_fck_ops);
+
+static struct clk gpt1_ick;
+
+static struct clk_hw_omap gpt1_ick_hw = {
+       .hw = {
+               .clk = &gpt1_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT2_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt2_ick;
+
+static struct clk_hw_omap gpt2_ick_hw = {
+       .hw = {
+               .clk = &gpt2_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT3_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt3_ick;
+
+static struct clk_hw_omap gpt3_ick_hw = {
+       .hw = {
+               .clk = &gpt3_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT4_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt4_ick;
+
+static struct clk_hw_omap gpt4_ick_hw = {
+       .hw = {
+               .clk = &gpt4_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT5_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt5_ick;
+
+static struct clk_hw_omap gpt5_ick_hw = {
+       .hw = {
+               .clk = &gpt5_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT6_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt6_ick;
+
+static struct clk_hw_omap gpt6_ick_hw = {
+       .hw = {
+               .clk = &gpt6_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT7_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt7_ick;
+
+static struct clk_hw_omap gpt7_ick_hw = {
+       .hw = {
+               .clk = &gpt7_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT8_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt8_ick;
+
+static struct clk_hw_omap gpt8_ick_hw = {
+       .hw = {
+               .clk = &gpt8_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT9_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt9_ick;
+
+static struct clk_hw_omap gpt9_ick_hw = {
+       .hw = {
+               .clk = &gpt9_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk hdq_fck;
+
+static struct clk_hw_omap hdq_fck_hw = {
+       .hw = {
+               .clk = &hdq_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk hdq_ick;
+
+static struct clk_hw_omap hdq_ick_hw = {
+       .hw = {
+               .clk = &hdq_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2c1_fck;
+
+static struct clk_hw_omap i2c1_fck_hw = {
+       .hw = {
+               .clk = &i2c1_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk i2c1_ick;
+
+static struct clk_hw_omap i2c1_ick_hw = {
+       .hw = {
+               .clk = &i2c1_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2c2_fck;
+
+static struct clk_hw_omap i2c2_fck_hw = {
+       .hw = {
+               .clk = &i2c2_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk i2c2_ick;
+
+static struct clk_hw_omap i2c2_ick_hw = {
+       .hw = {
+               .clk = &i2c2_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,
+                        OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+                        OMAP2420_CLKSEL_IVA_MASK,
+                        OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+                        OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait,
+                        dsp_fck_parent_names, dsp_fck_ops);
+
+static struct clk iva1_mpu_int_ifck;
+
+static const char *iva1_mpu_int_ifck_parent_names[] = {
+       "iva1_ifck",
+};
+
+static const struct clk_ops iva1_mpu_int_ifck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_dflt_clk_enable,
+       .disable        = &omap2_dflt_clk_disable,
+       .is_enabled     = &omap2_dflt_clk_is_enabled,
+       .recalc_rate    = &omap_fixed_divisor_recalc,
+};
+
+static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
+       .hw = {
+               .clk = &iva1_mpu_int_ifck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+       .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
+       .clkdm_name     = "iva1_clkdm",
+       .fixed_div      = 2,
+};
+
+DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names,
+                 iva1_mpu_int_ifck_ops);
+
+static struct clk mailboxes_ick;
+
+static struct clk_hw_omap mailboxes_ick_hw = {
+       .hw = {
+               .clk = &mailboxes_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+       { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel mcbsp_fck_clksel[] = {
+       { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
+       { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
+       { .parent = NULL },
+};
+
+static const char *mcbsp1_fck_parent_names[] = {
+       "func_96m_ck", "mcbsp_clks",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+                        OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+                        OMAP2_MCBSP1_CLKS_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
+                        mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp1_ick;
+
+static struct clk_hw_omap mcbsp1_ick_hw = {
+       .hw = {
+               .clk = &mcbsp1_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+                        OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+                        OMAP2_MCBSP2_CLKS_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
+                        mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp2_ick;
+
+static struct clk_hw_omap mcbsp2_ick_hw = {
+       .hw = {
+               .clk = &mcbsp2_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mcspi1_fck;
+
+static const char *mcspi1_fck_parent_names[] = {
+       "func_48m_ck",
+};
+
+static struct clk_hw_omap mcspi1_fck_hw = {
+       .hw = {
+               .clk = &mcspi1_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk mcspi1_ick;
+
+static struct clk_hw_omap mcspi1_ick_hw = {
+       .hw = {
+               .clk = &mcspi1_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mcspi2_fck;
+
+static struct clk_hw_omap mcspi2_fck_hw = {
+       .hw = {
+               .clk = &mcspi2_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk mcspi2_ick;
+
+static struct clk_hw_omap mcspi2_ick_hw = {
+       .hw = {
+               .clk = &mcspi2_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mmc_fck;
+
+static struct clk_hw_omap mmc_fck_hw = {
+       .hw = {
+               .clk = &mmc_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP2420_EN_MMC_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk mmc_ick;
+
+static struct clk_hw_omap mmc_ick_hw = {
+       .hw = {
+               .clk = &mmc_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP2420_EN_MMC_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
+                  OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+                  OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
+                  CLK_DIVIDER_ONE_BASED, NULL);
+
+static struct clk mpu_wdt_fck;
+
+static struct clk_hw_omap mpu_wdt_fck_hw = {
+       .hw = {
+               .clk = &mpu_wdt_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk mpu_wdt_ick;
+
+static struct clk_hw_omap mpu_wdt_ick_hw = {
+       .hw = {
+               .clk = &mpu_wdt_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk mspro_fck;
+
+static struct clk_hw_omap mspro_fck_hw = {
+       .hw = {
+               .clk = &mspro_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk mspro_ick;
+
+static struct clk_hw_omap mspro_ick_hw = {
+       .hw = {
+               .clk = &mspro_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk omapctrl_ick;
+
+static struct clk_hw_omap omapctrl_ick_hw = {
+       .hw = {
+               .clk = &omapctrl_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
+       .flags          = ENABLE_ON_INIT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk pka_ick;
+
+static struct clk_hw_omap pka_ick_hw = {
+       .hw = {
+               .clk = &pka_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+       .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk rng_ick;
+
+static struct clk_hw_omap rng_ick_hw = {
+       .hw = {
+               .clk = &rng_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+       .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk sdma_fck;
+
+DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
+DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sdma_ick;
+
+static struct clk_hw_omap sdma_ick_hw = {
+       .hw = {
+               .clk = &sdma_ick,
+       },
+       .ops            = &clkhwops_iclk,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+       .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
+       .clkdm_name     = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sdrc_ick;
+
+static struct clk_hw_omap sdrc_ick_hw = {
+       .hw = {
+               .clk = &sdrc_ick,
+       },
+       .ops            = &clkhwops_iclk,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+       .enable_bit     = OMAP24XX_AUTO_SDRC_SHIFT,
+       .flags          = ENABLE_ON_INIT,
+       .clkdm_name     = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sha_ick;
+
+static struct clk_hw_omap sha_ick_hw = {
+       .hw = {
+               .clk = &sha_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+       .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk ssi_l4_ick;
+
+static struct clk_hw_omap ssi_l4_ick_hw = {
+       .hw = {
+               .clk = &ssi_l4_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+       { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+       { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+       { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+       { .div = 6, .val = 6, .flags = RATE_IN_242X },
+       { .div = 8, .val = 8, .flags = RATE_IN_242X },
+       { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+       { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+       { .parent = NULL },
+};
+
+static const char *ssi_ssr_sst_fck_parent_names[] = {
+       "core_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
+                        ssi_ssr_sst_fck_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                        OMAP24XX_CLKSEL_SSI_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+                        OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
+                        ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
+
+static struct clk sync_32k_ick;
+
+static struct clk_hw_omap sync_32k_ick_hw = {
+       .hw = {
+               .clk = &sync_32k_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
+       .flags          = ENABLE_ON_INIT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+       { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+       { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+       { .div = 1, .val = 3, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel common_clkout_src_clksel[] = {
+       { .parent = &core_ck, .rates = common_clkout_src_core_rates },
+       { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
+       { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+       { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+       { .parent = NULL },
+};
+
+static const char *sys_clkout_src_parent_names[] = {
+       "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
+                        OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
+                        OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
+                        NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
+
+DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
+                  OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
+                  OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
+                        common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL,
+                        OMAP2420_CLKOUT2_SOURCE_MASK,
+                        OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT,
+                        NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
+
+DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0,
+                  OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT,
+                  OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static struct clk uart1_fck;
+
+static struct clk_hw_omap uart1_fck_hw = {
+       .hw = {
+               .clk = &uart1_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart1_ick;
+
+static struct clk_hw_omap uart1_ick_hw = {
+       .hw = {
+               .clk = &uart1_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk uart2_fck;
+
+static struct clk_hw_omap uart2_fck_hw = {
+       .hw = {
+               .clk = &uart2_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart2_ick;
+
+static struct clk_hw_omap uart2_ick_hw = {
+       .hw = {
+               .clk = &uart2_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk uart3_fck;
+
+static struct clk_hw_omap uart3_fck_hw = {
+       .hw = {
+               .clk = &uart3_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart3_ick;
+
+static struct clk_hw_omap uart3_ick_hw = {
+       .hw = {
+               .clk = &uart3_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk usb_fck;
+
+static struct clk_hw_omap usb_fck_hw = {
+       .hw = {
+               .clk = &usb_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+       .clkdm_name     = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+       { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+       { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel usb_l4_ick_clksel[] = {
+       { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+       { .parent = NULL },
+};
+
+static const char *usb_l4_ick_parent_names[] = {
+       "core_l3_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                        OMAP24XX_CLKSEL_USB_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+                        OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
+                        usb_l4_ick_parent_names, dsp_fck_ops);
+
+static struct clk virt_prcm_set;
+
+static const char *virt_prcm_set_parent_names[] = {
+       "mpu_ck",
+};
+
+static const struct clk_ops virt_prcm_set_ops = {
+       .recalc_rate    = &omap2_table_mpu_recalc,
+       .set_rate       = &omap2_select_table_rate,
+       .round_rate     = &omap2_round_to_table_rate,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
+DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
+
+static const struct clksel_rate vlynq_fck_96m_rates[] = {
+       { .div = 1, .val = 0, .flags = RATE_IN_242X },
+       { .div = 0 }
+};
+
+static const struct clksel_rate vlynq_fck_core_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_242X },
+       { .div = 2, .val = 2, .flags = RATE_IN_242X },
+       { .div = 3, .val = 3, .flags = RATE_IN_242X },
+       { .div = 4, .val = 4, .flags = RATE_IN_242X },
+       { .div = 6, .val = 6, .flags = RATE_IN_242X },
+       { .div = 8, .val = 8, .flags = RATE_IN_242X },
+       { .div = 9, .val = 9, .flags = RATE_IN_242X },
+       { .div = 12, .val = 12, .flags = RATE_IN_242X },
+       { .div = 16, .val = 16, .flags = RATE_IN_242X },
+       { .div = 18, .val = 18, .flags = RATE_IN_242X },
+       { .div = 0 }
+};
+
+static const struct clksel vlynq_fck_clksel[] = {
+       { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
+       { .parent = &core_ck, .rates = vlynq_fck_core_rates },
+       { .parent = NULL },
+};
+
+static const char *vlynq_fck_parent_names[] = {
+       "func_96m_ck", "core_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                        OMAP2420_CLKSEL_VLYNQ_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait,
+                        vlynq_fck_parent_names, dss1_fck_ops);
+
+static struct clk vlynq_ick;
+
+static struct clk_hw_omap vlynq_ick_hw = {
+       .hw = {
+               .clk = &vlynq_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
+       .clkdm_name     = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt1_ick;
+
+static struct clk_hw_omap wdt1_ick_hw = {
+       .hw = {
+               .clk = &wdt1_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt1_osc_ck;
+
+static const struct clk_ops wdt1_osc_ck_ops = {};
+
+DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
+DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
+
+static struct clk wdt3_fck;
+
+static struct clk_hw_omap wdt3_fck_hw = {
+       .hw = {
+               .clk = &wdt3_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk wdt3_ick;
+
+static struct clk_hw_omap wdt3_ick_hw = {
+       .hw = {
+               .clk = &wdt3_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt4_fck;
+
+static struct clk_hw_omap wdt4_fck_hw = {
+       .hw = {
+               .clk = &wdt4_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk wdt4_ick;
+
+static struct clk_hw_omap wdt4_ick_hw = {
+       .hw = {
+               .clk = &wdt4_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
+
+/*
+ * clkdev integration
+ */
+
+static struct omap_clk omap2420_clks[] = {
+       /* external root sources */
+       CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_242X),
+       CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_242X),
+       CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
+       CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
+       CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
+       CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
+       /* internal analog sources */
+       CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
+       CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_242X),
+       CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_242X),
+       /* internal prcm root sources */
+       CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
+       CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
+       CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
+       CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
+       CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
+       CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_242X),
+       CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_242X),
+       CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_242X),
+       CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
+       CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
+       CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
+       /* mpu domain clocks */
+       CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_242X),
+       /* dsp domain clocks */
+       CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_242X),
+       CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
+       CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
+       CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+       /* GFX domain clocks */
+       CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_242X),
+       CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_242X),
+       CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
+       /* DSS domain clocks */
+       CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
+       CLK(NULL,       "dss_ick",              &dss_ick,       CK_242X),
+       CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_242X),
+       CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_242X),
+       CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_242X),
+       /* L3 domain clocks */
+       CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_242X),
+       CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_242X),
+       CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_242X),
+       /* L4 domain clocks */
+       CLK(NULL,       "l4_ck",        &l4_ck,         CK_242X),
+       CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_242X),
+       CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_242X),
+       /* virtual meta-group clock */
+       CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_242X),
+       /* general l4 interface ck, multi-parent functional clk */
+       CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_242X),
+       CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_242X),
+       CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_242X),
+       CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_242X),
+       CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_242X),
+       CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_242X),
+       CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_242X),
+       CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_242X),
+       CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_242X),
+       CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_242X),
+       CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_242X),
+       CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_242X),
+       CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_242X),
+       CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_242X),
+       CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_242X),
+       CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_242X),
+       CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_242X),
+       CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_242X),
+       CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_242X),
+       CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_242X),
+       CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_242X),
+       CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_242X),
+       CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
+       CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
+       CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
+       CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_242X),
+       CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_242X),
+       CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
+       CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_242X),
+       CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_242X),
+       CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
+       CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_242X),
+       CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_242X),
+       CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
+       CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_242X),
+       CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_242X),
+       CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
+       CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
+       CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_242X),
+       CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_242X),
+       CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_242X),
+       CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_242X),
+       CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
+       CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
+       CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
+       CLK(NULL,       "mpu_wdt_ick",          &mpu_wdt_ick,   CK_242X),
+       CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_242X),
+       CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
+       CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
+       CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
+       CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
+       CLK(NULL,       "cam_fck",      &cam_fck,       CK_242X),
+       CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
+       CLK(NULL,       "cam_ick",      &cam_ick,       CK_242X),
+       CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
+       CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
+       CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
+       CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
+       CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
+       CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
+       CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
+       CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
+       CLK(NULL,       "mmc_ick",      &mmc_ick,       CK_242X),
+       CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
+       CLK(NULL,       "mmc_fck",      &mmc_fck,       CK_242X),
+       CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
+       CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
+       CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
+       CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
+       CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
+       CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_242X),
+       CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_242X),
+       CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_242X),
+       CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
+       CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_242X),
+       CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_242X),
+       CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
+       CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_242X),
+       CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_242X),
+       CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
+       CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
+       CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
+       CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_242X),
+       CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
+       CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
+       CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
+       CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
+       CLK(NULL,       "sha_ick",      &sha_ick,       CK_242X),
+       CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
+       CLK(NULL,       "rng_ick",              &rng_ick,       CK_242X),
+       CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
+       CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
+       CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
+       CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
+       CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
+       CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_242X),
+       CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_242X),
+       CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_242X),
+       CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_242X),
+};
+
+
+static const char *enable_init_clks[] = {
+       "apll96_ck",
+       "apll54_ck",
+       "sync_32k_ick",
+       "omapctrl_ick",
+       "gpmc_fck",
+       "sdrc_ick",
+};
+
+/*
+ * init code
+ */
+
+int __init omap2420_clk_init(void)
+{
+       const struct prcm_config *prcm;
+       struct omap_clk *c;
+       unsigned long clkrate;
+
+       prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
+       cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
+       cpu_mask = RATE_IN_242X;
+       rate_table = omap2420_rate_table;
+
+       /* Check the MPU rate set by bootloader */
+       clkrate = omap2xxx_clk_get_core_rate(&dpll_ck_hw);
+       for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+               if (!(prcm->flags & cpu_mask))
+                       continue;
+               if (prcm->xtal_speed != sys_ck.rate)
+                       continue;
+               if (prcm->dpll_speed <= clkrate)
+                       break;
+       }
+
+       curr_prcm_set = prcm;
+
+       for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
+            c++) {
+               clkdev_add(&c->lk);
+               if (!__clk_init(NULL, c->lk.clk))
+                       omap2_init_clk_hw_omap_clocks(c->lk.clk);
+       }
+
+       omap2_clk_disable_autoidle_all();
+
+       omap2_clk_enable_init_clocks(enable_init_clks,
+                                    ARRAY_SIZE(enable_init_clks));
+
+       pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
+               (clk_get_rate(&sys_ck) / 1000000),
+               (clk_get_rate(&sys_ck) / 100000) % 10,
+               (clk_get_rate(&dpll_ck) / 1000000),
+               (clk_get_rate(&mpu_ck) / 1000000));
+
+       return 0;
+}

arch/arm/mach-omap2/cclock2430_data.c new file +2076 -0

new file mode 100644
index 0000000..102fbba
@@ -0,0 +1,2076 @@
+/*
+ * OMAP2430 clock data
+ *
+ * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <[email protected]>
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/list.h>
+
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm2xxx.h"
+#include "prm2xxx.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "control.h"
+
+#define OMAP_CM_REGADDR                        OMAP2430_CM_REGADDR
+
+/*
+ * 2430 clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ *     many cases the parent is selectable. The set parent calls will
+ *     also switch sources.
+ *
+ *     Several sources are given initial rates which may be wrong, this will
+ *     be fixed up in the init func.
+ *
+ *     Things are broadly separated below by clock domains. It is
+ *     noteworthy that most peripherals have dependencies on multiple clock
+ *     domains. Many get their interface clocks from the L4 domain, but get
+ *     functional clocks from fixed sources or other core domain derived
+ *     clocks.
+ */
+
+DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
+
+static struct clk osc_ck;
+
+static const struct clk_ops osc_ck_ops = {
+       .enable         = &omap2_enable_osc_ck,
+       .disable        = omap2_disable_osc_ck,
+       .recalc_rate    = &omap2_osc_clk_recalc,
+};
+
+static struct clk_hw_omap osc_ck_hw = {
+       .hw = {
+               .clk = &osc_ck,
+       },
+};
+
+static struct clk osc_ck = {
+       .name   = "osc_ck",
+       .ops    = &osc_ck_ops,
+       .hw     = &osc_ck_hw.hw,
+       .flags  = CLK_IS_ROOT,
+};
+
+DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+static struct clk sys_ck;
+
+static const char *sys_ck_parent_names[] = {
+       "osc_ck",
+};
+
+static const struct clk_ops sys_ck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .recalc_rate    = &omap2xxx_sys_clk_recalc,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
+
+static struct dpll_data dpll_dd = {
+       .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .mult_mask      = OMAP24XX_DPLL_MULT_MASK,
+       .div1_mask      = OMAP24XX_DPLL_DIV_MASK,
+       .clk_bypass     = &sys_ck,
+       .clk_ref        = &sys_ck,
+       .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_mask    = OMAP24XX_EN_DPLL_MASK,
+       .max_multiplier = 1023,
+       .min_divider    = 1,
+       .max_divider    = 16,
+};
+
+static struct clk dpll_ck;
+
+static const char *dpll_ck_parent_names[] = {
+       "sys_ck",
+};
+
+static const struct clk_ops dpll_ck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .get_parent             = &omap2_init_dpll_parent,
+       .recalc_rate    = &omap2_dpllcore_recalc,
+       .round_rate     = &omap2_dpll_round_rate,
+       .set_rate       = &omap2_reprogram_dpllcore,
+};
+
+static struct clk_hw_omap dpll_ck_hw = {
+       .hw = {
+               .clk = &dpll_ck,
+       },
+       .ops            = &clkhwops_omap2xxx_dpll,
+       .dpll_data      = &dpll_dd,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
+
+static struct clk core_ck;
+
+static const char *core_ck_parent_names[] = {
+       "dpll_ck",
+};
+
+static const struct clk_ops core_ck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
+
+DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
+                  OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                  OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
+                  CLK_DIVIDER_ONE_BASED, NULL);
+
+DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
+                  OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                  OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
+                  CLK_DIVIDER_ONE_BASED, NULL);
+
+static struct clk aes_ick;
+
+static const char *aes_ick_parent_names[] = {
+       "l4_ck",
+};
+
+static const struct clk_ops aes_ick_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_dflt_clk_enable,
+       .disable        = &omap2_dflt_clk_disable,
+       .is_enabled     = &omap2_dflt_clk_is_enabled,
+};
+
+static struct clk_hw_omap aes_ick_hw = {
+       .hw = {
+               .clk = &aes_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+       .enable_bit     = OMAP24XX_EN_AES_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk apll54_ck;
+
+static const struct clk_ops apll54_ck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_clk_apll54_enable,
+       .disable        = &omap2_clk_apll_disable,
+       .recalc_rate    = &omap2_clk_apll54_recalc,
+};
+
+static struct clk_hw_omap apll54_ck_hw = {
+       .hw = {
+               .clk = &apll54_ck,
+       },
+       .ops            = &clkhwops_apll54,
+       .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
+       .flags          = ENABLE_ON_INIT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
+
+static struct clk apll96_ck;
+
+static const struct clk_ops apll96_ck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_clk_apll96_enable,
+       .disable        = &omap2_clk_apll_disable,
+       .recalc_rate    = &omap2_clk_apll96_recalc,
+};
+
+static struct clk_hw_omap apll96_ck_hw = {
+       .hw = {
+               .clk = &apll96_ck,
+       },
+       .ops            = &clkhwops_apll96,
+       .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
+       .flags          = ENABLE_ON_INIT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
+
+static const char *func_96m_ck_parent_names[] = {
+       "apll96_ck", "alt_ck",
+};
+
+DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0,
+              OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT,
+              OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL);
+
+static struct clk cam_fck;
+
+static const char *cam_fck_parent_names[] = {
+       "func_96m_ck",
+};
+
+static struct clk_hw_omap cam_fck_hw = {
+       .hw = {
+               .clk = &cam_fck,
+       },
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+       .clkdm_name     = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk cam_ick;
+
+static struct clk_hw_omap cam_ick_hw = {
+       .hw = {
+               .clk = &cam_ick,
+       },
+       .ops            = &clkhwops_iclk,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk des_ick;
+
+static struct clk_hw_omap des_ick_hw = {
+       .hw = {
+               .clk = &des_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+       .enable_bit     = OMAP24XX_EN_DES_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate dsp_fck_core_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+       { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+       { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+       { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel dsp_fck_clksel[] = {
+       { .parent = &core_ck, .rates = dsp_fck_core_rates },
+       { .parent = NULL },
+};
+
+static const char *dsp_fck_parent_names[] = {
+       "core_ck",
+};
+
+static struct clk dsp_fck;
+
+static const struct clk_ops dsp_fck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_dflt_clk_enable,
+       .disable        = &omap2_dflt_clk_disable,
+       .is_enabled     = &omap2_dflt_clk_is_enabled,
+       .recalc_rate    = &omap2_clksel_recalc,
+       .set_rate       = &omap2_clksel_set_rate,
+       .round_rate     = &omap2_clksel_round_rate,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
+                        OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+                        OMAP24XX_CLKSEL_DSP_MASK,
+                        OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+                        OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
+                        dsp_fck_parent_names, dsp_fck_ops);
+
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+       { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel_rate dss1_fck_core_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+       { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+       { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+       { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+       { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+       { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+       { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+       { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+       { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+       { .div = 16, .val = 16, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel dss1_fck_clksel[] = {
+       { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
+       { .parent = &core_ck, .rates = dss1_fck_core_rates },
+       { .parent = NULL },
+};
+
+static const char *dss1_fck_parent_names[] = {
+       "sys_ck", "core_ck",
+};
+
+static const struct clk_ops dss1_fck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_dflt_clk_enable,
+       .disable        = &omap2_dflt_clk_disable,
+       .is_enabled     = &omap2_dflt_clk_is_enabled,
+       .recalc_rate    = &omap2_clksel_recalc,
+       .get_parent     = &omap2_clksel_find_parent_index,
+       .set_parent     = &omap2_clksel_set_parent,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                        OMAP24XX_CLKSEL_DSS1_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_DSS1_SHIFT, NULL,
+                        dss1_fck_parent_names, dss1_fck_ops);
+
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+       { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel_rate func_48m_apll96_rates[] = {
+       { .div = 2, .val = 0, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel_rate func_48m_alt_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel func_48m_clksel[] = {
+       { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+       { .parent = &alt_ck, .rates = func_48m_alt_rates },
+       { .parent = NULL },
+};
+
+static const char *func_48m_ck_parent_names[] = {
+       "apll96_ck", "alt_ck",
+};
+
+static struct clk func_48m_ck;
+
+static const struct clk_ops func_48m_ck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .recalc_rate    = &omap2_clksel_recalc,
+       .set_rate       = &omap2_clksel_set_rate,
+       .round_rate     = &omap2_clksel_round_rate,
+       .get_parent     = &omap2_clksel_find_parent_index,
+       .set_parent     = &omap2_clksel_set_parent,
+};
+
+static struct clk_hw_omap func_48m_ck_hw = {
+       .hw = {
+               .clk = &func_48m_ck,
+       },
+       .clksel         = func_48m_clksel,
+       .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
+
+static const struct clksel dss2_fck_clksel[] = {
+       { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
+       { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+       { .parent = NULL },
+};
+
+static const char *dss2_fck_parent_names[] = {
+       "sys_ck", "func_48m_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                        OMAP24XX_CLKSEL_DSS2_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_DSS2_SHIFT, NULL,
+                        dss2_fck_parent_names, dss1_fck_ops);
+
+static const char *func_54m_ck_parent_names[] = {
+       "apll54_ck", "alt_ck",
+};
+
+DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
+              OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+              OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL);
+
+static struct clk dss_54m_fck;
+
+static const char *dss_54m_fck_parent_names[] = {
+       "func_54m_ck",
+};
+
+static struct clk_hw_omap dss_54m_fck_hw = {
+       .hw = {
+               .clk = &dss_54m_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_TV_SHIFT,
+       .clkdm_name     = "dss_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
+
+static struct clk dss_ick;
+
+static struct clk_hw_omap dss_ick_hw = {
+       .hw = {
+               .clk = &dss_ick,
+       },
+       .ops            = &clkhwops_iclk,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+       .clkdm_name     = "dss_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk emul_ck;
+
+static struct clk_hw_omap emul_ck_hw = {
+       .hw = {
+               .clk = &emul_ck,
+       },
+       .enable_reg     = OMAP2430_PRCM_CLKEMUL_CTRL,
+       .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
+
+DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
+
+static struct clk fac_fck;
+
+static const char *fac_fck_parent_names[] = {
+       "func_12m_ck",
+};
+
+static struct clk_hw_omap fac_fck_hw = {
+       .hw = {
+               .clk = &fac_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk fac_ick;
+
+static struct clk_hw_omap fac_ick_hw = {
+       .hw = {
+               .clk = &fac_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel gfx_fck_clksel[] = {
+       { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+       { .parent = NULL },
+};
+
+static const char *gfx_2d_fck_parent_names[] = {
+       "core_l3_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
+                        OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+                        OMAP_CLKSEL_GFX_MASK,
+                        OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+                        OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
+                        gfx_2d_fck_parent_names, dsp_fck_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
+                        OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+                        OMAP_CLKSEL_GFX_MASK,
+                        OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+                        OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
+                        gfx_2d_fck_parent_names, dsp_fck_ops);
+
+static struct clk gfx_ick;
+
+static const char *gfx_ick_parent_names[] = {
+       "core_l3_ck",
+};
+
+static struct clk_hw_omap gfx_ick_hw = {
+       .hw = {
+               .clk = &gfx_ick,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+       .enable_bit     = OMAP_EN_GFX_SHIFT,
+       .clkdm_name     = "gfx_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
+
+static struct clk gpio5_fck;
+
+static const char *gpio5_fck_parent_names[] = {
+       "func_32k_ck",
+};
+
+static struct clk_hw_omap gpio5_fck_hw = {
+       .hw = {
+               .clk = &gpio5_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops);
+
+static struct clk gpio5_ick;
+
+static struct clk_hw_omap gpio5_ick_hw = {
+       .hw = {
+               .clk = &gpio5_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk gpios_fck;
+
+static struct clk_hw_omap gpios_fck_hw = {
+       .hw = {
+               .clk = &gpios_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops);
+
+static struct clk wu_l4_ick;
+
+DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
+DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
+
+static struct clk gpios_ick;
+
+static const char *gpios_ick_parent_names[] = {
+       "wu_l4_ick",
+};
+
+static struct clk_hw_omap gpios_ick_hw = {
+       .hw = {
+               .clk = &gpios_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk gpmc_fck;
+
+static struct clk_hw_omap gpmc_fck_hw = {
+       .hw = {
+               .clk = &gpmc_fck,
+       },
+       .ops            = &clkhwops_iclk,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+       .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
+       .flags          = ENABLE_ON_INIT,
+       .clkdm_name     = "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
+
+static const struct clksel_rate gpt_alt_rates[] = {
+       { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+       { .div = 0 }
+};
+
+static const struct clksel omap24xx_gpt_clksel[] = {
+       { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+       { .parent = &sys_ck, .rates = gpt_sys_rates },
+       { .parent = &alt_ck, .rates = gpt_alt_rates },
+       { .parent = NULL },
+};
+
+static const char *gpt10_fck_parent_names[] = {
+       "func_32k_ck", "sys_ck", "alt_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT10_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt10_ick;
+
+static struct clk_hw_omap gpt10_ick_hw = {
+       .hw = {
+               .clk = &gpt10_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT11_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt11_ick;
+
+static struct clk_hw_omap gpt11_ick_hw = {
+       .hw = {
+               .clk = &gpt11_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT12_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt12_ick;
+
+static struct clk_hw_omap gpt12_ick_hw = {
+       .hw = {
+               .clk = &gpt12_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clk_ops gpt1_fck_ops = {
+       .init           = &omap2_init_clk_clkdm,
+       .enable         = &omap2_dflt_clk_enable,
+       .disable        = &omap2_dflt_clk_disable,
+       .is_enabled     = &omap2_dflt_clk_is_enabled,
+       .recalc_rate    = &omap2_clksel_recalc,
+       .set_rate       = &omap2_clksel_set_rate,
+       .round_rate     = &omap2_clksel_round_rate,
+       .get_parent     = &omap2_clksel_find_parent_index,
+       .set_parent     = &omap2_clksel_set_parent,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+                        OMAP24XX_CLKSEL_GPT1_MASK,
+                        OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+                        OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, gpt1_fck_ops);
+
+static struct clk gpt1_ick;
+
+static struct clk_hw_omap gpt1_ick_hw = {
+       .hw = {
+               .clk = &gpt1_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT2_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt2_ick;
+
+static struct clk_hw_omap gpt2_ick_hw = {
+       .hw = {
+               .clk = &gpt2_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT3_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt3_ick;
+
+static struct clk_hw_omap gpt3_ick_hw = {
+       .hw = {
+               .clk = &gpt3_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT4_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt4_ick;
+
+static struct clk_hw_omap gpt4_ick_hw = {
+       .hw = {
+               .clk = &gpt4_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT5_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt5_ick;
+
+static struct clk_hw_omap gpt5_ick_hw = {
+       .hw = {
+               .clk = &gpt5_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT6_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt6_ick;
+
+static struct clk_hw_omap gpt6_ick_hw = {
+       .hw = {
+               .clk = &gpt6_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT7_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt7_ick;
+
+static struct clk_hw_omap gpt7_ick_hw = {
+       .hw = {
+               .clk = &gpt7_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk gpt8_fck;
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT8_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt8_ick;
+
+static struct clk_hw_omap gpt8_ick_hw = {
+       .hw = {
+               .clk = &gpt8_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                        OMAP24XX_CLKSEL_GPT9_MASK,
+                        OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                        OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
+                        gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt9_ick;
+
+static struct clk_hw_omap gpt9_ick_hw = {
+       .hw = {
+               .clk = &gpt9_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk hdq_fck;
+
+static struct clk_hw_omap hdq_fck_hw = {
+       .hw = {
+               .clk = &hdq_fck,
+       },
+       .ops            = &clkhwops_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk hdq_ick;
+
+static struct clk_hw_omap hdq_ick_hw = {
+       .hw = {
+               .clk = &hdq_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2c1_ick;
+
+static struct clk_hw_omap i2c1_ick_hw = {
+       .hw = {
+               .clk = &i2c1_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2c2_ick;
+
+static struct clk_hw_omap i2c2_ick_hw = {
+       .hw = {
+               .clk = &i2c2_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2chs1_fck;
+
+static struct clk_hw_omap i2chs1_fck_hw = {
+       .hw = {
+               .clk = &i2chs1_fck,
+       },
+       .ops            = &clkhwops_omap2430_i2chs_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk i2chs2_fck;
+
+static struct clk_hw_omap i2chs2_fck_hw = {
+       .hw = {
+               .clk = &i2chs2_fck,
+       },
+       .ops            = &clkhwops_omap2430_i2chs_wait,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+       .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
+       .clkdm_name     = "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk icr_ick;
+
+static struct clk_hw_omap icr_ick_hw = {
+       .hw = {
+               .clk = &icr_ick,
+       },
+       .ops            = &clkhwops_iclk_wait,
+       .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_bit     = OMAP2430_EN_ICR_SHIFT,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static const struct clksel dsp_ick_clksel[] = {
+       { .parent = &dsp_fck, .rates = dsp_ick_rates },
+       { .parent = NULL },
+};
+
+static const char *iva2_1_ick_parent_names[] = {
+       "dsp_fck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel,
+                        OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+                        OMAP24XX_CLKSEL_DSP_IF_MASK,
+                        OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+                        OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
+                        iva2_1_ick_parent_names, dsp_fck_ops);
+
+static struct clk mailboxes_ick;
[… more lines in the raw message]

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arch/arm/mach-omap2/cm-regbits-24xx.h +5 -0

index 6862904..f3fcba2 100644

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arch/arm/mach-omap2/prm-regbits-24xx.h +2 -0

index 638da6d..91aa510 100644

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Signature · 1 line

1.7.10.4

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Paul Walmsley

maintainer

2012-11-09 21:22 UTC #58 lore raw

PATCH v2 15/26 ARM: omap2: clock: Add 24xx data using common struct clk

Quoted 7 lines · Mike Turquette

Quoting Paul Walmsley (2012-11-09 12:32:59)
Quoted 4 lines
Here's another update on this one to add the twl.fck clock alias, recently added by commit defa6be1c8216ed2d52d65db81a8a148e73be5f7 ("mfd: Fix compile for twl-core.c by removing cpu_is_omap usage").
I'll post a new series to the list with these fixes rolled in.

Unless you've got other changes, no need to worry about it - will deal with it here.

Quoted 4 lines

Do you want me to squash the clkdm_clk_disable/usecount patch into another patch in the series or keep it separate? Separate might be good since we're going to replace that solution with some force-disable thing in the future.

Have moved that one up earlier in the patch stack and added the matching cleanup to the last patch. Will repush the branch once it completes testing again.

Re the upstream CCF support for this, would suggest adding the CCF support for the new function pointer in this merge window (3.8) since it should be relatively straightforward. Then during the 3.9 merge window, the OMAP code can be switched over to use it.

- Paul

Mike Turquette

author

2012-11-09 22:21 UTC #59 lore raw

PATCH v2 15/26 ARM: omap2: clock: Add 24xx data using common struct clk

Quoting Paul Walmsley (2012-11-09 13:22:00)

Quoted 8 lines · Mike Turquette

Quoted 2 lines
Quoting Paul Walmsley (2012-11-09 12:32:59)
Re the upstream CCF support for this, would suggest adding the CCF support for the new function pointer in this merge window (3.8) since it should be relatively straightforward. Then during the 3.9 merge window, the OMAP code can be switched over to use it.

Will do.

Regards,
Mike

Quoted 2 lines

- Paul

Paul Walmsley

maintainer

2012-11-12 22:13 UTC #60 lore raw

PATCH v2 15/26 ARM: omap2: clock: Add 24xx data using common struct clk

In reply to a message not in the archive

This patch needed some updates during the rebase, mostly surrounding the APLL and virt_prcm_set clock handling. Updated patch follows.

- Paul

ARM: OMAP2: clock: Add 24xx data using common struct clk

From: Rajendra Nayak <[email protected]>

The patch is the output from a python script which converts from the old OMAP clk format to COMMON clk format using a JSON parser in between which was developed by Paul Walmsley.

Signed-off-by Rajendra Nayak <[email protected]>

[mturquette at ti.com: removed deprecated variables from omap24x0_clk_init]

Signed-off-by Mike Turquette <[email protected]>

[paul at pwsan.com: fixed boot crash due to missing clock init code; added twl.fck
alias; fix DPLL rate initialization; fix APLL clocks and virt_prcm_set initialization]

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/cclock2420_data.c  | 1950 ++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/cclock2430_data.c  | 2065 ++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/cm-regbits-24xx.h  |    5 
 arch/arm/mach-omap2/prm-regbits-24xx.h |    2 
 4 files changed, 4022 insertions(+)
 create mode 100644 arch/arm/mach-omap2/cclock2420_data.c
 create mode 100644 arch/arm/mach-omap2/cclock2430_data.c

arch/arm/mach-omap2/cclock2420_data.c new file +1950 -0

new file mode 100644
index 0000000..7e5febe
@@ -0,0 +1,1950 @@
+/*
+ * OMAP2420 clock data
+ *
+ * Copyright (C) 2005-2012 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <[email protected]>
+ * Paul Walmsley
+ * Updated to COMMON clk format by Rajendra Nayak <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/list.h>
+
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm2xxx.h"
+#include "prm2xxx.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "control.h"
+
+#define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
+
+/*
+ * 2420 clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ *	many cases the parent is selectable. The set parent calls will
+ *	also switch sources.
+ *
+ *	Several sources are given initial rates which may be wrong, this will
+ *	be fixed up in the init func.
+ *
+ *	Things are broadly separated below by clock domains. It is
+ *	noteworthy that most peripherals have dependencies on multiple clock
+ *	domains. Many get their interface clocks from the L4 domain, but get
+ *	functional clocks from fixed sources or other core domain derived
+ *	clocks.
+ */
+
+DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
+
+static struct clk osc_ck;
+
+static const struct clk_ops osc_ck_ops = {
+	.recalc_rate	= &omap2_osc_clk_recalc,
+};
+
+static struct clk_hw_omap osc_ck_hw = {
+	.hw = {
+		.clk = &osc_ck,
+	},
+};
+
+static struct clk osc_ck = {
+	.name	= "osc_ck",
+	.ops	= &osc_ck_ops,
+	.hw	= &osc_ck_hw.hw,
+	.flags	= CLK_IS_ROOT,
+};
+
+DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+static struct clk sys_ck;
+
+static const char *sys_ck_parent_names[] = {
+	"osc_ck",
+};
+
+static const struct clk_ops sys_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.recalc_rate	= &omap2xxx_sys_clk_recalc,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
+
+static struct dpll_data dpll_dd = {
+	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+	.mult_mask	= OMAP24XX_DPLL_MULT_MASK,
+	.div1_mask	= OMAP24XX_DPLL_DIV_MASK,
+	.clk_bypass	= &sys_ck,
+	.clk_ref	= &sys_ck,
+	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+	.enable_mask	= OMAP24XX_EN_DPLL_MASK,
+	.max_multiplier	= 1023,
+	.min_divider	= 1,
+	.max_divider	= 16,
+};
+
+static struct clk dpll_ck;
+
+static const char *dpll_ck_parent_names[] = {
+	"sys_ck",
+};
+
+static const struct clk_ops dpll_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap2_dpllcore_recalc,
+	.round_rate	= &omap2_dpll_round_rate,
+	.set_rate	= &omap2_reprogram_dpllcore,
+};
+
+static struct clk_hw_omap dpll_ck_hw = {
+	.hw = {
+		.clk = &dpll_ck,
+	},
+	.ops		= &clkhwops_omap2xxx_dpll,
+	.dpll_data	= &dpll_dd,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
+
+static struct clk core_ck;
+
+static const char *core_ck_parent_names[] = {
+	"dpll_ck",
+};
+
+static const struct clk_ops core_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
+
+DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
+		   OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+		   OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
+		   CLK_DIVIDER_ONE_BASED, NULL);
+
+DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
+		   OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+		   OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
+		   CLK_DIVIDER_ONE_BASED, NULL);
+
+static struct clk aes_ick;
+
+static const char *aes_ick_parent_names[] = {
+	"l4_ck",
+};
+
+static const struct clk_ops aes_ick_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+static struct clk_hw_omap aes_ick_hw = {
+	.hw = {
+		.clk = &aes_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+	.enable_bit	= OMAP24XX_EN_AES_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk apll54_ck;
+
+static const struct clk_ops apll54_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_clk_apll54_enable,
+	.disable	= &omap2_clk_apll54_disable,
+	.recalc_rate	= &omap2_clk_apll54_recalc,
+};
+
+static struct clk_hw_omap apll54_ck_hw = {
+	.hw = {
+		.clk = &apll54_ck,
+	},
+	.ops		= &clkhwops_apll54,
+	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+	.enable_bit	= OMAP24XX_EN_54M_PLL_SHIFT,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
+
+static struct clk apll96_ck;
+
+static const struct clk_ops apll96_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_clk_apll96_enable,
+	.disable	= &omap2_clk_apll96_disable,
+	.recalc_rate	= &omap2_clk_apll96_recalc,
+};
+
+static struct clk_hw_omap apll96_ck_hw = {
+	.hw = {
+		.clk = &apll96_ck,
+	},
+	.ops		= &clkhwops_apll96,
+	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+	.enable_bit	= OMAP24XX_EN_96M_PLL_SHIFT,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
+
+static struct clk func_96m_ck;
+
+static const char *func_96m_ck_parent_names[] = {
+	"apll96_ck",
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops);
+
+static struct clk cam_fck;
+
+static const char *cam_fck_parent_names[] = {
+	"func_96m_ck",
+};
+
+static struct clk_hw_omap cam_fck_hw = {
+	.hw = {
+		.clk = &cam_fck,
+	},
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_CAM_SHIFT,
+	.clkdm_name	= "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk cam_ick;
+
+static struct clk_hw_omap cam_ick_hw = {
+	.hw = {
+		.clk = &cam_ick,
+	},
+	.ops		= &clkhwops_iclk,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_CAM_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk des_ick;
+
+static struct clk_hw_omap des_ick_hw = {
+	.hw = {
+		.clk = &des_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+	.enable_bit	= OMAP24XX_EN_DES_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate dsp_fck_core_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
+	{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
+	{ .div = 6, .val = 6, .flags = RATE_IN_242X },
+	{ .div = 8, .val = 8, .flags = RATE_IN_242X },
+	{ .div = 12, .val = 12, .flags = RATE_IN_242X },
+	{ .div = 0 }
+};
+
+static const struct clksel dsp_fck_clksel[] = {
+	{ .parent = &core_ck, .rates = dsp_fck_core_rates },
+	{ .parent = NULL },
+};
+
+static const char *dsp_fck_parent_names[] = {
+	"core_ck",
+};
+
+static const struct clk_ops dsp_fck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+	.recalc_rate	= &omap2_clksel_recalc,
+	.set_rate	= &omap2_clksel_set_rate,
+	.round_rate	= &omap2_clksel_round_rate,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
+			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+			 OMAP24XX_CLKSEL_DSP_MASK,
+			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+			 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
+			 dsp_fck_parent_names, dsp_fck_ops);
+
+static const struct clksel dsp_ick_clksel[] = {
+	{ .parent = &dsp_fck, .rates = dsp_ick_rates },
+	{ .parent = NULL },
+};
+
+static const char *dsp_ick_parent_names[] = {
+	"dsp_fck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel,
+			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+			 OMAP24XX_CLKSEL_DSP_IF_MASK,
+			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+			 OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait,
+			 dsp_ick_parent_names, dsp_fck_ops);
+
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate dss1_fck_core_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
+	{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
+	{ .div = 5, .val = 5, .flags = RATE_IN_24XX },
+	{ .div = 6, .val = 6, .flags = RATE_IN_24XX },
+	{ .div = 8, .val = 8, .flags = RATE_IN_24XX },
+	{ .div = 9, .val = 9, .flags = RATE_IN_24XX },
+	{ .div = 12, .val = 12, .flags = RATE_IN_24XX },
+	{ .div = 16, .val = 16, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel dss1_fck_clksel[] = {
+	{ .parent = &sys_ck, .rates = dss1_fck_sys_rates },
+	{ .parent = &core_ck, .rates = dss1_fck_core_rates },
+	{ .parent = NULL },
+};
+
+static const char *dss1_fck_parent_names[] = {
+	"sys_ck", "core_ck",
+};
+
+static struct clk dss1_fck;
+
+static const struct clk_ops dss1_fck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+	.recalc_rate	= &omap2_clksel_recalc,
+	.get_parent	= &omap2_clksel_find_parent_index,
+	.set_parent	= &omap2_clksel_set_parent,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+			 OMAP24XX_CLKSEL_DSS1_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_DSS1_SHIFT, NULL,
+			 dss1_fck_parent_names, dss1_fck_ops);
+
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate func_48m_apll96_rates[] = {
+	{ .div = 2, .val = 0, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate func_48m_alt_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel func_48m_clksel[] = {
+	{ .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+	{ .parent = &alt_ck, .rates = func_48m_alt_rates },
+	{ .parent = NULL },
+};
+
+static const char *func_48m_ck_parent_names[] = {
+	"apll96_ck", "alt_ck",
+};
+
+static struct clk func_48m_ck;
+
+static const struct clk_ops func_48m_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.recalc_rate	= &omap2_clksel_recalc,
+	.set_rate	= &omap2_clksel_set_rate,
+	.round_rate	= &omap2_clksel_round_rate,
+	.get_parent	= &omap2_clksel_find_parent_index,
+	.set_parent	= &omap2_clksel_set_parent,
+};
+
+static struct clk_hw_omap func_48m_ck_hw = {
+	.hw = {
+		.clk = &func_48m_ck,
+	},
+	.clksel		= func_48m_clksel,
+	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+	.clksel_mask	= OMAP24XX_48M_SOURCE_MASK,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
+
+static const struct clksel dss2_fck_clksel[] = {
+	{ .parent = &sys_ck, .rates = dss2_fck_sys_rates },
+	{ .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+	{ .parent = NULL },
+};
+
+static const char *dss2_fck_parent_names[] = {
+	"sys_ck", "func_48m_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+			 OMAP24XX_CLKSEL_DSS2_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_DSS2_SHIFT, NULL,
+			 dss2_fck_parent_names, dss1_fck_ops);
+
+static const char *func_54m_ck_parent_names[] = {
+	"apll54_ck", "alt_ck",
+};
+
+DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
+	       OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+	       OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH,
+	       0x0, NULL);
+
+static struct clk dss_54m_fck;
+
+static const char *dss_54m_fck_parent_names[] = {
+	"func_54m_ck",
+};
+
+static struct clk_hw_omap dss_54m_fck_hw = {
+	.hw = {
+		.clk = &dss_54m_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_TV_SHIFT,
+	.clkdm_name	= "dss_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
+
+static struct clk dss_ick;
+
+static struct clk_hw_omap dss_ick_hw = {
+	.hw = {
+		.clk = &dss_ick,
+	},
+	.ops		= &clkhwops_iclk,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_DSS1_SHIFT,
+	.clkdm_name	= "dss_clkdm",
+};
+
+DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk eac_fck;
+
+static struct clk_hw_omap eac_fck_hw = {
+	.hw = {
+		.clk = &eac_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP2420_EN_EAC_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk eac_ick;
+
+static struct clk_hw_omap eac_ick_hw = {
+	.hw = {
+		.clk = &eac_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP2420_EN_EAC_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk emul_ck;
+
+static struct clk_hw_omap emul_ck_hw = {
+	.hw = {
+		.clk = &emul_ck,
+	},
+	.enable_reg	= OMAP2420_PRCM_CLKEMUL_CTRL,
+	.enable_bit	= OMAP24XX_EMULATION_EN_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
+
+DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
+
+static struct clk fac_fck;
+
+static const char *fac_fck_parent_names[] = {
+	"func_12m_ck",
+};
+
+static struct clk_hw_omap fac_fck_hw = {
+	.hw = {
+		.clk = &fac_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_FAC_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk fac_ick;
+
+static struct clk_hw_omap fac_ick_hw = {
+	.hw = {
+		.clk = &fac_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_FAC_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel gfx_fck_clksel[] = {
+	{ .parent = &core_l3_ck, .rates = gfx_l3_rates },
+	{ .parent = NULL },
+};
+
+static const char *gfx_2d_fck_parent_names[] = {
+	"core_l3_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
+			 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+			 OMAP_CLKSEL_GFX_MASK,
+			 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+			 OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
+			 gfx_2d_fck_parent_names, dsp_fck_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
+			 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+			 OMAP_CLKSEL_GFX_MASK,
+			 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+			 OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
+			 gfx_2d_fck_parent_names, dsp_fck_ops);
+
+static struct clk gfx_ick;
+
+static const char *gfx_ick_parent_names[] = {
+	"core_l3_ck",
+};
+
+static struct clk_hw_omap gfx_ick_hw = {
+	.hw = {
+		.clk = &gfx_ick,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP_EN_GFX_SHIFT,
+	.clkdm_name	= "gfx_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
+
+static struct clk gpios_fck;
+
+static const char *gpios_fck_parent_names[] = {
+	"func_32k_ck",
+};
+
+static struct clk_hw_omap gpios_fck_hw = {
+	.hw = {
+		.clk = &gpios_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+	.enable_bit	= OMAP24XX_EN_GPIOS_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk wu_l4_ick;
+
+DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
+DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
+
+static struct clk gpios_ick;
+
+static const char *gpios_ick_parent_names[] = {
+	"wu_l4_ick",
+};
+
+static struct clk_hw_omap gpios_ick_hw = {
+	.hw = {
+		.clk = &gpios_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP24XX_EN_GPIOS_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk gpmc_fck;
+
+static struct clk_hw_omap gpmc_fck_hw = {
+	.hw = {
+		.clk = &gpmc_fck,
+	},
+	.ops		= &clkhwops_iclk,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+	.enable_bit	= OMAP24XX_AUTO_GPMC_SHIFT,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
+
+static const struct clksel_rate gpt_alt_rates[] = {
+	{ .div = 1, .val = 2, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel omap24xx_gpt_clksel[] = {
+	{ .parent = &func_32k_ck, .rates = gpt_32k_rates },
+	{ .parent = &sys_ck, .rates = gpt_sys_rates },
+	{ .parent = &alt_ck, .rates = gpt_alt_rates },
+	{ .parent = NULL },
+};
+
+static const char *gpt10_fck_parent_names[] = {
+	"func_32k_ck", "sys_ck", "alt_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT10_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt10_ick;
+
+static struct clk_hw_omap gpt10_ick_hw = {
+	.hw = {
+		.clk = &gpt10_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT10_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT11_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt11_ick;
+
+static struct clk_hw_omap gpt11_ick_hw = {
+	.hw = {
+		.clk = &gpt11_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT11_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT12_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt12_ick;
+
+static struct clk_hw_omap gpt12_ick_hw = {
+	.hw = {
+		.clk = &gpt12_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT12_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clk_ops gpt1_fck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+	.recalc_rate	= &omap2_clksel_recalc,
+	.set_rate	= &omap2_clksel_set_rate,
+	.round_rate	= &omap2_clksel_round_rate,
+	.get_parent	= &omap2_clksel_find_parent_index,
+	.set_parent	= &omap2_clksel_set_parent,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+			 OMAP24XX_CLKSEL_GPT1_MASK,
+			 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+			 OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, gpt1_fck_ops);
+
+static struct clk gpt1_ick;
+
+static struct clk_hw_omap gpt1_ick_hw = {
+	.hw = {
+		.clk = &gpt1_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP24XX_EN_GPT1_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT2_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt2_ick;
+
+static struct clk_hw_omap gpt2_ick_hw = {
+	.hw = {
+		.clk = &gpt2_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT3_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt3_ick;
+
+static struct clk_hw_omap gpt3_ick_hw = {
+	.hw = {
+		.clk = &gpt3_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT3_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT4_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt4_ick;
+
+static struct clk_hw_omap gpt4_ick_hw = {
+	.hw = {
+		.clk = &gpt4_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT4_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT5_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt5_ick;
+
+static struct clk_hw_omap gpt5_ick_hw = {
+	.hw = {
+		.clk = &gpt5_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT5_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT6_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt6_ick;
+
+static struct clk_hw_omap gpt6_ick_hw = {
+	.hw = {
+		.clk = &gpt6_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT6_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT7_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt7_ick;
+
+static struct clk_hw_omap gpt7_ick_hw = {
+	.hw = {
+		.clk = &gpt7_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT7_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT8_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt8_ick;
+
+static struct clk_hw_omap gpt8_ick_hw = {
+	.hw = {
+		.clk = &gpt8_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT8_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+			 OMAP24XX_CLKSEL_GPT9_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
+			 gpt10_fck_parent_names, dss1_fck_ops);
+
+static struct clk gpt9_ick;
+
+static struct clk_hw_omap gpt9_ick_hw = {
+	.hw = {
+		.clk = &gpt9_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_GPT9_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk hdq_fck;
+
+static struct clk_hw_omap hdq_fck_hw = {
+	.hw = {
+		.clk = &hdq_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_HDQ_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk hdq_ick;
+
+static struct clk_hw_omap hdq_ick_hw = {
+	.hw = {
+		.clk = &hdq_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_HDQ_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2c1_fck;
+
+static struct clk_hw_omap i2c1_fck_hw = {
+	.hw = {
+		.clk = &i2c1_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk i2c1_ick;
+
+static struct clk_hw_omap i2c1_ick_hw = {
+	.hw = {
+		.clk = &i2c1_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk i2c2_fck;
+
+static struct clk_hw_omap i2c2_fck_hw = {
+	.hw = {
+		.clk = &i2c2_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops);
+
+static struct clk i2c2_ick;
+
+static struct clk_hw_omap i2c2_ick_hw = {
+	.hw = {
+		.clk = &i2c2_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,
+			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+			 OMAP2420_CLKSEL_IVA_MASK,
+			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+			 OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait,
+			 dsp_fck_parent_names, dsp_fck_ops);
+
+static struct clk iva1_mpu_int_ifck;
+
+static const char *iva1_mpu_int_ifck_parent_names[] = {
+	"iva1_ifck",
+};
+
+static const struct clk_ops iva1_mpu_int_ifck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+	.recalc_rate	= &omap_fixed_divisor_recalc,
+};
+
+static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
+	.hw = {
+		.clk = &iva1_mpu_int_ifck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+	.enable_bit	= OMAP2420_EN_IVA_MPU_SHIFT,
+	.clkdm_name	= "iva1_clkdm",
+	.fixed_div	= 2,
+};
+
+DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names,
+		  iva1_mpu_int_ifck_ops);
+
+static struct clk mailboxes_ick;
+
+static struct clk_hw_omap mailboxes_ick_hw = {
+	.hw = {
+		.clk = &mailboxes_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_MAILBOXES_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel mcbsp_fck_clksel[] = {
+	{ .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
+	{ .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
+	{ .parent = NULL },
+};
+
+static const char *mcbsp1_fck_parent_names[] = {
+	"func_96m_ck", "mcbsp_clks",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+			 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+			 OMAP2_MCBSP1_CLKS_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
+			 mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp1_ick;
+
+static struct clk_hw_omap mcbsp1_ick_hw = {
+	.hw = {
+		.clk = &mcbsp1_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_MCBSP1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+			 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+			 OMAP2_MCBSP2_CLKS_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
+			 mcbsp1_fck_parent_names, dss1_fck_ops);
+
+static struct clk mcbsp2_ick;
+
+static struct clk_hw_omap mcbsp2_ick_hw = {
+	.hw = {
+		.clk = &mcbsp2_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_MCBSP2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mcspi1_fck;
+
+static const char *mcspi1_fck_parent_names[] = {
+	"func_48m_ck",
+};
+
+static struct clk_hw_omap mcspi1_fck_hw = {
+	.hw = {
+		.clk = &mcspi1_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_MCSPI1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk mcspi1_ick;
+
+static struct clk_hw_omap mcspi1_ick_hw = {
+	.hw = {
+		.clk = &mcspi1_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_MCSPI1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mcspi2_fck;
+
+static struct clk_hw_omap mcspi2_fck_hw = {
+	.hw = {
+		.clk = &mcspi2_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_MCSPI2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk mcspi2_ick;
+
+static struct clk_hw_omap mcspi2_ick_hw = {
+	.hw = {
+		.clk = &mcspi2_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_MCSPI2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk mmc_fck;
+
+static struct clk_hw_omap mmc_fck_hw = {
+	.hw = {
+		.clk = &mmc_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP2420_EN_MMC_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk mmc_ick;
+
+static struct clk_hw_omap mmc_ick_hw = {
+	.hw = {
+		.clk = &mmc_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP2420_EN_MMC_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops);
+
+DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
+		   OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+		   OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
+		   CLK_DIVIDER_ONE_BASED, NULL);
+
+static struct clk mpu_wdt_fck;
+
+static struct clk_hw_omap mpu_wdt_fck_hw = {
+	.hw = {
+		.clk = &mpu_wdt_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+	.enable_bit	= OMAP24XX_EN_MPU_WDT_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk mpu_wdt_ick;
+
+static struct clk_hw_omap mpu_wdt_ick_hw = {
+	.hw = {
+		.clk = &mpu_wdt_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP24XX_EN_MPU_WDT_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk mspro_fck;
+
+static struct clk_hw_omap mspro_fck_hw = {
+	.hw = {
+		.clk = &mspro_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_MSPRO_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
+
+static struct clk mspro_ick;
+
+static struct clk_hw_omap mspro_ick_hw = {
+	.hw = {
+		.clk = &mspro_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_MSPRO_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk omapctrl_ick;
+
+static struct clk_hw_omap omapctrl_ick_hw = {
+	.hw = {
+		.clk = &omapctrl_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP24XX_EN_OMAPCTRL_SHIFT,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk pka_ick;
+
+static struct clk_hw_omap pka_ick_hw = {
+	.hw = {
+		.clk = &pka_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+	.enable_bit	= OMAP24XX_EN_PKA_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk rng_ick;
+
+static struct clk_hw_omap rng_ick_hw = {
+	.hw = {
+		.clk = &rng_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+	.enable_bit	= OMAP24XX_EN_RNG_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk sdma_fck;
+
+DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
+DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sdma_ick;
+
+static struct clk_hw_omap sdma_ick_hw = {
+	.hw = {
+		.clk = &sdma_ick,
+	},
+	.ops		= &clkhwops_iclk,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+	.enable_bit	= OMAP24XX_AUTO_SDMA_SHIFT,
+	.clkdm_name	= "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sdrc_ick;
+
+static struct clk_hw_omap sdrc_ick_hw = {
+	.hw = {
+		.clk = &sdrc_ick,
+	},
+	.ops		= &clkhwops_iclk,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+	.enable_bit	= OMAP24XX_AUTO_SDRC_SHIFT,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
+
+static struct clk sha_ick;
+
+static struct clk_hw_omap sha_ick_hw = {
+	.hw = {
+		.clk = &sha_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+	.enable_bit	= OMAP24XX_EN_SHA_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk ssi_l4_ick;
+
+static struct clk_hw_omap ssi_l4_ick_hw = {
+	.hw = {
+		.clk = &ssi_l4_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+	.enable_bit	= OMAP24XX_EN_SSI_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
+	{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
+	{ .div = 6, .val = 6, .flags = RATE_IN_242X },
+	{ .div = 8, .val = 8, .flags = RATE_IN_242X },
+	{ .div = 0 }
+};
+
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+	{ .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+	{ .parent = NULL },
+};
+
+static const char *ssi_ssr_sst_fck_parent_names[] = {
+	"core_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
+			 ssi_ssr_sst_fck_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+			 OMAP24XX_CLKSEL_SSI_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+			 OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
+			 ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
+
+static struct clk sync_32k_ick;
+
+static struct clk_hw_omap sync_32k_ick_hw = {
+	.hw = {
+		.clk = &sync_32k_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP24XX_EN_32KSYNC_SHIFT,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+	{ .div = 1, .val = 2, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+	{ .div = 1, .val = 3, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel common_clkout_src_clksel[] = {
+	{ .parent = &core_ck, .rates = common_clkout_src_core_rates },
+	{ .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
+	{ .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+	{ .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+	{ .parent = NULL },
+};
+
+static const char *sys_clkout_src_parent_names[] = {
+	"core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
+			 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
+			 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
+			 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
+
+DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
+		   OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
+		   OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
+			 common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL,
+			 OMAP2420_CLKOUT2_SOURCE_MASK,
+			 OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT,
+			 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
+
+DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0,
+		   OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT,
+		   OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static struct clk uart1_fck;
+
+static struct clk_hw_omap uart1_fck_hw = {
+	.hw = {
+		.clk = &uart1_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_UART1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart1_ick;
+
+static struct clk_hw_omap uart1_ick_hw = {
+	.hw = {
+		.clk = &uart1_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_UART1_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk uart2_fck;
+
+static struct clk_hw_omap uart2_fck_hw = {
+	.hw = {
+		.clk = &uart2_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_UART2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart2_ick;
+
+static struct clk_hw_omap uart2_ick_hw = {
+	.hw = {
+		.clk = &uart2_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_UART2_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk uart3_fck;
+
+static struct clk_hw_omap uart3_fck_hw = {
+	.hw = {
+		.clk = &uart3_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+	.enable_bit	= OMAP24XX_EN_UART3_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static struct clk uart3_ick;
+
+static struct clk_hw_omap uart3_ick_hw = {
+	.hw = {
+		.clk = &uart3_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+	.enable_bit	= OMAP24XX_EN_UART3_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk usb_fck;
+
+static struct clk_hw_omap usb_fck_hw = {
+	.hw = {
+		.clk = &usb_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+	.enable_bit	= OMAP24XX_EN_USB_SHIFT,
+	.clkdm_name	= "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
+
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
+	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
+	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
+	{ .div = 0 }
+};
+
+static const struct clksel usb_l4_ick_clksel[] = {
+	{ .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+	{ .parent = NULL },
+};
+
+static const char *usb_l4_ick_parent_names[] = {
+	"core_l3_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+			 OMAP24XX_CLKSEL_USB_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+			 OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
+			 usb_l4_ick_parent_names, dsp_fck_ops);
+
+static struct clk virt_prcm_set;
+
+static const char *virt_prcm_set_parent_names[] = {
+	"mpu_ck",
+};
+
+static const struct clk_ops virt_prcm_set_ops = {
+	.recalc_rate	= &omap2_table_mpu_recalc,
+	.set_rate	= &omap2_select_table_rate,
+	.round_rate	= &omap2_round_to_table_rate,
+};
+
+DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
+DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
+
+static const struct clksel_rate vlynq_fck_96m_rates[] = {
+	{ .div = 1, .val = 0, .flags = RATE_IN_242X },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate vlynq_fck_core_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_242X },
+	{ .div = 2, .val = 2, .flags = RATE_IN_242X },
+	{ .div = 3, .val = 3, .flags = RATE_IN_242X },
+	{ .div = 4, .val = 4, .flags = RATE_IN_242X },
+	{ .div = 6, .val = 6, .flags = RATE_IN_242X },
+	{ .div = 8, .val = 8, .flags = RATE_IN_242X },
+	{ .div = 9, .val = 9, .flags = RATE_IN_242X },
+	{ .div = 12, .val = 12, .flags = RATE_IN_242X },
+	{ .div = 16, .val = 16, .flags = RATE_IN_242X },
+	{ .div = 18, .val = 18, .flags = RATE_IN_242X },
+	{ .div = 0 }
+};
+
+static const struct clksel vlynq_fck_clksel[] = {
+	{ .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
+	{ .parent = &core_ck, .rates = vlynq_fck_core_rates },
+	{ .parent = NULL },
+};
+
+static const char *vlynq_fck_parent_names[] = {
+	"func_96m_ck", "core_ck",
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+			 OMAP2420_CLKSEL_VLYNQ_MASK,
+			 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+			 OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait,
+			 vlynq_fck_parent_names, dss1_fck_ops);
+
+static struct clk vlynq_ick;
+
+static struct clk_hw_omap vlynq_ick_hw = {
+	.hw = {
+		.clk = &vlynq_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP2420_EN_VLYNQ_SHIFT,
+	.clkdm_name	= "core_l3_clkdm",
+};
+
+DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt1_ick;
+
+static struct clk_hw_omap wdt1_ick_hw = {
+	.hw = {
+		.clk = &wdt1_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+	.enable_bit	= OMAP24XX_EN_WDT1_SHIFT,
+	.clkdm_name	= "wkup_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt1_osc_ck;
+
+static const struct clk_ops wdt1_osc_ck_ops = {};
+
+DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
+DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
+
+static struct clk wdt3_fck;
+
+static struct clk_hw_omap wdt3_fck_hw = {
+	.hw = {
+		.clk = &wdt3_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP2420_EN_WDT3_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk wdt3_ick;
+
+static struct clk_hw_omap wdt3_ick_hw = {
+	.hw = {
+		.clk = &wdt3_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP2420_EN_WDT3_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops);
+
+static struct clk wdt4_fck;
+
+static struct clk_hw_omap wdt4_fck_hw = {
+	.hw = {
+		.clk = &wdt4_fck,
+	},
+	.ops		= &clkhwops_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP24XX_EN_WDT4_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops);
+
+static struct clk wdt4_ick;
+
+static struct clk_hw_omap wdt4_ick_hw = {
+	.hw = {
+		.clk = &wdt4_ick,
+	},
+	.ops		= &clkhwops_iclk_wait,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP24XX_EN_WDT4_SHIFT,
+	.clkdm_name	= "core_l4_clkdm",
+};
+
+DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
+
+/*
+ * clkdev integration
+ */
+
+static struct omap_clk omap2420_clks[] = {
+	/* external root sources */
+	CLK(NULL,	"func_32k_ck",	&func_32k_ck,	CK_242X),
+	CLK(NULL,	"secure_32k_ck", &secure_32k_ck, CK_242X),
+	CLK(NULL,	"osc_ck",	&osc_ck,	CK_242X),
+	CLK(NULL,	"sys_ck",	&sys_ck,	CK_242X),
+	CLK(NULL,	"alt_ck",	&alt_ck,	CK_242X),
+	CLK(NULL,	"mcbsp_clks",	&mcbsp_clks,	CK_242X),
+	/* internal analog sources */
+	CLK(NULL,	"dpll_ck",	&dpll_ck,	CK_242X),
+	CLK(NULL,	"apll96_ck",	&apll96_ck,	CK_242X),
+	CLK(NULL,	"apll54_ck",	&apll54_ck,	CK_242X),
+	/* internal prcm root sources */
+	CLK(NULL,	"func_54m_ck",	&func_54m_ck,	CK_242X),
+	CLK(NULL,	"core_ck",	&core_ck,	CK_242X),
+	CLK(NULL,	"func_96m_ck",	&func_96m_ck,	CK_242X),
+	CLK(NULL,	"func_48m_ck",	&func_48m_ck,	CK_242X),
+	CLK(NULL,	"func_12m_ck",	&func_12m_ck,	CK_242X),
+	CLK(NULL,	"ck_wdt1_osc",	&wdt1_osc_ck,	CK_242X),
+	CLK(NULL,	"sys_clkout_src", &sys_clkout_src, CK_242X),
+	CLK(NULL,	"sys_clkout",	&sys_clkout,	CK_242X),
+	CLK(NULL,	"sys_clkout2_src", &sys_clkout2_src, CK_242X),
+	CLK(NULL,	"sys_clkout2",	&sys_clkout2,	CK_242X),
+	CLK(NULL,	"emul_ck",	&emul_ck,	CK_242X),
+	/* mpu domain clocks */
+	CLK(NULL,	"mpu_ck",	&mpu_ck,	CK_242X),
+	/* dsp domain clocks */
+	CLK(NULL,	"dsp_fck",	&dsp_fck,	CK_242X),
+	CLK(NULL,	"dsp_ick",	&dsp_ick,	CK_242X),
+	CLK(NULL,	"iva1_ifck",	&iva1_ifck,	CK_242X),
+	CLK(NULL,	"iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+	/* GFX domain clocks */
+	CLK(NULL,	"gfx_3d_fck",	&gfx_3d_fck,	CK_242X),
+	CLK(NULL,	"gfx_2d_fck",	&gfx_2d_fck,	CK_242X),
+	CLK(NULL,	"gfx_ick",	&gfx_ick,	CK_242X),
+	/* DSS domain clocks */
+	CLK("omapdss_dss",	"ick",		&dss_ick,	CK_242X),
+	CLK(NULL,	"dss_ick",		&dss_ick,	CK_242X),
+	CLK(NULL,	"dss1_fck",		&dss1_fck,	CK_242X),
+	CLK(NULL,	"dss2_fck",	&dss2_fck,	CK_242X),
+	CLK(NULL,	"dss_54m_fck",	&dss_54m_fck,	CK_242X),
+	/* L3 domain clocks */
+	CLK(NULL,	"core_l3_ck",	&core_l3_ck,	CK_242X),
+	CLK(NULL,	"ssi_fck",	&ssi_ssr_sst_fck, CK_242X),
+	CLK(NULL,	"usb_l4_ick",	&usb_l4_ick,	CK_242X),
+	/* L4 domain clocks */
+	CLK(NULL,	"l4_ck",	&l4_ck,		CK_242X),
+	CLK(NULL,	"ssi_l4_ick",	&ssi_l4_ick,	CK_242X),
+	CLK(NULL,	"wu_l4_ick",	&wu_l4_ick,	CK_242X),
+	/* virtual meta-group clock */
+	CLK(NULL,	"virt_prcm_set", &virt_prcm_set, CK_242X),
+	/* general l4 interface ck, multi-parent functional clk */
+	CLK(NULL,	"gpt1_ick",	&gpt1_ick,	CK_242X),
+	CLK(NULL,	"gpt1_fck",	&gpt1_fck,	CK_242X),
+	CLK(NULL,	"gpt2_ick",	&gpt2_ick,	CK_242X),
+	CLK(NULL,	"gpt2_fck",	&gpt2_fck,	CK_242X),
+	CLK(NULL,	"gpt3_ick",	&gpt3_ick,	CK_242X),
+	CLK(NULL,	"gpt3_fck",	&gpt3_fck,	CK_242X),
+	CLK(NULL,	"gpt4_ick",	&gpt4_ick,	CK_242X),
+	CLK(NULL,	"gpt4_fck",	&gpt4_fck,	CK_242X),
+	CLK(NULL,	"gpt5_ick",	&gpt5_ick,	CK_242X),
+	CLK(NULL,	"gpt5_fck",	&gpt5_fck,	CK_242X),
+	CLK(NULL,	"gpt6_ick",	&gpt6_ick,	CK_242X),
+	CLK(NULL,	"gpt6_fck",	&gpt6_fck,	CK_242X),
+	CLK(NULL,	"gpt7_ick",	&gpt7_ick,	CK_242X),
+	CLK(NULL,	"gpt7_fck",	&gpt7_fck,	CK_242X),
+	CLK(NULL,	"gpt8_ick",	&gpt8_ick,	CK_242X),
+	CLK(NULL,	"gpt8_fck",	&gpt8_fck,	CK_242X),
+	CLK(NULL,	"gpt9_ick",	&gpt9_ick,	CK_242X),
+	CLK(NULL,	"gpt9_fck",	&gpt9_fck,	CK_242X),
+	CLK(NULL,	"gpt10_ick",	&gpt10_ick,	CK_242X),
+	CLK(NULL,	"gpt10_fck",	&gpt10_fck,	CK_242X),
+	CLK(NULL,	"gpt11_ick",	&gpt11_ick,	CK_242X),
+	CLK(NULL,	"gpt11_fck",	&gpt11_fck,	CK_242X),
+	CLK(NULL,	"gpt12_ick",	&gpt12_ick,	CK_242X),
+	CLK(NULL,	"gpt12_fck",	&gpt12_fck,	CK_242X),
+	CLK("omap-mcbsp.1", "ick",	&mcbsp1_ick,	CK_242X),
+	CLK(NULL,	"mcbsp1_ick",	&mcbsp1_ick,	CK_242X),
+	CLK(NULL,	"mcbsp1_fck",	&mcbsp1_fck,	CK_242X),
+	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_242X),
+	CLK(NULL,	"mcbsp2_ick",	&mcbsp2_ick,	CK_242X),
+	CLK(NULL,	"mcbsp2_fck",	&mcbsp2_fck,	CK_242X),
+	CLK("omap2_mcspi.1", "ick",	&mcspi1_ick,	CK_242X),
+	CLK(NULL,	"mcspi1_ick",	&mcspi1_ick,	CK_242X),
+	CLK(NULL,	"mcspi1_fck",	&mcspi1_fck,	CK_242X),
+	CLK("omap2_mcspi.2", "ick",	&mcspi2_ick,	CK_242X),
+	CLK(NULL,	"mcspi2_ick",	&mcspi2_ick,	CK_242X),
+	CLK(NULL,	"mcspi2_fck",	&mcspi2_fck,	CK_242X),
+	CLK(NULL,	"uart1_ick",	&uart1_ick,	CK_242X),
+	CLK(NULL,	"uart1_fck",	&uart1_fck,	CK_242X),
+	CLK(NULL,	"uart2_ick",	&uart2_ick,	CK_242X),
+	CLK(NULL,	"uart2_fck",	&uart2_fck,	CK_242X),
+	CLK(NULL,	"uart3_ick",	&uart3_ick,	CK_242X),
+	CLK(NULL,	"uart3_fck",	&uart3_fck,	CK_242X),
+	CLK(NULL,	"gpios_ick",	&gpios_ick,	CK_242X),
+	CLK(NULL,	"gpios_fck",	&gpios_fck,	CK_242X),
+	CLK("omap_wdt",	"ick",		&mpu_wdt_ick,	CK_242X),
+	CLK(NULL,	"mpu_wdt_ick",		&mpu_wdt_ick,	CK_242X),
+	CLK(NULL,	"mpu_wdt_fck",	&mpu_wdt_fck,	CK_242X),
+	CLK(NULL,	"sync_32k_ick",	&sync_32k_ick,	CK_242X),
+	CLK(NULL,	"wdt1_ick",	&wdt1_ick,	CK_242X),
+	CLK(NULL,	"omapctrl_ick",	&omapctrl_ick,	CK_242X),
+	CLK("omap24xxcam", "fck",	&cam_fck,	CK_242X),
+	CLK(NULL,	"cam_fck",	&cam_fck,	CK_242X),
+	CLK("omap24xxcam", "ick",	&cam_ick,	CK_242X),
+	CLK(NULL,	"cam_ick",	&cam_ick,	CK_242X),
+	CLK(NULL,	"mailboxes_ick", &mailboxes_ick,	CK_242X),
+	CLK(NULL,	"wdt4_ick",	&wdt4_ick,	CK_242X),
+	CLK(NULL,	"wdt4_fck",	&wdt4_fck,	CK_242X),
+	CLK(NULL,	"wdt3_ick",	&wdt3_ick,	CK_242X),
+	CLK(NULL,	"wdt3_fck",	&wdt3_fck,	CK_242X),
+	CLK(NULL,	"mspro_ick",	&mspro_ick,	CK_242X),
+	CLK(NULL,	"mspro_fck",	&mspro_fck,	CK_242X),
+	CLK("mmci-omap.0", "ick",	&mmc_ick,	CK_242X),
+	CLK(NULL,	"mmc_ick",	&mmc_ick,	CK_242X),
+	CLK("mmci-omap.0", "fck",	&mmc_fck,	CK_242X),
+	CLK(NULL,	"mmc_fck",	&mmc_fck,	CK_242X),
+	CLK(NULL,	"fac_ick",	&fac_ick,	CK_242X),
+	CLK(NULL,	"fac_fck",	&fac_fck,	CK_242X),
+	CLK(NULL,	"eac_ick",	&eac_ick,	CK_242X),
+	CLK(NULL,	"eac_fck",	&eac_fck,	CK_242X),
+	CLK("omap_hdq.0", "ick",	&hdq_ick,	CK_242X),
+	CLK(NULL,	"hdq_ick",	&hdq_ick,	CK_242X),
+	CLK("omap_hdq.0", "fck",	&hdq_fck,	CK_242X),
+	CLK(NULL,	"hdq_fck",	&hdq_fck,	CK_242X),
+	CLK("omap_i2c.1", "ick",	&i2c1_ick,	CK_242X),
+	CLK(NULL,	"i2c1_ick",	&i2c1_ick,	CK_242X),
+	CLK(NULL,	"i2c1_fck",	&i2c1_fck,	CK_242X),
+	CLK("omap_i2c.2", "ick",	&i2c2_ick,	CK_242X),
+	CLK(NULL,	"i2c2_ick",	&i2c2_ick,	CK_242X),
+	CLK(NULL,	"i2c2_fck",	&i2c2_fck,	CK_242X),
+	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_242X),
+	CLK(NULL,	"sdma_fck",	&sdma_fck,	CK_242X),
+	CLK(NULL,	"sdma_ick",	&sdma_ick,	CK_242X),
+	CLK(NULL,	"sdrc_ick",	&sdrc_ick,	CK_242X),
+	CLK(NULL,	"vlynq_ick",	&vlynq_ick,	CK_242X),
+	CLK(NULL,	"vlynq_fck",	&vlynq_fck,	CK_242X),
+	CLK(NULL,	"des_ick",	&des_ick,	CK_242X),
+	CLK("omap-sham",	"ick",	&sha_ick,	CK_242X),
+	CLK(NULL,	"sha_ick",	&sha_ick,	CK_242X),
+	CLK("omap_rng",	"ick",		&rng_ick,	CK_242X),
+	CLK(NULL,	"rng_ick",		&rng_ick,	CK_242X),
+	CLK("omap-aes",	"ick",	&aes_ick,	CK_242X),
+	CLK(NULL,	"aes_ick",	&aes_ick,	CK_242X),
+	CLK(NULL,	"pka_ick",	&pka_ick,	CK_242X),
+	CLK(NULL,	"usb_fck",	&usb_fck,	CK_242X),
+	CLK("musb-hdrc",	"fck",	&osc_ck,	CK_242X),
+	CLK(NULL,	"timer_32k_ck",	&func_32k_ck,	CK_242X),
+	CLK(NULL,	"timer_sys_ck",	&sys_ck,	CK_242X),
+	CLK(NULL,	"timer_ext_ck",	&alt_ck,	CK_242X),
+	CLK(NULL,	"cpufreq_ck",	&virt_prcm_set,	CK_242X),
+};
+
+
+static const char *enable_init_clks[] = {
+	"apll96_ck",
+	"apll54_ck",
+	"sync_32k_ick",
+	"omapctrl_ick",
+	"gpmc_fck",
+	"sdrc_ick",
+};
+
+/*
+ * init code
+ */
+
+int __init omap2420_clk_init(void)
+{
+	struct omap_clk *c;
+
+	prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
+	cpu_mask = RATE_IN_242X;
+	rate_table = omap2420_rate_table;
+
+	omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
+
+	omap2xxx_clkt_vps_check_bootloader_rates();
+
+	for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
+	     c++) {
+		clkdev_add(&c->lk);
+		if (!__clk_init(NULL, c->lk.clk))
+			omap2_init_clk_hw_omap_clocks(c->lk.clk);
+	}
+
+	omap2_clk_disable_autoidle_all();
+
+	omap2_clk_enable_init_clocks(enable_init_clks,
+				     ARRAY_SIZE(enable_init_clks));
+
+	pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
+		(clk_get_rate(&sys_ck) / 1000000),
+		(clk_get_rate(&sys_ck) / 100000) % 10,
+		(clk_get_rate(&dpll_ck) / 1000000),
+		(clk_get_rate(&mpu_ck) / 1000000));
+
+	return 0;
+}

arch/arm/mach-omap2/cclock2430_data.c new file +2065 -0

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Paul Walmsley

maintainer

2012-11-09 21:12 UTC #61 lore raw

v2 cover Move OMAP2+ over to common clk framework

In reply to Mike Turquette

With the fixes that have been posted, this is testing clean here. Mike and Rajendra have put in months of work on these patches under often-difficult conditions, and it's really great that we've arrived at this point with zero obvious remaining regressions from the current code.

The branch has been posted for the time being at
git://git.pwsan.com/linux-2.6 in the branch 'common_clk_devel_3.8', with the head at commit 376676b429cb6dc95c39cdac82b2be816ea22893, in case anyone else wants to try it.

Anyway, barring any further regressions that haven't reared their ugly heads yet, and barring anything truly horrible in the code or data that I've missed so far, will take this branch from here. It still needs some more work before it's ready to merge. The clockdomain usecounting fix patch needs to be split and moved earlier in the patch stack so 'git bisect' doesn't result in warnings and broken PM on OMAP3. And it all is going to be rebased on the second set of PRCM cleanup patches at commit b99db36cdf37decb1b5575c5f293d170cbbc53d6, which I'm assuming Tony is planning to pull. Then will plan to send that pull request to Tony.

Then after that, if there's still time to merge some of the clock changes that have showed up on the lists for 3.8, those will get stacked onto a topic branch based on the branch that's sent to Tony.

- Paul

Tony Lindgren

maintainer

2012-11-09 22:09 UTC #62 lore raw

v2 cover Move OMAP2+ over to common clk framework

Quoted 7 lines · Paul Walmsley

Hi
With the fixes that have been posted, this is testing clean here. Mike and Rajendra have put in months of work on these patches under often-difficult conditions, and it's really great that we've arrived at this point with zero obvious remaining regressions from the current code.

That's excellent news :)

Quoted 15 lines

The branch has been posted for the time being at
git://git.pwsan.com/linux-2.6 in the branch 'common_clk_devel_3.8', with the head at commit 376676b429cb6dc95c39cdac82b2be816ea22893, in case anyone else wants to try it.
Anyway, barring any further regressions that haven't reared their ugly heads yet, and barring anything truly horrible in the code or data that I've missed so far, will take this branch from here. It still needs some more work before it's ready to merge. The clockdomain usecounting fix patch needs to be split and moved earlier in the patch stack so 'git bisect' doesn't result in warnings and broken PM on OMAP3. And it all is going to be rebased on the second set of PRCM cleanup patches at commit b99db36cdf37decb1b5575c5f293d170cbbc53d6, which I'm assuming Tony is planning to pull. Then will plan to send that pull request to Tony.

Quoted 3 lines

Then after that, if there's still time to merge some of the clock changes that have showed up on the lists for 3.8, those will get stacked onto a topic branch based on the branch that's sent to Tony.

Sounds good to me.

Thanks,

Tony

Mike Turquette

author

2012-11-09 22:18 UTC #63 lore raw

v2 cover Move OMAP2+ over to common clk framework

In reply to Paul Walmsley

Quoting Paul Walmsley (2012-11-09 13:12:24)

Quoted 7 lines

Hi
With the fixes that have been posted, this is testing clean here. Mike and Rajendra have put in months of work on these patches under often-difficult conditions, and it's really great that we've arrived at this point with zero obvious remaining regressions from the current code.

Quoted 5 lines

The branch has been posted for the time being at
git://git.pwsan.com/linux-2.6 in the branch 'common_clk_devel_3.8', with the head at commit 376676b429cb6dc95c39cdac82b2be816ea22893, in case anyone else wants to try it.

Thanks a lot Paul. You put in a lot of work on this series as well and that should not go unnoticed. I'm truly happy to see this series come together.

Quoted 10 lines

Anyway, barring any further regressions that haven't reared their ugly heads yet, and barring anything truly horrible in the code or data that I've missed so far, will take this branch from here. It still needs some more work before it's ready to merge. The clockdomain usecounting fix patch needs to be split and moved earlier in the patch stack so 'git bisect' doesn't result in warnings and broken PM on OMAP3. And it all is going to be rebased on the second set of PRCM cleanup patches at commit b99db36cdf37decb1b5575c5f293d170cbbc53d6, which I'm assuming Tony is planning to pull. Then will plan to send that pull request to Tony.

I just did some more testing on your branch and everything looks great. The only thing that caught my eye was using the clk-private.h header in the top-most patch. The following patch will help me sleep better at night:

arch/arm/mach-omap2/clockdomain.c +1 -1

index ba4d14c..3848735 100644
@@ -22,7 +22,7 @@
 #include <linux/clk.h>
 #include <linux/limits.h>
 #include <linux/err.h>
-#include <linux/clk-private.h>
+#include <linux/clk-provider.h>
 
 #include <linux/io.h>

Tested on 3530 ES3.0 Beagleboard, boot + suspend/resume.

Regards,
Mike

Quoted 6 lines

Then after that, if there's still time to merge some of the clock changes that have showed up on the lists for 3.8, those will get stacked onto a topic branch based on the branch that's sent to Tony.
- Paul

Paul Walmsley

maintainer

2012-11-09 23:47 UTC #64 lore raw

v2 cover Move OMAP2+ over to common clk framework

Quoted 10 lines · Mike Turquette

I just did some more testing on your branch and everything looks great. The only thing that caught my eye was using the clk-private.h header in the top-most patch. The following patch will help me sleep better at night:
arch/arm/mach-omap2/clockdomain.c +0 -0
index ba4d14c..3848735 100644

arch/arm/mach-omap2/clockdomain.c line 27

Quoted 7 lines

arch/arm/mach-omap2/clockdomain.c +1 -1

@@ -22,7 +22,7 @@
 #include <linux/clk.h>
 #include <linux/limits.h>
 #include <linux/err.h>
-#include <linux/clk-private.h>
+#include <linux/clk-provider.h>
 
 #include <linux/io.h>

Just folded this one in, the updated patch follows.

Quoted 1 line

Tested on 3530 ES3.0 Beagleboard, boot + suspend/resume.

Great!

- Paul

From: Mike Turquette <[email protected]>
Date: Fri, 9 Nov 2012 11:28:42 -0700
Subject: [PATCH] ARM: OMAP2+: clockdomain: bypass clockdomain handling when
disabling unused clks

[1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824

Signed-off-by Mike Turquette <[email protected]>

[paul at pwsan.com: split the hwmod and clock disable cases; modified the
code to skip the clockdomain handling during the disable-unused-clocks phase; added COMMON_CLK ifdef; removed include of clk-private.h at Mike's request]

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/clockdomain.c |   91 ++++++++++++++++++++++---------------
 1 file changed, 54 insertions(+), 37 deletions(-)

arch/arm/mach-omap2/clockdomain.c +54 ~~-37~~

index 64e5046..4424f3d 100644
@@ -22,6 +22,7 @@
 #include <linux/clk.h>
 #include <linux/limits.h>
 #include <linux/err.h>
+#include <linux/clk-provider.h>
 
 #include <linux/io.h>

@@ -947,35 +948,6 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
 	return 0;
 }
 
-static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
-{
-	unsigned long flags;
-
-	if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
-		return -EINVAL;
-
-	spin_lock_irqsave(&clkdm->lock, flags);
-
-	if (atomic_read(&clkdm->usecount) == 0) {
-		spin_unlock_irqrestore(&clkdm->lock, flags);
-		WARN_ON(1); /* underflow */
-		return -ERANGE;
-	}
-
-	if (atomic_dec_return(&clkdm->usecount) > 0) {
-		spin_unlock_irqrestore(&clkdm->lock, flags);
-		return 0;
-	}
-
-	arch_clkdm->clkdm_clk_disable(clkdm);
-	pwrdm_state_switch(clkdm->pwrdm.ptr);
-	spin_unlock_irqrestore(&clkdm->lock, flags);
-
-	pr_debug("clockdomain: %s: disabled\n", clkdm->name);
-
-	return 0;
-}
-
 /**
  * clkdm_clk_enable - add an enabled downstream clock to this clkdm
  * @clkdm: struct clockdomain *

@@ -1018,15 +990,39 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
  */
 int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
 {
-	/*
-	 * XXX Rewrite this code to maintain a list of enabled
-	 * downstream clocks for debugging purposes?
-	 */
+	unsigned long flags;
 
-	if (!clk)
+	if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
 		return -EINVAL;
 
-	return _clkdm_clk_hwmod_disable(clkdm);
+	spin_lock_irqsave(&clkdm->lock, flags);
+
+#ifdef CONFIG_COMMON_CLK
+	/* corner case: disabling unused clocks */
+	if (__clk_get_enable_count(clk) == 0)
+		goto ccd_exit;
+#endif
+
+	if (atomic_read(&clkdm->usecount) == 0) {
+		spin_unlock_irqrestore(&clkdm->lock, flags);
+		WARN_ON(1); /* underflow */
+		return -ERANGE;
+	}
+
+	if (atomic_dec_return(&clkdm->usecount) > 0) {
+		spin_unlock_irqrestore(&clkdm->lock, flags);
+		return 0;
+	}
+
+	arch_clkdm->clkdm_clk_disable(clkdm);
+	pwrdm_state_switch(clkdm->pwrdm.ptr);
+
+	pr_debug("clockdomain: %s: disabled\n", clkdm->name);
+
+ccd_exit:
+	spin_unlock_irqrestore(&clkdm->lock, flags);
+
+	return 0;
 }
 
 /**

@@ -1077,6 +1073,8 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
  */
 int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
 {
+	unsigned long flags;
+
 	/* The clkdm attribute does not exist yet prior OMAP4 */
 	if (cpu_is_omap24xx() || cpu_is_omap34xx())
 		return 0;

@@ -1086,9 +1084,28 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
 	 * downstream hwmods for debugging purposes?
 	 */
 
-	if (!oh)
+	if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
 		return -EINVAL;
 
-	return _clkdm_clk_hwmod_disable(clkdm);
+	spin_lock_irqsave(&clkdm->lock, flags);
+
+	if (atomic_read(&clkdm->usecount) == 0) {
+		spin_unlock_irqrestore(&clkdm->lock, flags);
+		WARN_ON(1); /* underflow */
+		return -ERANGE;
+	}
+
+	if (atomic_dec_return(&clkdm->usecount) > 0) {
+		spin_unlock_irqrestore(&clkdm->lock, flags);
+		return 0;
+	}
+
+	arch_clkdm->clkdm_clk_disable(clkdm);
+	pwrdm_state_switch(clkdm->pwrdm.ptr);
+	spin_unlock_irqrestore(&clkdm->lock, flags);
+
+	pr_debug("clockdomain: %s: disabled\n", clkdm->name);
+
+	return 0;
 }

Signature · 1 line

1.7.10.4

Paul Walmsley

maintainer

2012-11-12 21:50 UTC #65 lore raw

PATCH 1/1 ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections

In reply to Mike Turquette

Remove all of the code that is compiled when CONFIG_COMMON_CLK=n in the OMAP3+ DPLL handling code.

Signed-off-by Paul Walmsley <[email protected]>

Cc Mike Turquette <[email protected]>

Cc Rajendra Nayak <[email protected]>

---

This will be merged as part of the OMAP CCF conversion set.

 arch/arm/mach-omap2/dpll3xxx.c |  231 +---------------------------------------
 1 file changed, 3 insertions(+), 228 deletions(-)

arch/arm/mach-omap2/dpll3xxx.c +3 ~~-228~~

index f72dedb..fafb28c 100644
@@ -43,11 +43,7 @@
 /* Private functions */
 
 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
-#ifdef CONFIG_COMMON_CLK
 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
-#else
-static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
-#endif
 {
 	const struct dpll_data *dd;
 	u32 v;

@@ -61,11 +57,7 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
 }
 
 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
-#ifdef CONFIG_COMMON_CLK
 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
-#else
-static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
-#endif
 {
 	const struct dpll_data *dd;
 	int i = 0;

@@ -73,11 +65,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 	const char *clk_name;
 
 	dd = clk->dpll_data;
-#ifdef CONFIG_COMMON_CLK
 	clk_name = __clk_get_name(clk->hw.clk);
-#else
-	clk_name = __clk_get_name(clk);
-#endif
 
 	state <<= __ffs(dd->idlest_mask);

@@ -101,11 +89,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 }
 
 /* From 3430 TRM ES2 4.7.6.2 */
-#ifdef CONFIG_COMMON_CLK
 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
-#else
-static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
-#endif
 {
 	unsigned long fint;
 	u16 f = 0;

@@ -150,22 +134,14 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
  * locked successfully, return 0; if the DPLL did not lock in the time
  * allotted, or DPLL3 was passed in, return -EINVAL.
  */
-#ifdef CONFIG_COMMON_CLK
 static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
-#else
-static int _omap3_noncore_dpll_lock(struct clk *clk)
-#endif
 {
 	const struct dpll_data *dd;
 	u8 ai;
 	u8 state = 1;
 	int r = 0;
 
-#ifdef CONFIG_COMMON_CLK
 	pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk));
-#else
-	pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
-#endif
 
 	dd = clk->dpll_data;
 	state <<= __ffs(dd->idlest_mask);

@@ -203,11 +179,7 @@ done:
  * DPLL3 was passed in, or the DPLL does not support low-power bypass,
  * return -EINVAL.
  */
-#ifdef CONFIG_COMMON_CLK
 static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
-#else
-static int _omap3_noncore_dpll_bypass(struct clk *clk)
-#endif
 {
 	int r;
 	u8 ai;

@@ -216,11 +188,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
 		return -EINVAL;
 
 	pr_debug("clock: configuring DPLL %s for low-power bypass\n",
-#ifdef CONFIG_COMMON_CLK
 		 __clk_get_name(clk->hw.clk));
-#else
-		 __clk_get_name(clk));
-#endif
 
 	ai = omap3_dpll_autoidle_read(clk);

@@ -243,22 +211,14 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
  * code.  If DPLL3 was passed in, or the DPLL does not support
  * low-power stop, return -EINVAL; otherwise, return 0.
  */
-#ifdef CONFIG_COMMON_CLK
 static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
-#else
-static int _omap3_noncore_dpll_stop(struct clk *clk)
-#endif
 {
 	u8 ai;
 
 	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
 		return -EINVAL;
 
-#ifdef CONFIG_COMMON_CLK
 	pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk));
-#else
-	pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
-#endif
 
 	ai = omap3_dpll_autoidle_read(clk);

@@ -282,19 +242,11 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
  * XXX This code is not needed for 3430/AM35xx; can it be optimized
  * out in non-multi-OMAP builds for those chips?
  */
-#ifdef CONFIG_COMMON_CLK
 static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
-#else
-static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
-#endif
 {
 	unsigned long fint, clkinp; /* watch out for overflow */
 
-#ifdef CONFIG_COMMON_CLK
 	clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
-#else
-	clkinp = __clk_get_rate(__clk_get_parent(clk));
-#endif
 	fint = (clkinp / n) * m;
 
 	if (fint < 1000000000)

@@ -315,20 +267,12 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
  * XXX This code is not needed for 3430/AM35xx; can it be optimized
  * out in non-multi-OMAP builds for those chips?
  */
-#ifdef CONFIG_COMMON_CLK
 static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
-#else
-static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
-#endif
 {
 	unsigned long clkinp, sd; /* watch out for overflow */
 	int mod1, mod2;
 
-#ifdef CONFIG_COMMON_CLK
 	clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
-#else
-	clkinp = __clk_get_rate(__clk_get_parent(clk));
-#endif
 
 	/*
 	 * target sigma-delta to near 250MHz

@@ -355,12 +299,8 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
  * Program the DPLL with the supplied M, N values, and wait for the DPLL to
  * lock..  Returns -EINVAL upon error, or 0 upon success.
  */
-#ifdef CONFIG_COMMON_CLK
 static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
 				      u16 freqsel)
-#else
-static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
-#endif
 {
 	struct dpll_data *dd = clk->dpll_data;
 	u8 dco, sd_div;

@@ -417,14 +357,10 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
  *
  * Recalculate and propagate the DPLL rate.
  */
-#ifdef CONFIG_COMMON_CLK
 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
 {
 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-#else
-unsigned long omap3_dpll_recalc(struct clk *clk)
-{
-#endif
+
 	return omap2_get_dpll_rate(clk);
 }

@@ -444,14 +380,9 @@ unsigned long omap3_dpll_recalc(struct clk *clk)
  * support low-power stop, or if the DPLL took too long to enter
  * bypass or lock, return -EINVAL; otherwise, return 0.
  */
-#ifdef CONFIG_COMMON_CLK
 int omap3_noncore_dpll_enable(struct clk_hw *hw)
 {
 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-#else
-int omap3_noncore_dpll_enable(struct clk *clk)
-{
-#endif
 	int r;
 	struct dpll_data *dd;
 	struct clk *parent;

@@ -460,7 +391,6 @@ int omap3_noncore_dpll_enable(struct clk *clk)
 	if (!dd)
 		return -EINVAL;
 
-#ifdef CONFIG_COMMON_CLK
 	if (clk->clkdm) {
 		r = clkdm_clk_enable(clk->clkdm, hw->clk);
 		if (r) {

@@ -475,11 +405,6 @@ int omap3_noncore_dpll_enable(struct clk *clk)
 	parent = __clk_get_parent(hw->clk);
 
 	if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
-#else
-	parent = __clk_get_parent(clk);
-
-	if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
-#endif
 		WARN_ON(parent != dd->clk_bypass);
 		r = _omap3_noncore_dpll_bypass(clk);
 	} else {

@@ -487,16 +412,6 @@ int omap3_noncore_dpll_enable(struct clk *clk)
 		r = _omap3_noncore_dpll_lock(clk);
 	}
 
-#ifndef CONFIG_COMMON_CLK
-	/*
-	 *FIXME: this is dubious - if clk->rate has changed, what about
-	 * propagating?
-	 */
-	if (!r)
-		clk->rate = (clk->recalc) ? clk->recalc(clk) :
-			omap2_get_dpll_rate(clk);
-#endif
-
 	return r;
 }

@@ -507,7 +422,6 @@ int omap3_noncore_dpll_enable(struct clk *clk)
  * Instructs a non-CORE DPLL to enter low-power stop.  This function is
  * intended for use in struct clkops.  No return value.
  */
-#ifdef CONFIG_COMMON_CLK
 void omap3_noncore_dpll_disable(struct clk_hw *hw)
 {
 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);

@@ -515,13 +429,6 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
 	_omap3_noncore_dpll_stop(clk);
 	if (clk->clkdm)
 		clkdm_clk_disable(clk->clkdm, hw->clk);
-#else
-void omap3_noncore_dpll_disable(struct clk *clk)
-{
-	_omap3_noncore_dpll_stop(clk);
-	if (clk->clkdm)
-		clkdm_clk_disable(clk->clkdm, clk);
-#endif
 }

@@ -538,7 +445,6 @@ void omap3_noncore_dpll_disable(struct clk *clk)
  * target rate if it hasn't been done already, then program and lock
  * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
  */
-#ifdef CONFIG_COMMON_CLK
 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
 					unsigned long parent_rate)
 {

@@ -608,85 +514,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	return 0;
 }
-#else
-int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
-{
-	struct clk *new_parent = NULL;
-	unsigned long hw_rate, bypass_rate;
-	u16 freqsel = 0;
-	struct dpll_data *dd;
-	int ret;
-
-	if (!clk || !rate)
-		return -EINVAL;
-
-	dd = clk->dpll_data;
-	if (!dd)
-		return -EINVAL;
-
-	hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
-	if (rate == hw_rate)
-		return 0;
-
-	/*
-	 * Ensure both the bypass and ref clocks are enabled prior to
-	 * doing anything; we need the bypass clock running to reprogram
-	 * the DPLL.
-	 */
-	omap2_clk_enable(dd->clk_bypass);
-	omap2_clk_enable(dd->clk_ref);
-
-	bypass_rate = __clk_get_rate(dd->clk_bypass);
-	if (bypass_rate == rate &&
-	    (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-		pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
-
-		ret = _omap3_noncore_dpll_bypass(clk);
-		if (!ret)
-			new_parent = dd->clk_bypass;
-	} else {
-		if (dd->last_rounded_rate != rate)
-			rate = clk->round_rate(clk, rate);
-
-		if (dd->last_rounded_rate == 0)
-			return -EINVAL;
-
-		/* No freqsel on OMAP4 and OMAP3630 */
-		if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
-			freqsel = _omap3_dpll_compute_freqsel(clk,
-						dd->last_rounded_n);
-			if (!freqsel)
-				WARN_ON(1);
-		}
-
-		pr_debug("clock: %s: set rate: locking rate to %lu.\n",
-			 __clk_get_name(clk), rate);
-
-		ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
-						 dd->last_rounded_n, freqsel);
-		if (!ret)
-			new_parent = dd->clk_ref;
-	}
-	if (!ret) {
-		/*
-		 * Switch the parent clock in the hierarchy, and make sure
-		 * that the new parent's usecount is correct.  Note: we
-		 * enable the new parent before disabling the old to avoid
-		 * any unnecessary hardware disable->enable transitions.
-		 */
-		if (clk->usecount) {
-			omap2_clk_enable(new_parent);
-			omap2_clk_disable(clk->parent);
-		}
-		clk_reparent(clk, new_parent);
-		clk->rate = rate;
-	}
-	omap2_clk_disable(dd->clk_ref);
-	omap2_clk_disable(dd->clk_bypass);
-
-	return 0;
-}
-#endif
 
 /* DPLL autoidle read/set code */

@@ -698,11 +525,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
  * -EINVAL if passed a null pointer or if the struct clk does not
  * appear to refer to a DPLL.
  */
-#ifdef CONFIG_COMMON_CLK
 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
-#else
-u32 omap3_dpll_autoidle_read(struct clk *clk)
-#endif
 {
 	const struct dpll_data *dd;
 	u32 v;

@@ -731,11 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)
  * OMAP3430.  The DPLL will enter low-power stop when its downstream
  * clocks are gated.  No return value.
  */
-#ifdef CONFIG_COMMON_CLK
 void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
-#else
-void omap3_dpll_allow_idle(struct clk *clk)
-#endif
 {
 	const struct dpll_data *dd;
 	u32 v;

@@ -745,13 +564,8 @@ void omap3_dpll_allow_idle(struct clk *clk)
 
 	dd = clk->dpll_data;
 
-	if (!dd->autoidle_reg) {
-#ifndef CONFIG_COMMON_CLK
-		pr_debug("clock: DPLL %s: autoidle not supported\n",
-			__clk_get_name(clk));
-#endif
+	if (!dd->autoidle_reg)
 		return;
-	}
 
 	/*
 	 * REVISIT: CORE DPLL can optionally enter low-power bypass

@@ -771,11 +585,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
  *
  * Disable DPLL automatic idle control.  No return value.
  */
-#ifdef CONFIG_COMMON_CLK
 void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
-#else
-void omap3_dpll_deny_idle(struct clk *clk)
-#endif
 {
 	const struct dpll_data *dd;
 	u32 v;

@@ -785,13 +595,8 @@ void omap3_dpll_deny_idle(struct clk *clk)
 
 	dd = clk->dpll_data;
 
-	if (!dd->autoidle_reg) {
-#ifndef CONFIG_COMMON_CLK
-		pr_debug("clock: DPLL %s: autoidle not supported\n",
-			__clk_get_name(clk));
-#endif
+	if (!dd->autoidle_reg)
 		return;
-	}
 
 	v = __raw_readl(dd->autoidle_reg);
 	v &= ~dd->autoidle_mask;

@@ -809,7 +614,6 @@ void omap3_dpll_deny_idle(struct clk *clk)
  * Using parent clock DPLL data, look up DPLL state.  If locked, set our
  * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
  */
-#ifdef CONFIG_COMMON_CLK
 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 				    unsigned long parent_rate)
 {

@@ -829,22 +633,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 			break;
 		pclk = to_clk_hw_omap(hw);
 	} while (pclk && !pclk->dpll_data);
-#else
-unsigned long omap3_clkoutx2_recalc(struct clk *clk)
-{
-	const struct dpll_data *dd;
-	unsigned long rate;
-	u32 v;
-	struct clk *pclk;
-	unsigned long parent_rate;
 
-	/* Walk up the parents of clk, looking for a DPLL */
-	pclk = __clk_get_parent(clk);
-	while (pclk && !pclk->dpll_data)
-		pclk = __clk_get_parent(pclk);
-
-	parent_rate = __clk_get_rate(__clk_get_parent(clk));
-#endif
 	/* clk does not have a DPLL as a parent?  error in the clock data */
 	if (!pclk) {
 		WARN_ON(1);

@@ -865,21 +654,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 }
 
 /* OMAP3/4 non-CORE DPLL clkops */
-#ifdef CONFIG_COMMON_CLK
 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
 	.allow_idle	= omap3_dpll_allow_idle,
 	.deny_idle	= omap3_dpll_deny_idle,
 };
-#else
-const struct clkops clkops_omap3_noncore_dpll_ops = {
-	.enable		= omap3_noncore_dpll_enable,
-	.disable	= omap3_noncore_dpll_disable,
-	.allow_idle	= omap3_dpll_allow_idle,
-	.deny_idle	= omap3_dpll_deny_idle,
-};
-
-const struct clkops clkops_omap3_core_dpll_ops = {
-	.allow_idle	= omap3_dpll_allow_idle,
-	.deny_idle	= omap3_dpll_deny_idle,
-};
-#endif

Signature · 1 line

1.7.10.4

Mike Turquette

author

2012-11-12 22:30 UTC #66 lore raw

PATCH 1/1 ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections

Quoting Paul Walmsley (2012-11-12 13:50:53)

Quoted 6 lines

Remove all of the code that is compiled when CONFIG_COMMON_CLK=n in the OMAP3+ DPLL handling code.
Signed-off-by Paul Walmsley <[email protected]>
Cc Mike Turquette <[email protected]>
Cc Rajendra Nayak <[email protected]>

Hmm, dpll3xxx.c fell through the cracks during #ifdef cleanup. Patch looks good to me.

Regards,
Mike

Quoted 488 lines

---

This will be merged as part of the OMAP CCF conversion set.

 arch/arm/mach-omap2/dpll3xxx.c |  231 +---------------------------------------
 1 file changed, 3 insertions(+), 228 deletions(-)

arch/arm/mach-omap2/dpll3xxx.c +3 ~~-228~~

index f72dedb..fafb28c 100644
@@ -43,11 +43,7 @@
 /* Private functions */
 
 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
-#ifdef CONFIG_COMMON_CLK
 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
-#else
-static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
-#endif
 {
        const struct dpll_data *dd;
        u32 v;

@@ -61,11 +57,7 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
 }
 
 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
-#ifdef CONFIG_COMMON_CLK
 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
-#else
-static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
-#endif
 {
        const struct dpll_data *dd;
        int i = 0;

@@ -73,11 +65,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
        const char *clk_name;
 
        dd = clk->dpll_data;
-#ifdef CONFIG_COMMON_CLK
        clk_name = __clk_get_name(clk->hw.clk);
-#else
-       clk_name = __clk_get_name(clk);
-#endif
 
        state <<= __ffs(dd->idlest_mask);

@@ -101,11 +89,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 }
 
 /* From 3430 TRM ES2 4.7.6.2 */
-#ifdef CONFIG_COMMON_CLK
 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
-#else
-static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
-#endif
 {
        unsigned long fint;
        u16 f = 0;

@@ -150,22 +134,14 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
  * locked successfully, return 0; if the DPLL did not lock in the time
  * allotted, or DPLL3 was passed in, return -EINVAL.
  */
-#ifdef CONFIG_COMMON_CLK
 static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
-#else
-static int _omap3_noncore_dpll_lock(struct clk *clk)
-#endif
 {
        const struct dpll_data *dd;
        u8 ai;
        u8 state = 1;
        int r = 0;
 
-#ifdef CONFIG_COMMON_CLK
        pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk));
-#else
-       pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
-#endif
 
        dd = clk->dpll_data;
        state <<= __ffs(dd->idlest_mask);

@@ -203,11 +179,7 @@ done:
  * DPLL3 was passed in, or the DPLL does not support low-power bypass,
  * return -EINVAL.
  */
-#ifdef CONFIG_COMMON_CLK
 static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
-#else
-static int _omap3_noncore_dpll_bypass(struct clk *clk)
-#endif
 {
        int r;
        u8 ai;

@@ -216,11 +188,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
                return -EINVAL;
 
        pr_debug("clock: configuring DPLL %s for low-power bypass\n",
-#ifdef CONFIG_COMMON_CLK
                 __clk_get_name(clk->hw.clk));
-#else
-                __clk_get_name(clk));
-#endif
 
        ai = omap3_dpll_autoidle_read(clk);

@@ -243,22 +211,14 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
  * code.  If DPLL3 was passed in, or the DPLL does not support
  * low-power stop, return -EINVAL; otherwise, return 0.
  */
-#ifdef CONFIG_COMMON_CLK
 static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
-#else
-static int _omap3_noncore_dpll_stop(struct clk *clk)
-#endif
 {
        u8 ai;
 
        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
                return -EINVAL;
 
-#ifdef CONFIG_COMMON_CLK
        pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk));
-#else
-       pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
-#endif
 
        ai = omap3_dpll_autoidle_read(clk);

@@ -282,19 +242,11 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
  * XXX This code is not needed for 3430/AM35xx; can it be optimized
  * out in non-multi-OMAP builds for those chips?
  */
-#ifdef CONFIG_COMMON_CLK
 static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
-#else
-static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
-#endif
 {
        unsigned long fint, clkinp; /* watch out for overflow */
 
-#ifdef CONFIG_COMMON_CLK
        clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
-#else
-       clkinp = __clk_get_rate(__clk_get_parent(clk));
-#endif
        fint = (clkinp / n) * m;
 
        if (fint < 1000000000)

@@ -315,20 +267,12 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
  * XXX This code is not needed for 3430/AM35xx; can it be optimized
  * out in non-multi-OMAP builds for those chips?
  */
-#ifdef CONFIG_COMMON_CLK
 static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
-#else
-static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
-#endif
 {
        unsigned long clkinp, sd; /* watch out for overflow */
        int mod1, mod2;
 
-#ifdef CONFIG_COMMON_CLK
        clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
-#else
-       clkinp = __clk_get_rate(__clk_get_parent(clk));
-#endif
 
        /*
         * target sigma-delta to near 250MHz

@@ -355,12 +299,8 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
  * Program the DPLL with the supplied M, N values, and wait for the DPLL to
  * lock..  Returns -EINVAL upon error, or 0 upon success.
  */
-#ifdef CONFIG_COMMON_CLK
 static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
                                      u16 freqsel)
-#else
-static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
-#endif
 {
        struct dpll_data *dd = clk->dpll_data;
        u8 dco, sd_div;

@@ -417,14 +357,10 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
  *
  * Recalculate and propagate the DPLL rate.
  */
-#ifdef CONFIG_COMMON_CLK
 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
 {
        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-#else
-unsigned long omap3_dpll_recalc(struct clk *clk)
-{
-#endif
+
        return omap2_get_dpll_rate(clk);
 }

@@ -444,14 +380,9 @@ unsigned long omap3_dpll_recalc(struct clk *clk)
  * support low-power stop, or if the DPLL took too long to enter
  * bypass or lock, return -EINVAL; otherwise, return 0.
  */
-#ifdef CONFIG_COMMON_CLK
 int omap3_noncore_dpll_enable(struct clk_hw *hw)
 {
        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-#else
-int omap3_noncore_dpll_enable(struct clk *clk)
-{
-#endif
        int r;
        struct dpll_data *dd;
        struct clk *parent;

@@ -460,7 +391,6 @@ int omap3_noncore_dpll_enable(struct clk *clk)
        if (!dd)
                return -EINVAL;
 
-#ifdef CONFIG_COMMON_CLK
        if (clk->clkdm) {
                r = clkdm_clk_enable(clk->clkdm, hw->clk);
                if (r) {

@@ -475,11 +405,6 @@ int omap3_noncore_dpll_enable(struct clk *clk)
        parent = __clk_get_parent(hw->clk);
 
        if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
-#else
-       parent = __clk_get_parent(clk);
-
-       if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
-#endif
                WARN_ON(parent != dd->clk_bypass);
                r = _omap3_noncore_dpll_bypass(clk);
        } else {

@@ -487,16 +412,6 @@ int omap3_noncore_dpll_enable(struct clk *clk)
                r = _omap3_noncore_dpll_lock(clk);
        }
 
-#ifndef CONFIG_COMMON_CLK
-       /*
-        *FIXME: this is dubious - if clk->rate has changed, what about
-        * propagating?
-        */
-       if (!r)
-               clk->rate = (clk->recalc) ? clk->recalc(clk) :
-                       omap2_get_dpll_rate(clk);
-#endif
-
        return r;
 }

@@ -507,7 +422,6 @@ int omap3_noncore_dpll_enable(struct clk *clk)
  * Instructs a non-CORE DPLL to enter low-power stop.  This function is
  * intended for use in struct clkops.  No return value.
  */
-#ifdef CONFIG_COMMON_CLK
 void omap3_noncore_dpll_disable(struct clk_hw *hw)
 {
        struct clk_hw_omap *clk = to_clk_hw_omap(hw);

@@ -515,13 +429,6 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
        _omap3_noncore_dpll_stop(clk);
        if (clk->clkdm)
                clkdm_clk_disable(clk->clkdm, hw->clk);
-#else
-void omap3_noncore_dpll_disable(struct clk *clk)
-{
-       _omap3_noncore_dpll_stop(clk);
-       if (clk->clkdm)
-               clkdm_clk_disable(clk->clkdm, clk);
-#endif
 }

@@ -538,7 +445,6 @@ void omap3_noncore_dpll_disable(struct clk *clk)
  * target rate if it hasn't been done already, then program and lock
  * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
  */
-#ifdef CONFIG_COMMON_CLK
 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
                                        unsigned long parent_rate)
 {

@@ -608,85 +514,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
 
        return 0;
 }
-#else
-int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
-{
-       struct clk *new_parent = NULL;
-       unsigned long hw_rate, bypass_rate;
-       u16 freqsel = 0;
-       struct dpll_data *dd;
-       int ret;
-
-       if (!clk || !rate)
-               return -EINVAL;
-
-       dd = clk->dpll_data;
-       if (!dd)
-               return -EINVAL;
-
-       hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
-       if (rate == hw_rate)
-               return 0;
-
-       /*
-        * Ensure both the bypass and ref clocks are enabled prior to
-        * doing anything; we need the bypass clock running to reprogram
-        * the DPLL.
-        */
-       omap2_clk_enable(dd->clk_bypass);
-       omap2_clk_enable(dd->clk_ref);
-
-       bypass_rate = __clk_get_rate(dd->clk_bypass);
-       if (bypass_rate == rate &&
-           (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-               pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
-
-               ret = _omap3_noncore_dpll_bypass(clk);
-               if (!ret)
-                       new_parent = dd->clk_bypass;
-       } else {
-               if (dd->last_rounded_rate != rate)
-                       rate = clk->round_rate(clk, rate);
-
-               if (dd->last_rounded_rate == 0)
-                       return -EINVAL;
-
-               /* No freqsel on OMAP4 and OMAP3630 */
-               if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
-                       freqsel = _omap3_dpll_compute_freqsel(clk,
-                                               dd->last_rounded_n);
-                       if (!freqsel)
-                               WARN_ON(1);
-               }
-
-               pr_debug("clock: %s: set rate: locking rate to %lu.\n",
-                        __clk_get_name(clk), rate);
-
-               ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
-                                                dd->last_rounded_n, freqsel);
-               if (!ret)
-                       new_parent = dd->clk_ref;
-       }
-       if (!ret) {
-               /*
-                * Switch the parent clock in the hierarchy, and make sure
-                * that the new parent's usecount is correct.  Note: we
-                * enable the new parent before disabling the old to avoid
-                * any unnecessary hardware disable->enable transitions.
-                */
-               if (clk->usecount) {
-                       omap2_clk_enable(new_parent);
-                       omap2_clk_disable(clk->parent);
-               }
-               clk_reparent(clk, new_parent);
-               clk->rate = rate;
-       }
-       omap2_clk_disable(dd->clk_ref);
-       omap2_clk_disable(dd->clk_bypass);
-
-       return 0;
-}
-#endif
 
 /* DPLL autoidle read/set code */

@@ -698,11 +525,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
  * -EINVAL if passed a null pointer or if the struct clk does not
  * appear to refer to a DPLL.
  */
-#ifdef CONFIG_COMMON_CLK
 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
-#else
-u32 omap3_dpll_autoidle_read(struct clk *clk)
-#endif
 {
        const struct dpll_data *dd;
        u32 v;

@@ -731,11 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)
  * OMAP3430.  The DPLL will enter low-power stop when its downstream
  * clocks are gated.  No return value.
  */
-#ifdef CONFIG_COMMON_CLK
 void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
-#else
-void omap3_dpll_allow_idle(struct clk *clk)
-#endif
 {
        const struct dpll_data *dd;
        u32 v;

@@ -745,13 +564,8 @@ void omap3_dpll_allow_idle(struct clk *clk)
 
        dd = clk->dpll_data;
 
-       if (!dd->autoidle_reg) {
-#ifndef CONFIG_COMMON_CLK
-               pr_debug("clock: DPLL %s: autoidle not supported\n",
-                       __clk_get_name(clk));
-#endif
+       if (!dd->autoidle_reg)
                return;
-       }
 
        /*
         * REVISIT: CORE DPLL can optionally enter low-power bypass

@@ -771,11 +585,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
  *
  * Disable DPLL automatic idle control.  No return value.
  */
-#ifdef CONFIG_COMMON_CLK
 void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
-#else
-void omap3_dpll_deny_idle(struct clk *clk)
-#endif
 {
        const struct dpll_data *dd;
        u32 v;

@@ -785,13 +595,8 @@ void omap3_dpll_deny_idle(struct clk *clk)
 
        dd = clk->dpll_data;
 
-       if (!dd->autoidle_reg) {
-#ifndef CONFIG_COMMON_CLK
-               pr_debug("clock: DPLL %s: autoidle not supported\n",
-                       __clk_get_name(clk));
-#endif
+       if (!dd->autoidle_reg)
                return;
-       }
 
        v = __raw_readl(dd->autoidle_reg);
        v &= ~dd->autoidle_mask;

@@ -809,7 +614,6 @@ void omap3_dpll_deny_idle(struct clk *clk)
  * Using parent clock DPLL data, look up DPLL state.  If locked, set our
  * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
  */
-#ifdef CONFIG_COMMON_CLK
 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
                                    unsigned long parent_rate)
 {

@@ -829,22 +633,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
                        break;
                pclk = to_clk_hw_omap(hw);
        } while (pclk && !pclk->dpll_data);
-#else
-unsigned long omap3_clkoutx2_recalc(struct clk *clk)
-{
-       const struct dpll_data *dd;
-       unsigned long rate;
-       u32 v;
-       struct clk *pclk;
-       unsigned long parent_rate;
 
-       /* Walk up the parents of clk, looking for a DPLL */
-       pclk = __clk_get_parent(clk);
-       while (pclk && !pclk->dpll_data)
-               pclk = __clk_get_parent(pclk);
-
-       parent_rate = __clk_get_rate(__clk_get_parent(clk));
-#endif
        /* clk does not have a DPLL as a parent?  error in the clock data */
        if (!pclk) {
                WARN_ON(1);

@@ -865,21 +654,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 }
 
 /* OMAP3/4 non-CORE DPLL clkops */
-#ifdef CONFIG_COMMON_CLK
 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
        .allow_idle     = omap3_dpll_allow_idle,
        .deny_idle      = omap3_dpll_deny_idle,
 };
-#else
-const struct clkops clkops_omap3_noncore_dpll_ops = {
-       .enable         = omap3_noncore_dpll_enable,
-       .disable        = omap3_noncore_dpll_disable,
-       .allow_idle     = omap3_dpll_allow_idle,
-       .deny_idle      = omap3_dpll_deny_idle,
-};
-
-const struct clkops clkops_omap3_core_dpll_ops = {
-       .allow_idle     = omap3_dpll_allow_idle,
-       .deny_idle      = omap3_dpll_deny_idle,
-};
-#endif

Signature · 1 line

1.7.10.4

Laurent Pinchart

Tested-by on the v2 series

2012-11-13 13:41 UTC #67 lore raw

In reply to Mike Turquette

Hi Mike,

Thank you for the patches.

Quoted 18 lines · On Wednesday 07 November 2012 17:12:35 Mike Turquette wrote:

From: Mike Turquette <[email protected]>
Hi all,
This series is based on top of Paul's PRM/CM clean-up work. It is a refresh of the patches Rajendra sent out a while back[1], with the addition of several fixes for PM regressions[2] across several platforms.
I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF patches (delta is zero) and also suspend/resume.
I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming appears sane. However Panda-ES never comes back from suspend/resume. This problem exists on the PRM/CM branch I based on and was not introduced by this series. I am investigating that independently of this series.

Quoted 5 lines

Anyone wanting to pull the work can find it at:
git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8
[1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771
[2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015

I've tested the whole series on a Beagleboard-xM. The kernel boots fine but spits a couple of WARN_ON due to missing clk_prepare in USB-related drivers. I haven't noticed any regression in the OMAP3 ISP driver.

I've also successfully tested rate back-propagation (CLK_SET_RATE_PARENT) on the dpll4_m5x2_ck and cam_mclk clocks with the OMAP3 ISP driver. I'll send a patch for that on top of your v3.

So,

Tested-by Laurent Pinchart <[email protected]>

Signature · 3 lines

Regards,

Laurent Pinchart

Mike Turquette

author

2012-11-13 16:43 UTC #68 lore raw

Quoting Laurent Pinchart (2012-11-13 05:42:35)

Quoted 26 lines

Hi Mike,
Thank you for the patches.
Quoted 21 lines · On Wednesday 07 November 2012 17:12:35 Mike Turquette wrote:
From: Mike Turquette <[email protected]>
Hi all,
This series is based on top of Paul's PRM/CM clean-up work. It is a refresh of the patches Rajendra sent out a while back[1], with the addition of several fixes for PM regressions[2] across several platforms.
I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF patches (delta is zero) and also suspend/resume.
I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming appears sane. However Panda-ES never comes back from suspend/resume. This problem exists on the PRM/CM branch I based on and was not introduced by this series. I am investigating that independently of this series.
Anyone wanting to pull the work can find it at:
git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8

Quoted 7 lines

Quoted 2 lines
[1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771
[2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015
I've tested the whole series on a Beagleboard-xM. The kernel boots fine but spits a couple of WARN_ON due to missing clk_prepare in USB-related drivers. I haven't noticed any regression in the OMAP3 ISP driver.

Those drivers need to be fixed. Can you provide a log?

Quoted 4 lines

I've also successfully tested rate back-propagation (CLK_SET_RATE_PARENT) on the dpll4_m5x2_ck and cam_mclk clocks with the OMAP3 ISP driver. I'll send a patch for that on top of your v3.

It is great to see this feature in action. Do you think the OMAP3 ISP driver can have parent clock info removed? The goal of the CLK_SET_RATE_PARENT flag is to make life easier for drivers by not having to know the details of the clock tree topology.

Quoted 4 lines

So,
Tested-by Laurent Pinchart <[email protected]>

Thanks for testing!

Regards,
Mike

Quoted 4 lines

Signature · 3 lines
Regards,

Laurent Pinchart

Laurent Pinchart

2012-11-15 00:56 UTC #69 lore raw

Hi Mike,

Quoted 26 lines · On Tuesday 13 November 2012 08:43:23 Mike Turquette wrote:

Quoting Laurent Pinchart (2012-11-13 05:42:35)
Quoted 25 lines · On Wednesday 07 November 2012 17:12:35 Mike Turquette wrote:
Quoted 23 lines
From: Mike Turquette <[email protected]>
Hi all,
This series is based on top of Paul's PRM/CM clean-up work. It is a refresh of the patches Rajendra sent out a while back[1], with the addition of several fixes for PM regressions[2] across several platforms.
I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF patches (delta is zero) and also suspend/resume.
I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming appears sane. However Panda-ES never comes back from suspend/resume. This problem exists on the PRM/CM branch I based on and was not introduced by this series. I am investigating that independently of this series.
Anyone wanting to pull the work can find it at:
git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8
[1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771
[2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015

Quoted 6 lines

Quoted 4 lines
I've tested the whole series on a Beagleboard-xM. The kernel boots fine but
spits a couple of WARN_ON due to missing clk_prepare in USB-related drivers. I haven't noticed any regression in the OMAP3 ISP driver.
Those drivers need to be fixed. Can you provide a log?

Complete boot log attached to this e-mail. My tree is based on your clk- omap-3.8 branch in git://git.linaro.org/people/mturquette/linux.git. I haven't checked yet if patches for the following warnings have been posted to linux- omap or other mailing lists.

Quoted 8 lines

Quoted 3 lines
I've also successfully tested rate back-propagation (CLK_SET_RATE_PARENT) on the dpll4_m5x2_ck and cam_mclk clocks with the OMAP3 ISP driver. I'll send a patch for that on top of your v3.
It is great to see this feature in action. Do you think the OMAP3 ISP driver can have parent clock info removed? The goal of the CLK_SET_RATE_PARENT flag is to make life easier for drivers by not having to know the details of the clock tree topology.

If you mean removing the explicit handling of dpll4_m5_ck and setting the cam_mclk rate directly then yes, that's the goal, and I'll submit patches for that when the successor to thiis patch series will reach mainline. If you mean something different please elaborate :-)

Quoted 5 lines

Quoted 3 lines
So,
Tested-by Laurent Pinchart <[email protected]>
Thanks for testing!

Signature · 3 lines

Regards,

Laurent Pinchart

[    0.000000] Booting Linux on physical CPU 0
[    0.000000] Linux version 3.7.0-rc2-00295-g2d0135b (laurent@avalon) (gcc version 4.4.1 ('cs2009q3-67-hard-sb4') ) #454 Thu Nov 15 01:52:32 CET 2012
[    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] Machine: OMAP3 Beagle Board
[    0.000000] Ignoring tag cmdline (using the default kernel command line)
[    0.000000] Reserving 16777216 bytes SDRAM for VRAM
[    0.000000] cma: CMA: reserved 16 MiB at 9dc00000
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] OMAP3630 ES1.2 (l2cache iva sgx neon isp 192mhz_clk )
[    0.000000] Clocking rate (Crystal/Core/MPU): 26.0/332/600 MHz
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 125696
[    0.000000] Kernel command line: console=ttyO2,115200 omapfb.mode=dvi:1024x768MR-32@60 omapdss.def_disp=dvi
[    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Memory: 495MB = 495MB total
[    0.000000] Memory: 471724k/471724k available, 52564k reserved, 0K highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xe0800000 - 0xff000000   ( 488 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0624dd0   (6260 kB)
[    0.000000]       .init : 0xc0625000 - 0xc065a300   ( 213 kB)
[    0.000000]       .data : 0xc065c000 - 0xc0815e50   (1768 kB)
[    0.000000]        .bss : 0xc0815e74 - 0xc0dd87c0   (5899 kB)
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts
[    0.000000] Total of 96 interrupts on 1 active controller
[    0.000000] OMAP clockevent source: GPTIMER12 at 32768 Hz
[    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms
[    0.000000] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000000] Console: colour dummy device 80x30
[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
[    0.000000] ... MAX_LOCK_DEPTH:          48
[    0.000000] ... MAX_LOCKDEP_KEYS:        8191
[    0.000000] ... CLASSHASH_SIZE:          4096
[    0.000000] ... MAX_LOCKDEP_ENTRIES:     16384
[    0.000000] ... MAX_LOCKDEP_CHAINS:      32768
[    0.000000] ... CHAINHASH_SIZE:          16384
[    0.000000]  memory used by lock dependency info: 3951 kB
[    0.000000]  per task-struct memory footprint: 2304 bytes
[    0.001037] Calibrating delay loop... 309.35 BogoMIPS (lpj=1210368)
[    0.085479] pid_max: default: 32768 minimum: 301
[    0.085968] Security Framework initialized
[    0.086120] Mount-cache hash table entries: 512
[    0.091644] CPU: Testing write buffer coherency: ok
[    0.092742] Setting up static identity map for 0x80454970 - 0x804549c8
[    0.145568] pinctrl core: initialized pinctrl subsystem
[    0.154937] regulator-dummy: no parameters
[    0.158966] NET: Registered protocol family 16
[    0.167388] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.170501] omap-gpmc omap-gpmc: GPMC revision 5.0
[    0.188903] OMAP GPIO hardware version 2.5
[    0.218780] omap_mux_init: Add partition: #1: core, flags: 0
[    0.222503] OMAP3 Beagle Rev: xM C
[    0.241485] _omap_mux_get_by_name: Could not find signal uart4_rx.uart4_rx
[    0.248382] Reprogramming SDRC clock to 332000000 Hz
[    0.254669] find_device_opp: Invalid parameters
[    0.254852] find_device_opp: Invalid parameters
[    0.254913] find_device_opp: Invalid parameters
[    0.254974] find_device_opp: Invalid parameters
[    0.255279] platform mpu.0: opp_set_availability: Device OPP not found (-19)
[    0.255310] beagle_opp_init: failed to enable higher opp -19
[    0.255340] platform mpu.0: opp_set_availability: Device OPP not found (-19)
[    0.255371] hw-breakpoint: debug architecture 0x4 unsupported.
[    0.282226] OMAP DMA hardware revision 5.0
[    0.290405]  arm-pmu: alias fck already exists
[    0.400115] bio: create slab <bio-0> at 0
[    0.544433] omap-dma-engine omap-dma-engine: OMAP DMA engine driver
[    0.553558] SCSI subsystem initialized
[    0.557891] usbcore: registered new interface driver usbfs
[    0.558776] usbcore: registered new interface driver hub
[    0.560089] usbcore: registered new device driver usb
[    0.562927] musb-omap2430 musb-omap2430: invalid resource
[    0.598785] twl 1-0048: PIH (irq 23) chaining IRQs 338..346
[    0.599578] twl 1-0048: power (irq 343) chaining IRQs 346..353
[    0.604217] twl4030_gpio twl4030_gpio: gpio (irq 338) chaining IRQs 354..371
[    0.614929] VUSB1V5: 1500 mV normal standby
[    0.618560] VUSB1V8: 1800 mV normal standby
[    0.622131] VUSB3V1: 3100 mV normal standby
[    0.630798] twl4030_usb twl4030_usb: Initialized TWL4030 USB module
[    0.636505] vdd_mpu_iva: 600 <--> 1450 mV normal 
[    0.639984] vdd_core: 600 <--> 1450 mV normal 
[    0.644073] VMMC1: 1850 <--> 3150 mV at 3000 mV normal standby
[    0.647918] VDAC: 1800 mV normal standby
[    0.651733] VDVI: 1800 mV normal standby
[    0.656005] VSIM: 1800 <--> 3000 mV at 1800 mV normal standby
[    0.660705] VAUX3: 1800 mV normal standby
[    0.665435] VAUX4: 1800 mV normal standby
[    0.666839] omap_i2c omap_i2c.1: bus 1 rev1.4.0 at 2600 kHz
[    0.679962] omap_i2c omap_i2c.3: bus 3 rev1.4.0 at 100 kHz
[    0.681274] media: Linux media interface: v0.10
[    0.682159] Linux video capture interface: v2.00
[    0.688049] omap-iommu omap-iommu.0: isp registered
[    0.690521] Advanced Linux Sound Architecture Driver Initialized.
[    0.696594] Switching to clocksource 32k_counter
[    0.899322] NET: Registered protocol family 2
[    0.902099] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[    0.902862] TCP bind hash table entries: 16384 (order: 7, 720896 bytes)
[    0.912445] TCP: Hash tables configured (established 16384 bind 16384)
[    0.912719] TCP: reno registered
[    0.912750] UDP hash table entries: 256 (order: 2, 24576 bytes)
[    0.913085] UDP-Lite hash table entries: 256 (order: 2, 24576 bytes)
[    0.914337] NET: Registered protocol family 1
[    0.916259] RPC: Registered named UNIX socket transport module.
[    0.916290] RPC: Registered udp transport module.
[    0.916320] RPC: Registered tcp transport module.
[    0.916320] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.916870] usbhs_omap usbhs_omap: xclk60mhsp2_ck set parentfailed error:-38
[    0.917388] ------------[ cut here ]------------
[    0.917419] WARNING: at drivers/clk/clk.c:512 __clk_enable+0x28/0x94()
[    0.917449] Modules linked in:
[    0.917480] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64)
[    0.917510] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c)
[    0.917541] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c03606f4>] (__clk_enable+0x28/0x94)
[    0.917572] [<c03606f4>] (__clk_enable+0x28/0x94) from [<c0360780>] (clk_enable+0x20/0x3c)
[    0.917602] [<c0360780>] (clk_enable+0x20/0x3c) from [<c029f2b8>] (usbhs_runtime_resume+0x74/0x90)
[    0.917633] [<c029f2b8>] (usbhs_runtime_resume+0x74/0x90) from [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38)
[    0.917663] [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38) from [<c02922bc>] (__rpm_callback+0x30/0x58)
[    0.917663] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c02922fc>] (rpm_callback+0x18/0x28)
[    0.917694] [<c02922fc>] (rpm_callback+0x18/0x28) from [<c02931d8>] (rpm_resume+0x3b0/0x4cc)
[    0.917724] [<c02931d8>] (rpm_resume+0x3b0/0x4cc) from [<c0293558>] (__pm_runtime_resume+0x48/0x60)
[    0.917755] [<c0293558>] (__pm_runtime_resume+0x48/0x60) from [<c0445260>] (usbhs_omap_probe+0x3b4/0x810)
[    0.917785] [<c0445260>] (usbhs_omap_probe+0x3b4/0x810) from [<c028be64>] (platform_drv_probe+0x18/0x1c)
[    0.917816] [<c028be64>] (platform_drv_probe+0x18/0x1c) from [<c028aca4>] (driver_probe_device+0xb0/0x1e8)
[    0.917846] [<c028aca4>] (driver_probe_device+0xb0/0x1e8) from [<c028ae44>] (__driver_attach+0x68/0x8c)
[    0.917846] [<c028ae44>] (__driver_attach+0x68/0x8c) from [<c0289728>] (bus_for_each_dev+0x44/0x74)
[    0.917877] [<c0289728>] (bus_for_each_dev+0x44/0x74) from [<c0289e10>] (bus_add_driver+0xa0/0x218)
[    0.917907] [<c0289e10>] (bus_add_driver+0xa0/0x218) from [<c028b444>] (driver_register+0xa0/0x138)
[    0.917938] [<c028b444>] (driver_register+0xa0/0x138) from [<c028c124>] (platform_driver_probe+0x18/0x8c)
[    0.917968] [<c028c124>] (platform_driver_probe+0x18/0x8c) from [<c0008840>] (do_one_initcall+0x94/0x168)
[    0.917968] [<c0008840>] (do_one_initcall+0x94/0x168) from [<c0440744>] (kernel_init+0xd8/0x2a0)
[    0.917999] [<c0440744>] (kernel_init+0xd8/0x2a0) from [<c0012a90>] (ret_from_fork+0x14/0x24)
[    0.918182] ---[ end trace 0eaa05360b28dfab ]---
[    0.918212] ------------[ cut here ]------------
[    0.918212] WARNING: at drivers/clk/clk.c:512 __clk_enable+0x28/0x94()
[    0.918243] Modules linked in:
[    0.918273] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64)
[    0.918273] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c)
[    0.918304] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c03606f4>] (__clk_enable+0x28/0x94)
[    0.918334] [<c03606f4>] (__clk_enable+0x28/0x94) from [<c0360780>] (clk_enable+0x20/0x3c)
[    0.918365] [<c0360780>] (clk_enable+0x20/0x3c) from [<c029f2c0>] (usbhs_runtime_resume+0x7c/0x90)
[    0.918395] [<c029f2c0>] (usbhs_runtime_resume+0x7c/0x90) from [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38)
[    0.918395] [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38) from [<c02922bc>] (__rpm_callback+0x30/0x58)
[    0.918426] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c02922fc>] (rpm_callback+0x18/0x28)
[    0.918457] [<c02922fc>] (rpm_callback+0x18/0x28) from [<c02931d8>] (rpm_resume+0x3b0/0x4cc)
[    0.918487] [<c02931d8>] (rpm_resume+0x3b0/0x4cc) from [<c0293558>] (__pm_runtime_resume+0x48/0x60)
[    0.918518] [<c0293558>] (__pm_runtime_resume+0x48/0x60) from [<c0445260>] (usbhs_omap_probe+0x3b4/0x810)
[    0.918518] [<c0445260>] (usbhs_omap_probe+0x3b4/0x810) from [<c028be64>] (platform_drv_probe+0x18/0x1c)
[    0.918548] [<c028be64>] (platform_drv_probe+0x18/0x1c) from [<c028aca4>] (driver_probe_device+0xb0/0x1e8)
[    0.918579] [<c028aca4>] (driver_probe_device+0xb0/0x1e8) from [<c028ae44>] (__driver_attach+0x68/0x8c)
[    0.918609] [<c028ae44>] (__driver_attach+0x68/0x8c) from [<c0289728>] (bus_for_each_dev+0x44/0x74)
[    0.918640] [<c0289728>] (bus_for_each_dev+0x44/0x74) from [<c0289e10>] (bus_add_driver+0xa0/0x218)
[    0.918640] [<c0289e10>] (bus_add_driver+0xa0/0x218) from [<c028b444>] (driver_register+0xa0/0x138)
[    0.918670] [<c028b444>] (driver_register+0xa0/0x138) from [<c028c124>] (platform_driver_probe+0x18/0x8c)
[    0.918701] [<c028c124>] (platform_driver_probe+0x18/0x8c) from [<c0008840>] (do_one_initcall+0x94/0x168)
[    0.918731] [<c0008840>] (do_one_initcall+0x94/0x168) from [<c0440744>] (kernel_init+0xd8/0x2a0)
[    0.918762] [<c0440744>] (kernel_init+0xd8/0x2a0) from [<c0012a90>] (ret_from_fork+0x14/0x24)
[    0.918762] ---[ end trace 0eaa05360b28dfac ]---
[    0.918823] ------------[ cut here ]------------
[    0.918853] WARNING: at drivers/clk/clk.c:471 clk_disable+0x20/0x34()
[    0.918853] Modules linked in:
[    0.918884] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64)
[    0.918914] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c)
[    0.918945] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c03606b8>] (clk_disable+0x20/0x34)
[    0.918945] [<c03606b8>] (clk_disable+0x20/0x34) from [<c029f32c>] (usbhs_runtime_suspend+0x58/0x90)
[    0.918975] [<c029f32c>] (usbhs_runtime_suspend+0x58/0x90) from [<c028e8b8>] (pm_generic_runtime_suspend+0x2c/0x38)
[    0.919006] [<c028e8b8>] (pm_generic_runtime_suspend+0x2c/0x38) from [<c00246b0>] (_od_runtime_suspend+0xc/0x24)
[    0.919036] [<c00246b0>] (_od_runtime_suspend+0xc/0x24) from [<c02922bc>] (__rpm_callback+0x30/0x58)
[    0.919067] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c02922fc>] (rpm_callback+0x18/0x28)
[    0.919067] [<c02922fc>] (rpm_callback+0x18/0x28) from [<c02927a4>] (rpm_suspend+0x28c/0x45c)
[    0.919097] [<c02927a4>] (rpm_suspend+0x28c/0x45c) from [<c02937a4>] (__pm_runtime_suspend+0x54/0x6c)
[    0.919128] [<c02937a4>] (__pm_runtime_suspend+0x54/0x6c) from [<c028eda8>] (pm_generic_runtime_idle+0x44/0x4c)
[    0.919158] [<c028eda8>] (pm_generic_runtime_idle+0x44/0x4c) from [<c02922bc>] (__rpm_callback+0x30/0x58)
[    0.919189] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c0292b64>] (rpm_idle+0x184/0x208)
[    0.919189] [<c0292b64>] (rpm_idle+0x184/0x208) from [<c0292c9c>] (__pm_runtime_idle+0x54/0x6c)
[    0.919219] [<c0292c9c>] (__pm_runtime_idle+0x54/0x6c) from [<c04453c4>] (usbhs_omap_probe+0x518/0x810)
[    0.919250] [<c04453c4>] (usbhs_omap_probe+0x518/0x810) from [<c028be64>] (platform_drv_probe+0x18/0x1c)
[    0.919281] [<c028be64>] (platform_drv_probe+0x18/0x1c) from [<c028aca4>] (driver_probe_device+0xb0/0x1e8)
[    0.919311] [<c028aca4>] (driver_probe_device+0xb0/0x1e8) from [<c028ae44>] (__driver_attach+0x68/0x8c)
[    0.919311] [<c028ae44>] (__driver_attach+0x68/0x8c) from [<c0289728>] (bus_for_each_dev+0x44/0x74)
[    0.919342] [<c0289728>] (bus_for_each_dev+0x44/0x74) from [<c0289e10>] (bus_add_driver+0xa0/0x218)
[    0.919372] [<c0289e10>] (bus_add_driver+0xa0/0x218) from [<c028b444>] (driver_register+0xa0/0x138)
[    0.919403] [<c028b444>] (driver_register+0xa0/0x138) from [<c028c124>] (platform_driver_probe+0x18/0x8c)
[    0.919433] [<c028c124>] (platform_driver_probe+0x18/0x8c) from [<c0008840>] (do_one_initcall+0x94/0x168)
[    0.919433] [<c0008840>] (do_one_initcall+0x94/0x168) from [<c0440744>] (kernel_init+0xd8/0x2a0)
[    0.919464] [<c0440744>] (kernel_init+0xd8/0x2a0) from [<c0012a90>] (ret_from_fork+0x14/0x24)
[    0.919494] ---[ end trace 0eaa05360b28dfad ]---
[    0.919494] ------------[ cut here ]------------
[    0.919525] WARNING: at drivers/clk/clk.c:471 clk_disable+0x20/0x34()
[    0.919525] Modules linked in:
[    0.919555] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64)
[    0.919586] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c)
[    0.919586] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c03606b8>] (clk_disable+0x20/0x34)
[    0.919616] [<c03606b8>] (clk_disable+0x20/0x34) from [<c029f334>] (usbhs_runtime_suspend+0x60/0x90)
[    0.919647] [<c029f334>] (usbhs_runtime_suspend+0x60/0x90) from [<c028e8b8>] (pm_generic_runtime_suspend+0x2c/0x38)
[    0.919677] [<c028e8b8>] (pm_generic_runtime_suspend+0x2c/0x38) from [<c00246b0>] (_od_runtime_suspend+0xc/0x24)
[    0.919677] [<c00246b0>] (_od_runtime_suspend+0xc/0x24) from [<c02922bc>] (__rpm_callback+0x30/0x58)
[    0.919708] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c02922fc>] (rpm_callback+0x18/0x28)
[    0.919738] [<c02922fc>] (rpm_callback+0x18/0x28) from [<c02927a4>] (rpm_suspend+0x28c/0x45c)
[    0.919769] [<c02927a4>] (rpm_suspend+0x28c/0x45c) from [<c02937a4>] (__pm_runtime_suspend+0x54/0x6c)
[    0.919799] [<c02937a4>] (__pm_runtime_suspend+0x54/0x6c) from [<c028eda8>] (pm_generic_runtime_idle+0x44/0x4c)
[    0.919799] [<c028eda8>] (pm_generic_runtime_idle+0x44/0x4c) from [<c02922bc>] (__rpm_callback+0x30/0x58)
[    0.919830] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c0292b64>] (rpm_idle+0x184/0x208)
[    0.919860] [<c0292b64>] (rpm_idle+0x184/0x208) from [<c0292c9c>] (__pm_runtime_idle+0x54/0x6c)
[    0.919891] [<c0292c9c>] (__pm_runtime_idle+0x54/0x6c) from [<c04453c4>] (usbhs_omap_probe+0x518/0x810)
[    0.919921] [<c04453c4>] (usbhs_omap_probe+0x518/0x810) from [<c028be64>] (platform_drv_probe+0x18/0x1c)
[    0.919921] [<c028be64>] (platform_drv_probe+0x18/0x1c) from [<c028aca4>] (driver_probe_device+0xb0/0x1e8)
[    0.919952] [<c028aca4>] (driver_probe_device+0xb0/0x1e8) from [<c028ae44>] (__driver_attach+0x68/0x8c)
[    0.919982] [<c028ae44>] (__driver_attach+0x68/0x8c) from [<c0289728>] (bus_for_each_dev+0x44/0x74)
[    0.920013] [<c0289728>] (bus_for_each_dev+0x44/0x74) from [<c0289e10>] (bus_add_driver+0xa0/0x218)
[    0.920043] [<c0289e10>] (bus_add_driver+0xa0/0x218) from [<c028b444>] (driver_register+0xa0/0x138)
[    0.920043] [<c028b444>] (driver_register+0xa0/0x138) from [<c028c124>] (platform_driver_probe+0x18/0x8c)
[    0.920074] [<c028c124>] (platform_driver_probe+0x18/0x8c) from [<c0008840>] (do_one_initcall+0x94/0x168)
[    0.920104] [<c0008840>] (do_one_initcall+0x94/0x168) from [<c0440744>] (kernel_init+0xd8/0x2a0)
[    0.920135] [<c0440744>] (kernel_init+0xd8/0x2a0) from [<c0012a90>] (ret_from_fork+0x14/0x24)
[    0.920135] ---[ end trace 0eaa05360b28dfae ]---
[    0.926208] NetWinder Floating Point Emulator V0.97 (double precision)
[    0.926727] CPU PMU: probing PMU on CPU 0
[    0.926910] hw perfevents: enabled with ARMv7 Cortex-A8 PMU driver, 5 counters available
[    1.136230] VFS: Disk quotas dquot_6.5.2
[    1.136352] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    1.139221] NFS: Registering the id_resolver key type
[    1.139862] Key type id_resolver registered
[    1.139892] Key type id_legacy registered
[    1.140136] jffs2: version 2.2. (NAND) (SUMMARY)  �© 2001-2006 Red Hat, Inc.
[    1.140930] msgmni has been set to 953
[    1.149475] io scheduler noop registered
[    1.149505] io scheduler deadline registered
[    1.149658] io scheduler cfq registered (default)
[    1.158386] OMAP DSS rev 2.0
[    1.177276] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    1.188354] omap_uart.0: ttyO0 at MMIO 0x4806a000 (irq = 88) is a OMAP UART0
[    1.191680] omap_uart.2: ttyO2 at MMIO 0x49020000 (irq = 90) is a OMAP UART2
[    2.921600] console [ttyO2] enabled
[    2.928222] omap_uart.3: ttyO3 at MMIO 0x49042000 (irq = 96) is a OMAP UART3
[    2.987121] brd: module loaded
[    3.018829] loop: module loaded
[    3.028900] mtdoops: mtd device (mtddev=name/number) must be supplied
[    3.036804] No NAND device found
[    3.040374] No NAND device found
[    3.045074] OneNAND driver initializing
[    3.066711] usbcore: registered new interface driver asix
[    3.073333] usbcore: registered new interface driver cdc_ether
[    3.080474] usbcore: registered new interface driver smsc95xx
[    3.087554] usbcore: registered new interface driver cdc_ncm
[    3.096282] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    3.104125] ------------[ cut here ]------------
[    3.108978] WARNING: at drivers/clk/clk.c:512 __clk_enable+0x28/0x94()
[    3.115814] Modules linked in:
[    3.119018] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64)
[    3.128845] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c)
[    3.138946] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c03606f4>] (__clk_enable+0x28/0x94)
[    3.148315] [<c03606f4>] (__clk_enable+0x28/0x94) from [<c0360780>] (clk_enable+0x20/0x3c)
[    3.156951] [<c0360780>] (clk_enable+0x20/0x3c) from [<c029f2b8>] (usbhs_runtime_resume+0x74/0x90)
[    3.166320] [<c029f2b8>] (usbhs_runtime_resume+0x74/0x90) from [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38)
[    3.177062] [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38) from [<c02922bc>] (__rpm_callback+0x30/0x58)
[    3.187225] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c02922fc>] (rpm_callback+0x18/0x28)
[    3.196258] [<c02922fc>] (rpm_callback+0x18/0x28) from [<c02931d8>] (rpm_resume+0x3b0/0x4cc)
[    3.205078] [<c02931d8>] (rpm_resume+0x3b0/0x4cc) from [<c0293104>] (rpm_resume+0x2dc/0x4cc)
[    3.213897] [<c0293104>] (rpm_resume+0x2dc/0x4cc) from [<c0293558>] (__pm_runtime_resume+0x48/0x60)
[    3.223358] [<c0293558>] (__pm_runtime_resume+0x48/0x60) from [<c030ad1c>] (ehci_hcd_omap_probe+0x194/0x220)
[    3.233642] [<c030ad1c>] (ehci_hcd_omap_probe+0x194/0x220) from [<c028be64>] (platform_drv_probe+0x18/0x1c)
[    3.243835] [<c028be64>] (platform_drv_probe+0x18/0x1c) from [<c028aca4>] (driver_probe_device+0xb0/0x1e8)
[    3.253906] [<c028aca4>] (driver_probe_device+0xb0/0x1e8) from [<c028ae44>] (__driver_attach+0x68/0x8c)
[    3.263732] [<c028ae44>] (__driver_attach+0x68/0x8c) from [<c0289728>] (bus_for_each_dev+0x44/0x74)
[    3.273193] [<c0289728>] (bus_for_each_dev+0x44/0x74) from [<c0289e10>] (bus_add_driver+0xa0/0x218)
[    3.282653] [<c0289e10>] (bus_add_driver+0xa0/0x218) from [<c028b444>] (driver_register+0xa0/0x138)
[    3.292114] [<c028b444>] (driver_register+0xa0/0x138) from [<c0644298>] (ehci_hcd_init+0xac/0x108)
[    3.301483] [<c0644298>] (ehci_hcd_init+0xac/0x108) from [<c0008840>] (do_one_initcall+0x94/0x168)
[    3.310852] [<c0008840>] (do_one_initcall+0x94/0x168) from [<c0440744>] (kernel_init+0xd8/0x2a0)
[    3.320037] [<c0440744>] (kernel_init+0xd8/0x2a0) from [<c0012a90>] (ret_from_fork+0x14/0x24)
[    3.328948] ---[ end trace 0eaa05360b28dfaf ]---
[    3.333770] ------------[ cut here ]------------
[    3.338592] WARNING: at drivers/clk/clk.c:512 __clk_enable+0x28/0x94()
[    3.345397] Modules linked in:
[    3.348602] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64)
[    3.358428] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c)
[    3.368530] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c03606f4>] (__clk_enable+0x28/0x94)
[    3.377899] [<c03606f4>] (__clk_enable+0x28/0x94) from [<c0360780>] (clk_enable+0x20/0x3c)
[    3.386535] [<c0360780>] (clk_enable+0x20/0x3c) from [<c029f2c0>] (usbhs_runtime_resume+0x7c/0x90)
[    3.395904] [<c029f2c0>] (usbhs_runtime_resume+0x7c/0x90) from [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38)
[    3.406616] [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38) from [<c02922bc>] (__rpm_callback+0x30/0x58)
[    3.416809] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c02922fc>] (rpm_callback+0x18/0x28)
[    3.425811] [<c02922fc>] (rpm_callback+0x18/0x28) from [<c02931d8>] (rpm_resume+0x3b0/0x4cc)
[    3.434631] [<c02931d8>] (rpm_resume+0x3b0/0x4cc) from [<c0293104>] (rpm_resume+0x2dc/0x4cc)
[    3.443450] [<c0293104>] (rpm_resume+0x2dc/0x4cc) from [<c0293558>] (__pm_runtime_resume+0x48/0x60)
[    3.452911] [<c0293558>] (__pm_runtime_resume+0x48/0x60) from [<c030ad1c>] (ehci_hcd_omap_probe+0x194/0x220)
[    3.463195] [<c030ad1c>] (ehci_hcd_omap_probe+0x194/0x220) from [<c028be64>] (platform_drv_probe+0x18/0x1c)
[    3.473358] [<c028be64>] (platform_drv_probe+0x18/0x1c) from [<c028aca4>] (driver_probe_device+0xb0/0x1e8)
[    3.483459] [<c028aca4>] (driver_probe_device+0xb0/0x1e8) from [<c028ae44>] (__driver_attach+0x68/0x8c)
[    3.493286] [<c028ae44>] (__driver_attach+0x68/0x8c) from [<c0289728>] (bus_for_each_dev+0x44/0x74)
[    3.502716] [<c0289728>] (bus_for_each_dev+0x44/0x74) from [<c0289e10>] (bus_add_driver+0xa0/0x218)
[    3.512176] [<c0289e10>] (bus_add_driver+0xa0/0x218) from [<c028b444>] (driver_register+0xa0/0x138)
[    3.521636] [<c028b444>] (driver_register+0xa0/0x138) from [<c0644298>] (ehci_hcd_init+0xac/0x108)
[    3.531005] [<c0644298>] (ehci_hcd_init+0xac/0x108) from [<c0008840>] (do_one_initcall+0x94/0x168)
[    3.540374] [<c0008840>] (do_one_initcall+0x94/0x168) from [<c0440744>] (kernel_init+0xd8/0x2a0)
[    3.549560] [<c0440744>] (kernel_init+0xd8/0x2a0) from [<c0012a90>] (ret_from_fork+0x14/0x24)
[    3.558441] ---[ end trace 0eaa05360b28dfb0 ]---
[    3.563446] ehci-omap ehci-omap.0: OMAP-EHCI Host Controller
[    3.573059] ehci-omap ehci-omap.0: new USB bus registered, assigned bus number 1
[    4.618804] ehci-omap ehci-omap.0: irq 93, io mem 0x48064800
[    4.634338] ehci-omap ehci-omap.0: USB 2.0 started, EHCI 1.00
[    4.641845] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    4.649047] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    4.656677] usb usb1: Product: OMAP-EHCI Host Controller
[    4.662292] usb usb1: Manufacturer: Linux 3.7.0-rc2-00295-g2d0135b ehci_hcd
[    4.669647] usb usb1: SerialNumber: ehci-omap.0
[    4.680297] hub 1-0:1.0: USB hub found
[    4.684539] hub 1-0:1.0: 3 ports detected
[    4.692901] musb-hdrc: version 6.0, ?dma?, otg (peripheral+host)
[    4.719635] input: twl4030_pwrbutton as /devices/platform/omap_i2c.1/i2c-1/1-0049/twl4030_pwrbutton/input/input0
[    4.733947] twl_rtc twl_rtc: Enabling TWL-RTC
[    4.745208] twl_rtc twl_rtc: rtc core: registered twl_rtc as rtc0
[    4.753814] i2c /dev entries driver
[    4.764495] omap_wdt: OMAP Watchdog Timer Rev 0x31: initial timeout 60 sec
[    4.773651] twl4030_wdt twl4030_wdt: Failed to register misc device
[    4.780364] twl4030_wdt: probe of twl4030_wdt failed with error -16
[    4.789031] cpu cpu0: opp_init_cpufreq_table: Device OPP not found (-19)
[    4.796478] cpu cpu0: omap_cpu_init: cpu0: failed creating freq table[-19]
[    4.803894] cpuidle: using governor ladder
[    4.808319] cpuidle: using governor menu
[    4.818847] omap_hsmmc omap_hsmmc.0: Failed to get debounce clk
[    4.825256] omap-dma-engine omap-dma-engine: allocating channel for 62
[    4.832244] omap-dma-engine omap-dma-engine: allocating channel for 61
[    5.032897] usb 1-2: new high-speed USB device number 2 using ehci-omap
[    5.197692] usb 1-2: New USB device found, idVendor=0424, idProduct=9514
[    5.204803] usb 1-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    5.224517] hub 1-2:1.0: USB hub found
[    5.230926] hub 1-2:1.0: 5 ports detected
[    5.253845] usbcore: registered new interface driver usbhid
[    5.259826] usbhid: USB HID core driver
[    5.275726] oprofile: using arm/armv7
[    5.280517] TCP: cubic registered
[    5.284118] Initializing XFRM netlink socket
[    5.288757] NET: Registered protocol family 17
[    5.293731] NET: Registered protocol family 15
[    5.299041] Key type dns_resolver registered
[    5.303680] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
[    5.328308] omap2_set_init_voltage: unable to find boot up OPP for vdd_mpu_iva
[    5.335998] omap2_set_init_voltage: unable to set vdd_mpu_iva
[    5.359069] mmc0: host does not support reading read-only switch. assuming write-enable.
[    5.371734] mmc0: new high speed SDHC card at address 5ffa
[    5.383026] omap_i2c omap_i2c.2: bus 2 rev1.4.0 at 100 kHz
[    5.389923] mmcblk0: mmc0:5ffa SD04G 3.69 GiB 
[    5.396697] ThumbEE CPU extension supported.
[    5.401672] SmartReflex Class3 initialized
[    5.412811]  mmcblk0: p1 p2 p3 p4
[    5.425964] fbcvt: 1024x768@60: CVT Name - .786M3-R
[    5.448333] VDVI: incomplete constraints, leaving on
[    5.453918] VDAC: incomplete constraints, leaving on
[    5.467254] input: gpio-keys as /devices/platform/gpio-keys/input/input1
[    5.478210] twl_rtc twl_rtc: setting system clock to 2012-10-16 18:17:33 UTC (1350411453)
[    5.487365] omap_vout omap_vout: Buffer Size = 3932160
[    5.496765] omap_vout omap_vout: : registered and initialized video device 0
[    5.504364] omap_vout omap_vout: Buffer Size = 3932160
[    5.512420] omap_vout omap_vout: : registered and initialized video device 1
[    5.521179] sr_init: No PMIC hook to init smartreflex
[    5.527221] smartreflex smartreflex.0: omap_sr_probe: SmartReflex driver initialized
[    5.536834] smartreflex smartreflex.1: omap_sr_probe: SmartReflex driver initialized
[    5.547363] ------------[ cut here ]------------
[    5.552246] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 clkdm_clk_disable+0x70/0xd0()
[    5.560943] Modules linked in:
[    5.564178] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64)
[    5.574005] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c)
[    5.584106] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c0029dfc>] (clkdm_clk_disable+0x70/0xd0)
[    5.593933] [<c0029dfc>] (clkdm_clk_disable+0x70/0xd0) from [<c035fc94>] (clk_disable_unused_subtree+0x74/0x88)
[    5.604461] [<c035fc94>] (clk_disable_unused_subtree+0x74/0x88) from [<c035fc40>] (clk_disable_unused_subtree+0x20/0x88)
[    5.615814] ---[ end trace 0eaa05360b28dfb2 ]---
[    5.621215] ------------[ cut here ]------------
[    5.626068] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 clkdm_clk_disable+0x70/0xd0()
[    5.634765] Modules linked in:
[    5.637969] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64)
[    5.647796] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c)
[    5.657897] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c0029dfc>] (clkdm_clk_disable+0x70/0xd0)
[    5.667724] [<c0029dfc>] (clkdm_clk_disable+0x70/0xd0) from [<c035fc94>] (clk_disable_unused_subtree+0x74/0x88)
[    5.678253] [<c035fc94>] (clk_disable_unused_subtree+0x74/0x88) from [<c035fc40>] (clk_disable_unused_subtree+0x20/0x88)
[    5.689605] ---[ end trace 0eaa05360b28dfb3 ]---
[    5.794860] usb 1-2.1: new high-speed USB device number 3 using ehci-omap
[    5.916992] usb 1-2.1: New USB device found, idVendor=0424, idProduct=ec00
[    5.924255] usb 1-2.1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    5.938629] smsc95xx v1.0.4
[    6.039916] smsc95xx 1-2.1:1.0 eth0: register 'smsc95xx' at usb-ehci-omap.0-2.1, smsc95xx USB 2.0 Ethernet, ae:b1:2c:0c:25:0d
[    6.134948] usb 1-2.5: new low-speed USB device number 4 using ehci-omap
[    6.276367] usb 1-2.5: New USB device found, idVendor=045e, idProduct=001e
[    6.283660] usb 1-2.5: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[    6.291381] usb 1-2.5: Product: Microsoft IntelliMouse�® Explorer
[    6.297790] usb 1-2.5: Manufacturer: Microsoft
[    6.322143] input: Microsoft Microsoft IntelliMouse�® Explorer as /devices/platform/usbhs_omap/ehci-omap.0/usb1/1-2/1-2.5/1-2.5:1.0/input/input2
[    6.335937] hid-generic 0003:045E:001E.0001: input: USB HID v1.00 Mouse [Microsoft Microsoft IntelliMouse�® Explorer] on usb-ehci-omap.0-2.5/input0
[    8.332000] smsc95xx 1-2.1:1.0 eth0: link up, 100Mbps, full-duplex, lpa 0xCDE1