Add clock framework for armada 370/XP

Hello Mike,

I hope this 4th version will meet your expectations. Beside the corrections you have asked I also changed the way I get resources for the clocks. Instead of referring to a node name, now I refer to a compatible name which should be a better use of the device tree.

Rather than taking this series in your git tree, would it possible to give your ack to the patches and let Jason Cooper take the patch set in his git tree. We have other series for mvebu which depend on this one (SMP, HWIOCC and SATA for now and more to come), and it will be easier for us to have everything in the same place.

The purpose of this patch set is to add support for clock framework for Armada 370 and Armada XP SoCs. All the support is done under the directory drivers/clk/mvebu/ as the support for other mvebu SoCs was in mind during the writing of the code.

Two kinds of clocks are added:

- The CPU clocks are only for Armada XP (which is multi-core)

- The core clocks are clocks which have their rate fixed during reset.

Many thanks to Thomas Petazzoni and Sebastian Hesselbarth for their review and feedback. The device tree bindings were really improved with the advices of Sebastian.

Changelog:
V3 -> V4
- Rebased on top of 3.7-rc3
- Replaced the whitespace by tab in the Documentation files
- Fixed the comment style according to the CodingStyle documentation
- Fixed incorrect indentation
- Removed redundant header in clk-cpu.c
- Replaced improper whitespace by tabs in armada-xp.dtsi
- In the device tree, the resources for the clocks do not rely anymore on the node name mvebu-sar but now only depend on the compatible name. (Issue reported by Sebastian Hesselbarth)

V2 -> V3:
- Rebased on top of v3.7-rc1
- Fixed a typo in device trees
- Fixed warning from checkpatch

V1 -> V2:
- Improved the spelling and the wording of the documentation and the 1st commit log
- Removed the "end_of_list" name which are unused here.
- Fix the cpu clock by using of_clk_src_onecell_get in the same way it was used for the core clocks

Regards,

Gregory CLEMENT (3):
clk: mvebu: add armada-370-xp specific clocks
clk: armada-370-xp: add support for clock framework
clocksource: time-armada-370-xp converted to clk framework

 .../devicetree/bindings/clock/mvebu-core-clock.txt |   40 +++
 .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   21 ++
 arch/arm/boot/dts/armada-370-db.dts                |    4 -
 arch/arm/boot/dts/armada-370-xp.dtsi               |    1 +
 arch/arm/boot/dts/armada-370.dtsi                  |   12 +
 arch/arm/boot/dts/armada-xp.dtsi                   |   48 +++
 arch/arm/mach-mvebu/Kconfig                        |    5 +
 arch/arm/mach-mvebu/armada-370-xp.c                |    8 +-
 arch/arm/mach-mvebu/common.h                       |    1 +
 drivers/clk/Makefile                               |    1 +
 drivers/clk/mvebu/Makefile                         |    2 +
 drivers/clk/mvebu/clk-core.c                       |  318 ++++++++++++++++++++
 drivers/clk/mvebu/clk-core.h                       |   19 ++
 drivers/clk/mvebu/clk-cpu.c                        |  154 ++++++++++
 drivers/clk/mvebu/clk-cpu.h                        |   19 ++
 drivers/clk/mvebu/clk.c                            |   36 +++
 drivers/clocksource/time-armada-370-xp.c           |   11 +-
 17 files changed, 690 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
 create mode 100644 drivers/clk/mvebu/Makefile
 create mode 100644 drivers/clk/mvebu/clk-core.c
 create mode 100644 drivers/clk/mvebu/clk-core.h
 create mode 100644 drivers/clk/mvebu/clk-cpu.c
 create mode 100644 drivers/clk/mvebu/clk-cpu.h
 create mode 100644 drivers/clk/mvebu/clk.c

1.7.9.5

Add Armada 370/XP specific clocks: core clocks and CPU clocks.

The CPU clocks are only for Armada XP for the SMP mode.

The core clocks are clocks which have their rate set during reset. The code was written with the other SoCs of the mvebu family in mind. Adding them should be pretty straight forward. For a new SoC, only 3 binding have to be added:
- one to provide the tclk frequency
- one to provde the pclk frequency
- and one to provide the ratio between the pclk and the children clocks

---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   40 +++
 .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   21 ++
 drivers/clk/Makefile                               |    1 +
 drivers/clk/mvebu/Makefile                         |    2 +
 drivers/clk/mvebu/clk-core.c                       |  318 ++++++++++++++++++++
 drivers/clk/mvebu/clk-core.h                       |   19 ++
 drivers/clk/mvebu/clk-cpu.c                        |  154 ++++++++++
 drivers/clk/mvebu/clk-cpu.h                        |   19 ++
 drivers/clk/mvebu/clk.c                            |   36 +++
 9 files changed, 610 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
 create mode 100644 drivers/clk/mvebu/Makefile
 create mode 100644 drivers/clk/mvebu/clk-core.c
 create mode 100644 drivers/clk/mvebu/clk-core.h
 create mode 100644 drivers/clk/mvebu/clk-cpu.c
 create mode 100644 drivers/clk/mvebu/clk-cpu.h
 create mode 100644 drivers/clk/mvebu/clk.c

new file mode 100644
index 0000000..eb54c62
@@ -0,0 +1,40 @@
+Device Tree Clock bindings for core clock of Marvell EBU platforms
+
+This is the binding for the "core" clock of the mvebu SoCs, the rate
+of this clocks are fixed during reset. Their value or ratio are taken
+from the Sample at Reset(SAR) register.
+
+Required properties:
+- compatible : shall be one of the following:
+	"marvell,armada-370-core-clockctrl" - core clock for Armada 370
+	"marvell,armada-xp-core-clockctrl" - core clock for Armada XP
+- reg : Address and length of the SAR register set
+- #clock-cells : should be set to 1.
+- clock-output-names: A list of clock output names that mvebu core
+  clocks provides.  The full list of all valid clock names, IDs and
+  description are below.
+	Name	    ID	    Description
+	tclk	    0	    Peripheral clock
+	pclk	    1	    CPU clock
+	nbclk	    2	    L2 clock
+	hclk	    3	    DRAM control clock
+	dramclk	    4	    DDR clock
+
+coreclk: mvebu-sar at d0018230 {
+	#clock-cells = <1>;
+	reg = <0xd0018230 0x08>;
+	compatible = "marvell,armada-370-core-clockctrl";
+	clock-output-names =
+		"tclk",	    /* 0 */
+		"pclk",	    /* 1 */
+		"nbclk",    /* 2 */
+		"hclk",	    /* 3 */
+		"dramclk";  /* 4 */
+};
+
+timer at d0020300 {
+	compatible = "marvell,armada-370-xp-timer";
+	reg = <0xd0020300 0x30>;
+	interrupts = <37>, <38>, <39>, <40>;
+	clocks = <&coreclk 0>;
+};

new file mode 100644
index 0000000..1fb5a64
@@ -0,0 +1,21 @@
+Device Tree Clock bindings for cpu clock of Marvell EBU platforms
+
+Required properties:
+- compatible : shall be one of the following:
+	"marvell,armada-xp-cpu-clockctrl" - cpu clocks for Armada XP
+- reg : Address and length of the clock complex register set
+- #clock-cells : should be set to 1.
+- clocks : shall be the input parent clock phandle for the clock.
+
+cpuclk: clock-complex at d0018700 {
+	#clock-cells = <1>;
+	compatible = "marvell,armada-xp-cpu-clockctrl";
+	reg = <0xd0018700 0xA0>;
+	clocks = <&coreclk 1>;
+}
+
+cpu at 0 {
+	compatible = "marvell,sheeva-v7";
+	reg = <0>;
+	clocks = <&cpuclk 0>;
+};

index 71a25b9..9c91d6c 100644
@@ -13,6 +13,7 @@ obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
 obj-$(CONFIG_ARCH_PRIMA2)	+= clk-prima2.o
+obj-$(CONFIG_ARCH_MVEBU)	+= mvebu/
 ifeq ($(CONFIG_COMMON_CLK), y)
 obj-$(CONFIG_ARCH_MMP)		+= mmp/
 endif

new file mode 100644
index 0000000..de94a87
@@ -0,0 +1,2 @@
+obj-y += clk.o clk-core.o
+obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o

new file mode 100644
index 0000000..a04f80b
@@ -0,0 +1,19 @@
+/*
+ *  * Marvell EBU clock core handling defined at reset
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MVEBU_CLK_CORE_H
+#define __MVEBU_CLK_CORE_H
+
+void __init of_core_clk_setup(struct device_node *node);
+void __init mvebu_core_clocks_init(void);
+
+#endif

new file mode 100644
index 0000000..5d28356
@@ -0,0 +1,19 @@
+/*
+ * Marvell MVEBU CPU clock handling.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MVEBU_CLK_CPU_H
+#define __MVEBU_CLK_CPU_H
+
+void __init of_cpu_clk_setup(struct device_node *node);
+void __init mvebu_cpu_clocks_init(void);
+
+#endif

new file mode 100644
index 0000000..0864df7
@@ -0,0 +1,36 @@
+/*
+ * Marvell EBU SoC clock handling.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
+#include "clk-cpu.h"
+#include "clk-core.h"
+
+static const __initconst struct of_device_id clk_match[] = {
+#ifdef CONFIG_MVEBU_CLK_CPU
+	{
+		.compatible = "marvell,armada-xp-cpu-clockctrl",
+		.data = of_cpu_clk_setup,
+	},
+#endif
+	{
+		/* sentinel */
+	}
+};
+
+void __init mvebu_clocks_init(void)
+{
+	mvebu_core_clocks_init();
+	of_clk_init(clk_match);
+}

1.7.9.5

---
 arch/arm/boot/dts/armada-370.dtsi   |   12 +++++++++
 arch/arm/boot/dts/armada-xp.dtsi    |   48 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-mvebu/Kconfig         |    5 ++++
 arch/arm/mach-mvebu/armada-370-xp.c |    8 +++++-
 arch/arm/mach-mvebu/common.h        |    1 +
 5 files changed, 73 insertions(+), 1 deletion(-)

index 2069151..ac495b4 100644
@@ -75,5 +75,17 @@
 			#interrupts-cells = <2>;
 			interrupts = <91>;
 		};
+		coreclk: mvebu-sar at d0018230 {
+			#clock-cells = <1>;
+			reg = <0xd0018230 0x08>;
+			compatible = "marvell,armada-370-core-clockctrl";
+			clock-output-names =
+				"tclk",	    /* 0 */
+				"pclk",	    /* 1 */
+				"nbclk",    /* 2 */
+				"hclk",	    /* 3 */
+				"dramclk";  /* 4 */
+		};
+
 	};
 };

index 416d46e..17d246b 100644
@@ -9,11 +9,16 @@ config ARCH_MVEBU
 	select PINCTRL
 	select PLAT_ORION
 	select SPARSE_IRQ
+	select CLKDEV_LOOKUP
+	select MVEBU_CLK_CPU
 
 if ARCH_MVEBU
 
 menu "Marvell SOC with device tree"
 
+config MVEBU_CLK_CPU
+	   bool
+
 config MACH_ARMADA_370_XP
 	bool
 	select ARMADA_370_XP_TIMER

index 49d7915..2af6ce5 100644
@@ -37,8 +37,14 @@ void __init armada_370_xp_map_io(void)
 	iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
 }
 
+void __init armada_370_xp_timer_and_clk_init(void)
+{
+	mvebu_clocks_init();
+	armada_370_xp_timer_init();
+}
+
 struct sys_timer armada_370_xp_timer = {
-	.init		= armada_370_xp_timer_init,
+	.init		= armada_370_xp_timer_and_clk_init,
 };
 
 static void __init armada_370_xp_dt_init(void)

index 02f89ea..281fab3 100644
@@ -16,6 +16,7 @@
 #define __ARCH_MVEBU_COMMON_H
 
 void mvebu_restart(char mode, const char *cmd);
+void mvebu_clocks_init(void);
 
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);

1.7.9.5

---
 arch/arm/boot/dts/armada-370-db.dts      |    4 ----
 arch/arm/boot/dts/armada-370-xp.dtsi     |    1 +
 drivers/clocksource/time-armada-370-xp.c |   11 ++++++-----
 3 files changed, 7 insertions(+), 9 deletions(-)

index fffd5c2..4a31b03 100644
@@ -34,9 +34,5 @@
 			clock-frequency = <200000000>;
 			status = "okay";
 		};
-		timer at d0020300 {
-			clock-frequency = <600000000>;
-			status = "okay";
-		};
 	};
 };

index 16cc82c..94b4b9e 100644
@@ -62,6 +62,7 @@
 			       compatible = "marvell,armada-370-xp-timer";
 			       reg = <0xd0020300 0x30>;
 			       interrupts = <37>, <38>, <39>, <40>;
+			       clocks = <&coreclk 2>;
 		};
 
 		addr-decoding at d0020000 {

index 4674f94..a4605fd 100644
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/kernel.h>
+#include <linux/clk.h>
 #include <linux/timer.h>
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>

@@ -167,7 +168,6 @@ void __init armada_370_xp_timer_init(void)
 	u32 u;
 	struct device_node *np;
 	unsigned int timer_clk;
-	int ret;
 	np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer");
 	timer_base = of_iomap(np, 0);
 	WARN_ON(!timer_base);

@@ -179,13 +179,14 @@ void __init armada_370_xp_timer_init(void)
 		       timer_base + TIMER_CTRL_OFF);
 		timer_clk = 25000000;
 	} else {
-		u32 clk = 0;
-		ret = of_property_read_u32(np, "clock-frequency", &clk);
-		WARN_ON(!clk || ret < 0);
+		unsigned long rate = 0;
+		struct clk *clk = of_clk_get(np, 0);
+		WARN_ON(IS_ERR(clk));
+		rate =  clk_get_rate(clk);
 		u = readl(timer_base + TIMER_CTRL_OFF);
 		writel(u & ~(TIMER0_25MHZ | TIMER1_25MHZ),
 		       timer_base + TIMER_CTRL_OFF);
-		timer_clk = clk / TIMER_DIVIDER;
+		timer_clk = rate / TIMER_DIVIDER;
 	}
 
 	/* We use timer 0 as clocksource, and timer 1 for

1.7.9.5

This is missing the patch description. Since none of it is code/hardware I'm familiar with, I can't really closely review whats being done. So its much more critical that the patch have a clear description of what its doing.

thanks
-john

Quoting Gregory CLEMENT (2012-10-30 11:23:30)

Hi Gregory,

After much delay:

Regards,
Mike