ARM: SPEAr: DT updates

Reviewed-by Vipin Kumar <[email protected]>

---
 .../bindings/pinctrl/pinctrl_spear_spics.txt       |  50 +++++
 drivers/pinctrl/spear/Makefile                     |   4 +-
 drivers/pinctrl/spear/pinctrl-spics.c              | 217 +++++++++++++++++++++
 3 files changed, 269 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl_spear_spics.txt
 create mode 100644 drivers/pinctrl/spear/pinctrl-spics.c

Documentation/devicetree/bindings/pinctrl/pinctrl_spear_spics.txt new file +50 -0

new file mode 100644
index 0000000..1c81280
@@ -0,0 +1,50 @@
+=== ST Microelectronics SPEAr SPI CS Driver ===
+
+SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
+Cell spi controller through its system registers, which otherwise remains under
+PL022 control. If chipselect remain under PL022 control then they would be
+released as soon as transfer is over and TxFIFO becomes empty. This is not
+desired by some of the device protocols above spi which expect (multiple)
+transfers without releasing their chipselects.
+
+Chipselects can be controlled by software by turning them as GPIOs. SPEAr
+provides another interface through system registers through which software can
+directly control each PL022 chipselect. Hence, it is natural for SPEAr to export
+the control of this interface as gpio.
+
+Required properties:
+
+  * compatible: should be defined as "st,spear-pinctrl-spics"
+  * reg: mentioning address range of spics controller
+  * st-spics,peripcfg-reg: peripheral configuration register offset
+  * st-spics,sw-enable-bit: bit offset to enable sw control
+  * st-spics,cs-value-bit: bit offset to drive chipselect low or high
+  * st-spics,cs-enable-mask: chip select number bit mask
+  * st-spics,cs-enable-shift: chip select number program offset
+  * gpio-controller: Marks the device node as gpio controller
+  * #gpio-cells: should be 1 and will mention chip select number
+
+All the above bit offsets are within peripcfg register.
+
+Example:
+-------
+spics: spics at e0700000{
+        compatible = "st,spear-spics-gpio";
+        reg = <0xe0700000 0x1000>;
+        st-spics,peripcfg-reg = <0x3b0>;
+        st-spics,sw-enable-bit = <12>;
+        st-spics,cs-value-bit = <11>;
+        st-spics,cs-enable-mask = <3>;
+        st-spics,cs-enable-shift = <8>;
+        gpio-controller;
+        #gpio-cells = <2>;
+};
+
+
+spi0: spi at e0100000 {
+        status = "okay";
+        num-cs = <3>;
+        cs-gpios = <&gpio1 7 0>, <&spics 0>,
+                   <&spics 1>;
+	...
+}

drivers/pinctrl/spear/Makefile +2 -2

index b28a7ba..6caec55 100644
@@ -5,5 +5,5 @@ obj-$(CONFIG_PINCTRL_SPEAR3XX)	+= pinctrl-spear3xx.o
 obj-$(CONFIG_PINCTRL_SPEAR300)	+= pinctrl-spear300.o
 obj-$(CONFIG_PINCTRL_SPEAR310)	+= pinctrl-spear310.o
 obj-$(CONFIG_PINCTRL_SPEAR320)	+= pinctrl-spear320.o
-obj-$(CONFIG_PINCTRL_SPEAR1310)	+= pinctrl-spear1310.o
-obj-$(CONFIG_PINCTRL_SPEAR1340)	+= pinctrl-spear1340.o
+obj-$(CONFIG_PINCTRL_SPEAR1310)	+= pinctrl-spear1310.o pinctrl-spics.o
+obj-$(CONFIG_PINCTRL_SPEAR1340)	+= pinctrl-spear1340.o pinctrl-spics.o

drivers/pinctrl/spear/pinctrl-spics.c new file +217 -0

217 lines not on this page · raw message

Signature · 1 line

1.7.12.rc2.18.g61b472e

Arnd Bergmann

maintainer

2012-11-12 15:03 UTC #2 lore raw

PATCH 1/14 pinctrl: SPEAr: add spi chipselect control driver

Quoted 6 lines · Viresh Kumar

From: Shiraz Hashim <[email protected]>
SPEAr platform provides a provision to control chipselects of ARM PL022 Prime Cell spi controller through its system registers, which otherwise remains under PL022 control which some protocols do not want.

Quoted 8 lines

This commit intends to provide the spi chipselect control in software over gpiolib interface. Since it is tied to pinctrl, we place it under 'drivers/pinctrl/spear/' directory.
spi chip drivers can use the exported gpiolib interface to define their chipselect through DT or platform data.
Cc Linus Walleij <[email protected]>

The driver looks ok to me, but I'll wait for Linus to take a look first and give his ack.

Arnd

Linus Walleij

2012-11-15 14:17 UTC #3 lore raw

PATCH 1/14 pinctrl: SPEAr: add spi chipselect control driver

Quoted 10 lines · Viresh Kumar

From: Shiraz Hashim <[email protected]>
SPEAr platform provides a provision to control chipselects of ARM PL022 Prime Cell spi controller through its system registers, which otherwise remains under PL022 control which some protocols do not want.
This commit intends to provide the spi chipselect control in software over gpiolib interface. Since it is tied to pinctrl, we place it under 'drivers/pinctrl/spear/' directory.

Quoted 7 lines

spi chip drivers can use the exported gpiolib interface to define their chipselect through DT or platform data.
Cc Linus Walleij <[email protected]>
Signed-off-by Shiraz Hashim <[email protected]>
Reviewed-by Vipin Kumar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>

This sure looks good, sorry for the delay.

Just one question: since this driver is not using any pinctrl interfaces, why is it under drivers/pinctrl/*?

Shouldn't it be under drivers/gpio from a technical point of view?

I think I'd accept it under drivers/pinctrl/spear/* if you just want this to keep everything SPEAr-related in one place though, so enlighten me.

Yours,
Linus Walleij

Viresh Kumar

author

2012-11-15 14:19 UTC #4 lore raw

PATCH 1/14 pinctrl: SPEAr: add spi chipselect control driver

Quoted 25 lines · Linus Walleij

Quoted 10 lines · Viresh Kumar
From: Shiraz Hashim <[email protected]>
SPEAr platform provides a provision to control chipselects of ARM PL022 Prime Cell spi controller through its system registers, which otherwise remains under PL022 control which some protocols do not want.
This commit intends to provide the spi chipselect control in software over gpiolib interface. Since it is tied to pinctrl, we place it under 'drivers/pinctrl/spear/' directory.
Quoted 7 lines
spi chip drivers can use the exported gpiolib interface to define their chipselect through DT or platform data.
Cc Linus Walleij <[email protected]>
Signed-off-by Shiraz Hashim <[email protected]>
Reviewed-by Vipin Kumar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
This sure looks good, sorry for the delay.
Just one question: since this driver is not using any pinctrl interfaces, why is it under drivers/pinctrl/*?

Quoted 6 lines

Shouldn't it be under drivers/gpio from a technical point of view?
I think I'd accept it under drivers/pinctrl/spear/* if you just want this to keep everything SPEAr-related in one place though, so enlighten me.

That's because they are controlling few pads. They are not actually gpio's but just pads that we are controlling.

That's why we thought they are better in this place.

--
viresh

Linus Walleij

2012-11-15 19:09 UTC #5 lore raw

PATCH 1/14 pinctrl: SPEAr: add spi chipselect control driver

Quoted 8 lines · Viresh Kumar

Quoted 6 lines · Linus Walleij
Just one question: since this driver is not using any pinctrl interfaces, why is it under drivers/pinctrl/*?
Shouldn't it be under drivers/gpio from a technical point of view?

Quoted 8 lines

Quoted 3 lines
I think I'd accept it under drivers/pinctrl/spear/* if you just want this to keep everything SPEAr-related in one place though, so enlighten me.
That's because they are controlling few pads. They are not actually gpio's but just pads that we are controlling.
That's why we thought they are better in this place.

The grouping of drivers in the kernel is about what in-kernel subsystem interface they're using, not how their electronics work...

Since this driver is only using the GPIO API it should be in drivers/gpio/gpio-*.c.

Many, many drivers in drivers/gpio* are controlling pads too, so it will be in good company ;-)

Yours,
Linus Walleij

Viresh Kumar

author

2012-11-16 05:15 UTC #6 lore raw

PATCH 1/16 gpio: SPEAr: add spi chipselect control driver

From: Shiraz Hashim <[email protected]>

This commit intends to provide the spi chipselect control in software over gpiolib interface. spi chip drivers can use the exported gpiolib interface to define their chipselect through DT or platform data.

Cc Grant Likely <[email protected]>

Reviewed-by Vipin Kumar <[email protected]>

---

Hi Grant,

This patch was earlier sent as part of drivers/pinctrl/spear directory and after some discussion over mainline it is moved to gpio now. It is already reviewed by Linus and Arnd, though they haven't given their Reviewed-by's.

 .../devicetree/bindings/gpio/spear_spics.txt       |  50 +++++
 arch/arm/plat-spear/Kconfig                        |   1 +
 drivers/gpio/Kconfig                               |   7 +
 drivers/gpio/Makefile                              |   1 +
 drivers/gpio/gpio-spear-spics.c                    | 217 +++++++++++++++++++++
 5 files changed, 276 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpio/spear_spics.txt
 create mode 100644 drivers/gpio/gpio-spear-spics.c

Documentation/devicetree/bindings/gpio/spear_spics.txt new file +50 -0

new file mode 100644
index 0000000..96c37eb
@@ -0,0 +1,50 @@
+=== ST Microelectronics SPEAr SPI CS Driver ===
+
+SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
+Cell spi controller through its system registers, which otherwise remains under
+PL022 control. If chipselect remain under PL022 control then they would be
+released as soon as transfer is over and TxFIFO becomes empty. This is not
+desired by some of the device protocols above spi which expect (multiple)
+transfers without releasing their chipselects.
+
+Chipselects can be controlled by software by turning them as GPIOs. SPEAr
+provides another interface through system registers through which software can
+directly control each PL022 chipselect. Hence, it is natural for SPEAr to export
+the control of this interface as gpio.
+
+Required properties:
+
+  * compatible: should be defined as "st,spear-spics-gpio"
+  * reg: mentioning address range of spics controller
+  * st-spics,peripcfg-reg: peripheral configuration register offset
+  * st-spics,sw-enable-bit: bit offset to enable sw control
+  * st-spics,cs-value-bit: bit offset to drive chipselect low or high
+  * st-spics,cs-enable-mask: chip select number bit mask
+  * st-spics,cs-enable-shift: chip select number program offset
+  * gpio-controller: Marks the device node as gpio controller
+  * #gpio-cells: should be 1 and will mention chip select number
+
+All the above bit offsets are within peripcfg register.
+
+Example:
+-------
+spics: spics at e0700000{
+        compatible = "st,spear-spics-gpio";
+        reg = <0xe0700000 0x1000>;
+        st-spics,peripcfg-reg = <0x3b0>;
+        st-spics,sw-enable-bit = <12>;
+        st-spics,cs-value-bit = <11>;
+        st-spics,cs-enable-mask = <3>;
+        st-spics,cs-enable-shift = <8>;
+        gpio-controller;
+        #gpio-cells = <2>;
+};
+
+
+spi0: spi at e0100000 {
+        status = "okay";
+        num-cs = <3>;
+        cs-gpios = <&gpio1 7 0>, <&spics 0>,
+                   <&spics 1>;
+	...
+}

arch/arm/plat-spear/Kconfig +1 -0

index f8db7b2..87dbd81 100644
@@ -12,6 +12,7 @@ config ARCH_SPEAR13XX
 	bool "ST SPEAr13xx with Device Tree"
 	select ARM_GIC
 	select CPU_V7
+	select GPIO_SPEAR_SPICS
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
 	select PINCTRL

drivers/gpio/Kconfig +7 -0

index d055cee..b846f60 100644
@@ -181,6 +181,13 @@ config GPIO_PXA
 	help
 	  Say yes here to support the PXA GPIO device
 
+config GPIO_SPEAR_SPICS
+	bool "ST SPEAr13xx SPI Chip Select as GPIO support"
+	depends on PLAT_SPEAR
+	select GENERIC_IRQ_CHIP
+	help
+	  Say yes here to support ST SPEAr SPI Chip Select as GPIO device
+
 config GPIO_STA2X11
 	bool "STA2x11/ConneXt GPIO support"
 	depends on MFD_STA2X11

drivers/gpio/Makefile +1 -0

index 9aeed67..2699355 100644
@@ -57,6 +57,7 @@ obj-$(CONFIG_PLAT_SAMSUNG)	+= gpio-samsung.o
 obj-$(CONFIG_ARCH_SA1100)	+= gpio-sa1100.o
 obj-$(CONFIG_GPIO_SCH)		+= gpio-sch.o
 obj-$(CONFIG_GPIO_SODAVILLE)	+= gpio-sodaville.o
+obj-$(CONFIG_GPIO_SPEAR_SPICS)	+= gpio-spear-spics.o
 obj-$(CONFIG_GPIO_STA2X11)	+= gpio-sta2x11.o
 obj-$(CONFIG_GPIO_STMPE)	+= gpio-stmpe.o
 obj-$(CONFIG_GPIO_STP_XWAY)	+= gpio-stp-xway.o

drivers/gpio/gpio-spear-spics.c new file +217 -0

217 lines not on this page · raw message

Signature · 1 line

1.7.12.rc2.18.g61b472e

Arnd Bergmann

maintainer

2012-11-16 08:19 UTC #7 lore raw

PATCH 1/16 gpio: SPEAr: add spi chipselect control driver

Quoted 6 lines · Viresh Kumar

From: Shiraz Hashim <[email protected]>
SPEAr platform provides a provision to control chipselects of ARM PL022 Prime Cell spi controller through its system registers, which otherwise remains under PL022 control which some protocols do not want.

Quoted 8 lines

This commit intends to provide the spi chipselect control in software over gpiolib interface. spi chip drivers can use the exported gpiolib interface to define their chipselect through DT or platform data.
Cc Grant Likely <[email protected]>
Signed-off-by Shiraz Hashim <[email protected]>
Reviewed-by Vipin Kumar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>

Acked-by Arnd Bergmann <[email protected]>

Viresh Kumar

author

2012-11-16 08:19 UTC #8 lore raw

PATCH 1/16 gpio: SPEAr: add spi chipselect control driver

Quoted 11 lines · Arnd Bergmann

Quoted 10 lines · Viresh Kumar
From: Shiraz Hashim <[email protected]>
SPEAr platform provides a provision to control chipselects of ARM PL022 Prime Cell spi controller through its system registers, which otherwise remains under PL022 control which some protocols do not want.
This commit intends to provide the spi chipselect control in software over gpiolib interface. spi chip drivers can use the exported gpiolib interface to define their chipselect through DT or platform data.

Quoted 6 lines

Quoted 4 lines
Cc Grant Likely <[email protected]>
Signed-off-by Shiraz Hashim <[email protected]>
Reviewed-by Vipin Kumar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
Acked-by Arnd Bergmann <[email protected]>

You can apply this series now :)

Linus Walleij

Applied

2012-11-17 23:02 UTC #9 lore raw

PATCH 1/16 gpio: SPEAr: add spi chipselect control driver

Quoted 14 lines · Viresh Kumar

From: Shiraz Hashim <[email protected]>
SPEAr platform provides a provision to control chipselects of ARM PL022 Prime Cell spi controller through its system registers, which otherwise remains under PL022 control which some protocols do not want.
This commit intends to provide the spi chipselect control in software over gpiolib interface. spi chip drivers can use the exported gpiolib interface to define their chipselect through DT or platform data.
Cc Grant Likely <[email protected]>
Signed-off-by Shiraz Hashim <[email protected]>
Reviewed-by Vipin Kumar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>

Quoted 7 lines

---
Hi Grant,
This patch was earlier sent as part of drivers/pinctrl/spear directory and after some discussion over mainline it is moved to gpio now. It is already reviewed by Linus and Arnd, though they haven't given their Reviewed-by's.

I've applied it to my gpio tree with Arnd's ACK, thanks!

Yours,
Linus Walleij

Viresh Kumar

author

2012-11-11 04:39 UTC #10 lore raw

PATCH 2/14 ARM: SPEAr13xx: DT: Add spics gpio controller nodes

From: Shiraz Hashim <[email protected]>

This patch adds spics controller nodes in device tree for various SPEAr13xx SoCs.

Cc Linus Walleij <[email protected]>

Reviewed-by Vipin Kumar <[email protected]>

---
 arch/arm/boot/dts/spear1310.dtsi | 12 ++++++++++++
 arch/arm/boot/dts/spear1340.dtsi | 14 ++++++++++++++
 2 files changed, 26 insertions(+)

arch/arm/boot/dts/spear1310.dtsi +12 -0

index 419ea74..d5661ee 100644
@@ -17,6 +17,18 @@
 	compatible = "st,spear1310";
 
 	ahb {
+		spics: spics at e0700000{
+			compatible = "st,spear-spics-gpio";
+			reg = <0xe0700000 0x1000>;
+			st-spics,peripcfg-reg = <0x3b0>;
+			st-spics,sw-enable-bit = <12>;
+			st-spics,cs-value-bit = <11>;
+			st-spics,cs-enable-mask = <3>;
+			st-spics,cs-enable-shift = <8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
 		ahci at b1000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1000000 0x10000>;

arch/arm/boot/dts/spear1340.dtsi +14 -0

index d71fe2a..1604425 100644
@@ -17,6 +17,20 @@
 	compatible = "st,spear1340";
 
 	ahb {
+
+		spics: spics at e0700000{
+			compatible = "st,spear-spics-gpio";
+			reg = <0xe0700000 0x1000>;
+			st-spics,peripcfg-reg = <0x42c>;
+			st-spics,sw-enable-bit = <21>;
+			st-spics,cs-value-bit = <20>;
+			st-spics,cs-enable-mask = <3>;
+			st-spics,cs-enable-shift = <18>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
 		ahci at b1000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1000000 0x10000>;

Signature · 1 line

1.7.12.rc2.18.g61b472e

Linus Walleij

2012-11-13 14:08 UTC #11 lore raw

PATCH 2/14 ARM: SPEAr13xx: DT: Add spics gpio controller nodes

Quoted 5 lines · Viresh Kumar

From: Shiraz Hashim <[email protected]>
SPEAr platform provides a provision to control chipselects of ARM PL022 Prime Cell spi controller through its system registers, which otherwise remains under PL022 control which some protocols do not want.

So I guess this platform us utilizing the cs_control field of the PL022 platform data to do the actual magic, right?

Quoted 7 lines

This patch adds spics controller nodes in device tree for various SPEAr13xx SoCs.
Cc Linus Walleij <[email protected]>
Signed-off-by Shiraz Hashim <[email protected]>
Reviewed-by Vipin Kumar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>

(...)

arch/arm/boot/dts/spear1310.dtsi line 31

Quoted 13 lines

        ahb {

arch/arm/boot/dts/spear1310.dtsi +12 -0

+               spics: spics at e0700000{
+                       compatible = "st,spear-spics-gpio";
+                       reg = <0xe0700000 0x1000>;
+                       st-spics,peripcfg-reg = <0x3b0>;
+                       st-spics,sw-enable-bit = <12>;
+                       st-spics,cs-value-bit = <11>;
+                       st-spics,cs-enable-mask = <3>;
+                       st-spics,cs-enable-shift = <8>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+

Are these bindings documented?

Apart from that remark:

Acked-by Linus Walleij <[email protected]>

Yours,
Linus Walleij

Viresh Kumar

author

2012-11-13 14:34 UTC #12 lore raw

PATCH 2/14 ARM: SPEAr13xx: DT: Add spics gpio controller nodes

Quoted 2 lines · Linus Walleij

On Sun, Nov 11, 2012 at 5:39 AM, Viresh Kumar <[email protected]>

Quoted 4 lines · wrote:

Quoted 4 lines
From: Shiraz Hashim <[email protected]>
SPEAr platform provides a provision to control chipselects of ARM PL022

Prime

Quoted 1 line

Quoted 1 line
Cell spi controller through its system registers, which otherwise

remains under

Quoted 4 lines

Quoted 1 line
PL022 control which some protocols do not want.
So I guess this platform us utilizing the cs_control field of the PL022 platform data to do the actual magic, right?

Correct.

Quoted 1 line

Quoted 1 line
This patch adds spics controller nodes in device tree for various

SPEAr13xx

Quoted 21 lines

Quoted 6 lines
SoCs.
Cc Linus Walleij <[email protected]>
Signed-off-by Shiraz Hashim <[email protected]>
Reviewed-by Vipin Kumar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
(...)
arch/arm/boot/dts/spear1310.dtsi line 31
Quoted 13 lines
        ahb {
arch/arm/boot/dts/spear1310.dtsi +12 -0
+               spics: spics at e0700000{
+                       compatible = "st,spear-spics-gpio";
+                       reg = <0xe0700000 0x1000>;
+                       st-spics,peripcfg-reg = <0x3b0>;
+                       st-spics,sw-enable-bit = <12>;
+                       st-spics,cs-value-bit = <11>;
+                       st-spics,cs-enable-mask = <3>;
+                       st-spics,cs-enable-shift = <8>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+

Quoted 1 line

Are these bindings documented?

The main patch waiting for ur comments is 1/14.

Quoted 5 lines

Apart from that remark:
Acked-by Linus Walleij <[email protected]>
Yours,
Linus Walleij

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121113/ccfa29d1/attachment-0001.html>

Linus Walleij

2012-11-15 14:06 UTC #13 lore raw

PATCH 2/14 ARM: SPEAr13xx: DT: Add spics gpio controller nodes

Quoted 18 lines · Viresh Kumar

Quoted 17 lines · Linus Walleij

Quoted 13 lines · Viresh Kumar

        ahb {

arch/arm/boot/dts/spear1310.dtsi +12 -0

+               spics: spics at e0700000{
+                       compatible = "st,spear-spics-gpio";
+                       reg = <0xe0700000 0x1000>;
+                       st-spics,peripcfg-reg = <0x3b0>;
+                       st-spics,sw-enable-bit = <12>;
+                       st-spics,cs-value-bit = <11>;
+                       st-spics,cs-enable-mask = <3>;
+                       st-spics,cs-enable-shift = <8>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+

Quoted 3 lines

Quoted 1 line
Are these bindings documented?
The main patch waiting for ur comments is 1/14.

I seldom comment on individual DT bindings, I just want to know that they're there :-)

Yours,
Linus Walleij

Viresh Kumar

author

2012-11-15 14:08 UTC #14 lore raw

PATCH 2/14 ARM: SPEAr13xx: DT: Add spics gpio controller nodes

Quoted 14 lines · Linus Walleij

Quoted 14 lines

Quoted 13 lines

        ahb {

arch/arm/boot/dts/spear1310.dtsi +12 -0

+               spics: spics at e0700000{
+                       compatible = "st,spear-spics-gpio";
+                       reg = <0xe0700000 0x1000>;
+                       st-spics,peripcfg-reg = <0x3b0>;
+                       st-spics,sw-enable-bit = <12>;
+                       st-spics,cs-value-bit = <11>;
+                       st-spics,cs-enable-mask = <3>;
+                       st-spics,cs-enable-shift = <8>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+

Quoted 6 lines

Quoted 3 lines
Quoted 1 line
Are these bindings documented?
The main patch waiting for ur comments is 1/14.
I seldom comment on individual DT bindings, I just want to know that they're there :-)

Its not that simple. You are required to Ack it, as we have added it in drivers/pinctrl/spear because we are controlling pins here :)

--
viresh

Linus Walleij

2012-11-15 17:25 UTC #15 lore raw

PATCH 2/14 ARM: SPEAr13xx: DT: Add spics gpio controller nodes

Quoted 7 lines · Viresh Kumar

Quoted 2 lines · Linus Walleij
I seldom comment on individual DT bindings, I just want to know that they're there :-)
Its not that simple. You are required to Ack it, as we have added it in drivers/pinctrl/spear because we are controlling pins here :)

Yeah I saw, I've commented on it now..

Yours,
Linus Walleij

Viresh Kumar

author

2012-11-11 04:39 UTC #16 lore raw

PATCH 3/14 ARM: SPEAr: DT: Update pinctrl list

From: Vipul Kumar Samar <[email protected]>

This patch updates pinctrl configuration for SPEAr SoC's.

Signed-off-by Vipul Kumar Samar <[email protected]>

---
 arch/arm/boot/dts/spear1310-evb.dts | 23 +++++++++++++++++------
 arch/arm/boot/dts/spear1340-evb.dts | 35 +++++++++++++++++++++--------------
 arch/arm/boot/dts/spear320-evb.dts  |  6 +-----
 3 files changed, 39 insertions(+), 25 deletions(-)

arch/arm/boot/dts/spear1310-evb.dts +17 -6

index dd4358b..08697ac 100644
@@ -30,10 +30,14 @@
 			pinctrl-0 = <&state_default>;
 
 			state_default: pinmux {
-				i2c0-pmx {
+				i2c0 {
 					st,pins = "i2c0_grp";
 					st,function = "i2c0";
 				};
+				i2s0 {
+					st,pins = "i2s0_grp";
+					st,function = "i2s0";
+				};
 				i2s1 {
 					st,pins = "i2s1_grp";
 					st,function = "i2s1";

@@ -42,6 +46,10 @@
 					st,pins = "arm_gpio_grp";
 					st,function = "arm_gpio";
 				};
+				clcd {
+					st,pins = "clcd_grp" , "clcd_high_res";
+					st,function = "clcd";
+				};
 				eth {
 					st,pins = "gmii_grp";
 					st,function = "gmii";

@@ -74,11 +82,6 @@
 					st,pins = "i2c_1_2_grp";
 					st,function = "i2c_1_2";
 				};
-				pci {
-					st,pins = "pcie0_grp","pcie1_grp",
-						"pcie2_grp";
-					st,function = "pci";
-				};
 				smii {
 					st,pins = "smii_0_1_2_grp";
 					st,function = "smii_0_1_2";

@@ -88,6 +91,14 @@
 						"nand_16bit_grp";
 					st,function = "nand";
 				};
+				sata {
+					st,pins = "sata0_grp";
+					st,function = "sata";
+				};
+				pcie {
+					st,pins = "pcie1_grp", "pcie2_grp";
+					st,function = "pci_express";
+				};
 			};
 		};

arch/arm/boot/dts/spear1340-evb.dts +21 ~~-14~~

index c9a54e0..8e35c14 100644
@@ -38,20 +38,15 @@
 					st,pins = "fsmc_8bit_grp";
 					st,function = "fsmc";
 				};
-				kbd {
-					st,pins = "keyboard_row_col_grp",
-						"keyboard_col5_grp";
-					st,function = "keyboard";
-				};
 				uart0 {
-					st,pins = "uart0_grp", "uart0_enh_grp";
+					st,pins = "uart0_grp";
 					st,function = "uart0";
 				};
-				i2c0-pmx {
+				i2c0 {
 					st,pins = "i2c0_grp";
 					st,function = "i2c0";
 				};
-				i2c1-pmx {
+				i2c1 {
 					st,pins = "i2c1_grp";
 					st,function = "i2c1";
 				};

@@ -64,14 +59,9 @@
 					st,function = "spdif_out";
 				};
 				ssp0 {
-					st,pins = "ssp0_grp", "ssp0_cs1_grp",
-						"ssp0_cs3_grp";
+					st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp";
 					st,function = "ssp0";
 				};
-				pwm {
-					st,pins = "pwm2_grp", "pwm3_grp";
-					st,function = "pwm";
-				};
 				smi-pmx {
 					st,pins = "smi_grp";
 					st,function = "smi";

@@ -84,6 +74,18 @@
 					st,pins = "gmii_grp", "rgmii_grp";
 					st,function = "gmac";
 				};
+				cam0 {
+					st,pins = "cam0_grp";
+					st,function = "cam0";
+				};
+				cam1 {
+					st,pins = "cam1_grp";
+					st,function = "cam1";
+				};
+				cam2 {
+					st,pins = "cam2_grp";
+					st,function = "cam2";
+				};
 				cam3 {
 					st,pins = "cam3_grp";
 					st,function = "cam3";

@@ -108,6 +110,11 @@
 					st,pins = "sata_grp";
 					st,function = "sata";
 				};
+				pcie {
+					st,pins = "pcie_grp";
+					st,function = "pcie";
+				};
+
 			};
 		};

arch/arm/boot/dts/spear320-evb.dts +1 -5

index 082328b..3f87cd0 100644
@@ -76,13 +76,9 @@
 					st,function = "mii2";
 				};
 				pwm0_1 {
-					st,pins = "pwm0_1_pin_14_15_grp";
+					st,pins = "pwm0_1_pin_37_38_grp";
 					st,function = "pwm0_1";
 				};
-				pwm2 {
-					st,pins = "pwm2_pin_13_grp";
-					st,function = "pwm2";
-				};
 			};
 		};

Signature · 1 line

1.7.12.rc2.18.g61b472e

Viresh Kumar

author

2012-11-11 04:39 UTC #17 lore raw

PATCH 4/14 ARM: SPEAr: DT: Update partition info for MTD devices

From: Vipin Kumar <[email protected]>

This patch enhances partition information of MTD devices like fsmc-nand and spear-smi.

Signed-off-by Vipin Kumar <[email protected]>

Signed-off-by Vipul Kumar Samar <[email protected]>

---
 arch/arm/boot/dts/spear1310-evb.dts | 43 ++++++++++++++++++++++++++++++++-----
 arch/arm/boot/dts/spear1340-evb.dts | 43 ++++++++++++++++++++++++++++++++-----
 arch/arm/boot/dts/spear300-evb.dts  | 18 +++++++++++-----
 arch/arm/boot/dts/spear310-evb.dts  | 18 +++++++++++-----
 arch/arm/boot/dts/spear320-evb.dts  | 18 +++++++++++-----
 arch/arm/boot/dts/spear600-evb.dts  | 18 +++++++++++-----
 6 files changed, 128 insertions(+), 30 deletions(-)

arch/arm/boot/dts/spear1310-evb.dts +38 -5

index 08697ac..2e2887b 100644
@@ -120,6 +120,31 @@
 
 		fsmc: flash at b0000000 {
 			status = "okay";
+
+			partition at 0 {
+				label = "xloader";
+				reg = <0x0 0x80000>;
+			};
+			partition at 80000 {
+				label = "u-boot";
+				reg = <0x80000 0x140000>;
+			};
+			partition at 1C0000 {
+				label = "environment";
+				reg = <0x1C0000 0x40000>;
+			};
+			partition at 200000 {
+				label = "dtb";
+				reg = <0x200000 0x40000>;
+			};
+			partition at 240000 {
+				label = "linux";
+				reg = <0x240000 0xC00000>;
+			};
+			partition at E40000 {
+				label = "rootfs";
+				reg = <0xE40000 0x0>;
+			};
 		};
 
 		gmac0: eth at e2000000 {

@@ -146,15 +171,23 @@
 				};
 				partition at 10000 {
 					label = "u-boot";
-					reg = <0x10000 0x40000>;
+					reg = <0x10000 0x50000>;
+				};
+				partition at 60000 {
+					label = "environment";
+					reg = <0x60000 0x10000>;
+				};
+				partition at 70000 {
+					label = "dtb";
+					reg = <0x70000 0x10000>;
 				};
-				partition at 50000 {
+				partition at 80000 {
 					label = "linux";
-					reg = <0x50000 0x2c0000>;
+					reg = <0x80000 0x310000>;
 				};
-				partition at 310000 {
+				partition at 390000 {
 					label = "rootfs";
-					reg = <0x310000 0x4f0000>;
+					reg = <0x390000 0x0>;
 				};
 			};
 		};

arch/arm/boot/dts/spear1340-evb.dts +38 -5

59 lines not on this page · raw message

arch/arm/boot/dts/spear300-evb.dts +13 -5

index 1e7c7a8..b3265f6 100644
@@ -100,15 +100,23 @@
 				};
 				partition at 10000 {
 					label = "u-boot";
-					reg = <0x10000 0x40000>;
+					reg = <0x10000 0x50000>;
 				};
-				partition at 50000 {
+				partition at 60000 {
+					label = "environment";
+					reg = <0x60000 0x10000>;
+				};
+				partition at 70000 {
+					label = "dtb";
+					reg = <0x70000 0x10000>;
+				};
+				partition at 80000 {
 					label = "linux";
-					reg = <0x50000 0x2c0000>;
+					reg = <0x80000 0x310000>;
 				};
-				partition at 310000 {
+				partition at 390000 {
 					label = "rootfs";
-					reg = <0x310000 0x4f0000>;
+					reg = <0x390000 0x0>;
 				};
 			};
 		};

arch/arm/boot/dts/spear310-evb.dts +13 -5

index b00544e..b30fa0e 100644
@@ -114,15 +114,23 @@
 				};
 				partition at 10000 {
 					label = "u-boot";
-					reg = <0x10000 0x40000>;
+					reg = <0x10000 0x50000>;
 				};
-				partition at 50000 {
+				partition at 60000 {
+					label = "environment";
+					reg = <0x60000 0x10000>;
+				};
+				partition at 70000 {
+					label = "dtb";
+					reg = <0x70000 0x10000>;
+				};
+				partition at 80000 {
 					label = "linux";
-					reg = <0x50000 0x2c0000>;
+					reg = <0x80000 0x310000>;
 				};
-				partition at 310000 {
+				partition at 390000 {
 					label = "rootfs";
-					reg = <0x310000 0x4f0000>;
+					reg = <0x390000 0x0>;
 				};
 			};
 		};

arch/arm/boot/dts/spear320-evb.dts +13 -5

index 3f87cd0..a3061ad 100644
@@ -118,15 +118,23 @@
 				};
 				partition at 10000 {
 					label = "u-boot";
-					reg = <0x10000 0x40000>;
+					reg = <0x10000 0x50000>;
 				};
-				partition at 50000 {
+				partition at 60000 {
+					label = "environment";
+					reg = <0x60000 0x10000>;
+				};
+				partition at 70000 {
+					label = "dtb";
+					reg = <0x70000 0x10000>;
+				};
+				partition at 80000 {
 					label = "linux";
-					reg = <0x50000 0x2c0000>;
+					reg = <0x80000 0x310000>;
 				};
-				partition at 310000 {
+				partition at 390000 {
 					label = "rootfs";
-					reg = <0x310000 0x4f0000>;
+					reg = <0x390000 0x0>;
 				};
 			};
 		};

arch/arm/boot/dts/spear600-evb.dts +13 -5

index 1119c22..16e4de4 100644
@@ -49,15 +49,23 @@
 				};
 				partition at 10000 {
 					label = "u-boot";
-					reg = <0x10000 0x40000>;
+					reg = <0x10000 0x50000>;
 				};
-				partition at 50000 {
+				partition at 60000 {
+					label = "environment";
+					reg = <0x60000 0x10000>;
+				};
+				partition at 70000 {
+					label = "dtb";
+					reg = <0x70000 0x10000>;
+				};
+				partition at 80000 {
 					label = "linux";
-					reg = <0x50000 0x2c0000>;
+					reg = <0x80000 0x310000>;
 				};
-				partition at 310000 {
+				partition at 390000 {
 					label = "rootfs";
-					reg = <0x310000 0x4f0000>;
+					reg = <0x390000 0x0>;
 				};
 			};
 		};

Signature · 1 line

1.7.12.rc2.18.g61b472e

Viresh Kumar

author

2012-11-11 04:39 UTC #18 lore raw

PATCH 5/14 ARM: SPEAr: DT: Fix existing DT support

From: Vipul Kumar Samar <[email protected]>

This patch fixes existing DT support for all SPEAr SoC's. This includes:
- Removing few nodes from board files
- Updating DT data of few nodes
- Updating ranges of few busses
- Moving devices to correct parent bus

Signed-off-by Bhavna Yadav <[email protected]>

Signed-off-by Deepak Sikri <[email protected]>

Signed-off-by Rajeev Kumar <[email protected]>

Signed-off-by Vijay Kumar Mishra <[email protected]>

Signed-off-by Vipin Kumar <[email protected]>

Signed-off-by Vipul Kumar Samar <[email protected]>

---
 arch/arm/boot/dts/spear1310-evb.dts | 13 +++++--------
 arch/arm/boot/dts/spear1310.dtsi    | 14 +++++++-------
 arch/arm/boot/dts/spear1340-evb.dts |  9 +++++----
 arch/arm/boot/dts/spear1340.dtsi    |  1 +
 arch/arm/boot/dts/spear13xx.dtsi    | 33 ++++++++++++++++++++++-----------
 arch/arm/boot/dts/spear300.dtsi     |  2 +-
 arch/arm/boot/dts/spear320-evb.dts  |  5 +----
 arch/arm/boot/dts/spear320.dtsi     |  4 ++--
 arch/arm/boot/dts/spear3xx.dtsi     |  2 +-
 9 files changed, 45 insertions(+), 38 deletions(-)

arch/arm/boot/dts/spear1310-evb.dts +5 -8

index 2e2887b..79a1654 100644
@@ -192,10 +192,6 @@
 			};
 		};
 
-		spi0: spi at e0100000 {
-			status = "okay";
-		};
-
 		ehci at e4800000 {
 			status = "okay";
 		};

@@ -229,10 +225,6 @@
 			       status = "okay";
 			};
 
-			i2c1: i2c at 5cd00000 {
-			       status = "okay";
-			};
-
 			kbd at e0300000 {
 				linux,keymap = < 0x00000001
 						 0x00010002

@@ -317,6 +309,7 @@
 						 0x08080052 >;
 			       autorepeat;
 			       st,mode = <0>;
+			       suspended_rate = <2000000>;
 			       status = "okay";
 			};

@@ -328,6 +321,10 @@
 			       status = "okay";
 			};
 
+			spi0: spi at e0100000 {
+				status = "okay";
+			};
+
 			wdt at ec800620 {
 			       status = "okay";
 			};

arch/arm/boot/dts/spear1310.dtsi +7 -7

index d5661ee..1e18f31 100644
@@ -82,13 +82,6 @@
 			status = "disabled";
 		};
 
-		spi1: spi at 5d400000 {
-			compatible = "arm,pl022", "arm,primecell";
-			reg = <0x5d400000 0x1000>;
-			interrupts = <0 99 0x4>;
-			status = "disabled";
-		};
-
 		apb {
 			i2c1: i2c at 5cd00000 {
 				#address-cells = <1>;

@@ -153,6 +146,13 @@
 				status = "disabled";
 			};
 
+			spi1: spi at 5d400000 {
+				compatible = "arm,pl022", "arm,primecell";
+				reg = <0x5d400000 0x1000>;
+				interrupts = <0 99 0x4>;
+				status = "disabled";
+			};
+
 			serial at 5c800000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x5c800000 0x1000>;

arch/arm/boot/dts/spear1340-evb.dts +5 -4

index 8d6339d..4c5fa85 100644
@@ -200,10 +200,6 @@
 			};
 		};
 
-		spi0: spi at e0100000 {
-			status = "okay";
-		};
-
 		ehci at e4800000 {
 			status = "okay";
 		};

@@ -325,6 +321,7 @@
 						 0x08080052 >;
 			       autorepeat;
 			       st,mode = <0>;
+			       suspended_rate = <2000000>;
 			       status = "okay";
 			};

@@ -340,6 +337,10 @@
 			       status = "okay";
 			};
 
+			spi0: spi at e0100000 {
+				status = "okay";
+			};
+
 			wdt at ec800620 {
 			       status = "okay";
 			};

arch/arm/boot/dts/spear1340.dtsi +1 -0

index 1604425..1446f1b 100644
@@ -52,6 +52,7 @@
 				compatible = "snps,designware-i2c";
 				reg = <0xb4000000 0x1000>;
 				interrupts = <0 104 0x4>;
+				write-16bit;
 				status = "disabled";
 			};

arch/arm/boot/dts/spear13xx.dtsi +22 ~~-11~~

index f7b84ac..4d35144 100644
@@ -70,6 +70,8 @@
 		compatible = "simple-bus";
 		ranges = <0x50000000 0x50000000 0x10000000
 			  0xb0000000 0xb0000000 0x10000000
+			  0xd0000000 0xd0000000 0x02000000
+			  0xd8000000 0xd8000000 0x01000000
 			  0xe0000000 0xe0000000 0x10000000>;
 
 		sdhci at b3000000 {

@@ -81,7 +83,7 @@
 
 		cf at b2800000 {
 			compatible = "arasan,cf-spear1340";
-			reg = <0xb2800000 0x100>;
+			reg = <0xb2800000 0x1000>;
 			interrupts = <0 29 0x4>;
 			status = "disabled";
 		};

@@ -113,6 +115,7 @@
 				      0 23 0x4>;
 			st,ale-off = <0x20000>;
 			st,cle-off = <0x10000>;
+			st,mode = <2>;
 			status = "disabled";
 		};

@@ -134,17 +137,11 @@
 			status = "disabled";
 		};
 
-		spi0: spi at e0100000 {
-			compatible = "arm,pl022", "arm,primecell";
-			reg = <0xe0100000 0x1000>;
-			interrupts = <0 31 0x4>;
-			status = "disabled";
-		};
-
 		ehci at e4800000 {
 			compatible = "st,spear600-ehci", "usb-ehci";
 			reg = <0xe4800000 0x1000>;
 			interrupts = <0 64 0x4>;
+			usbh0_id = <0>;
 			status = "disabled";
 		};

@@ -152,6 +149,7 @@
 			compatible = "st,spear600-ehci", "usb-ehci";
 			reg = <0xe5800000 0x1000>;
 			interrupts = <0 66 0x4>;
+			usbh1_id = <1>;
 			status = "disabled";
 		};

@@ -159,6 +157,7 @@
 			compatible = "st,spear600-ohci", "usb-ohci";
 			reg = <0xe4000000 0x1000>;
 			interrupts = <0 65 0x4>;
+			usbh0_id = <0>;
 			status = "disabled";
 		};

@@ -166,6 +165,7 @@
 			compatible = "st,spear600-ohci", "usb-ohci";
 			reg = <0xe5000000 0x1000>;
 			interrupts = <0 67 0x4>;
+			usbh1_id = <1>;
 			status = "disabled";
 		};

@@ -175,6 +175,8 @@
 			compatible = "simple-bus";
 			ranges = <0x50000000 0x50000000 0x10000000
 				  0xb0000000 0xb0000000 0x10000000
+				  0xd0000000 0xd0000000 0x02000000
+				  0xd8000000 0xd8000000 0x01000000
 				  0xe0000000 0xe0000000 0x10000000>;
 
 			gpio0: gpio at e0600000 {

@@ -215,8 +217,15 @@
 				status = "disabled";
 			};
 
+			spi0: spi at e0100000 {
+				compatible = "arm,pl022", "arm,primecell";
+				reg = <0xe0100000 0x1000>;
+				interrupts = <0 31 0x4>;
+				status = "disabled";
+			};
+
 			rtc at e0580000 {
-				compatible = "st,spear-rtc";
+				compatible = "st,spear600-rtc";
 				reg = <0xe0580000 0x1000>;
 				interrupts = <0 36 0x4>;
 				status = "disabled";

@@ -232,7 +241,7 @@
 			adc at e0080000 {
 				compatible = "st,spear600-adc";
 				reg = <0xe0080000 0x1000>;
-				interrupts = <0 44 0x4>;
+				interrupts = <0 12 0x4>;
 				status = "disabled";
 			};

@@ -245,7 +254,8 @@
 			timer at ec800600 {
 				compatible = "arm,cortex-a9-twd-timer";
 				reg = <0xec800600 0x20>;
-				interrupts = <1 13 0x301>;
+				interrupts = <1 13 0x4>;
+				status = "disabled";
 			};
 
 			wdt at ec800620 {

@@ -257,6 +267,7 @@
 			thermal at e07008c4 {
 				compatible = "st,thermal-spear1340";
 				reg = <0xe07008c4 0x4>;
+				thermal_flags = <0x7000>;
 			};
 		};
 	};

arch/arm/boot/dts/spear300.dtsi +1 -1

index ed3627c..fdac871 100644
@@ -27,7 +27,7 @@
 		};
 
 		clcd at 60000000 {
-			compatible = "arm,clcd-pl110", "arm,primecell";
+			compatible = "arm,pl110", "arm,primecell";
 			reg = <0x60000000 0x1000>;
 			interrupts = <30>;
 			status = "disabled";

arch/arm/boot/dts/spear320-evb.dts +1 -4

index a3061ad..d62ee20 100644
@@ -82,10 +82,6 @@
 			};
 		};
 
-		clcd at 90000000 {
-			status = "okay";
-		};
-
 		dma at fc400000 {
 			status = "okay";
 		};

@@ -99,6 +95,7 @@
 		};
 
 		sdhci at 70000000 {
+			power-gpio = <&gpiopinctrl 61 1>;
 			status = "okay";
 		};

arch/arm/boot/dts/spear320.dtsi +2 -2

index 1f49d69..02113f3 100644
@@ -27,7 +27,7 @@
 		};
 
 		clcd at 90000000 {
-			compatible = "arm,clcd-pl110", "arm,primecell";
+			compatible = "arm,pl110", "arm,primecell";
 			reg = <0x90000000 0x1000>;
 			interrupts = <33>;
 			status = "disabled";

@@ -68,7 +68,7 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "simple-bus";
-			ranges = <0xa0000000 0xa0000000 0x10000000
+			ranges = <0xa0000000 0xa0000000 0x20000000
 				  0xd0000000 0xd0000000 0x30000000>;
 
 			i2c1: i2c at a7000000 {

arch/arm/boot/dts/spear3xx.dtsi +1 -1

index 3a8bb57..b02721f 100644
@@ -120,7 +120,7 @@
 			};
 
 			rtc at fc900000 {
-				compatible = "st,spear-rtc";
+				compatible = "st,spear600-rtc";
 				reg = <0xfc900000 0x1000>;
 				interrupts = <10>;
 				status = "disabled";

Signature · 1 line

1.7.12.rc2.18.g61b472e

Viresh Kumar

author

2012-11-11 04:39 UTC #19 lore raw

PATCH 6/14 ARM: SPEAr: DT: Modify DT bindings for STMMAC

From: Deepak Sikri <[email protected]>

This patch modifies the DT bindings for the GMAC IP existings for the SPEAr family. The DT bindings now additionally pass the phy mode as a configuration parameter for the ethernet device.

Signed-off-by Deepak Sikri <[email protected]>

---
 arch/arm/boot/dts/spear1310-evb.dts | 1 +
 arch/arm/boot/dts/spear1310.dtsi    | 4 ++++
 arch/arm/boot/dts/spear1340-evb.dts | 1 +
 arch/arm/boot/dts/spear3xx.dtsi     | 1 +
 arch/arm/boot/dts/spear600.dtsi     | 1 +
 5 files changed, 8 insertions(+)

arch/arm/boot/dts/spear1310-evb.dts +1 -0

index 79a1654..a4ff5cb 100644
@@ -148,6 +148,7 @@
 		};
 
 		gmac0: eth at e2000000 {
+			phy-mode = "gmii";
 			status = "okay";
 		};

arch/arm/boot/dts/spear1310.dtsi +4 -0

index 1e18f31..bd6b64b 100644
@@ -55,6 +55,7 @@
 			reg = <0x5c400000 0x8000>;
 			interrupts = <0 95 0x4>;
 			interrupt-names = "macirq";
+			phy-mode = "mii";
 			status = "disabled";
 		};

@@ -63,6 +64,7 @@
 			reg = <0x5c500000 0x8000>;
 			interrupts = <0 96 0x4>;
 			interrupt-names = "macirq";
+			phy-mode = "mii";
 			status = "disabled";
 		};

@@ -71,6 +73,7 @@
 			reg = <0x5c600000 0x8000>;
 			interrupts = <0 97 0x4>;
 			interrupt-names = "macirq";
+			phy-mode = "rmii";
 			status = "disabled";
 		};

@@ -79,6 +82,7 @@
 			reg = <0x5c700000 0x8000>;
 			interrupts = <0 98 0x4>;
 			interrupt-names = "macirq";
+			phy-mode = "rgmii";
 			status = "disabled";
 		};

arch/arm/boot/dts/spear1340-evb.dts +1 -0

index 4c5fa85..63c352f 100644
@@ -156,6 +156,7 @@
 		};
 
 		gmac0: eth at e2000000 {
+			phy-mode = "rgmii";
 			status = "okay";
 		};

arch/arm/boot/dts/spear3xx.dtsi +1 -0

index b02721f..4946360 100644
@@ -53,6 +53,7 @@
 			reg = <0xe0800000 0x8000>;
 			interrupts = <23 22>;
 			interrupt-names = "macirq", "eth_wake_irq";
+			phy-mode = "mii";
 			status = "disabled";
 		};

arch/arm/boot/dts/spear600.dtsi +1 -0

index a3c36e4..f74feea 100644
@@ -59,6 +59,7 @@
 			interrupt-parent = <&vic1>;
 			interrupts = <24 23>;
 			interrupt-names = "macirq", "eth_wake_irq";
+			phy-mode = "gmii";
 			status = "disabled";
 		};

Signature · 1 line

1.7.12.rc2.18.g61b472e

Viresh Kumar

author

2012-11-11 04:39 UTC #20 lore raw

PATCH 7/14 ARM: SPEAr: DT: add uart state to fix warning

From: Vipul Kumar Samar <[email protected]>

amba-pl011 driver supports two pin state "default" and "sleep" and it expect from dt to provide this pinctrl states and phandler otherwise it gives a warning message.

To remove this warning message pass default state with null phandler to uart pins in device node (In our case all the pins are configured in default states so we pass null phandler to pins).

Signed-off-by Vipul Kumar Samar <[email protected]>

---
 arch/arm/boot/dts/spear1310-evb.dts |  2 ++
 arch/arm/boot/dts/spear1340-evb.dts |  4 ++++
 arch/arm/boot/dts/spear300-evb.dts  |  2 ++
 arch/arm/boot/dts/spear310-evb.dts  | 12 ++++++++++++
 arch/arm/boot/dts/spear320-evb.dts  |  6 ++++++
 arch/arm/boot/dts/spear600-evb.dts  |  4 ++++
 6 files changed, 30 insertions(+)

arch/arm/boot/dts/spear1310-evb.dts +2 -0

index a4ff5cb..c60c3f8 100644
@@ -320,6 +320,8 @@
 
 			serial at e0000000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			spi0: spi at e0100000 {

arch/arm/boot/dts/spear1340-evb.dts +4 -0

index 63c352f..c6051dd 100644
@@ -332,10 +332,14 @@
 
 			serial at e0000000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			serial at b4100000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			spi0: spi at e0100000 {

arch/arm/boot/dts/spear300-evb.dts +2 -0

index b3265f6..5de1431 100644
@@ -243,6 +243,8 @@
 
 			serial at d0000000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			wdt at fc880000 {

arch/arm/boot/dts/spear310-evb.dts +12 -0

index b30fa0e..b096329 100644
@@ -166,26 +166,38 @@
 
 			serial at d0000000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			serial at b2000000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			serial at b2080000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			serial at b2100000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			serial at b2180000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			serial at b2200000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			wdt at fc880000 {

arch/arm/boot/dts/spear320-evb.dts +6 -0

index d62ee20..02f06c5 100644
@@ -179,14 +179,20 @@
 
 			serial at d0000000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			serial at a3000000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			serial at a4000000 {
 			       status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			wdt at fc880000 {

arch/arm/boot/dts/spear600-evb.dts +4 -0

index 16e4de4..5e6ef03 100644
@@ -73,10 +73,14 @@
 		apb {
 			serial at d0000000 {
 				status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			serial at d0080000 {
 				status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <>;
 			};
 
 			i2c at d0200000 {

Signature · 1 line

1.7.12.rc2.18.g61b472e

Viresh Kumar

author

2012-11-11 04:39 UTC #21 lore raw

PATCH 8/14 ARM: SPEAr: DT: Update device nodes

From: Shiraz Hashim <[email protected]>

This patch adds multiple device nodes for SPEAr machines and boards.

Signed-off-by Bhavna Yadav <[email protected]>

Signed-off-by Deepak Sikri <[email protected]>

Signed-off-by Rajeev Kumar <[email protected]>

Signed-off-by Vijay Kumar Mishra <[email protected]>

Signed-off-by Vipin Kumar <[email protected]>

Signed-off-by Vipul Kumar Samar <[email protected]>

---
 arch/arm/boot/dts/spear1310-evb.dts |  89 +++++++++++++++++++
 arch/arm/boot/dts/spear1310.dtsi    |   2 +
 arch/arm/boot/dts/spear1340-evb.dts | 172 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/spear1340.dtsi    |  46 ++++++++++
 arch/arm/boot/dts/spear13xx.dtsi    |  39 ++++++++
 arch/arm/boot/dts/spear320.dtsi     |  11 +++
 arch/arm/boot/dts/spear3xx.dtsi     |   2 +
 arch/arm/boot/dts/spear600-evb.dts  |  24 +++++
 arch/arm/boot/dts/spear600.dtsi     |  15 ++++
 9 files changed, 400 insertions(+)

arch/arm/boot/dts/spear1310-evb.dts +89 -0

index c60c3f8..56ea6d5 100644
@@ -147,6 +147,20 @@
 			};
 		};
 
+		gpio_keys {
+			compatible = "gpio-keys";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			button at 1 {
+				label = "wakeup";
+				linux,code = <0x100>;
+				gpios = <&gpio0 7 0x4>;
+				debounce-interval = <20>;
+				gpio-key,wakeup = <1>;
+			};
+		};
+
 		gmac0: eth at e2000000 {
 			phy-mode = "gmii";
 			status = "okay";

@@ -326,6 +340,81 @@
 
 			spi0: spi at e0100000 {
 				status = "okay";
+				num-cs = <3>;
+				cs-gpios = <&gpio1 7 0>, <&spics 0>, <&spics 1>;
+
+				stmpe610 at 0 {
+					status = "okay";
+					compatible = "st,stmpe610";
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					spi-max-frequency = <1000000>;
+					spi-cpha;
+					pl022,hierarchy = <0>;
+					pl022,interface = <0>;
+					pl022,slave-tx-disable;
+					pl022,com-mode = <0>;
+					pl022,rx-level-trig = <0>;
+					pl022,tx-level-trig = <0>;
+					pl022,ctrl-len = <0x7>;
+					pl022,wait-state = <0>;
+					pl022,duplex = <0>;
+					id = <0>;
+					blocks = <4>;
+					irq_over_gpio;
+					irq-gpios = <&gpio1 6 0x4>;
+					irq-trigger = <0x2>;
+
+					stmpe610-ts {
+						compatible = "stmpe,ts";
+						reg = <0>;
+						ts,sample-time = <4>;
+						ts,mod-12b = <1>;
+						ts,ref-sel = <0>;
+						ts,adc-freq = <1>;
+						ts,ave-ctrl = <1>;
+						ts,touch-det-delay = <2>;
+						ts,settling = <2>;
+						ts,fraction-z = <7>;
+						ts,i-drive = <1>;
+					};
+				};
+
+				m25p80 at 1 {
+					status = "okay";
+					compatible = "st,m25p80";
+					reg = <1>;
+					spi-max-frequency = <12000000>;
+					spi-cpol;
+					spi-cpha;
+					pl022,hierarchy = <0>;
+					pl022,interface = <0>;
+					pl022,slave-tx-disable;
+					pl022,com-mode = <0x2>;
+					pl022,rx-level-trig = <0>;
+					pl022,tx-level-trig = <0>;
+					pl022,ctrl-len = <0x11>;
+					pl022,wait-state = <0>;
+					pl022,duplex = <0>;
+				};
+
+				spidev at 2 {
+					status = "okay";
+					compatible = "spidev";
+					reg = <2>;
+					spi-max-frequency = <25000000>;
+					spi-cpha;
+					pl022,hierarchy = <0>;
+					pl022,interface = <0>;
+					pl022,slave-tx-disable;
+					pl022,com-mode = <0x2>;
+					pl022,rx-level-trig = <0>;
+					pl022,tx-level-trig = <0>;
+					pl022,ctrl-len = <0x11>;
+					pl022,wait-state = <0>;
+					pl022,duplex = <0>;
+				};
 			};
 
 			wdt at ec800620 {

arch/arm/boot/dts/spear1310.dtsi +2 -0

index bd6b64b..8fb22b9 100644
@@ -154,6 +154,8 @@
 				compatible = "arm,pl022", "arm,primecell";
 				reg = <0x5d400000 0x1000>;
 				interrupts = <0 99 0x4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				status = "disabled";
 			};

arch/arm/boot/dts/spear1340-evb.dts +172 -0

215 lines not on this page · raw message

arch/arm/boot/dts/spear1340.dtsi +46 -0

55 lines not on this page · raw message

arch/arm/boot/dts/spear13xx.dtsi +39 -0

index 4d35144..2e650f9 100644
@@ -64,6 +64,18 @@
 		bootargs = "console=ttyAMA0,115200";
 	};
 
+	cpufreq {
+		compatible = "st,cpufreq";
+		cpufreq_tbl = < 166000
+			200000
+			250000
+			300000
+			400000
+			500000
+			600000 >;
+		status = "disable";
+	};
+
 	ahb {
 		#address-cells = <1>;
 		#size-cells = <1>;

@@ -128,6 +140,13 @@
 			status = "disabled";
 		};
 
+		pcm {
+			compatible = "st,pcm-audio";
+			#address-cells = <0>;
+			#size-cells = <0>;
+			status = "disable";
+		};
+
 		smi: flash at ea000000 {
 			compatible = "st,spear600-smi";
 			#address-cells = <1>;

@@ -217,9 +236,29 @@
 				status = "disabled";
 			};
 
+			i2s at e0180000 {
+				compatible = "st,designware-i2s";
+				reg = <0xe0180000 0x1000>;
+				interrupt-names = "play_irq", "record_irq";
+				interrupts = <0 10 0x4
+					      0 11 0x4 >;
+				status = "disabled";
+			};
+
+			i2s at e0200000 {
+				compatible = "st,designware-i2s";
+				reg = <0xe0200000 0x1000>;
+				interrupt-names = "play_irq", "record_irq";
+				interrupts = <0 26 0x4
+					      0 53 0x4>;
+				status = "disabled";
+			};
+
 			spi0: spi at e0100000 {
 				compatible = "arm,pl022", "arm,primecell";
 				reg = <0xe0100000 0x1000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				interrupts = <0 31 0x4>;
 				status = "disabled";
 			};

arch/arm/boot/dts/spear320.dtsi +11 -0

index 02113f3..582ded7 100644
@@ -55,15 +55,26 @@
 		spi1: spi at a5000000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0xa5000000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
 		};
 
 		spi2: spi at a6000000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0xa6000000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
 		};
 
+		pwm: pwm at a8000000 {
+			compatible ="st,spear-pwm";
+			reg = <0xa8000000 0x1000>;
+			#pwm-cells = <2>;
+			status = "disabled";
+                };
+
 		apb {
 			#address-cells = <1>;
 			#size-cells = <1>;

arch/arm/boot/dts/spear3xx.dtsi +2 -0

index 4946360..c2a852d 100644
@@ -70,6 +70,8 @@
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0xd0100000 0x1000>;
 			interrupts = <20>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 			status = "disabled";
 		};

arch/arm/boot/dts/spear600-evb.dts +24 -0

index 5e6ef03..d865a89 100644
@@ -24,15 +24,35 @@
 	};
 
 	ahb {
+		clcd at fc200000 {
+			status = "okay";
+		};
+
 		dma at fc400000 {
 			status = "okay";
 		};
 
+		ehci at e1800000 {
+			status = "okay";
+		};
+
+		ehci at e2000000 {
+			status = "okay";
+		};
+
 		gmac: ethernet at e0800000 {
 			phy-mode = "gmii";
 			status = "okay";
 		};
 
+		ohci at e1900000 {
+			status = "okay";
+		};
+
+		ohci at e2100000 {
+			status = "okay";
+		};
+
 		smi: flash at fc000000 {
 			status = "okay";
 			clock-rate=<50000000>;

@@ -83,6 +103,10 @@
 				pinctrl-0 = <>;
 			};
 
+			rtc at fc900000 {
+			       status = "okay";
+			};
+
 			i2c at d0200000 {
 				clock-frequency = <400000>;
 				status = "okay";

arch/arm/boot/dts/spear600.dtsi +15 -0

index f74feea..e051dde 100644
@@ -45,6 +45,14 @@
 			#interrupt-cells = <1>;
 		};
 
+		clcd at fc200000 {
+			compatible = "arm,pl110", "arm,primecell";
+			reg = <0xfc200000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <12>;
+			status = "disabled";
+		};
+
 		dma at fc400000 {
 			compatible = "arm,pl080", "arm,primecell";
 			reg = <0xfc400000 0x1000>;

@@ -179,6 +187,13 @@
 				status = "disabled";
 			};
 
+			rtc at fc900000 {
+				compatible = "st,spear600-rtc";
+				reg = <0xfc900000 0x1000>;
+				interrupts = <10>;
+				status = "disabled";
+			};
+
 			timer at f0000000 {
 				compatible = "st,spear-timer";
 				reg = <0xf0000000 0x400>;

Signature · 1 line

1.7.12.rc2.18.g61b472e

Viresh Kumar

author

2012-11-26 11:25 UTC #22 lore raw

PATCH 8/14 ARM: SPEAr: DT: Update device nodes

Quoted 4 lines · Viresh Kumar

From: Shiraz Hashim <[email protected]>
This patch adds multiple device nodes for SPEAr machines and boards.

Quoted 8 lines

Signed-off-by Bhavna Yadav <[email protected]>
Signed-off-by Deepak Sikri <[email protected]>
Signed-off-by Rajeev Kumar <[email protected]>
Signed-off-by Shiraz Hashim <[email protected]>
Signed-off-by Vijay Kumar Mishra <[email protected]>
Signed-off-by Vipin Kumar <[email protected]>
Signed-off-by Vipul Kumar Samar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>

Arnd/Olof,

As discussed (With Arnd) over IRC, i would be sending a PULL request for this patchset.

There are few updates/fixes in the bindings for few nodes (as the drivers for them
just got pushed by their maintainers after some updates) and here is a diff for that. I will merge this diff with current patch in my PULL request.

From: Viresh Kumar <[email protected]>
Date: Mon, 26 Nov 2012 16:44:53 +0530
Subject: [PATCH] fixup! ARM: SPEAr: DT: Update device nodes

---
 arch/arm/boot/dts/spear1310-evb.dts | 14 ++++----------
 arch/arm/boot/dts/spear1340-evb.dts | 25 ++++++++-----------------
 arch/arm/boot/dts/spear13xx.dtsi    | 14 +++++++-------
 3 files changed, 19 insertions(+), 34 deletions(-)

(quoted diff) +0 -0

b/arch/arm/boot/dts/spear1310-evb.dts
index cd4e2f8..b56a801 100644

arch/arm/boot/dts/spear1310-evb.dts +4 ~~-10~~

@@ -348,7 +348,6 @@
 				cs-gpios = <&gpio1 7 0>, <&spics 0>, <&spics 1>;
 
 				stmpe610 at 0 {
-					status = "okay";
 					compatible = "st,stmpe610";
 					reg = <0>;
 					#address-cells = <1>;

@@ -364,15 +363,12 @@
 					pl022,ctrl-len = <0x7>;
 					pl022,wait-state = <0>;
 					pl022,duplex = <0>;
-					id = <0>;
-					blocks = <4>;
-					irq_over_gpio;
-					irq-gpios = <&gpio1 6 0x4>;
+					interrupts = <6 0x4>;
+					interrupt-parent = <&gpio1>;
 					irq-trigger = <0x2>;
 
-					stmpe610-ts {
-						compatible = "stmpe,ts";
-						reg = <0>;
+					stmpe_touchscreen {
+						compatible = "st,stmpe-ts";
 						ts,sample-time = <4>;
 						ts,mod-12b = <1>;
 						ts,ref-sel = <0>;

@@ -386,7 +382,6 @@
 				};
 
 				m25p80 at 1 {
-					status = "okay";
 					compatible = "st,m25p80";
 					reg = <1>;
 					spi-max-frequency = <12000000>;

@@ -404,7 +399,6 @@
 				};
 
 				spidev at 2 {
-					status = "okay";
 					compatible = "spidev";
 					reg = <2>;
 					spi-max-frequency = <25000000>;

(quoted diff) +0 -0

b/arch/arm/boot/dts/spear1340-evb.dts
index c519fa1..d6c30ae 100644

arch/arm/boot/dts/spear1340-evb.dts +8 ~~-17~~

@@ -319,15 +319,12 @@
 					#address-cells = <1>;
 					#size-cells = <0>;
 					reg = <0x41>;
-					irq-over-gpio;
-					irq-gpios = <&gpio0 4 0x4>;
-					id = <0>;
-					blocks = <1>;
+					interrupts = <4 0x4>;
+					interrupt-parent = <&gpio0>;
 					irq-trigger = <0x2>;
 
-					stmpegpio: stmpe-gpio {
-						compatible = "stmpe,gpio";
-						reg = <0>;
+					stmpegpio: stmpe_gpio {
+						compatible = "st,stmpe-gpio";
 						gpio-controller;
 						#gpio-cells = <2>;
 					};

@@ -445,7 +442,6 @@
 					   <&gpiopinctrl 85 0>;
 
 				m25p80 at 0 {
-					status = "okay";
 					compatible = "m25p80";
 					reg = <0>;
 					spi-max-frequency = <12000000>;

@@ -463,7 +459,6 @@
 				};
 
 				stmpe610 at 1 {
-					status = "okay";
 					compatible = "st,stmpe610";
 					spi-max-frequency = <1000000>;
 					spi-cpha;

@@ -477,17 +472,14 @@
 					pl022,ctrl-len = <0x7>;
 					pl022,wait-state = <0>;
 					pl022,duplex = <0>;
-					irq-over-gpio;
-					irq-gpios = <&gpiopinctrl 100 0>;
-					id = <0>;
-					blocks = <4>;
+					interrupts = <100 0>;
+					interrupt-parent = <&gpiopinctrl>;
 					irq-trigger = <0x2>;
 					#address-cells = <1>;
 					#size-cells = <0>;
 
-					stmpe610-ts {
-						compatible = "stmpe,ts";
-						reg = <0>;
+					stmpe_touchscreen {
+						compatible = "st,stmpe-ts";
 						ts,sample-time = <4>;
 						ts,mod-12b = <1>;
 						ts,ref-sel = <0>;

@@ -501,7 +493,6 @@
 				};
 
 				spidev at 2 {
-					status = "okay";
 					compatible = "spidev";
 					reg = <2>;
 					spi-max-frequency = <25000000>;

arch/arm/boot/dts/spear13xx.dtsi +7 -7

index 2e650f9..009096d 100644
@@ -65,14 +65,14 @@
 	};
 
 	cpufreq {
-		compatible = "st,cpufreq";
+		compatible = "st,cpufreq-spear";
 		cpufreq_tbl = < 166000
-			200000
-			250000
-			300000
-			400000
-			500000
-			600000 >;
+				200000
+				250000
+				300000
+				400000
+				500000
+				600000 >;
 		status = "disable";
 	};

--
viresh

Viresh Kumar

author

2012-11-11 04:39 UTC #23 lore raw

PATCH 9/14 ARM: SPEAr1310: Move 1310 specific misc register into machine specific files

From: Vipul Kumar Samar <[email protected]>

This patch moves some global macro definitions to the files where they are used. Its a step towards removing spear.h completely later on.

Signed-off-by Vipul Kumar Samar <[email protected]>

---
 arch/arm/mach-spear13xx/include/mach/spear.h | 8 --------
 arch/arm/mach-spear13xx/spear1310.c          | 5 +++++
 drivers/clk/spear/spear1310_clock.c          | 1 +
 3 files changed, 6 insertions(+), 8 deletions(-)

arch/arm/mach-spear13xx/include/mach/spear.h +0 -8

index 07d90ac..7cfa681 100644
@@ -47,14 +47,6 @@
 #define DMAC1_BASE				UL(0xEB000000)
 #define MCIF_CF_BASE				UL(0xB2800000)
 
-/* Devices present in SPEAr1310 */
-#ifdef CONFIG_MACH_SPEAR1310
-#define SPEAR1310_RAS_GRP1_BASE			UL(0xD8000000)
-#define VA_SPEAR1310_RAS_GRP1_BASE		UL(0xFA000000)
-#define SPEAR1310_RAS_BASE			UL(0xD8400000)
-#define VA_SPEAR1310_RAS_BASE			IOMEM(UL(0xFA400000))
-#endif /* CONFIG_MACH_SPEAR1310 */
-
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE			UART_BASE
 #define VA_SPEAR_DBG_UART_BASE			VA_UART_BASE

arch/arm/mach-spear13xx/spear1310.c +5 -0

index 9fbbfc5..593a756 100644
@@ -27,6 +27,11 @@
 #define SPEAR1310_SATA1_BASE			UL(0xB1800000)
 #define SPEAR1310_SATA2_BASE			UL(0xB4000000)
 
+#define SPEAR1310_RAS_GRP1_BASE			UL(0xD8000000)
+#define VA_SPEAR1310_RAS_GRP1_BASE		UL(0xFA000000)
+#define SPEAR1310_RAS_BASE			UL(0xD8400000)
+#define VA_SPEAR1310_RAS_BASE			IOMEM(UL(0xFA400000))
+
 /* ssp device registration */
 static struct pl022_ssp_controller ssp1_plat_data = {
 	.bus_id = 0,

drivers/clk/spear/spear1310_clock.c +1 -0

index 0fcec2a..cf7e176 100644
@@ -20,6 +20,7 @@
 #include <mach/spear.h>
 #include "clk.h"
 
+#define VA_SPEAR1310_RAS_BASE			IOMEM(UL(0xFA400000))
 /* PLL related registers and bit values */
 #define SPEAR1310_PLL_CFG			(VA_MISC_BASE + 0x210)
 	/* PLL_CFG bit values */

Signature · 1 line

1.7.12.rc2.18.g61b472e

Viresh Kumar

author

2012-11-11 04:39 UTC #24 lore raw

PATCH 10/14 ARM: SPEAr13xx: Remove fields not required for ssp controller

From: Shiraz Hashim <[email protected]>

Few fields are not required to be programmed in platform data of spi controller now, as it comes via DT. Remove them.

---
 arch/arm/mach-spear13xx/spear1310.c | 2 --
 arch/arm/mach-spear13xx/spear13xx.c | 2 --
 2 files changed, 4 deletions(-)

arch/arm/mach-spear13xx/spear1310.c +0 -2

index 593a756..451f3b1 100644
@@ -34,9 +34,7 @@
 
 /* ssp device registration */
 static struct pl022_ssp_controller ssp1_plat_data = {
-	.bus_id = 0,
 	.enable_dma = 0,
-	.num_chipselect = 3,
 };
 
 /* Add SPEAr1310 auxdata to pass platform data */

arch/arm/mach-spear13xx/spear13xx.c +0 -2

index 5633d69..c4af775 100644
@@ -57,12 +57,10 @@ static struct dw_dma_slave ssp_dma_param[] = {
 };
 
 struct pl022_ssp_controller pl022_plat_data = {
-	.bus_id = 0,
 	.enable_dma = 1,
 	.dma_filter = dw_dma_filter,
 	.dma_rx_param = &ssp_dma_param[1],
 	.dma_tx_param = &ssp_dma_param[0],
-	.num_chipselect = 3,
 };
 
 /* CF device registration */

Signature · 1 line

1.7.12.rc2.18.g61b472e

Viresh Kumar

author

2012-11-11 04:39 UTC #25 lore raw

PATCH 11/14 ARM: SPEAr1310: Fix AUXDATA for compact flash controller

From: Vipul Kumar Samar <[email protected]>

This patch fixes the platform data for compact flash controller.

Signed-off-by Vipul Kumar Samar <[email protected]>

---
 arch/arm/mach-spear13xx/spear1310.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

arch/arm/mach-spear13xx/spear1310.c +8 -1

index 451f3b1..02f4724 100644
@@ -15,6 +15,7 @@
 
 #include <linux/amba/pl022.h>
 #include <linux/of_platform.h>
+#include <linux/pata_arasan_cf_data.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>

@@ -32,6 +33,12 @@
 #define SPEAR1310_RAS_BASE			UL(0xD8400000)
 #define VA_SPEAR1310_RAS_BASE			IOMEM(UL(0xFA400000))
 
+static struct arasan_cf_pdata cf_pdata = {
+	.cf_if_clk = CF_IF_CLK_166M,
+	.quirk = CF_BROKEN_UDMA,
+	.dma_priv = &cf_dma_priv,
+};
+
 /* ssp device registration */
 static struct pl022_ssp_controller ssp1_plat_data = {
 	.enable_dma = 0,

@@ -39,7 +46,7 @@ static struct pl022_ssp_controller ssp1_plat_data = {
 
 /* Add SPEAr1310 auxdata to pass platform data */
 static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
-	OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
+	OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata),
 	OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
 	OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
 	OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),

Signature · 1 line

1.7.12.rc2.18.g61b472e

Viresh Kumar

author

2012-11-11 04:39 UTC #26 lore raw

PATCH 12/14 ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT

From: Shiraz Hashim <[email protected]>

SPEAr3xx architecture includes shared/multiplexed irqs for certain set of devices. The multiplexor provides a single interrupt to parent interrupt controller (VIC) on behalf of a group of devices.

There can be multiple groups available on SPEAr3xx variants but not exceeding 4. The number of devices in a group can differ, further they may share same set of status/mask registers spanning across different bit masks. Also in some cases the group may not have enable or other registers. This makes software little complex.

Present implementation was non-DT and had few complex data structures to decipher banks, number of irqs supported, mask and registers involved.

This patch simplifies the overall design and convert it in to DT. It also removes all registration from individual SoC files and bring them in to common shirq.c.

Also updated the corresponding documentation for DT binding of shirq.

---
 .../devicetree/bindings/arm/spear/shirq.txt        |  48 ++++
 arch/arm/mach-spear3xx/include/mach/irqs.h         |  10 +-
 arch/arm/mach-spear3xx/spear300.c                  | 103 -------
 arch/arm/mach-spear3xx/spear310.c                  | 202 --------------
 arch/arm/mach-spear3xx/spear320.c                  | 204 --------------
 arch/arm/mach-spear3xx/spear3xx.c                  |   4 +
 arch/arm/plat-spear/include/plat/shirq.h           |  35 +--
 arch/arm/plat-spear/shirq.c                        | 305 +++++++++++++++++----
 8 files changed, 320 insertions(+), 591 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear/shirq.txt

Documentation/devicetree/bindings/arm/spear/shirq.txt new file +48 -0

new file mode 100644
index 0000000..13fbb88
@@ -0,0 +1,48 @@
+* SPEAr Shared IRQ layer (shirq)
+
+SPEAr3xx architecture includes shared/multiplexed irqs for certain set
+of devices. The multiplexor provides a single interrupt to parent
+interrupt controller (VIC) on behalf of a group of devices.
+
+There can be multiple groups available on SPEAr3xx variants but not
+exceeding 4. The number of devices in a group can differ, further they
+may share same set of status/mask registers spanning across different
+bit masks. Also in some cases the group may not have enable or other
+registers. This makes software little complex.
+
+A single node in the device tree is used to describe the shared
+interrupt multiplexor (one node for all groups). A group in the
+interrupt controller shares config/control registers with other groups.
+For example, a 32-bit interrupt enable/disable config register can
+accommodate upto 4 interrupt groups.
+
+Required properties:
+  - compatible: should be, either of
+     - "st,spear300-shirq"
+     - "st,spear310-shirq"
+     - "st,spear320-shirq"
+  - interrupt-controller: Identifies the node as an interrupt controller.
+  - #interrupt-cells: should be <1> which basically contains the offset
+    (starting from 0) of interrupts for all the groups.
+  - reg: Base address and size of shirq registers.
+  - interrupts: The list of interrupts generated by the groups which are
+    then connected to a parent interrupt controller. Each group is
+    associated with one of the interrupts, hence number of interrupts (to
+    parent) is equal to number of groups. The format of the interrupt
+    specifier depends in the interrupt parent controller.
+
+  Optional properties:
+  - interrupt-parent: pHandle of the parent interrupt controller, if not
+    inherited from the parent node.
+
+Example:
+
+The following is an example from the SPEAr320 SoC dtsi file.
+
+shirq: interrupt-controller at 0xb3000000 {
+	compatible = "st,spear320-shirq";
+	reg = <0xb3000000 0x1000>;
+	interrupts = <28 29 30 1>;
+	#interrupt-cells = <1>;
+	interrupt-controller;
+};

arch/arm/mach-spear3xx/include/mach/irqs.h +1 -9

index 803de76..f95e5b2 100644
@@ -14,14 +14,6 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
 
-/* FIXME: probe all these from DT */
-#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM		1
-#define SPEAR3XX_IRQ_GEN_RAS_1			28
-#define SPEAR3XX_IRQ_GEN_RAS_2			29
-#define SPEAR3XX_IRQ_GEN_RAS_3			30
-#define SPEAR3XX_IRQ_VIC_END			32
-#define SPEAR3XX_VIRQ_START			SPEAR3XX_IRQ_VIC_END
-
-#define NR_IRQS			160
+#define NR_IRQS			256
 
 #endif /* __MACH_IRQS_H */

arch/arm/mach-spear3xx/spear300.c +0 ~~-103~~

123 lines not on this page · raw message

arch/arm/mach-spear3xx/spear310.c +0 ~~-202~~

225 lines not on this page · raw message

arch/arm/mach-spear3xx/spear320.c +0 ~~-204~~

227 lines not on this page · raw message

arch/arm/mach-spear3xx/spear3xx.c +4 -0

index 98144ba..781aec9 100644
@@ -20,6 +20,7 @@
 #include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <plat/pl080.h>
+#include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/spear.h>

@@ -121,6 +122,9 @@ struct sys_timer spear3xx_timer = {
 
 static const struct of_device_id vic_of_match[] __initconst = {
 	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+	{ .compatible = "st,spear300-shirq", .data = spear3xx_shirq_of_init, },
+	{ .compatible = "st,spear310-shirq", .data = spear3xx_shirq_of_init, },
+	{ .compatible = "st,spear320-shirq", .data = spear3xx_shirq_of_init, },
 	{ /* Sentinel */ }
 };

arch/arm/plat-spear/include/plat/shirq.h +12 ~~-23~~

index 88a7fbd..1215afe 100644
@@ -18,24 +18,8 @@
 #include <linux/types.h>
 
 /*
- * struct shirq_dev_config: shared irq device configuration
- *
- * virq: virtual irq number of device
- * enb_mask: enable mask of device
- * status_mask: status mask of device
- * clear_mask: clear mask of device
- */
-struct shirq_dev_config {
-	u32 virq;
-	u32 enb_mask;
-	u32 status_mask;
-	u32 clear_mask;
-};
-
-/*
  * struct shirq_regs: shared irq register configuration
  *
- * base: base address of shared irq register
  * enb_reg: enable register offset
  * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
  * status_reg: status register offset

@@ -44,11 +28,9 @@ struct shirq_dev_config {
  * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
  */
 struct shirq_regs {
-	void __iomem *base;
 	u32 enb_reg;
 	u32 reset_to_enb;
 	u32 status_reg;
-	u32 status_reg_mask;
 	u32 clear_reg;
 	u32 reset_to_clear;
 };

@@ -57,17 +39,24 @@ struct shirq_regs {
  * struct spear_shirq: shared irq structure
  *
  * irq: hardware irq number
- * dev_config: array of device config structures which are using "irq" line
- * dev_count: size of dev_config array
+ * irq_base: base irq in linux domain
+ * irq_nr: no. of shared interrupts in a particular block
+ * irq_bit_off: starting bit offset in the status register
+ * invalid_irq: irq group is currently disabled
+ * base: base address of shared irq register
  * regs: register configuration for shared irq block
  */
 struct spear_shirq {
 	u32 irq;
-	struct shirq_dev_config *dev_config;
-	u32 dev_count;
+	u32 irq_base;
+	u32 irq_nr;
+	u32 irq_bit_off;
+	int invalid_irq;
+	void __iomem *base;
 	struct shirq_regs regs;
 };
 
-int spear_shirq_register(struct spear_shirq *shirq);
+int __init spear3xx_shirq_of_init(struct device_node *np,
+		struct device_node *parent);
 
 #endif /* __PLAT_SHIRQ_H */

arch/arm/plat-spear/shirq.c +255 ~~-50~~

363 lines not on this page · raw message

Signature · 1 line

1.7.12.rc2.18.g61b472e

Arnd Bergmann

maintainer

2012-11-12 15:09 UTC #27 lore raw

PATCH 12/14 ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT

Quoted 12 lines · Viresh Kumar

From: Shiraz Hashim <[email protected]>
SPEAr3xx architecture includes shared/multiplexed irqs for certain set of devices. The multiplexor provides a single interrupt to parent interrupt controller (VIC) on behalf of a group of devices.
There can be multiple groups available on SPEAr3xx variants but not exceeding 4. The number of devices in a group can differ, further they may share same set of status/mask registers spanning across different bit masks. Also in some cases the group may not have enable or other registers. This makes software little complex.

Quoted 8 lines

Present implementation was non-DT and had few complex data structures to decipher banks, number of irqs supported, mask and registers involved.
This patch simplifies the overall design and convert it in to DT. It also removes all registration from individual SoC files and bring them in to common shirq.c.
Also updated the corresponding documentation for DT binding of shirq.

Looks basically ok, but I have a few comments.

Quoted 11 lines

---
 .../devicetree/bindings/arm/spear/shirq.txt        |  48 ++++
 arch/arm/mach-spear3xx/include/mach/irqs.h         |  10 +-
 arch/arm/mach-spear3xx/spear300.c                  | 103 -------
 arch/arm/mach-spear3xx/spear310.c                  | 202 --------------
 arch/arm/mach-spear3xx/spear320.c                  | 204 --------------
 arch/arm/mach-spear3xx/spear3xx.c                  |   4 +
 arch/arm/plat-spear/include/plat/shirq.h           |  35 +--
 arch/arm/plat-spear/shirq.c                        | 305 +++++++++++++++++----

I guess it would be nice to move this to drivers/irqchip/st-shirq.c now that we have introduced that directory.

Quoted 6 lines

static const char * const spear320_dt_board_compat[] = {
arch/arm/mach-spear3xx/spear3xx.c +0 -0
index 98144ba..781aec9 100644

arch/arm/mach-spear3xx/spear3xx.c struct sys_timer spear3xx_timer = { · line 129

Quoted 8 lines

arch/arm/mach-spear3xx/spear3xx.c +3 -0

@@ -121,6 +122,9 @@ struct sys_timer spear3xx_timer = {
 
 static const struct of_device_id vic_of_match[] __initconst = {
 	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+	{ .compatible = "st,spear300-shirq", .data = spear3xx_shirq_of_init, },
+	{ .compatible = "st,spear310-shirq", .data = spear3xx_shirq_of_init, },
+	{ .compatible = "st,spear320-shirq", .data = spear3xx_shirq_of_init, },
 	{ /* Sentinel */ }
 };

You list three "compatible" values here with the same init function, and then

Quoted 30 lines

arch/arm/mach-spear3xx/spear3xx.c +30 -0

+int __init spear3xx_shirq_of_init(struct device_node *np,
+		struct device_node *parent)
+{
+	struct spear_shirq **shirq_blocks;
+	void __iomem *base;
+	int block_nr, ret;
+
+	base = of_iomap(np, 0);
+	if (!base) {
+		pr_err("%s: failed to map shirq registers\n", __func__);
+		return -ENXIO;
+	}
+
+	if (of_device_is_compatible(np, "st,spear300-shirq")) {
+		shirq_blocks = spear300_shirq_blocks;
+		block_nr = ARRAY_SIZE(spear300_shirq_blocks);
+	} else if (of_device_is_compatible(np, "st,spear310-shirq")) {
+		shirq_blocks = spear310_shirq_blocks;
+		block_nr = ARRAY_SIZE(spear310_shirq_blocks);
+	} else if (of_device_is_compatible(np, "st,spear320-shirq")) {
+		shirq_blocks = spear320_shirq_blocks;
+		block_nr = ARRAY_SIZE(spear320_shirq_blocks);
+	} else {
+		pr_err("%s: unknown platform\n", __func__);
+		ret = -EINVAL;
+		goto unmap;
+	}
+
+	ret = shirq_init(shirq_blocks, block_nr, base, np);
+	if (ret) {

arch/arm/mach-spear3xx/spear3xx.c struct sys_timer spear3xx_timer = {

Quoted 10 lines

arch/arm/mach-spear3xx/spear3xx.c +10 -0

+		pr_err("%s: shirq initialization failed\n", __func__);
+		goto unmap;
+	}
+
+	return ret;
+
+unmap:
+	iounmap(base);
+	return ret;
+}

In that multiplex between thre three again. I think it would be cleaner to have three separate functions and move the call to of_iomap into shirq_init.

Arnd

viresh kumar

author

2012-11-12 16:37 UTC #28 lore raw

PATCH 12/14 ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT

Quoted 11 lines · Arnd Bergmann

Quoted 8 lines · Viresh Kumar

 .../devicetree/bindings/arm/spear/shirq.txt        |  48 ++++
 arch/arm/mach-spear3xx/include/mach/irqs.h         |  10 +-
 arch/arm/mach-spear3xx/spear300.c                  | 103 -------
 arch/arm/mach-spear3xx/spear310.c                  | 202 --------------
 arch/arm/mach-spear3xx/spear320.c                  | 204 --------------
 arch/arm/mach-spear3xx/spear3xx.c                  |   4 +
 arch/arm/plat-spear/include/plat/shirq.h           |  35 +--
 arch/arm/plat-spear/shirq.c                        | 305 +++++++++++++++++----

Quoted 2 lines

I guess it would be nice to move this to drivers/irqchip/st-shirq.c now that we have introduced that directory.

I was sure that i will get this one :)
I wanted to, but was just trying the basic patch first :)

I would add another patch in this series as the last patch to move stuff out of plat :)

Quoted 17 lines

Quoted 6 lines
static const char * const spear320_dt_board_compat[] = {
arch/arm/mach-spear3xx/spear3xx.c +0 -0
index 98144ba..781aec9 100644
arch/arm/mach-spear3xx/spear3xx.c struct sys_timer spear3xx_timer = { · line 129
Quoted 8 lines
arch/arm/mach-spear3xx/spear3xx.c +3 -0
@@ -121,6 +122,9 @@ struct sys_timer spear3xx_timer = {
 
 static const struct of_device_id vic_of_match[] __initconst = {
      { .compatible = "arm,pl190-vic", .data = vic_of_init, },
+     { .compatible = "st,spear300-shirq", .data = spear3xx_shirq_of_init, },
+     { .compatible = "st,spear310-shirq", .data = spear3xx_shirq_of_init, },
+     { .compatible = "st,spear320-shirq", .data = spear3xx_shirq_of_init, },
      { /* Sentinel */ }
 };
You list three "compatible" values here with the same init function, and then

Quoted 7 lines

arch/arm/mach-spear3xx/spear3xx.c struct sys_timer spear3xx_timer = {
Quoted 4 lines
arch/arm/mach-spear3xx/spear3xx.c +4 -0
+int __init spear3xx_shirq_of_init(struct device_node *np,
+             struct device_node *parent)
+{
+}
In that multiplex between thre three again. I think it would be cleaner to have three separate functions and move the call to of_iomap into shirq_init.

I reworked a bit on this patch after picking the initial patch from Shiraz. And i
am disappointed that i missed this basic thing.

--
viresh

Arnd Bergmann

maintainer

2012-11-12 17:00 UTC #29 lore raw

PATCH 12/14 ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT

Quoted 12 lines · viresh kumar

Quoted 11 lines · Arnd Bergmann

Quoted 8 lines · Viresh Kumar

 .../devicetree/bindings/arm/spear/shirq.txt        |  48 ++++
 arch/arm/mach-spear3xx/include/mach/irqs.h         |  10 +-
 arch/arm/mach-spear3xx/spear300.c                  | 103 -------
 arch/arm/mach-spear3xx/spear310.c                  | 202 --------------
 arch/arm/mach-spear3xx/spear320.c                  | 204 --------------
 arch/arm/mach-spear3xx/spear3xx.c                  |   4 +
 arch/arm/plat-spear/include/plat/shirq.h           |  35 +--
 arch/arm/plat-spear/shirq.c                        | 305 +++++++++++++++++----

Quoted 8 lines

Quoted 2 lines
I guess it would be nice to move this to drivers/irqchip/st-shirq.c now that we have introduced that directory.
I was sure that i will get this one :)
I wanted to, but was just trying the basic patch first :)
I would add another patch in this series as the last patch to move stuff out of plat :)

Ok, no problem. Do it later then.

Arnd

Viresh Kumar

author

2012-11-12 17:16 UTC #30 lore raw

PATCH 1/1 fixup! ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT

---

Hi Arnd,

This is the fixup of the major issues you pointed out. Please go ahead and apply this series. I will then move all this out of plat.

 arch/arm/mach-spear3xx/spear3xx.c        |  6 +--
 arch/arm/plat-spear/include/plat/shirq.h |  6 ++-
 arch/arm/plat-spear/shirq.c              | 70 ++++++++++++++------------------
 3 files changed, 39 insertions(+), 43 deletions(-)

arch/arm/mach-spear3xx/spear3xx.c +3 -3

index 781aec9..f1aaf5b 100644
@@ -122,9 +122,9 @@ struct sys_timer spear3xx_timer = {
 
 static const struct of_device_id vic_of_match[] __initconst = {
 	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
-	{ .compatible = "st,spear300-shirq", .data = spear3xx_shirq_of_init, },
-	{ .compatible = "st,spear310-shirq", .data = spear3xx_shirq_of_init, },
-	{ .compatible = "st,spear320-shirq", .data = spear3xx_shirq_of_init, },
+	{ .compatible = "st,spear300-shirq", .data = spear300_shirq_of_init, },
+	{ .compatible = "st,spear310-shirq", .data = spear310_shirq_of_init, },
+	{ .compatible = "st,spear320-shirq", .data = spear320_shirq_of_init, },
 	{ /* Sentinel */ }
 };

arch/arm/plat-spear/include/plat/shirq.h +5 -1

index 1215afe..c51b355 100644
@@ -56,7 +56,11 @@ struct spear_shirq {
 	struct shirq_regs regs;
 };
 
-int __init spear3xx_shirq_of_init(struct device_node *np,
+int __init spear300_shirq_of_init(struct device_node *np,
+		struct device_node *parent);
+int __init spear310_shirq_of_init(struct device_node *np,
+		struct device_node *parent);
+int __init spear320_shirq_of_init(struct device_node *np,
 		struct device_node *parent);
 
 #endif /* __PLAT_SHIRQ_H */

arch/arm/plat-spear/shirq.c +31 ~~-39~~

101 lines not on this page · raw message

Signature · 1 line

1.7.12.rc2.18.g61b472e

Viresh Kumar

author

2012-11-12 17:35 UTC #31 lore raw

PATCH 1/1 ARM: SPEAr3xx: Shirq: Move shirq controller out of plat/

This patch moves shirq interrupt controllers driver and header file out of plat-spear directory. It is moved to drivers/irqchip/ directory.

http://www.spinics.net/lists/arm-kernel/msg206253.html

---

Hi Arnd,

This is an follow-up patch of my earlier patchset:

Please apply it after applying them.

 arch/arm/mach-spear3xx/spear3xx.c                              |  2 +-
 arch/arm/plat-spear/Makefile                                   |  2 +-
 drivers/irqchip/Makefile                                       |  5 +++--
 arch/arm/plat-spear/shirq.c => drivers/irqchip/spear-shirq.c   |  9 +++++----
 .../plat/shirq.h => include/linux/irqchip/spear-shirq.h        | 10 ++++------
 5 files changed, 14 insertions(+), 14 deletions(-)
 rename arch/arm/plat-spear/shirq.c => drivers/irqchip/spear-shirq.c (97%)
 rename arch/arm/plat-spear/include/plat/shirq.h => include/linux/irqchip/spear-shirq.h (90%)

arch/arm/mach-spear3xx/spear3xx.c +1 -1

index f1aaf5b..38fe95d 100644
@@ -15,12 +15,12 @@
 
 #include <linux/amba/pl022.h>
 #include <linux/amba/pl08x.h>
+#include <linux/irqchip/spear-shirq.h>
 #include <linux/of_irq.h>
 #include <linux/io.h>
 #include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <plat/pl080.h>
-#include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/spear.h>

arch/arm/plat-spear/Makefile +1 -1

index 2607bd0..01e8853 100644
@@ -5,5 +5,5 @@
 # Common support
 obj-y	:= restart.o time.o
 
-obj-$(CONFIG_ARCH_SPEAR3XX)	+= pl080.o shirq.o
+obj-$(CONFIG_ARCH_SPEAR3XX)	+= pl080.o
 obj-$(CONFIG_ARCH_SPEAR6XX)	+= pl080.o

drivers/irqchip/Makefile +3 -2

index e2e6eb5..fee05b1 100644
@@ -1,2 +1,3 @@
-obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
-obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
+obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
+obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o
+obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o

drivers/irqchip/spear-shirq.c renamed from arch/arm/plat-spear/shirq.c +5 -4

similarity index 97%
rename from arch/arm/plat-spear/shirq.c
rename to drivers/irqchip/spear-shirq.c
index 955c724..80e1d2f 100644
@@ -1,11 +1,12 @@
 /*
- * arch/arm/plat-spear/shirq.c
- *
  * SPEAr platform shared irq layer source file
  *
- * Copyright (C) 2009 ST Microelectronics
+ * Copyright (C) 2009-2012 ST Microelectronics
  * Viresh Kumar <[email protected]>
  *
+ * Copyright (C) 2012 ST Microelectronics
+ * Shiraz Hashim <[email protected]>
+ *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.

@@ -18,11 +19,11 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/spear-shirq.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/spinlock.h>
-#include <plat/shirq.h>
 
 static DEFINE_SPINLOCK(lock);

include/linux/irqchip/spear-shirq.h renamed from arch/arm/plat-spear/include/plat/shirq.h +4 -6

similarity index 90%
rename from arch/arm/plat-spear/include/plat/shirq.h
rename to include/linux/irqchip/spear-shirq.h
index c51b355..c8be16d 100644
@@ -1,9 +1,7 @@
 /*
- * arch/arm/plat-spear/include/plat/shirq.h
- *
  * SPEAr platform shared irq layer header file
  *
- * Copyright (C) 2009 ST Microelectronics
+ * Copyright (C) 2009-2012 ST Microelectronics
  * Viresh Kumar <[email protected]>
  *
  * This file is licensed under the terms of the GNU General Public

@@ -11,8 +9,8 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __PLAT_SHIRQ_H
-#define __PLAT_SHIRQ_H
+#ifndef __SPEAR_SHIRQ_H
+#define __SPEAR_SHIRQ_H
 
 #include <linux/irq.h>
 #include <linux/types.h>

@@ -63,4 +61,4 @@ int __init spear310_shirq_of_init(struct device_node *np,
 int __init spear320_shirq_of_init(struct device_node *np,
 		struct device_node *parent);
 
-#endif /* __PLAT_SHIRQ_H */
+#endif /* __SPEAR_SHIRQ_H */

Signature · 1 line

1.7.12.rc2.18.g61b472e

Viresh Kumar

author

2012-11-11 04:39 UTC #32 lore raw

PATCH 13/14 ARM: SPEAr3xx: DT: add shirq node for interrupt multiplexor

From: Shiraz Hashim <[email protected]>

shirq layer has been adapted to DT, add corresponding nodes in all SPEAr3xx variants.

---
 arch/arm/boot/dts/spear300.dtsi | 12 ++++++++++++
 arch/arm/boot/dts/spear310.dtsi | 18 ++++++++++++++++++
 arch/arm/boot/dts/spear320.dtsi | 24 ++++++++++++++++++++++--
 3 files changed, 52 insertions(+), 2 deletions(-)

arch/arm/boot/dts/spear300.dtsi +12 -0

index fdac871..090adc6 100644
@@ -52,6 +52,14 @@
 			status = "disabled";
 		};
 
+		shirq: interrupt-controller at 0x50000000 {
+			compatible = "st,spear300-shirq";
+			reg = <0x50000000 0x1000>;
+			interrupts = <28>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+		};
+
 		apb {
 			#address-cells = <1>;
 			#size-cells = <1>;

@@ -64,12 +72,16 @@
 				compatible = "arm,pl061", "arm,primecell";
 				gpio-controller;
 				reg = <0xa9000000 0x1000>;
+				interrupts = <8>;
+				interrupt-parent = <&shirq>;
 				status = "disabled";
 			};
 
 			kbd at a0000000 {
 				compatible = "st,spear300-kbd";
 				reg = <0xa0000000 0x1000>;
+				interrupts = <7>;
+				interrupt-parent = <&shirq>;
 				status = "disabled";
 			};
 		};

arch/arm/boot/dts/spear310.dtsi +18 -0

index 62fc4fb..0527e3a 100644
@@ -39,6 +39,14 @@
 			status = "disabled";
 		};
 
+		shirq: interrupt-controller at 0xb4000000 {
+			compatible = "st,spear310-shirq";
+			reg = <0xb4000000 0x1000>;
+			interrupts = <28 29 30 1>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+		};
+
 		apb {
 			#address-cells = <1>;
 			#size-cells = <1>;

@@ -49,30 +57,40 @@
 			serial at b2000000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0xb2000000 0x1000>;
+				interrupts = <8>;
+				interrupt-parent = <&shirq>;
 				status = "disabled";
 			};
 
 			serial at b2080000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0xb2080000 0x1000>;
+				interrupts = <9>;
+				interrupt-parent = <&shirq>;
 				status = "disabled";
 			};
 
 			serial at b2100000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0xb2100000 0x1000>;
+				interrupts = <10>;
+				interrupt-parent = <&shirq>;
 				status = "disabled";
 			};
 
 			serial at b2180000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0xb2180000 0x1000>;
+				interrupts = <11>;
+				interrupt-parent = <&shirq>;
 				status = "disabled";
 			};
 
 			serial at b2200000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0xb2200000 0x1000>;
+				interrupts = <12>;
+				interrupt-parent = <&shirq>;
 				status = "disabled";
 			};
 		};

arch/arm/boot/dts/spear320.dtsi +22 -2

index 582ded7..52b9c05 100644
@@ -29,7 +29,8 @@
 		clcd at 90000000 {
 			compatible = "arm,pl110", "arm,primecell";
 			reg = <0x90000000 0x1000>;
-			interrupts = <33>;
+			interrupts = <8>;
+			interrupt-parent = <&shirq>;
 			status = "disabled";
 		};

@@ -48,13 +49,24 @@
 		sdhci at 70000000 {
 			compatible = "st,sdhci-spear";
 			reg = <0x70000000 0x100>;
-			interrupts = <29>;
+			interrupts = <10>;
+			interrupt-parent = <&shirq>;
 			status = "disabled";
 		};
 
+		shirq: interrupt-controller at 0xb3000000 {
+			compatible = "st,spear320-shirq";
+			reg = <0xb3000000 0x1000>;
+			interrupts = <30 28 29 1>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+		};
+
 		spi1: spi at a5000000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0xa5000000 0x1000>;
+			interrupts = <15>;
+			interrupt-parent = <&shirq>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";

@@ -63,6 +75,8 @@
 		spi2: spi at a6000000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0xa6000000 0x1000>;
+			interrupts = <16>;
+			interrupt-parent = <&shirq>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";

@@ -87,18 +101,24 @@
 				#size-cells = <0>;
 				compatible = "snps,designware-i2c";
 				reg = <0xa7000000 0x1000>;
+				interrupts = <21>;
+				interrupt-parent = <&shirq>;
 				status = "disabled";
 			};
 
 			serial at a3000000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0xa3000000 0x1000>;
+				interrupts = <13>;
+				interrupt-parent = <&shirq>;
 				status = "disabled";
 			};
 
 			serial at a4000000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0xa4000000 0x1000>;
+				interrupts = <14>;
+				interrupt-parent = <&shirq>;
 				status = "disabled";
 			};
 		};

Signature · 1 line

1.7.12.rc2.18.g61b472e

Viresh Kumar

author

2012-11-11 04:39 UTC #33 lore raw

PATCH 14/14 ARM: SPEAr320: DT: Add SPEAr 320 HMI board support

From: Shiraz Hashim <[email protected]>

This adds support for SPEAr320-HMI board.

---
 arch/arm/boot/dts/Makefile         |   3 +-
 arch/arm/boot/dts/spear320-hmi.dts | 305 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-spear3xx/spear320.c  |   1 +
 3 files changed, 308 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/spear320-hmi.dts

arch/arm/boot/dts/Makefile +2 -1

index b994045..c3295b2 100644
@@ -84,7 +84,8 @@ dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
 	spear1340-evb.dtb
 dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
 	spear310-evb.dtb \
-	spear320-evb.dtb
+	spear320-evb.dtb \
+	spear320-hmi.dtb
 dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \

arch/arm/boot/dts/spear320-hmi.dts new file +305 -0

305 lines not on this page · raw message

arch/arm/mach-spear3xx/spear320.c +1 -0

index 707504b..66e3a0c 100644
@@ -247,6 +247,7 @@ static void __init spear320_dt_init(void)
 static const char * const spear320_dt_board_compat[] = {
 	"st,spear320",
 	"st,spear320-evb",
+	"st,spear320-hmi",
 	NULL,
 };

Signature · 1 line

1.7.12.rc2.18.g61b472e

Arnd Bergmann

maintainer

2012-11-12 15:21 UTC #34 lore raw

cover ARM: SPEAr: DT updates