core, cpu and gated clocks for mvebu
Subsystems (7)
Andrew Lunn
maintainercover core, cpu and gated clocks for mvebu
This patchset combines code from Gregory Clement, Sebastian Hesselbarth and myself to implement core clks, cpu clock and gated clocks on Marvel MVEBU SoCs.
The Armada 370/XP core clock code is a refactored version of the already submitted and ACKed code from Gregory. It has been made to fit inside a framework developed by Sebastian which can handle all MVEBU SoCs. The Armarda 370/XP SoCs have more core clocks than the older SoCs, and the framework needs to handle this. Rather than specify the clock frequencies in DT, a Sample At Reset register is used, which describes each core clock frequency.
Armarda XP is an SMP processor, with each CPU having its own clock. Gregories code for this has been taken as is.
The Armarda 370/XP clock source has been converted to the common clock framework.
Dove, Kirkword, and probably Armarda 370/XP have the ability to gate clocks to various blocks. A clk-gate clock is created for each of the gateable clocks on Dove and Kirkwood. Armarda 370/XP clock gates are currently unimplemented. Dove and Kirkwood board-dt.c and DT descriptions are then modified to make use of these clk gates.
This code has been tested on:
Kirkwood based QNAP TS219
Armarda 370 based mirabox
Armara XP based OpenBlocks
and by Sebastian on:
Dove based Cubox.
Andrew Lunn (1):
ARM: Kirkwood: switch to DT clock providers
Gregory CLEMENT (3):
clk: mvebu: add armada-370-xp CPU specific clocks
clk: armada-370-xp: add support for clock framework
clocksource: time-armada-370-xp converted to clk framework
Sebastian Hesselbarth (3):
clk: mvebu: add mvebu core clocks.
clk: mvebu: add clock gating control provider for DT
ARM: dove: switch to DT clock providers
.../devicetree/bindings/clock/mvebu-core-clock.txt | 47 ++ .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 21 + .../bindings/clock/mvebu-gated-clock.txt | 76 +++ arch/arm/Kconfig | 1 + arch/arm/boot/dts/armada-370-db.dts | 4 - arch/arm/boot/dts/armada-370-xp.dtsi | 1 + arch/arm/boot/dts/armada-370.dtsi | 7 + arch/arm/boot/dts/armada-xp.dtsi | 42 ++ arch/arm/boot/dts/dove.dtsi | 20 + arch/arm/boot/dts/kirkwood.dtsi | 22 + arch/arm/mach-dove/Kconfig | 2 + arch/arm/mach-dove/common.c | 64 +- arch/arm/mach-kirkwood/Kconfig | 2 + arch/arm/mach-kirkwood/board-dt.c | 72 ++- arch/arm/mach-mvebu/Kconfig | 6 + arch/arm/mach-mvebu/armada-370-xp.c | 9 +- arch/arm/plat-orion/include/plat/common.h | 1 + drivers/clk/Kconfig | 2 + drivers/clk/Makefile | 1 + drivers/clk/mvebu/Kconfig | 8 + drivers/clk/mvebu/Makefile | 3 + drivers/clk/mvebu/clk-core.c | 675 ++++++++++++++++++++ drivers/clk/mvebu/clk-core.h | 18 + drivers/clk/mvebu/clk-cpu.c | 155 +++++ drivers/clk/mvebu/clk-cpu.h | 18 + drivers/clk/mvebu/clk-gating-ctrl.c | 177 +++++ drivers/clk/mvebu/clk.c | 37 ++ drivers/clocksource/time-armada-370-xp.c | 11 +- include/linux/clk/mvebu.h | 23 + 29 files changed, 1487 insertions(+), 38 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt create mode 100644 drivers/clk/mvebu/Kconfig create mode 100644 drivers/clk/mvebu/Makefile create mode 100644 drivers/clk/mvebu/clk-core.c create mode 100644 drivers/clk/mvebu/clk-core.h create mode 100644 drivers/clk/mvebu/clk-cpu.c create mode 100644 drivers/clk/mvebu/clk-cpu.h create mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c create mode 100644 drivers/clk/mvebu/clk.c create mode 100644 include/linux/clk/mvebu.h
Signature · 1 line
1.7.10.4
Andrew Lunn
maintainerPATCH 1/7 clk: mvebu: add mvebu core clocks.
From: Sebastian Hesselbarth <[email protected]>
This driver allows to provide DT clocks for core clocks found on Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and ratios are determined by decoding the Sample-At-Reset registers.
Although technically correct, using a divider of 0 will lead to div_by_zero panic. Let's use a ratio of 0/1 instead to fail later with a zero clock.
--- .../devicetree/bindings/clock/mvebu-core-clock.txt | 47 ++ drivers/clk/Kconfig | 2 + drivers/clk/Makefile | 1 + drivers/clk/mvebu/Kconfig | 3 + drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/clk-core.c | 675 ++++++++++++++++++++ drivers/clk/mvebu/clk-core.h | 18 + drivers/clk/mvebu/clk.c | 23 + include/linux/clk/mvebu.h | 22 + 9 files changed, 792 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt create mode 100644 drivers/clk/mvebu/Kconfig create mode 100644 drivers/clk/mvebu/Makefile create mode 100644 drivers/clk/mvebu/clk-core.c create mode 100644 drivers/clk/mvebu/clk-core.h create mode 100644 drivers/clk/mvebu/clk.c create mode 100644 include/linux/clk/mvebu.h
Documentation/devicetree/bindings/clock/mvebu-core-clock.txt new file +47 -0
@@ -0,0 +1,47 @@ +* Core Clock bindings for Marvell MVEBU SoCs + +Marvell MVEBU SoCs usually allow to determine core clock frequencies by +reading the Sample-At-Reset (SAR) register. The core clock consumer should +specify the desired clock by having the clock ID in its "clocks" phandle cell. + +The following is a list of provided IDs and clock names on Kirkwood and Dove: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU0 clock) + 2 = l2clk (L2 Cache clock derived from CPU0 clock) + 3 = ddrclk (DDR controller clock derived from CPU0 clock) + +The following is a list of provided IDs and clock names on 370/XP: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU clock) + 2 = nbclk (L2 Cache clock) + 3 = hclk (DRAM control clock) + 4 = dramclk (DDR clock) + +Required properties: +- compatible : shall be one of the following: + "marvell,dove-core-clocks" - for Dove SoC core clocks + "marvell,kirkwood-core-clocks" - for Kirkwood SoC (except mv88f6180) + "marvell,mv88f6180-core-clocks" - for Kirkwood MV88f6180 SoC + "marvell,370-core-clocks" - For 370 SoC core clocks + "marvell,xp-core-clocks" - For XP SoC core clocks +- reg : shall be the register address of the Sample-At-Reset (SAR) register +- #clock-cells : from common clock binding; shall be set to 1 + +Optional properties: +- clock-output-names : from common clock binding; allows overwrite default clock + output names ("tclk", "cpuclk", "l2clk", "ddrclk") + +Example: + +core_clk: core-clocks at d0214 { + compatible = "marvell,dove-core-clocks"; + reg = <0xd0214 0x4>; + #clock-cells = <1>; +}; + +spi0: spi at 10600 { + compatible = "marvell,orion-spi"; + /* ... */ + /* get tclk from core clock provider */ + clocks = <&core_clk 0>; +};
drivers/clk/Kconfig +2 -0
@@ -54,3 +54,5 @@ config COMMON_CLK_MAX77686 This driver supports Maxim 77686 crystal oscillator clock. endmenu + +source "drivers/clk/mvebu/Kconfig"
drivers/clk/Makefile +1 -0
@@ -13,6 +13,7 @@ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o +obj-$(CONFIG_PLAT_ORION) += mvebu/ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endif
drivers/clk/mvebu/Kconfig new file +3 -0
@@ -0,0 +1,3 @@ +config MVEBU_CLK_CORE + bool +
drivers/clk/mvebu/Makefile new file +1 -0
@@ -0,0 +1 @@ +obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
drivers/clk/mvebu/clk-core.c new file +675 -0
675 lines not on this page · raw message
drivers/clk/mvebu/clk-core.h new file +18 -0
@@ -0,0 +1,18 @@ +/* +* * Marvell EBU clock core handling defined at reset +* +* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/ + +#ifndef __MVEBU_CLK_CORE_H +#define __MVEBU_CLK_CORE_H + +void __init mvebu_core_clk_init (void ); + +#endif
drivers/clk/mvebu/clk.c new file +23 -0
@@ -0,0 +1,23 @@ +/* +* Marvell EBU SoC clock handling. +* +* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/ +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/clk/mvebu.h> +#include <linux/of.h> +#include "clk-core.h" + +void __init mvebu_clocks_init (void ) +{ +mvebu_core_clk_init (); +}
include/linux/clk/mvebu.h new file +22 -0
@@ -0,0 +1,22 @@ +/* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#ifndef __CLK_MVEBU_H_ +#define __CLK_MVEBU_H_ + +void __init mvebu_clocks_init (void ); + +#endif
Signature · 1 line
1.7.10.4
PATCH 1/7 clk: mvebu: add mvebu core clocks.
Hi Andrew,
Quoted 41 lines · Andrew Lunn
From: Sebastian Hesselbarth <[email protected]>
This driver allows to provide DT clocks for core clocks found on Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and ratios are determined by decoding the Sample-At-Reset registers.
Although technically correct, using a divider of 0 will lead to
div_by_zeropanic. Let's use a ratio of 0/1 instead to fail later with a zero clock.Signed-off-by Gregory CLEMENT <[email protected]>Signed-off-by Sebastian Hesselbarth <[email protected]>Signed-off-by Andrew Lunn <[email protected]>--- .../devicetree/bindings/clock/mvebu-core-clock.txt | 47 ++ drivers/clk/Kconfig | 2 + drivers/clk/Makefile | 1 + drivers/clk/mvebu/Kconfig | 3 + drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/clk-core.c | 675 ++++++++++++++++++++ drivers/clk/mvebu/clk-core.h | 18 + drivers/clk/mvebu/clk.c | 23 + include/linux/clk/mvebu.h | 22 + 9 files changed, 792 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt create mode 100644 drivers/clk/mvebu/Kconfig create mode 100644 drivers/clk/mvebu/Makefile create mode 100644 drivers/clk/mvebu/clk-core.c create mode 100644 drivers/clk/mvebu/clk-core.h create mode 100644 drivers/clk/mvebu/clk.c create mode 100644 include/linux/clk/mvebu.hDocumentation/devicetree/bindings/clock/mvebu-core-clock.txt new file +3
-0@@ -0,0 +1,47 @@ +* Core Clock bindings for Marvell MVEBU SoCs + +Marvell MVEBU SoCs usually allow to determine core clock frequencies by
Documentation/devicetree/bindings/clock/mvebu-core-clock.txt line 13
Quoted 10 lines
Documentation/devicetree/bindings/clock/mvebu-core-clock.txt new file +10
-0+reading the Sample-At-Reset (SAR) register. The core clock consumer should +specify the desired clock by having the clock ID in its "clocks" phandle cell. + +The following is a list of provided IDs and clock names on Kirkwood and Dove: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU0 clock) + 2 = l2clk (L2 Cache clock derived from CPU0 clock) + 3 = ddrclk (DDR controller clock derived from CPU0 clock) + +The following is a list of provided IDs and clock names on 370/XP:
You should call them Aramda 370 and Aramda XP. You do this modification in the 2nd patch but it should be squashed in this patch.
Documentation/devicetree/bindings/clock/mvebu-core-clock.txt line 26
Quoted 13 lines
Documentation/devicetree/bindings/clock/mvebu-core-clock.txt new file +13
-0+ 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU clock) + 2 = nbclk (L2 Cache clock) + 3 = hclk (DRAM control clock) + 4 = dramclk (DDR clock) + +Required properties: +- compatible : shall be one of the following: + "marvell,dove-core-clocks" - for Dove SoC core clocks + "marvell,kirkwood-core-clocks" - for Kirkwood SoC (except mv88f6180) + "marvell,mv88f6180-core-clocks" - for Kirkwood MV88f6180 SoC + "marvell,370-core-clocks" - For 370 SoC core clocks + "marvell,xp-core-clocks" - For XP SoC core clocks
Same here.
Quoted 160 lines
Documentation/devicetree/bindings/clock/mvebu-core-clock.txt new file +21
-0+- reg : shall be the register address of the Sample-At-Reset (SAR) register +- #clock-cells : from common clock binding; shall be set to 1 + +Optional properties: +- clock-output-names : from common clock binding; allows overwrite default clock + output names ("tclk", "cpuclk", "l2clk", "ddrclk") + +Example: + +core_clk: core-clocks at d0214 { + compatible = "marvell,dove-core-clocks"; + reg = <0xd0214 0x4>; + #clock-cells = <1>; +}; + +spi0: spi at 10600 { + compatible = "marvell,orion-spi"; + /* ... */ + /* get tclk from core clock provider */ + clocks = <&core_clk 0>; +};drivers/clk/Kconfig +2
-0@@ -54,3 +54,5 @@ config COMMON_CLK_MAX77686 This driver supports Maxim 77686 crystal oscillator clock. endmenu + +source "drivers/clk/mvebu/Kconfig"drivers/clk/Makefile +1
-0@@ -13,6 +13,7 @@ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o +obj-$(CONFIG_PLAT_ORION) += mvebu/ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endifdrivers/clk/mvebu/Kconfig new file +3
-0@@ -0,0 +1,3 @@ +config MVEBU_CLK_CORE + bool +drivers/clk/mvebu/Makefile new file +1
-0@@ -0,0 +1 @@ +obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.odrivers/clk/mvebu/clk-core.c new file +95
-0@@ -0,0 +1,675 @@ +/* +* Marvell EBU clock core handling defined at reset +* +* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* Sebastian Hesselbarth <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/ +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/io.h> +#include <linux/of.h> +#include "clk-core.h" + +struct core_ratio { +int id; +const char *name; +}; + +struct core_clocks { +u32 (*get_tclk_freq)(void __iomem *sar); +u32 (*get_cpu_freq)(void __iomem *sar); +void (*get_clk_ratio)(void __iomem *sar,int id,int *mult,int *div); +const struct core_ratio *ratios; +int num_ratios; +}; + +static struct clk_onecell_data clk_data; + +static void __init mvebu_clk_core_setup (struct device_node *np, +struct core_clocks *coreclk) +{ +const char *tclk_name ="tclk" ; +const char *cpuclk_name ="cpuclk" ; +void __iomem *base; +unsigned long rate; +int n; + + base =of_iomap (np,0 ); +if (WARN_ON (!base)) +return ; + +/* +* Allocate struct for TCLK, cpu clk, and core ratio clocks +*/ + clk_data.clk_num =2 + coreclk->num_ratios; + clk_data.clks =kzalloc (clk_data.clk_num *sizeof (struct clk *), +GFP_KERNEL ); +if (WARN_ON (!clk_data.clks)) +return ; + +/* +* Register TCLK +*/ +of_property_read_string_index (np,"clock-output-names" ,0 , + &tclk_name); + rate = coreclk->get_tclk_freq (base); + clk_data.clks[0 ] =clk_register_fixed_rate (NULL , tclk_name,NULL , +CLK_IS_ROOT , rate); +WARN_ON (IS_ERR (clk_data.clks[0 ])); + +/* +* Register CPU clock +*/ +of_property_read_string_index (np,"clock-output-names" ,1 , + &cpuclk_name); + rate = coreclk->get_cpu_freq (base); + clk_data.clks[1 ] =clk_register_fixed_rate (NULL , cpuclk_name,NULL , +CLK_IS_ROOT , rate); +WARN_ON (IS_ERR (clk_data.clks[1 ])); + +/* +* Register fixed-factor clocks derived from CPU clock +*/ +for (n =0 ; n < coreclk->num_ratios; n++) { +const char *rclk_name = coreclk->ratios[n].name; +int mult, div; + +of_property_read_string_index (np,"clock-output-names" , +2 +n, &rclk_name); + coreclk->get_clk_ratio (base, coreclk->ratios[n].id, + &mult, &div); + clk_data.clks[2 +n] =clk_register_fixed_factor (NULL , rclk_name, + cpuclk_name,0 , mult, div); +WARN_ON (IS_ERR (clk_data.clks[2 +n])); + }; + +/*
drivers/clk/mvebu/clk-core.c line 105
Quoted 10 lines
drivers/clk/mvebu/clk-core.c new file +10
-0+* SAR register isn't needed anymore +*/ +iounmap (base); + +of_clk_add_provider (np, of_clk_src_onecell_get, &clk_data); +} + +#ifdef CONFIG_MACH_ARMADA_370_XP +/* +* 370/XP Sample At Reset is a 64 bit bitfiled split in two register
Add "Armada" in front of 370/XP please.
Quoted 13 lines
drivers/clk/mvebu/clk-core.c new file +13
-0+* of 32 bits +*/ + +#define SARL 0/* Low part [0:31] */ +#define SARL_AXP_PCLK_FREQ_OPT 21 +#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7 +#define SARL_A370_PCLK_FREQ_OPT 11 +#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF +#define SARL_AXP_FAB_FREQ_OPT 24 +#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF +#define SARL_A370_FAB_FREQ_OPT 15 +#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F +#define SARL_A370_TCLK_FREQ_OPT 20
drivers/clk/mvebu/clk-core.c line 128
Quoted 10 lines
drivers/clk/mvebu/clk-core.c new file +10
-0+#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1 +#define SARH 4/* High part [32:63] */ +#define SARH_AXP_PCLK_FREQ_OPT (52-32) +#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1 +#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3 +#define SARH_AXP_FAB_FREQ_OPT (51-32) +#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1 +#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4 + +static const u32 __initconst a370_tclk_frequencies[] = {
In all other part in the kernel the relatives functions to Armada 370 or Armada XP are suffixed by armada_370 or armada_xp. Could we do the same here for being consistent?
It will help when one wants to grep code relative to the armada 370 or the armada XP.
drivers/clk/mvebu/clk-core.c line 133
Quoted 5 lines
drivers/clk/mvebu/clk-core.c new file +5
-0+16600000 , + 20000000, +}; + +static u32 __init a370_get_tclk_freq (void __iomem *sar)
Same here.
Quoted 103 lines
drivers/clk/mvebu/clk-core.c new file +103
-0+{ +u8 tclk_freq_select =0 ; + + tclk_freq_select = ((readl (sar) >>SARL_A370_TCLK_FREQ_OPT ) & +SARL_A370_TCLK_FREQ_OPT_MASK ); +return a370_tclk_frequencies[tclk_freq_select]; +} + +static const u32 __initconst a370_cpu_frequencies[] = { +400000000 , +533000000 , +667000000 , +800000000 , +1000000000 , +1067000000 , +1200000000 , +}; + +static u32 __init a370_get_cpu_freq (void __iomem *sar) +{ +u32 cpu_freq; +u8 cpu_freq_select =0 ; + + cpu_freq_select = ((readl (sar) >>SARL_A370_PCLK_FREQ_OPT ) & +SARL_A370_PCLK_FREQ_OPT_MASK ); +if (cpu_freq_select >ARRAY_SIZE (a370_cpu_frequencies)) { +pr_err ("CPU freq select unsuported %d\n" , cpu_freq_select); + cpu_freq =0 ; + }else + cpu_freq = a370_cpu_frequencies[cpu_freq_select]; + +return cpu_freq; +} + +enum {A370_XP_NBCLK ,A370_XP_HCLK ,A370_XP_DRAMCLK }; + +static const struct core_ratio __initconst a370_xp_core_ratios[] = { + { .id =A370_XP_NBCLK , .name ="nbclk" }, + { .id =A370_XP_HCLK , .name ="hclk" }, + { .id =A370_XP_DRAMCLK , .name ="dramclk" }, +}; + +static const int __initconst a370_xp_nbclk_ratios[32 ][2 ] = { + {0 ,1 }, {1 ,2 }, {2 ,2 }, {2 ,2 }, + {1 ,2 }, {1 ,2 }, {1 ,1 }, {2 ,3 }, + {0 ,1 }, {1 ,2 }, {2 ,4 }, {0 ,1 }, + {1 ,2 }, {0 ,1 }, {0 ,1 }, {2 ,2 }, + {0 ,1 }, {0 ,1 }, {0 ,1 }, {1 ,1 }, + {2 ,3 }, {0 ,1 }, {0 ,1 }, {0 ,1 }, + {0 ,1 }, {0 ,1 }, {0 ,1 }, {1 ,1 }, + {0 ,1 }, {0 ,1 }, {0 ,1 }, {0 ,1 }, +}; + +static const int __initconst a370_xp_hclk_ratios[32 ][2 ] = { + {0 ,1 }, {1 ,2 }, {2 ,6 }, {2 ,3 }, + {1 ,3 }, {1 ,4 }, {1 ,2 }, {2 ,6 }, + {0 ,1 }, {1 ,6 }, {2 ,10 }, {0 ,1 }, + {1 ,4 }, {0 ,1 }, {0 ,1 }, {2 ,5 }, + {0 ,1 }, {0 ,1 }, {0 ,1 }, {1 ,2 }, + {2 ,6 }, {0 ,1 }, {0 ,1 }, {0 ,1 }, + {0 ,1 }, {0 ,1 }, {0 ,1 }, {1 ,1 }, + {0 ,1 }, {0 ,1 }, {0 ,1 }, {0 ,1 }, +}; + +static const int __initconst a370_xp_dramclk_ratios[32 ][2 ] = { + {0 ,1 }, {1 ,2 }, {2 ,3 }, {2 ,3 }, + {1 ,3 }, {1 ,2 }, {1 ,2 }, {2 ,6 }, + {0 ,1 }, {1 ,3 }, {2 ,5 }, {0 ,1 }, + {1 ,4 }, {0 ,1 }, {0 ,1 }, {2 ,5 }, + {0 ,1 }, {0 ,1 }, {0 ,1 }, {1 ,1 }, + {2 ,3 }, {0 ,1 }, {0 ,1 }, {0 ,1 }, + {0 ,1 }, {0 ,1 }, {0 ,1 }, {1 ,1 }, + {0 ,1 }, {0 ,1 }, {0 ,1 }, {0 ,1 }, +}; + +static void __init a370_xp_get_clk_ratio (u32 opt, +void __iomem *sar,int id,int *mult,int *div) +{ +switch (id) { +case A370_XP_NBCLK : + *mult = a370_xp_nbclk_ratios[opt][0 ]; + *div = a370_xp_nbclk_ratios[opt][1 ]; +break ; +case A370_XP_HCLK : + *mult = a370_xp_hclk_ratios[opt][0 ]; + *div = a370_xp_hclk_ratios[opt][1 ]; +break ; +case A370_XP_DRAMCLK : + *mult = a370_xp_dramclk_ratios[opt][0 ]; + *div = a370_xp_dramclk_ratios[opt][1 ]; +break ; + } +} + +static void __init a370_get_clk_ratio ( +void __iomem *sar,int id,int *mult,int *div) +{ +u32 opt = ((readl (sar) >>SARL_A370_FAB_FREQ_OPT ) & +SARL_A370_FAB_FREQ_OPT_MASK ); + +a370_xp_get_clk_ratio (opt, sar, id, mult, div); +} +
drivers/clk/mvebu/clk-core.c line 246
Quoted 10 lines
drivers/clk/mvebu/clk-core.c new file +10
-0+ +static const struct core_clocks a370_core_clocks = { + .get_tclk_freq = a370_get_tclk_freq, + .get_cpu_freq = a370_get_cpu_freq, + .get_clk_ratio = a370_get_clk_ratio, + .ratios = a370_xp_core_ratios, + .num_ratios =ARRAY_SIZE (a370_xp_core_ratios), +}; + +static const u32 __initconst xp_cpu_frequencies[] = {
And for Armada XP even the 'a' disappeared!
Gregory
Andrew Lunn
maintainerPATCH 2/7 clk: mvebu: add armada-370-xp CPU specific clocks
In reply to Andrew LunnFrom: Gregory CLEMENT <[email protected]>
Add Armada 370/XP specific CPU clocks
--- .../devicetree/bindings/clock/mvebu-core-clock.txt | 18 +-- .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 21 +++ drivers/clk/mvebu/Kconfig | 3 + drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/clk-core.c | 4 +- drivers/clk/mvebu/clk-cpu.c | 155 ++++++++++++++++++++ drivers/clk/mvebu/clk-cpu.h | 18 +++ drivers/clk/mvebu/clk.c | 14 ++ 8 files changed, 223 insertions(+), 11 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt create mode 100644 drivers/clk/mvebu/clk-cpu.c create mode 100644 drivers/clk/mvebu/clk-cpu.h
Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +9 -9
@@ -4,26 +4,26 @@ Marvell MVEBU SoCs usually allow to determine core clock frequencies by reading the Sample-At-Reset (SAR) register. The core clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. -The following is a list of provided IDs and clock names on Kirkwood and Dove: - 0 = tclk (Internal Bus clock) - 1 = cpuclk (CPU0 clock) - 2 = l2clk (L2 Cache clock derived from CPU0 clock) - 3 = ddrclk (DDR controller clock derived from CPU0 clock) - -The following is a list of provided IDs and clock names on 370/XP: +The following is a list of provided IDs and clock names on Armada 370/XP: 0 = tclk (Internal Bus clock) 1 = cpuclk (CPU clock) 2 = nbclk (L2 Cache clock) 3 = hclk (DRAM control clock) 4 = dramclk (DDR clock) +The following is a list of provided IDs and clock names on Kirkwood and Dove: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU0 clock) + 2 = l2clk (L2 Cache clock derived from CPU0 clock) + 3 = ddrclk (DDR controller clock derived from CPU0 clock) + Required properties: - compatible : shall be one of the following: + "marvell,armada-370-core-clocks" - For Armada 370 SoC core clocks + "marvell,armada-xp-core-clocks" - For Armada XP SoC core clocks "marvell,dove-core-clocks" - for Dove SoC core clocks "marvell,kirkwood-core-clocks" - for Kirkwood SoC (except mv88f6180) "marvell,mv88f6180-core-clocks" - for Kirkwood MV88f6180 SoC - "marvell,370-core-clocks" - For 370 SoC core clocks - "marvell,xp-core-clocks" - For XP SoC core clocks - reg : shall be the register address of the Sample-At-Reset (SAR) register - #clock-cells : from common clock binding; shall be set to 1
Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt new file +21 -0
@@ -0,0 +1,21 @@ +Device Tree Clock bindings for cpu clock of Marvell EBU platforms + +Required properties: +- compatible : shall be one of the following: + "marvell,armada-xp-cpu-clockctrl" - cpu clocks for Armada XP +- reg : Address and length of the clock complex register set +- #clock-cells : should be set to 1. +- clocks : shall be the input parent clock phandle for the clock. + +cpuclk: clock-complex at d0018700 { + #clock-cells = <1>; + compatible = "marvell,armada-xp-cpu-clockctrl"; + reg = <0xd0018700 0xA0>; + clocks = <&coreclk 1>; +} + +cpu at 0 { + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; +};
drivers/clk/mvebu/Kconfig +3 -0
@@ -1,3 +1,6 @@ config MVEBU_CLK_CORE bool +config MVEBU_CLK_CPU + bool +
drivers/clk/mvebu/Makefile +1 -0
@@ -1 +1,2 @@ obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o +obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
drivers/clk/mvebu/clk-core.c +2 -2
@@ -634,11 +634,11 @@ static const struct core_clocks mv88f6180_core_clocks = {static const __initdata struct of_device_id clk_core_match[] = { #ifdef CONFIG_MACH_ARMADA_370_XP { - .compatible ="marvell,370-core-clocks" , + .compatible ="marvell,armada-370-core-clocks" , .data = &a370_core_clocks, }, { - .compatible ="marvell,xp-core-clocks" , + .compatible ="marvell,armada-xp-core-clocks" , .data = &xp_core_clocks, }, #endif
drivers/clk/mvebu/clk-cpu.c new file +155 -0
155 lines not on this page · raw message
drivers/clk/mvebu/clk-cpu.h new file +18 -0
@@ -0,0 +1,18 @@ +/* +* Marvell MVEBU CPU clock handling. +* +* Copyright (C) 2012 Marvell +* +* Gregory CLEMENT <[email protected]> +* +* This file is licensed under the terms of the GNU General Public +* License version 2. This program is licensed "as is" without any +* warranty of any kind, whether express or implied. +*/ + +#ifndef __MVEBU_CLK_CPU_H +#define __MVEBU_CLK_CPU_H + +void __init of_cpu_clk_setup (struct device_node *node); + +#endif
drivers/clk/mvebu/clk.c +14 -0
@@ -16,8 +16,22 @@#include <linux/clk/mvebu.h> #include <linux/of.h> #include "clk-core.h" +#include "clk-cpu.h" + +static const __initconst struct of_device_id clk_match[] = { +#ifdef CONFIG_MVEBU_CLK_CPU + { + .compatible ="marvell,armada-xp-cpu-clockctrl" , + .data = of_cpu_clk_setup, + }, +#endif + { +/* sentinel */ + } +};void __init mvebu_clocks_init (void ) {mvebu_core_clk_init (); +of_clk_init (clk_match); }
Signature · 1 line
1.7.10.4
PATCH 2/7 clk: mvebu: add armada-370-xp CPU specific clocks
Dear Andrew Lunn,
Quoted 7 lines · Andrew Lunn
From: Gregory CLEMENT <[email protected]>
Add Armada 370/XP specific CPU clocks
Signed-off-by Gregory CLEMENT <[email protected]>--- .../devicetree/bindings/clock/mvebu-core-clock.txt | 18 +--
The changes to this file.
Quoted 4 lines
.../devicetree/bindings/clock/mvebu-cpu-clock.txt | 21 +++ drivers/clk/mvebu/Kconfig | 3 + drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/clk-core.c | 4 +-
And this one don't appear to belong in this commit, do they?
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Andrew Lunn
maintainerPATCH 3/7 clk: armada-370-xp: add support for clock framework
In reply to Andrew LunnFrom: Gregory CLEMENT <[email protected]>
--- arch/arm/boot/dts/armada-370.dtsi | 7 ++++++ arch/arm/boot/dts/armada-xp.dtsi | 42 +++++++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/Kconfig | 6 +++++ arch/arm/mach-mvebu/armada-370-xp.c | 9 +++++++- 4 files changed, 63 insertions(+), 1 deletion(-)
arch/arm/boot/dts/armada-370.dtsi +7 -0
@@ -75,5 +75,12 @@ #interrupts-cells = <2>; interrupts = <91>; }; + + coreclk: mvebu-sar at d0018230 { + compatible = "marvell,armada-370-core-clocks"; + reg = <0xd0018230 0x08>; + #clock-cells = <1>; + }; + }; };
arch/arm/boot/dts/armada-xp.dtsi +42 -0
54 lines not on this page · raw message
arch/arm/mach-mvebu/Kconfig +6 -0
@@ -9,11 +9,17 @@ config ARCH_MVEBU select PINCTRL select PLAT_ORION select SPARSE_IRQ + select CLKDEV_LOOKUP + select MVEBU_CLK_CORE + select MVEBU_CLK_CPU if ARCH_MVEBU menu "Marvell SOC with device tree" +config MVEBU_CLK_CPU + bool + config MACH_ARMADA_370_XP bool select ARMADA_370_XP_TIMER
arch/arm/mach-mvebu/armada-370-xp.c +8 -1
@@ -17,6 +17,7 @@#include <linux/of_platform.h> #include <linux/io.h> #include <linux/time-armada-370-xp.h> +#include <linux/clk/mvebu.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h>
@@ -37,8 +38,14 @@ void __init armada_370_xp_map_io(void)iotable_init (armada_370_xp_io_desc,ARRAY_SIZE (armada_370_xp_io_desc)); } +void __init armada_370_xp_timer_and_clk_init (void ) +{ +mvebu_clocks_init (); +armada_370_xp_timer_init (); +} +struct sys_timer armada_370_xp_timer = { - .init = armada_370_xp_timer_init, + .init = armada_370_xp_timer_and_clk_init, };static void __init armada_370_xp_dt_init (void )
Signature · 1 line
1.7.10.4
PATCH 3/7 clk: armada-370-xp: add support for clock framework
Dear Andrew Lunn,
Quoted 9 lines · Andrew Lunn
arch/arm/mach-mvebu/Kconfig +1
-0@@ -9,11 +9,17 @@ config ARCH_MVEBU select PINCTRL select PLAT_ORION select SPARSE_IRQ + select CLKDEV_LOOKUP
arch/arm/mach-mvebu/Kconfig config ARCH_MVEBU · line 22
Quoted 10 lines
arch/arm/mach-mvebu/Kconfig +5
-0+ select MVEBU_CLK_CORE + select MVEBU_CLK_CPU if ARCH_MVEBU menu "Marvell SOC with device tree" +config MVEBU_CLK_CPU + bool +
This config option is added to drivers/clk/mvebu/Kconfig in patch 2/7, so I think it shouldn't be added here in patch 3/7.
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Andrew Lunn
maintainerPATCH 4/7 clocksource: time-armada-370-xp converted to clk framework
In reply to Andrew LunnFrom: Gregory CLEMENT <[email protected]>
--- arch/arm/boot/dts/armada-370-db.dts | 4 ---- arch/arm/boot/dts/armada-370-xp.dtsi | 1 + drivers/clocksource/time-armada-370-xp.c | 11 ++++++----- 3 files changed, 7 insertions(+), 9 deletions(-)
arch/arm/boot/dts/armada-370-db.dts +0 -4
@@ -34,9 +34,5 @@ clock-frequency = <200000000>; status = "okay"; }; - timer at d0020300 { - clock-frequency = <600000000>; - status = "okay"; - }; }; };
arch/arm/boot/dts/armada-370-xp.dtsi +1 -0
@@ -62,6 +62,7 @@ compatible = "marvell,armada-370-xp-timer"; reg = <0xd0020300 0x30>; interrupts = <37>, <38>, <39>, <40>; + clocks = <&coreclk 2>; }; addr-decoding at d0020000 {
drivers/clocksource/time-armada-370-xp.c +6 -5
@@ -18,6 +18,7 @@#include <linux/init.h> #include <linux/platform_device.h> #include <linux/kernel.h> +#include <linux/clk.h> #include <linux/timer.h> #include <linux/clockchips.h> #include <linux/interrupt.h>
@@ -167,7 +168,6 @@ void __init armada_370_xp_timer_init(void)u32 u;struct device_node *np;unsigned int timer_clk; -int ret; np =of_find_compatible_node (NULL ,NULL ,"marvell,armada-370-xp-timer" ); timer_base =of_iomap (np,0 );WARN_ON (!timer_base);
@@ -179,13 +179,14 @@ void __init armada_370_xp_timer_init(void) timer_base + TIMER_CTRL_OFF); timer_clk =25000000 ; }else { -u32 clk =0 ; - ret =of_property_read_u32 (np,"clock-frequency" , &clk); -WARN_ON (!clk || ret <0 ); +unsigned long rate =0 ; +struct clk *clk =of_clk_get (np,0 ); +WARN_ON (IS_ERR (clk)); + rate =clk_get_rate (clk); u =readl (timer_base +TIMER_CTRL_OFF );writel (u & ~(TIMER0_25MHZ |TIMER1_25MHZ ), timer_base +TIMER_CTRL_OFF ); - timer_clk = clk /TIMER_DIVIDER ; + timer_clk = rate /TIMER_DIVIDER ; }/* We use timer 0 as clocksource, and timer 1 for
Signature · 1 line
1.7.10.4
PATCH 4/7 clocksource: time-armada-370-xp converted to clk framework
Dear Andrew Lunn,
Title should be "clocksource: convert time-armada-370-xp to the clk framework".
Quoted 29 lines · Andrew Lunn
drivers/clocksource/time-armada-370-xp.c +3
-4@@ -18,6 +18,7 @@#include <linux/init.h> #include <linux/platform_device.h> #include <linux/kernel.h> +#include <linux/clk.h> #include <linux/timer.h> #include <linux/clockchips.h> #include <linux/interrupt.h> @@ -167,7 +168,6 @@ void __init armada_370_xp_timer_init(void)u32 u;struct device_node *np;unsigned int timer_clk; -int ret; np =of_find_compatible_node (NULL ,NULL ,"marvell,armada-370-xp-timer" ); timer_base =of_iomap (np,0 );WARN_ON (!timer_base);@@ -179,13 +179,14 @@ void __init armada_370_xp_timer_init(void) timer_base + TIMER_CTRL_OFF); timer_clk =25000000 ; }else { -u32 clk =0 ; - ret =of_property_read_u32 (np,"clock-frequency" , &clk); -WARN_ON (!clk || ret <0 ); +unsigned long rate =0 ; +struct clk *clk =of_clk_get (np,0 );
drivers/clocksource/time-armada-370-xp.c void __init armada_370_xp_timer_init(void) · line 192
Quoted 10 lines
drivers/clocksource/time-armada-370-xp.c +3
-1+WARN_ON (IS_ERR (clk)); + rate =clk_get_rate (clk); u =readl (timer_base +TIMER_CTRL_OFF );writel (u & ~(TIMER0_25MHZ |TIMER1_25MHZ ), timer_base +TIMER_CTRL_OFF ); - timer_clk = clk /TIMER_DIVIDER ; + timer_clk = rate /TIMER_DIVIDER ; }/* We use timer 0 as clocksource, and timer 1 for
This change requires an update to Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt. The previous clock-frequency property was not documented, but maybe the new clocks property should.
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Andrew Lunn
maintainerPATCH 5/7 clk: mvebu: add clock gating control provider for DT
In reply to Andrew LunnFrom: Sebastian Hesselbarth <[email protected]>
This driver allows to provide DT clocks for clock gates found on Marvell Dove and Kirkwood SoCs. The clock gates are referenced by the phandle index of the corresponding bit in the clock gating control register to ease lookup in the datasheet.
--- .../bindings/clock/mvebu-gated-clock.txt | 76 +++++++++ drivers/clk/mvebu/Kconfig | 2 + drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/clk-gating-ctrl.c | 177 ++++++++++++++++++++ include/linux/clk/mvebu.h | 1 + 5 files changed, 257 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt create mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt new file +76 -0
@@ -0,0 +1,76 @@ +* Gated Clock bindings for Marvell Orion SoCs + +Marvell Dove and Kirkwood allow some peripheral clocks to be gated to save +some power. The clock consumer should specify the desired clock by having +the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to +the corresponding clock gating control bit in HW to ease manual clock lookup +in datasheet. + +The following is a list of provided IDs for Dove: +ID Clock Peripheral +----------------------------------- +0 usb0 USB Host 0 +1 usb1 USB Host 1 +2 ge Gigabit Ethernet +3 sata SATA Host +4 pex0 PCIe Cntrl 0 +5 pex1 PCIe Cntrl 1 +8 sdio0 SDHCI Host 0 +9 sdio1 SDHCI Host 1 +10 nand NAND Cntrl +11 camera Camera Cntrl +12 i2s0 I2S Cntrl 0 +13 i2s1 I2S Cntrl 1 +15 crypto CESA engine +21 ac97 AC97 Cntrl +22 pdma Peripheral DMA +23 xor0 XOR DMA 0 +24 xor1 XOR DMA 1 +30 gephy Gigabit Ethernel PHY +Note: gephy(30) is implemented as a parent clock of ge(2) + +The following is a list of provided IDs for Kirkwood: +ID Clock Peripheral +----------------------------------- +0 ge0 Gigabit Ethernet 0 +2 pex0 PCIe Cntrl 0 +3 usb0 USB Host 0 +4 sdio SDIO Cntrl +5 tsu Transp. Stream Unit +6 dunit SDRAM Cntrl +7 runit Runit +8 xor0 XOR DMA 0 +9 audio I2S Cntrl 0 +14 sata0 SATA Host 0 +15 sata1 SATA Host 1 +16 xor1 XOR DMA 1 +17 crypto CESA engine +18 pex1 PCIe Cntrl 1 +19 ge1 Gigabit Ethernet 0 +20 tdm Time Division Mplx + +Required properties: +- compatible : shall be one of the following: + "marvell,dove-clock-gating" - for Dove SoC clock gating + "marvell,kirkwood-clock-gating" - for Kirkwood SoC clock gating +- reg : shall be the register address of the Clock Gating Control register +- #clock-cells : from common clock binding; shall be set to 1 + +Optional properties: +- clocks : default parent clock phandle (e.g. tclk) + +Example: + +clk_gate: clock-gating-control at d0038 { + compatible = "marvell,dove-clock-gating"; + reg = <0xd0038 0x4>; + /* default parent clock is tclk */ + clocks = <&core_clk 0>; + #clock-cells = <1>; +}; + +sdio0: sdio at 92000 { + compatible = "marvell,dove-sdhci"; + /* get clk gate bit 8 (sdio0) */ + clocks = <&clk_gate 8>; +};
drivers/clk/mvebu/Kconfig +2 -0
@@ -4,3 +4,5 @@ config MVEBU_CLK_CORE config MVEBU_CLK_CPU bool +config MVEBU_CLK_GATING + bool
drivers/clk/mvebu/Makefile +1 -0
@@ -1,2 +1,3 @@ obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o +obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
drivers/clk/mvebu/clk-gating-ctrl.c new file +177 -0
177 lines not on this page · raw message
include/linux/clk/mvebu.h +1 -0
@@ -18,5 +18,6 @@#define __CLK_MVEBU_H_void __init mvebu_clocks_init (void ); +void mvebu_clk_gating_init (void );#endif
Signature · 1 line
1.7.10.4
cover Add clock gating support for Armada 370/XP
Hi Andrew,
With this 2 patches I added clock gating support for Armada 370 and Armada XP. I compiled and tested on the boards, and managed to see the new clock using debugfs.
Feel free to squash them in your series if you want.
Regards,
Gregory CLEMENT (2):
clk: mvebu: armada 370/XP add clock gating control provider for DT
arm: mvebu: armada 370/XP adding clock gating support: dt binding
.../bindings/clock/mvebu-gated-clock.txt | 43 ++++++++++++++ arch/arm/boot/dts/armada-370.dtsi | 8 +++ arch/arm/boot/dts/armada-xp.dtsi | 7 +++ arch/arm/mach-mvebu/Kconfig | 1 + drivers/clk/mvebu/clk-gating-ctrl.c | 61 ++++++++++++++++++++ 5 files changed, 120 insertions(+)
Signature · 1 line
1.7.9.5
PATCH 1/2 clk: mvebu: armada 370/XP add clock gating control provider for DT
--- .../bindings/clock/mvebu-gated-clock.txt | 43 ++++++++++++++ arch/arm/mach-mvebu/Kconfig | 1 + drivers/clk/mvebu/clk-gating-ctrl.c | 61 ++++++++++++++++++++ 3 files changed, 105 insertions(+)
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +43 -0
@@ -6,6 +6,49 @@ the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to the corresponding clock gating control bit in HW to ease manual clock lookup in datasheet. +The following is a list of provided IDs for Armada XP: +ID Clock Peripheral +----------------------------------- +0 Audio AC97 Cntrl +1 pex0_en PCIe 0 Clock out +2 pex1_en PCIe 1 Clock out +3 ge1 Gigabit Ethernet 1 +4 ge0 Gigabit Ethernet 0 +5 pex0 PCIe Cntrl 0 +9 pex1 PCIe Cntrl 1 +15 sata0 SATA Host 0 +17 sdio SDHCI Host +25 tdm Time Division Mplx +28 ddr DDR Cntrl +30 sata1 SATA Host 0 + +The following is a list of provided IDs for Armada XP: +ID Clock Peripheral +----------------------------------- +0 audio Audio Cntrl +1 ge3 Gigabit Ethernet 3 +2 ge2 Gigabit Ethernet 2 +3 ge1 Gigabit Ethernet 1 +4 ge0 Gigabit Ethernet 0 +5 pex0 PCIe Cntrl 0 +6 pex1 PCIe Cntrl 1 +7 pex2 PCIe Cntrl 2 +8 pex3 PCIe Cntrl 3 +13 bp +14 sata0lnk +15 sata0 SATA Host 0 +16 lcd LCD Cntrl +17 sdio SDHCI Host +18 usb0 USB Host 0 +19 usb1 USB Host 1 +20 usb2 USB Host 2 +22 xor0 XOR DMA 0 +23 crypto CESA engine +25 tdm Time Division Mplx +28 xor1 XOR DMA 1 +29 sata1lnk +30 sata1 SATA Host 0 + The following is a list of provided IDs for Dove: ID Clock Peripheral -----------------------------------
arch/arm/mach-mvebu/Kconfig +1 -0
@@ -12,6 +12,7 @@ config ARCH_MVEBU select CLKDEV_LOOKUP select MVEBU_CLK_CORE select MVEBU_CLK_CPU + select MVEBU_CLK_GATING if ARCH_MVEBU
drivers/clk/mvebu/clk-gating-ctrl.c +61 -0
73 lines not on this page · raw message
Signature · 1 line
1.7.9.5
Andrew Lunn
maintainerRe: [PATCH 1/2] clk: mvebu: armada 370/XP add clock gating control provider for DT
Hi Gregory
Nice work
Quoted 12 lines · Gregory CLEMENT
Signed-off-by Gregory CLEMENT <[email protected]>--- .../bindings/clock/mvebu-gated-clock.txt | 43 ++++++++++++++ arch/arm/mach-mvebu/Kconfig | 1 + drivers/clk/mvebu/clk-gating-ctrl.c | 61 ++++++++++++++++++++ 3 files changed, 105 insertions(+)Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +0
-0
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to · line 9
Quoted 4 lines
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +1
-0@@ -6,6 +6,49 @@ the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to the corresponding clock gating control bit in HW to ease manual clock lookup in datasheet. +The following is a list of provided IDs for Armada XP:
Should that the 370, not XP?
Quoted 4 lines
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +4
-0+ID Clock Peripheral +----------------------------------- +0 Audio AC97 Cntrl +1 pex0_en PCIe 0 Clock out
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to · line 23
Quoted 10 lines
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +10
-0+2 pex1_en PCIe 1 Clock out +3 ge1 Gigabit Ethernet 1 +4 ge0 Gigabit Ethernet 0 +5 pex0 PCIe Cntrl 0 +9 pex1 PCIe Cntrl 1 +15 sata0 SATA Host 0 +17 sdio SDHCI Host +25 tdm Time Division Mplx +28 ddr DDR Cntrl +30 sata1 SATA Host 0
Not many clocks there. USB? XOR? Crypto?
What is the ddr clock for? Does bad things happen if you turn it off? Kirkwood has a similar clock, dunit, which i decided not to export, since when you turn it off, the whole SoC locks up.
Thanks
Andrew
Re: [PATCH 1/2] clk: mvebu: armada 370/XP add clock gating control provider for DT
Hi Andrew
Quoted 3 lines · Andrew Lunn
Hi Gregory
Nice work
Thanks!
Quoted 17 lines · Gregory CLEMENT
Quoted 15 lines
Signed-off-by Gregory CLEMENT <[email protected]>--- .../bindings/clock/mvebu-gated-clock.txt | 43 ++++++++++++++ arch/arm/mach-mvebu/Kconfig | 1 + drivers/clk/mvebu/clk-gating-ctrl.c | 61 ++++++++++++++++++++ 3 files changed, 105 insertions(+)Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +0
-0@@ -6,6 +6,49 @@ the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to the corresponding clock gating control bit in HW to ease manual clock lookup in datasheet.
Quoted 3 lines
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to · line 9
Quoted 1 line
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +1
-0+The following is a list of provided IDs for Armada XP:Should that the 370, not XP?
Yes indeed, it was a wrong copy and paste.
Quoted 16 lines
Quoted 5 lines
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +4
-0+ID Clock Peripheral +----------------------------------- +0 Audio AC97 Cntrl +1 pex0_en PCIe 0 Clock outDocumentation/devicetree/bindings/clock/mvebu-gated-clock.txt the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to · line 23
Quoted 10 lines
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +10
-0+2 pex1_en PCIe 1 Clock out +3 ge1 Gigabit Ethernet 1 +4 ge0 Gigabit Ethernet 0 +5 pex0 PCIe Cntrl 0 +9 pex1 PCIe Cntrl 1 +15 sata0 SATA Host 0 +17 sdio SDHCI Host +25 tdm Time Division Mplx +28 ddr DDR Cntrl +30 sata1 SATA Host 0
Quoted 1 line
Not many clocks there. USB? XOR? Crypto?
Yes I was surprised too, but it was I found on the datasheet. For USB, for example you can turn the USB in low power mode but at the PHY level.
Quoted 4 lines
What is the ddr clock for? Does bad things happen if you turn it off? Kirkwood has a similar clock, dunit, which i decided not to export, since when you turn it off, the whole SoC locks up.
Well of course if you code run in DDR then it could be a problem. But I think it could be useful to turn it off when going to suspend, it the DDR can do self-refresh. In this case it should be possible to run the code from SRAM or L2 Cache.
Gregory
Andrew Lunn
maintainerRe: [PATCH 1/2] clk: mvebu: armada 370/XP add clock gating control provider for DT
Quoted 8 lines
Quoted 3 lines
What is the ddr clock for? Does bad things happen if you turn it off? Kirkwood has a similar clock, dunit, which i decided not to export, since when you turn it off, the whole SoC locks up.
Well of course if you code run in DDR then it could be a problem. But I think it could be useful to turn it off when going to suspend, it the DDR can do self-refresh. In this case it should be possible to run the code from SRAM or L2 Cache.
O.K. Just watch out for the lateinit call in the clock framework.
Andrew
Re: [PATCH 1/2] clk: mvebu: armada 370/XP add clock gating control provider for DT
Quoting Andrew Lunn (2012-11-17 05:54:35)
Quoted 11 lines
Quoted 8 lines
Quoted 3 lines
What is the ddr clock for? Does bad things happen if you turn it off? Kirkwood has a similar clock, dunit, which i decided not to export, since when you turn it off, the whole SoC locks up.
Well of course if you code run in DDR then it could be a problem. But I think it could be useful to turn it off when going to suspend, it the DDR can do self-refresh. In this case it should be possible to run the code from SRAM or L2 Cache.
O.K. Just watch out for the lateinit call in the clock framework.
CLK_IGNORE_UNUSED is the flag you want for this situation.
Regards,
Mike
Quoted 6 lines
Andrew
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Re: [PATCH 1/2] clk: mvebu: armada 370/XP add clock gating control provider for DT
In reply to Andrew LunnDear Andrew Lunn,
Quoted 10 lines · Andrew Lunn
Quoted 8 lines
Quoted 3 lines
What is the ddr clock for? Does bad things happen if you turn it off? Kirkwood has a similar clock, dunit, which i decided not to export, since when you turn it off, the whole SoC locks up.
Well of course if you code run in DDR then it could be a problem. But I think it could be useful to turn it off when going to suspend, it the DDR can do self-refresh. In this case it should be possible to run the code from SRAM or L2 Cache.
O.K. Just watch out for the lateinit call in the clock framework.
I don't think there is a problem with the dramclk and the lateinit call of the clock framework. The dramclk is a fixed factor clock, and the fixed factor clock driver does not implement the ->disable() operation. And therefore, the clk_disable_unused() code executed as the lateinit call will not be able to disable it:
if (__clk_is_enabled(clk) && clk->ops->disable) clk->ops->disable(clk->hw);
So I think we're quite safe with fixed rate clocks and fixed factor clocks in that no-one can disable them :-)
Best regards,
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Andrew Lunn
maintainerRe: [PATCH 1/2] clk: mvebu: armada 370/XP add clock gating control provider for DT
Quoted 20 lines · Thomas Petazzoni
Dear Andrew Lunn,
Quoted 10 lines · Andrew Lunn
Quoted 8 lines
Quoted 3 lines
What is the ddr clock for? Does bad things happen if you turn it off? Kirkwood has a similar clock, dunit, which i decided not to export, since when you turn it off, the whole SoC locks up.
Well of course if you code run in DDR then it could be a problem. But I think it could be useful to turn it off when going to suspend, it the DDR can do self-refresh. In this case it should be possible to run the code from SRAM or L2 Cache.
O.K. Just watch out for the lateinit call in the clock framework.
I don't think there is a problem with the dramclk and the lateinit call of the clock framework. The dramclk is a fixed factor clock, and the fixed factor clock driver does not implement the ->disable() operation. And therefore, the
clk_disable_unused()code executed as the lateinit call will not be able to disable it:
Quoted 5 lines
if (__clk_is_enabled(clk) && clk->ops->disable) clk->ops->disable(clk->hw);So I think we're quite safe with fixed rate clocks and fixed factor clocks in that no-one can disable them :-)
Hi Thomas
I don't think we are taking about the same clock. I mean the gate clock:
28 ddr DDR Cntrl
not the core clock.
Andrew
Re: [PATCH 1/2] clk: mvebu: armada 370/XP add clock gating control provider for DT
Dear Andrew Lunn,
Quoted 6 lines · Andrew Lunn
I don't think we are taking about the same clock. I mean the gate clock:
28 ddr DDR Cntrl
not the core clock.
Right, after discussion with Gregory, I found out my misunderstanding. I'm looking now as to how this clock affects the system behavior. I indeed see this clock ->disable() hook being called, but it doesn't seem to cause any sort of problem on the system. It still works nicely. So not sure this clock is actually doing something, or at least maybe not what we think it does.
Best regards,
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Sebastian Hesselbarth
maintainerRe: [PATCH 1/2] clk: mvebu: armada 370/XP add clock gating control provider for DT
In reply to Thomas PetazzoniQuoted 20 lines · Thomas Petazzoni
Dear Andrew Lunn,
Quoted 10 lines · Andrew Lunn
Quoted 8 lines
Quoted 3 lines
What is the ddr clock for? Does bad things happen if you turn it off? Kirkwood has a similar clock, dunit, which i decided not to export, since when you turn it off, the whole SoC locks up.
Well of course if you code run in DDR then it could be a problem. But I think it could be useful to turn it off when going to suspend, it the DDR can do self-refresh. In this case it should be possible to run the code from SRAM or L2 Cache.
O.K. Just watch out for the lateinit call in the clock framework.
I don't think there is a problem with the dramclk and the lateinit call of the clock framework. The dramclk is a fixed factor clock, and the fixed factor clock driver does not implement the ->disable() operation. And therefore, the
clk_disable_unused()code executed as the lateinit call will not be able to disable it:
Quoted 5 lines
if (__clk_is_enabled(clk)&& clk->ops->disable) clk->ops->disable(clk->hw);So I think we're quite safe with fixed rate clocks and fixed factor clocks in that no-one can disable them :-)
Thomas,
I guess Andrew was referring to the clock gating control bit for ddr on Armada 370 not the fixed factor clock. If there is a clk_gate installed, it will be disabled if not taken by any driver or init code. You disable either the ddr controller clock or the external ddr clock or both, but all will lead to a system lock up.
If unsure, you should remove bit 28 from clk-gating-ctrl.c and it's devicetree documentation for Armada 370. Well get all the gates straight as soon as we have more support for e.g. PMU, GEPHY, aso.
Sebastian
PATCH 2/2 arm: mvebu: armada 370/XP adding clock gating support: dt binding
In reply to Gregory CLEMENT--- arch/arm/boot/dts/armada-370.dtsi | 8 ++++++++ arch/arm/boot/dts/armada-xp.dtsi | 7 +++++++ 2 files changed, 15 insertions(+)
arch/arm/boot/dts/armada-370.dtsi +8 -0
@@ -82,5 +82,13 @@ #clock-cells = <1>; }; + clk_gate: clock-gating-control at d0018220 { + compatible = "marvell,armada-370-clock-gating"; + reg = <0xd0018220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + }; };
arch/arm/boot/dts/armada-xp.dtsi +7 -0
@@ -99,6 +99,13 @@ clocks = <&coreclk 1>; }; + clk_gate: clock-gating-control at d001821c { + compatible = "marvell,armada-xp-clock-gating"; + reg = <0xd001821c 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + system-controller at d0018200 { compatible = "marvell,armada-370-xp-system-controller"; reg = <0xd0018200 0x500>;
Signature · 1 line
1.7.9.5
Andrew Lunn
maintainerPATCH 6/7 ARM: dove: switch to DT clock providers
In reply to Andrew LunnFrom: Sebastian Hesselbarth <[email protected]>
With true DT clock providers available switch Dove clock setup in DT- enabled boards. While AUXDATA can be removed completely from bus probing, some devices still don't know about DT at all. Therefore, some clock aliases are created until the devices also move to DT.
--- arch/arm/Kconfig | 1 + arch/arm/boot/dts/dove.dtsi | 20 ++++++++++++++ arch/arm/mach-dove/Kconfig | 2 ++ arch/arm/mach-dove/common.c | 64 +++++++++++++++++++++++++++++++++---------- 4 files changed, 72 insertions(+), 15 deletions(-)
arch/arm/Kconfig +1 -0
@@ -533,6 +533,7 @@ config ARCH_IXP4XX config ARCH_DOVE bool "Marvell Dove" select ARCH_REQUIRE_GPIOLIB + select COMMON_CLK_DOVE select CPU_V7 select GENERIC_CLOCKEVENTS select MIGHT_HAVE_PCI
arch/arm/boot/dts/dove.dtsi +20 -0
@@ -31,6 +31,19 @@ reg = <0x20204 0x04>, <0x20214 0x04>; }; + core_clk: core-clocks at d0214 { + compatible = "marvell,dove-core-clocks"; + reg = <0xd0214 0x4>; + #clock-cells = <1>; + }; + + clk_gate: clock-gating-control at d0038 { + compatible = "marvell,dove-clock-gating"; + reg = <0xd0038 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + uart0: serial at 12000 { compatible = "ns16550a"; reg = <0x12000 0x100>;
@@ -100,6 +113,7 @@ cell-index = <0>; interrupts = <6>; reg = <0x10600 0x28>; + clocks = <&core_clk 0>; status = "disabled"; };
@@ -110,6 +124,7 @@ cell-index = <1>; interrupts = <5>; reg = <0x14600 0x28>; + clocks = <&core_clk 0>; status = "disabled"; };
@@ -121,6 +136,7 @@ interrupts = <11>; clock-frequency = <400000>; timeout-ms = <1000>; + clocks = <&core_clk 0>; status = "disabled"; };
@@ -128,6 +144,7 @@ compatible = "marvell,dove-sdhci"; reg = <0x92000 0x100>; interrupts = <35>, <37>; + clocks = <&clk_gate 8>; status = "disabled"; };
@@ -135,6 +152,7 @@ compatible = "marvell,dove-sdhci"; reg = <0x90000 0x100>; interrupts = <36>, <38>; + clocks = <&clk_gate 9>; status = "disabled"; };
@@ -142,6 +160,7 @@ compatible = "marvell,orion-sata"; reg = <0xa0000 0x2400>; interrupts = <62>; + clocks = <&clk_gate 3>; nr-ports = <1>; status = "disabled"; };
@@ -152,6 +171,7 @@ <0xc8000000 0x800>; reg-names = "regs", "sram"; interrupts = <31>; + clocks = <&clk_gate 15>; status = "okay"; }; };
arch/arm/mach-dove/Kconfig +2 -0
@@ -17,6 +17,8 @@ config MACH_CM_A510 config MACH_DOVE_DT bool "Marvell Dove Flattened Device Tree" + select MVEBU_CLK_CORE + select MVEBU_CLK_GATING select USE_OF help Say 'Y' here if you want your kernel to support the
arch/arm/mach-dove/common.c +49 -15
89 lines not on this page · raw message
Signature · 1 line
1.7.10.4
PATCH 6/7 ARM: dove: switch to DT clock providers
Dear Andrew Lunn,
arch/arm/boot/dts/dove.dtsi line 45
Quoted 12 lines · Andrew Lunn
arch/arm/boot/dts/dove.dtsi +12
-0+ core_clk: core-clocks at d0214 { + compatible = "marvell,dove-core-clocks"; + reg = <0xd0214 0x4>; + #clock-cells = <1>; + }; + + clk_gate: clock-gating-control at d0038 { + compatible = "marvell,dove-clock-gating"; + reg = <0xd0038 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + };
I'm nitpicking maybe, but names lack a bit of coherency here:
core_clk vs. clk_gate marvell,dove-core-clocks vs. marvell,dove-clock-gating
Maybe:
core_clk / gate_clk marvell,dove-core-clocks / marvell,dove-gating-clocks
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Andrew Lunn
maintainerPATCH 7/7 ARM: Kirkwood: switch to DT clock providers
In reply to Andrew LunnWith true DT clock providers available switch Kirkwood clock setup in DT- enabled boards. While AUXDATA can be removed completely from bus probing, some devices still don't know about DT. Therefore, some clkdev aliases are created until these devices also move to DT.
--- arch/arm/boot/dts/kirkwood.dtsi | 22 +++++++++ arch/arm/mach-kirkwood/Kconfig | 2 + arch/arm/mach-kirkwood/board-dt.c | 72 +++++++++++++++++++++++------ arch/arm/plat-orion/include/plat/common.h | 1 + 4 files changed, 84 insertions(+), 13 deletions(-)
arch/arm/boot/dts/kirkwood.dtsi +22 -0
@@ -19,6 +19,12 @@ #address-cells = <1>; #size-cells = <1>; + core_clk: core-clocks at 10030 { + compatible = "marvell,kirkwood-core-clocks"; + reg = <0x10030 0x4>; + #clock-cells = <1>; + }; + gpio0: gpio at 10100 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>;
@@ -42,6 +48,7 @@ reg = <0x12000 0x100>; reg-shift = <2>; interrupts = <33>; + clocks = <&clk_gate 7>; /* set clock-frequency in board dts */ status = "disabled"; };
@@ -51,6 +58,7 @@ reg = <0x12100 0x100>; reg-shift = <2>; interrupts = <34>; + clocks = <&clk_gate 7>; /* set clock-frequency in board dts */ status = "disabled"; };
@@ -68,12 +76,21 @@ cell-index = <0>; interrupts = <23>; reg = <0x10600 0x28>; + clocks = <&clk_gate 7>; status = "disabled"; }; + clk_gate: clock-gating-control at 2011c { + compatible = "marvell,kirkwood-clock-gating"; + reg = <0x2011c 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + wdt at 20300 { compatible = "marvell,orion-wdt"; reg = <0x20300 0x28>; + clocks = <&clk_gate 7>; status = "okay"; };
@@ -81,6 +98,8 @@ compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; interrupts = <21>; + clocks = <&clk_gate 14>, <&clk_gate 15>; + clock-names = "0", "1"; status = "disabled"; };
@@ -94,6 +113,7 @@ reg = <0x3000000 0x400>; chip-delay = <25>; /* set partition map and/or chip-delay in board dts */ + clocks = <&clk_gate 7>; status = "disabled"; };
@@ -104,6 +124,7 @@ #size-cells = <0>; interrupts = <29>; clock-frequency = <100000>; + clocks = <&clk_gate 7>; status = "disabled"; };
@@ -113,6 +134,7 @@ <0xf5000000 0x800>; reg-names = "regs", "sram"; interrupts = <22>; + clocks = <&clk_gate 17>; status = "okay"; }; };
arch/arm/mach-kirkwood/Kconfig +2 -0
@@ -46,6 +46,8 @@ config MACH_GURUPLUG config ARCH_KIRKWOOD_DT bool "Marvell Kirkwood Flattened Device Tree" + select MVEBU_CLK_CORE + select MVEBU_CLK_GATING select USE_OF help Say 'Y' here if you want your kernel to support the
arch/arm/mach-kirkwood/board-dt.c +59 -13
101 lines not on this page · raw message
arch/arm/plat-orion/include/plat/common.h +1 -0
@@ -12,6 +12,7 @@#include <linux/mv643xx_eth.h> struct dsa_platform_data ; +struct mv_sata_platform_data ; void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase,
Signature · 1 line
1.7.10.4
PATCH 7/7 ARM: Kirkwood: switch to DT clock providers
Quoted 189 lines · Andrew Lunn
With true DT clock providers available switch Kirkwood clock setup in DT- enabled boards. While AUXDATA can be removed completely from bus probing, some devices still don't know about DT. Therefore, some clkdev aliases are created until these devices also move to DT.
Signed-off-by Andrew Lunn <[email protected]>--- arch/arm/boot/dts/kirkwood.dtsi | 22 +++++++++ arch/arm/mach-kirkwood/Kconfig | 2 + arch/arm/mach-kirkwood/board-dt.c | 72 +++++++++++++++++++++++------ arch/arm/plat-orion/include/plat/common.h | 1 + 4 files changed, 84 insertions(+), 13 deletions(-)arch/arm/boot/dts/kirkwood.dtsi +22
-0@@ -19,6 +19,12 @@ #address-cells = <1>; #size-cells = <1>; + core_clk: core-clocks at 10030 { + compatible = "marvell,kirkwood-core-clocks"; + reg = <0x10030 0x4>; + #clock-cells = <1>; + }; + gpio0: gpio at 10100 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>;@@ -42,6 +48,7 @@ reg = <0x12000 0x100>; reg-shift = <2>; interrupts = <33>; + clocks = <&clk_gate 7>; /* set clock-frequency in board dts */ status = "disabled"; };@@ -51,6 +58,7 @@ reg = <0x12100 0x100>; reg-shift = <2>; interrupts = <34>; + clocks = <&clk_gate 7>; /* set clock-frequency in board dts */ status = "disabled"; };@@ -68,12 +76,21 @@ cell-index = <0>; interrupts = <23>; reg = <0x10600 0x28>; + clocks = <&clk_gate 7>; status = "disabled"; }; + clk_gate: clock-gating-control at 2011c { + compatible = "marvell,kirkwood-clock-gating"; + reg = <0x2011c 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + wdt at 20300 { compatible = "marvell,orion-wdt"; reg = <0x20300 0x28>; + clocks = <&clk_gate 7>; status = "okay"; };@@ -81,6 +98,8 @@ compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; interrupts = <21>; + clocks = <&clk_gate 14>, <&clk_gate 15>; + clock-names = "0", "1"; status = "disabled"; };@@ -94,6 +113,7 @@ reg = <0x3000000 0x400>; chip-delay = <25>; /* set partition map and/or chip-delay in board dts */ + clocks = <&clk_gate 7>; status = "disabled"; };@@ -104,6 +124,7 @@ #size-cells = <0>; interrupts = <29>; clock-frequency = <100000>; + clocks = <&clk_gate 7>; status = "disabled"; };@@ -113,6 +134,7 @@ <0xf5000000 0x800>; reg-names = "regs", "sram"; interrupts = <22>; + clocks = <&clk_gate 17>; status = "okay"; }; };arch/arm/mach-kirkwood/Kconfig +2
-0@@ -46,6 +46,8 @@ config MACH_GURUPLUG config ARCH_KIRKWOOD_DT bool "Marvell Kirkwood Flattened Device Tree" + select MVEBU_CLK_CORE + select MVEBU_CLK_GATING select USE_OF help Say 'Y' here if you want your kernel to support thearch/arm/mach-kirkwood/board-dt.c +45
-10@@ -14,11 +14,15 @@#include <linux/init.h> #include <linux/of.h> #include <linux/of_platform.h> +#include <linux/clk-provider.h> +#include <linux/clk/mvebu.h> #include <linux/kexec.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/bridge-regs.h> +#include <linux/platform_data/usb-ehci-orion.h> #include <plat/irq.h> +#include <plat/common.h> #include "common.h" static struct of_device_id kirkwood_dt_match_table[]__initdata = {@@ -26,16 +30,59 @@ static struct of_device_id kirkwood_dt_match_table[] __initdata = { { } }; -struct of_dev_auxdata kirkwood_auxdata_lookup[]__initdata = { -OF_DEV_AUXDATA ("marvell,orion-spi" ,0xf1010600 ,"orion_spi.0" ,NULL ), -OF_DEV_AUXDATA ("marvell,mv64xxx-i2c" ,0xf1011000 ,"mv64xxx_i2c.0" , -NULL ), -OF_DEV_AUXDATA ("marvell,orion-wdt" ,0xf1020300 ,"orion_wdt" ,NULL ), -OF_DEV_AUXDATA ("marvell,orion-sata" ,0xf1080000 ,"sata_mv.0" ,NULL ), -OF_DEV_AUXDATA ("marvell,orion-nand" ,0xf4000000 ,"orion_nand" ,NULL ), -OF_DEV_AUXDATA ("marvell,orion-crypto" ,0xf1030000 ,"mv_crypto" ,NULL ), - {}, -}; +/* +* There are still devices that doesn't know about DT yet. Get clock +* gates here and add a clock lookup alias, so that old platform +* devices still work. +*/ + +static void __init kirkwood_legacy_clk_init (void ) +{ + +struct device_node *np =of_find_compatible_node (NULL ,NULL , +"marvell,kirkwood-clock-gating" ); + +struct of_phandle_args clkspec; + + clkspec.np = np; + clkspec.args_count =1 ; + + clkspec.args[0 ] =CGC_BIT_GE0 ; +orion_clkdev_add (NULL ,"mv643xx_eth_port.0" , +of_clk_get_from_provider (&clkspec)); + + clkspec.args[0 ] =CGC_BIT_PEX0 ; +orion_clkdev_add ("0" ,"pcie" , +of_clk_get_from_provider (&clkspec)); + + clkspec.args[0 ] =CGC_BIT_USB0 ; +orion_clkdev_add (NULL ,"orion-ehci.0" , +of_clk_get_from_provider (&clkspec)); + + clkspec.args[0 ] =CGC_BIT_XOR0 ; +orion_clkdev_add (NULL ,"mv_xor_shared.0" , +of_clk_get_from_provider (&clkspec)); + + clkspec.args[0 ] =CGC_BIT_XOR1 ; +orion_clkdev_add (NULL ,"mv_xor_shared.1" , +of_clk_get_from_provider (&clkspec)); + + clkspec.args[0 ] =CGC_BIT_PEX1 ; +orion_clkdev_add ("1" ,"pcie" , +of_clk_get_from_provider (&clkspec)); +
arch/arm/mach-kirkwood/board-dt.c static struct of_device_id kirkwood_dt_match_table[] __initdata = { · line 83
Quoted 10 lines
arch/arm/mach-kirkwood/board-dt.c +10
-0+ clkspec.args[0 ] =CGC_BIT_GE1 ; +orion_clkdev_add (NULL ,"mv643xx_eth_port.1" , +of_clk_get_from_provider (&clkspec)); + +} + +static void __init kirkwood_of_clk_init (void ) +{ +mvebu_clocks_init (); +mvebu_clk_gating_init ();
What do you think about moving mvebu_clk_gating_init() inside mvebu_clocks_init ?
It is what we have done for the cpu_clk.
Quoted 37 lines
arch/arm/mach-kirkwood/board-dt.c +4
-3+kirkwood_legacy_clk_init (); +}static void __init kirkwood_dt_init (void ) {@@ -54,7 +101,7 @@ static void __init kirkwood_dt_init(void)kirkwood_l2_init ();/* Setup root of clk tree */ -kirkwood_clk_init (); +kirkwood_of_clk_init ();/* internal devices that every board has */ kirkwood_xor0_init ();@@ -94,8 +141,7 @@ static void __init kirkwood_dt_init(void)if (of_machine_is_compatible ("keymile,km_kirkwood" ))km_kirkwood_init (); -of_platform_populate (NULL , kirkwood_dt_match_table, - kirkwood_auxdata_lookup,NULL ); +of_platform_populate (NULL , kirkwood_dt_match_table,NULL ,NULL ); }static const char *kirkwood_dt_board_compat[] = {arch/arm/plat-orion/include/plat/common.h +1
-0@@ -12,6 +12,7 @@#include <linux/mv643xx_eth.h> struct dsa_platform_data ; +struct mv_sata_platform_data ; void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase,
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
cover core, cpu and gated clocks for mvebu
In reply to Andrew LunnDear Andrew Lunn,
Quoted 15 lines · Andrew Lunn
This patchset combines code from Gregory Clement, Sebastian Hesselbarth and myself to implement core clks, cpu clock and gated clocks on Marvel MVEBU SoCs.
The Armada 370/XP core clock code is a refactored version of the already submitted and ACKed code from Gregory. It has been made to fit inside a framework developed by Sebastian which can handle all MVEBU SoCs. The Armarda 370/XP SoCs have more core clocks than the older SoCs, and the framework needs to handle this. Rather than specify the clock frequencies in DT, a Sample At Reset register is used, which describes each core clock frequency.
Armarda XP is an SMP processor, with each CPU having its own clock. Gregories code for this has been taken as is.
Quoted 8 lines
The Armarda 370/XP clock source has been converted to the common clock framework.
Dove, Kirkword, and probably Armarda 370/XP have the ability to gate clocks to various blocks. A clk-gate clock is created for each of the gateable clocks on Dove and Kirkwood. Armarda 370/XP clock gates are currently unimplemented. Dove and Kirkwood
board-dt.cand DT descriptions are then modified to make use of these clk gates.
I had a quick look and made a few comments, but overall, it looks really great. I really hope we can get this in 3.8.
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Andrew Lunn
maintainercover core, cpu and gated clocks for mvebu
Quoted 2 lines
I had a quick look and made a few comments, but overall, it looks really great. I really hope we can get this in 3.8.
Hi Thomas
Thanks for the quick feedback.
It looks like i squashed some patches from Sebastian in the wrong place. I will fix this and your other comments. I will probably send out a new version tomorrow to give others chance to comment.
Andrew
cover core, cpu and gated clocks for mvebu
In reply to Andrew LunnQuoted 26 lines · Andrew Lunn
This patchset combines code from Gregory Clement, Sebastian Hesselbarth and myself to implement core clks, cpu clock and gated clocks on Marvel MVEBU SoCs.
The Armada 370/XP core clock code is a refactored version of the already submitted and ACKed code from Gregory. It has been made to fit inside a framework developed by Sebastian which can handle all MVEBU SoCs. The Armarda 370/XP SoCs have more core clocks than the older SoCs, and the framework needs to handle this. Rather than specify the clock frequencies in DT, a Sample At Reset register is used, which describes each core clock frequency.
Armarda XP is an SMP processor, with each CPU having its own clock. Gregories code for this has been taken as is.
The Armarda 370/XP clock source has been converted to the common clock framework.
Dove, Kirkword, and probably Armarda 370/XP have the ability to gate clocks to various blocks. A clk-gate clock is created for each of the gateable clocks on Dove and Kirkwood. Armarda 370/XP clock gates are currently unimplemented. Dove and Kirkwood
board-dt.cand DT descriptions are then modified to make use of these clk gates.This code has been tested on:
Quoted 8 lines
Kirkwood based QNAP TS219
Armarda 370 based mirabox
Armara XP based OpenBlocksand by Sebastian on:
Dove based Cubox.
Hi Andrew,
great job!
I have only few comments on the first patch.
Besides this I have tested the whole series on my Armada 370 and Armada XP development boards. With these boards I had the possibility to change the frequency configuration. I also enable to COMMON_CLK_DEBUG to check the clock rate value, and after having done the tests on few combination and I didn't see any regression.
For the first 4 patches you can add my
Tested-by Gregory CLEMENT <[email protected]>.
Mike I hope you will be able to have a look on the next version. With the few incoming changes in the next version, this series will be at least as good as mine and the only notable difference for the first patches of this series is just adding new SoCs with more or less the same framework.
Thanks
Quoted 56 lines
Andrew Lunn (1):
ARM: Kirkwood: switch to DT clock providersGregory CLEMENT (3):
clk: mvebu: add armada-370-xp CPU specific clocks
clk: armada-370-xp: add support for clock framework
clocksource: time-armada-370-xp converted to clk frameworkSebastian Hesselbarth (3):
clk: mvebu: add mvebu core clocks.
clk: mvebu: add clock gating control provider for DT
ARM: dove: switch to DT clock providers.../devicetree/bindings/clock/mvebu-core-clock.txt | 47 ++ .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 21 + .../bindings/clock/mvebu-gated-clock.txt | 76 +++ arch/arm/Kconfig | 1 + arch/arm/boot/dts/armada-370-db.dts | 4 - arch/arm/boot/dts/armada-370-xp.dtsi | 1 + arch/arm/boot/dts/armada-370.dtsi | 7 + arch/arm/boot/dts/armada-xp.dtsi | 42 ++ arch/arm/boot/dts/dove.dtsi | 20 + arch/arm/boot/dts/kirkwood.dtsi | 22 + arch/arm/mach-dove/Kconfig | 2 + arch/arm/mach-dove/common.c | 64 +- arch/arm/mach-kirkwood/Kconfig | 2 + arch/arm/mach-kirkwood/board-dt.c | 72 ++- arch/arm/mach-mvebu/Kconfig | 6 + arch/arm/mach-mvebu/armada-370-xp.c | 9 +- arch/arm/plat-orion/include/plat/common.h | 1 + drivers/clk/Kconfig | 2 + drivers/clk/Makefile | 1 + drivers/clk/mvebu/Kconfig | 8 + drivers/clk/mvebu/Makefile | 3 + drivers/clk/mvebu/clk-core.c | 675 ++++++++++++++++++++ drivers/clk/mvebu/clk-core.h | 18 + drivers/clk/mvebu/clk-cpu.c | 155 +++++ drivers/clk/mvebu/clk-cpu.h | 18 + drivers/clk/mvebu/clk-gating-ctrl.c | 177 +++++ drivers/clk/mvebu/clk.c | 37 ++ drivers/clocksource/time-armada-370-xp.c | 11 +- include/linux/clk/mvebu.h | 23 + 29 files changed, 1487 insertions(+), 38 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt create mode 100644 drivers/clk/mvebu/Kconfig create mode 100644 drivers/clk/mvebu/Makefile create mode 100644 drivers/clk/mvebu/clk-core.c create mode 100644 drivers/clk/mvebu/clk-core.h create mode 100644 drivers/clk/mvebu/clk-cpu.c create mode 100644 drivers/clk/mvebu/clk-cpu.h create mode 100644 drivers/clk/mvebu/clk-gating-ctrl.c create mode 100644 drivers/clk/mvebu/clk.c create mode 100644 include/linux/clk/mvebu.h
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Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com