ioat: remove chanerr mask setting for IOAT v3.x
Subsystems (2)
PATCH v2 1/1 ioat: remove chanerr mask setting for IOAT v3.x
The existing code set a value in the PCI_CHANERRMSK_INT register for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when the hardware was released. There is no need for this code.
---
drivers/dma/ioat/dma_v3.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-)
drivers/dma/ioat/dma_v3.c +1 -6
@@ -1126,12 +1126,7 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan) chanerr =readl (chan->reg_base +IOAT_CHANERR_OFFSET );writel (chanerr, chan->reg_base +IOAT_CHANERR_OFFSET ); -/* -= IOAT ver.3 workarounds =- */ -/* Write CHANERRMSK_INT with 3E07h to mask out the errors -* that can cause stability issues for IOAT ver.3, and clear any -* pending errors -*/ -pci_write_config_dword (pdev,IOAT_PCI_CHANERRMASK_INT_OFFSET ,0x3e07 ); +/* clear any pending errors */ err =pci_read_config_dword (pdev,IOAT_PCI_CHANERR_INT_OFFSET , &chanerr);if (err) {dev_err (&pdev->dev,"channel error register unreachable\n" );
Greg KH
maintainerQuoted 10 lines · Dave Jiang
The existing code set a value in the
PCI_CHANERRMSK_INTregister for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when the hardware was released. There is no need for this code.Signed-off-by Dave Jiang <[email protected]>---
drivers/dma/ioat/dma_v3.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-)
<formletter>
This is not the correct way to submit patches for inclusion in the stable kernel tree. Please read Documentation/stable_kernel_rules.txt for how to do this properly.
</formletter>
Quoted 6 lines · Dave Jiang
The existing code set a value in the
PCI_CHANERRMSK_INTregister for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when the hardware was released. There is no need for this code.Signed-off-by Dave Jiang <[email protected]>
Quoted 16 lines · Dave
The existing code set a value in the
PCI_CHANERRMSK_INTregister for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when the hardware was released. There is no need for this code.Signed-off-by Dave Jiang <[email protected]>---
drivers/dma/ioat/dma_v3.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-)drivers/dma/ioat/dma_v3.c +0
-0
drivers/dma/ioat/dma_v3.c static int ioat3_reset_hw(struct ioat_chan_common *chan) · line 1133
Quoted 8 lines
drivers/dma/ioat/dma_v3.c +0
-5@@ -1126,12 +1126,7 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan) chanerr =readl (chan->reg_base +IOAT_CHANERR_OFFSET );writel (chanerr, chan->reg_base +IOAT_CHANERR_OFFSET ); -/* -= IOAT ver.3 workarounds =- */ -/* Write CHANERRMSK_INT with 3E07h to mask out the errors -* that can cause stability issues for IOAT ver.3, and clear any -* pending errors -*/
What is this code based against? i dont have above lines in -rc1 or my next?
Quoted 6 lines
drivers/dma/ioat/dma_v3.c +1
-1-pci_write_config_dword (pdev,IOAT_PCI_CHANERRMASK_INT_OFFSET ,0x3e07 ); +/* clear any pending errors */ err =pci_read_config_dword (pdev,IOAT_PCI_CHANERR_INT_OFFSET , &chanerr);if (err) {dev_err (&pdev->dev,"channel error register unreachable\n" );
Quoted 20 lines · Vinod Koul
Quoted 19 lines · Dave
The existing code set a value in the
PCI_CHANERRMSK_INTregister for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when the hardware was released. There is no need for this code.Signed-off-by Dave Jiang <[email protected]>---
drivers/dma/ioat/dma_v3.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-)drivers/dma/ioat/dma_v3.c +0
-0@@ -1126,12 +1126,7 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan) chanerr =readl (chan->reg_base +IOAT_CHANERR_OFFSET );writel (chanerr, chan->reg_base +IOAT_CHANERR_OFFSET );
Quoted 6 lines
drivers/dma/ioat/dma_v3.c static int ioat3_reset_hw(struct ioat_chan_common *chan) · line 1133
Quoted 5 lines
drivers/dma/ioat/dma_v3.c +0
-5-/* -= IOAT ver.3 workarounds =- */ -/* Write CHANERRMSK_INT with 3E07h to mask out the errors -* that can cause stability issues for IOAT ver.3, and clear any -* pending errors -*/ What is this code based against? i dont have above lines in -rc1 or my next?
Looking at the Linus tree it looks like it's already upstream somehow? Commit 6decffd.
Quoted 6 lines
Quoted 6 lines
drivers/dma/ioat/dma_v3.c +1
-1-pci_write_config_dword (pdev,IOAT_PCI_CHANERRMASK_INT_OFFSET ,0x3e07 ); +/* clear any pending errors */ err =pci_read_config_dword (pdev,IOAT_PCI_CHANERR_INT_OFFSET , &chanerr);if (err) {dev_err (&pdev->dev,"channel error register unreachable\n" );