ARM: EXYNOS5250: Add support for USB 3.0 dwc3 controller

PATCH Superseded Vivek Gautam 3 participants 7 messages Nov 8, 2012 – Dec 19, 2012

Subsystems (5)

Device tree bindings Arm (32-bit) USB Arm sub-architectures +1 more subsystems

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Vivek Gautam

author

2012-11-08 08:27 UTC #0 lore raw

PATCH v2 1/1 ARM: EXYNOS5250: Add support for USB 3.0 dwc3 controller

Changes from v1:
- Changed the device node name from 'dwc3' to 'usb@12000000'.
- Added the documentation for device tree bindings for dwc3 controller.

Based on changes for USB 2.0:
'https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-November/022046.html'

Tested with required driver DT patches for dwc3-exynos:
http://www.spinics.net/lists/linux-usb/msg73857.html
and USB 3.0 phy support patches:
https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-November/021926.html

Vivek Gautam (1):
ARM: Exynos5250: Enabling dwc3-exynos driver

 .../devicetree/bindings/usb/exynos-usb.txt         |   14 +++++++++++
 arch/arm/boot/dts/exynos5250.dtsi                  |    6 +++++
 arch/arm/mach-exynos/Kconfig                       |    1 +
 arch/arm/mach-exynos/clock-exynos5.c               |   24 ++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    2 +
 6 files changed, 48 insertions(+), 0 deletions(-)

Signature · 1 line

1.7.6.5

Vivek Gautam

author

2012-11-08 08:29 UTC #1 lore raw

PATCH v2 1/1 ARM: Exynos5250: Enabling dwc3-exynos driver

Adding DWC3 device tree node for Exynos5250 along with the device address and clock support needed for the controller.

Signed-off-by Vivek Gautam <[email protected]>

---
 .../devicetree/bindings/usb/exynos-usb.txt         |   14 +++++++++++
 arch/arm/boot/dts/exynos5250.dtsi                  |    6 +++++
 arch/arm/mach-exynos/Kconfig                       |    1 +
 arch/arm/mach-exynos/clock-exynos5.c               |   24 ++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    2 +
 6 files changed, 48 insertions(+), 0 deletions(-)

Documentation/devicetree/bindings/usb/exynos-usb.txt +14 -0

index 5ff3def1..a7e3eaa 100644
@@ -38,3 +38,17 @@ Example:
 		reg = <0x12120000 0x100>;
 		interrupts = <0 71 0>;
 	};
+
+DWC3
+Required properties:
+ - compatible: should be "samsung,exynos-dwc3" for USB 3.0 DWC3 controller.
+ - reg: physical base address of the controller and length of memory mapped
+   region.
+ - interrupts: interrupt number to the cpu.
+
+Example:
+	usb@12000000 {
+		compatible = "samsung,exynos-dwc3";
+		reg = <0x12000000 0x10000>;
+		interrupts = <0 72 0>;
+	};

arch/arm/boot/dts/exynos5250.dtsi +6 -0

index f18abe0..d349636 100644
@@ -68,6 +68,12 @@
 		interrupts = <0 96 0>;
 	};
 
+	usb@12000000 {
+		compatible = "samsung,exynos-dwc3";
+		reg = <0x12000000 0x10000>;
+		interrupts = <0 72 0>;
+	};
+
 	rtc {
 		compatible = "samsung,s3c6410-rtc";
 		reg = <0x101E0000 0x100>;

arch/arm/mach-exynos/Kconfig +1 -0

index bb3b09a..588814a 100644
@@ -422,6 +422,7 @@ config MACH_EXYNOS5_DT
 	select ARM_AMBA
 	select SOC_EXYNOS5250
 	select USE_OF
+	select USB_ARCH_HAS_XHCI
 	help
 	  Machine support for Samsung EXYNOS5 machine with device tree enabled.
 	  Select this if a fdt blob is available for the EXYNOS5 SoC based board.

arch/arm/mach-exynos/clock-exynos5.c +24 -0

index a88e0d9..ee094ee 100644
@@ -740,6 +740,11 @@ static struct clk exynos5_init_clocks_off[] = {
 		.enable		= exynos5_clk_ip_fsys_ctrl ,
 		.ctrlbit	= (1 << 18),
 	}, {
+		.name		= "usbdrd30",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 19),
+	}, {
 		.name		= "usbotg",
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 7),

@@ -1004,6 +1009,16 @@ struct clksrc_sources exynos5_clkset_group = {
 	.nr_sources	= ARRAY_SIZE(exynos5_clkset_group_list),
 };
 
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+	[0] = &exynos5_clk_mout_mpll.clk,
+	[1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+	.sources        = exynos5_clkset_usbdrd30_list,
+	.nr_sources     = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
 /* Possible clock sources for aclk_266_gscl_sub Mux */
 static struct clk *clk_src_gscl_266_list[] = {
 	[0] = &clk_ext_xtal_mux,

@@ -1288,6 +1303,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
 			.parent		= &exynos5_clk_mout_cpll.clk,
 		},
 		.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+	}, {
+		.clk    = {
+			.name           = "sclk_usbdrd30",
+			.enable         = exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit        = (1 << 28),
+		},
+		.sources = &exynos5_clkset_usbdrd30,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 },
 	},
 };

arch/arm/mach-exynos/include/mach/map.h +1 -0

index 471ffaf..064ca1c 100644
@@ -197,6 +197,7 @@
 #define EXYNOS4_PA_EHCI			0x12580000
 #define EXYNOS4_PA_OHCI			0x12590000
 #define EXYNOS4_PA_HSPHY		0x125B0000
+#define EXYNOS5_PA_DRD			0x12000000
 #define EXYNOS5_PA_EHCI			0x12110000
 #define EXYNOS5_PA_OHCI			0x12120000
 #define EXYNOS4_PA_MFC			0x13400000

arch/arm/mach-exynos/mach-exynos5-dt.c +2 -0

index c03f3dd..3032222 100644
@@ -90,6 +90,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 				"s5p-ehci", NULL),
 	OF_DEV_AUXDATA("samsung,exynos-ohci", EXYNOS5_PA_OHCI,
 				"exynos-ohci", NULL),
+	OF_DEV_AUXDATA("samsung,exynos-dwc3", EXYNOS5_PA_DRD,
+				"exynos-dwc3", NULL),
 	{},
 };

Signature · 1 line

1.7.6.5

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Signature · 2 lines

Thanks & Regards
Vivek

Grant Likely

2012-12-06 10:15 UTC #3 lore raw

PATCH v2 1/1 ARM: Exynos5250: Enabling dwc3-exynos driver

In reply to Vivek Gautam

Quoted 18 lines · Vivek Gautam

Adding DWC3 device tree node for Exynos5250 along with the device address and clock support needed for the controller.
Signed-off-by Vivek Gautam <[email protected]>
---
 .../devicetree/bindings/usb/exynos-usb.txt         |   14 +++++++++++
 arch/arm/boot/dts/exynos5250.dtsi                  |    6 +++++
 arch/arm/mach-exynos/Kconfig                       |    1 +
 arch/arm/mach-exynos/clock-exynos5.c               |   24 ++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    2 +
 6 files changed, 48 insertions(+), 0 deletions(-)
Documentation/devicetree/bindings/usb/exynos-usb.txt +0 -0
index 5ff3def1..a7e3eaa 100644

Documentation/devicetree/bindings/usb/exynos-usb.txt Example: · line 44

Quoted 7 lines

Documentation/devicetree/bindings/usb/exynos-usb.txt +4 -0

@@ -38,3 +38,17 @@ Example:
 		reg = <0x12120000 0x100>;
 		interrupts = <0 71 0>;
 	};
+
+DWC3
+Required properties:
+ - compatible: should be "samsung,exynos-dwc3" for USB 3.0 DWC3 controller.

Nit: Please use a specific chip in compatible strings. ie. "samsung,exynos5250-dwc3". Newer parts using the same core can claim compatibility by including the older string in the compatible list.

Quoted 121 lines

Documentation/devicetree/bindings/usb/exynos-usb.txt +10 -0

+ - reg: physical base address of the controller and length of memory mapped
+   region.
+ - interrupts: interrupt number to the cpu.
+
+Example:
+	usb at 12000000 {
+		compatible = "samsung,exynos-dwc3";
+		reg = <0x12000000 0x10000>;
+		interrupts = <0 72 0>;
+	};

arch/arm/boot/dts/exynos5250.dtsi +6 -0

index f18abe0..d349636 100644
@@ -68,6 +68,12 @@
 		interrupts = <0 96 0>;
 	};
 
+	usb at 12000000 {
+		compatible = "samsung,exynos-dwc3";
+		reg = <0x12000000 0x10000>;
+		interrupts = <0 72 0>;
+	};
+
 	rtc {
 		compatible = "samsung,s3c6410-rtc";
 		reg = <0x101E0000 0x100>;

arch/arm/mach-exynos/Kconfig +1 -0

index bb3b09a..588814a 100644
@@ -422,6 +422,7 @@ config MACH_EXYNOS5_DT
 	select ARM_AMBA
 	select SOC_EXYNOS5250
 	select USE_OF
+	select USB_ARCH_HAS_XHCI
 	help
 	  Machine support for Samsung EXYNOS5 machine with device tree enabled.
 	  Select this if a fdt blob is available for the EXYNOS5 SoC based board.

arch/arm/mach-exynos/clock-exynos5.c +24 -0

index a88e0d9..ee094ee 100644
@@ -740,6 +740,11 @@ static struct clk exynos5_init_clocks_off[] = {
 		.enable		= exynos5_clk_ip_fsys_ctrl ,
 		.ctrlbit	= (1 << 18),
 	}, {
+		.name		= "usbdrd30",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 19),
+	}, {
 		.name		= "usbotg",
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 7),

@@ -1004,6 +1009,16 @@ struct clksrc_sources exynos5_clkset_group = {
 	.nr_sources	= ARRAY_SIZE(exynos5_clkset_group_list),
 };
 
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+	[0] = &exynos5_clk_mout_mpll.clk,
+	[1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+	.sources        = exynos5_clkset_usbdrd30_list,
+	.nr_sources     = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
 /* Possible clock sources for aclk_266_gscl_sub Mux */
 static struct clk *clk_src_gscl_266_list[] = {
 	[0] = &clk_ext_xtal_mux,

@@ -1288,6 +1303,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
 			.parent		= &exynos5_clk_mout_cpll.clk,
 		},
 		.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+	}, {
+		.clk    = {
+			.name           = "sclk_usbdrd30",
+			.enable         = exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit        = (1 << 28),
+		},
+		.sources = &exynos5_clkset_usbdrd30,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 },
 	},
 };

arch/arm/mach-exynos/include/mach/map.h +1 -0

index 471ffaf..064ca1c 100644
@@ -197,6 +197,7 @@
 #define EXYNOS4_PA_EHCI			0x12580000
 #define EXYNOS4_PA_OHCI			0x12590000
 #define EXYNOS4_PA_HSPHY		0x125B0000
+#define EXYNOS5_PA_DRD			0x12000000
 #define EXYNOS5_PA_EHCI			0x12110000
 #define EXYNOS5_PA_OHCI			0x12120000
 #define EXYNOS4_PA_MFC			0x13400000

arch/arm/mach-exynos/mach-exynos5-dt.c +2 -0

index c03f3dd..3032222 100644
@@ -90,6 +90,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 				"s5p-ehci", NULL),
 	OF_DEV_AUXDATA("samsung,exynos-ohci", EXYNOS5_PA_OHCI,
 				"exynos-ohci", NULL),
+	OF_DEV_AUXDATA("samsung,exynos-dwc3", EXYNOS5_PA_DRD,
+				"exynos-dwc3", NULL),
 	{},
 };

Signature · 7 lines

1.7.6.5


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Signature · 2 lines

Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.

Vivek Gautam

2012-12-06 10:33 UTC #4 lore raw

PATCH v2 1/1 ARM: Exynos5250: Enabling dwc3-exynos driver

Hi Grant,

Quoted 14 lines · Grant Likely

Quoted 13 lines · Vivek Gautam
Adding DWC3 device tree node for Exynos5250 along with the device address and clock support needed for the controller.
Signed-off-by Vivek Gautam <[email protected]>
---
 .../devicetree/bindings/usb/exynos-usb.txt         |   14 +++++++++++
 arch/arm/boot/dts/exynos5250.dtsi                  |    6 +++++
 arch/arm/mach-exynos/Kconfig                       |    1 +
 arch/arm/mach-exynos/clock-exynos5.c               |   24 ++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    2 +
 6 files changed, 48 insertions(+), 0 deletions(-)

Quoted 17 lines

Documentation/devicetree/bindings/usb/exynos-usb.txt Example: · line 44
Quoted 12 lines
Documentation/devicetree/bindings/usb/exynos-usb.txt +4 -0
index 5ff3def1..a7e3eaa 100644
@@ -38,3 +38,17 @@ Example:
              reg = <0x12120000 0x100>;
              interrupts = <0 71 0>;
      };
+
+DWC3
+Required properties:
+ - compatible: should be "samsung,exynos-dwc3" for USB 3.0 DWC3 controller.
Nit: Please use a specific chip in compatible strings. ie. "samsung,exynos5250-dwc3". Newer parts using the same core can claim compatibility by including the older string in the compatible list.

The compatible string "samsung,exynos-dwc3" is added in accordance with the driver dt changes
present at drivers "drivers/usb/dwc3/dwc3-exynos.c". Should i be amending the driver side also likewise ?

Quoted 129 lines

Quoted 117 lines

Documentation/devicetree/bindings/usb/exynos-usb.txt +10 -0

+ - reg: physical base address of the controller and length of memory mapped
+   region.
+ - interrupts: interrupt number to the cpu.
+
+Example:
+     usb at 12000000 {
+             compatible = "samsung,exynos-dwc3";
+             reg = <0x12000000 0x10000>;
+             interrupts = <0 72 0>;
+     };

arch/arm/boot/dts/exynos5250.dtsi +6 -0

index f18abe0..d349636 100644
@@ -68,6 +68,12 @@
              interrupts = <0 96 0>;
      };
 
+     usb at 12000000 {
+             compatible = "samsung,exynos-dwc3";
+             reg = <0x12000000 0x10000>;
+             interrupts = <0 72 0>;
+     };
+
      rtc {
              compatible = "samsung,s3c6410-rtc";
              reg = <0x101E0000 0x100>;

arch/arm/mach-exynos/Kconfig +1 -0

index bb3b09a..588814a 100644
@@ -422,6 +422,7 @@ config MACH_EXYNOS5_DT
      select ARM_AMBA
      select SOC_EXYNOS5250
      select USE_OF
+     select USB_ARCH_HAS_XHCI
      help
        Machine support for Samsung EXYNOS5 machine with device tree enabled.
        Select this if a fdt blob is available for the EXYNOS5 SoC based board.

arch/arm/mach-exynos/clock-exynos5.c +24 -0

index a88e0d9..ee094ee 100644
@@ -740,6 +740,11 @@ static struct clk exynos5_init_clocks_off[] = {
              .enable         = exynos5_clk_ip_fsys_ctrl ,
              .ctrlbit        = (1 << 18),
      }, {
+             .name           = "usbdrd30",
+             .parent         = &exynos5_clk_aclk_200.clk,
+             .enable         = exynos5_clk_ip_fsys_ctrl,
+             .ctrlbit        = (1 << 19),
+     }, {
              .name           = "usbotg",
              .enable         = exynos5_clk_ip_fsys_ctrl,
              .ctrlbit        = (1 << 7),

@@ -1004,6 +1009,16 @@ struct clksrc_sources exynos5_clkset_group = {
      .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
 };
 
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+     [0] = &exynos5_clk_mout_mpll.clk,
+     [1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+     .sources        = exynos5_clkset_usbdrd30_list,
+     .nr_sources     = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
 /* Possible clock sources for aclk_266_gscl_sub Mux */
 static struct clk *clk_src_gscl_266_list[] = {
      [0] = &clk_ext_xtal_mux,

@@ -1288,6 +1303,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
                      .parent         = &exynos5_clk_mout_cpll.clk,
              },
              .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+     }, {
+             .clk    = {
+                     .name           = "sclk_usbdrd30",
+                     .enable         = exynos5_clksrc_mask_fsys_ctrl,
+                     .ctrlbit        = (1 << 28),
+             },
+             .sources = &exynos5_clkset_usbdrd30,
+             .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 },
+             .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 },
      },
 };

arch/arm/mach-exynos/include/mach/map.h +1 -0

index 471ffaf..064ca1c 100644
@@ -197,6 +197,7 @@
 #define EXYNOS4_PA_EHCI                      0x12580000
 #define EXYNOS4_PA_OHCI                      0x12590000
 #define EXYNOS4_PA_HSPHY             0x125B0000
+#define EXYNOS5_PA_DRD                       0x12000000
 #define EXYNOS5_PA_EHCI                      0x12110000
 #define EXYNOS5_PA_OHCI                      0x12120000
 #define EXYNOS4_PA_MFC                       0x13400000

arch/arm/mach-exynos/mach-exynos5-dt.c +2 -1

index c03f3dd..3032222 100644
@@ -90,6 +90,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                              "s5p-ehci", NULL),
      OF_DEV_AUXDATA("samsung,exynos-ohci", EXYNOS5_PA_OHCI,
                              "exynos-ohci", NULL),
+     OF_DEV_AUXDATA("samsung,exynos-dwc3", EXYNOS5_PA_DRD,
+                             "exynos-dwc3", NULL),
      {},
 };
 
--

1.7.6.5

Quoted 4 lines

_______________________________________________
linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.
_______________________________________________
devicetree-discuss mailing list
devicetree-discuss at lists.ozlabs.org
https://lists.ozlabs.org/listinfo/devicetree-discuss

Signature · 2 lines

Thanks & Regards
Vivek

Vivek Gautam

author

2012-12-13 16:41 UTC #5 lore raw

PATCH v3 1/1 ARM: Exynos5250: Enabling dwc3-exynos driver

Adding DWC3 device tree node for Exynos5250 along with the device address and clock support needed for the controller.

Signed-off-by Vivek Gautam <[email protected]>

---
Changes from v2:
- Changed the compatible string to chip specific(samsung,exynos5250), since dwc3-exynos is being used from exynso5250 onwards.
- Based on changes for USB 2.0:
https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-December/024413.html

Changes from v1:
- Changed the device node name from 'dwc3' to 'usb@12000000'.
- Added the documentation for device tree bindings for dwc3 controller.

 .../devicetree/bindings/usb/exynos-usb.txt         |   14 +++++++++++
 arch/arm/boot/dts/exynos5250.dtsi                  |    6 +++++
 arch/arm/mach-exynos/Kconfig                       |    1 +
 arch/arm/mach-exynos/clock-exynos5.c               |   24 ++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    2 +
 6 files changed, 48 insertions(+), 0 deletions(-)

Documentation/devicetree/bindings/usb/exynos-usb.txt +14 -0

index f66fcdd..d660410 100644
@@ -38,3 +38,17 @@ Example:
 		reg = <0x12120000 0x100>;
 		interrupts = <0 71 0>;
 	};
+
+DWC3
+Required properties:
+ - compatible: should be "samsung,exynos5250-dwc3" for USB 3.0 DWC3 controller.
+ - reg: physical base address of the controller and length of memory mapped
+   region.
+ - interrupts: interrupt number to the cpu.
+
+Example:
+	usb@12000000 {
+		compatible = "samsung,exynos5250-dwc3";
+		reg = <0x12000000 0x10000>;
+		interrupts = <0 72 0>;
+	};

arch/arm/boot/dts/exynos5250.dtsi +6 -0

index 75510d1..001a31b 100644
@@ -299,6 +299,12 @@
 		rx-dma-channel = <&pdma0 11>; /* preliminary */
 	};
 
+	usb@12000000 {
+		compatible = "samsung,exynos5250-dwc3";
+		reg = <0x12000000 0x10000>;
+		interrupts = <0 72 0>;
+	};
+
 	usb@12110000 {
 		compatible = "samsung,exynos4210-ehci";
 		reg = <0x12110000 0x100>;

arch/arm/mach-exynos/Kconfig +1 -0

index 91d5b6f..09f9587 100644
@@ -426,6 +426,7 @@ config MACH_EXYNOS5_DT
 	depends on ARCH_EXYNOS5
 	select ARM_AMBA
 	select USE_OF
+	select USB_ARCH_HAS_XHCI
 	help
 	  Machine support for Samsung EXYNOS5 machine with device tree enabled.
 	  Select this if a fdt blob is available for the EXYNOS5 SoC based board.

arch/arm/mach-exynos/clock-exynos5.c +24 -0

index 5c63bc7..f2214a0 100644
@@ -768,6 +768,11 @@ static struct clk exynos5_init_clocks_off[] = {
 		.enable		= exynos5_clk_ip_fsys_ctrl ,
 		.ctrlbit	= (1 << 18),
 	}, {
+		.name		= "usbdrd30",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 19),
+	}, {
 		.name		= "usbotg",
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 7),

@@ -1121,6 +1126,16 @@ static struct clksrc_sources exynos5_clkset_group = {
 	.nr_sources	= ARRAY_SIZE(exynos5_clkset_group_list),
 };
 
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+	[0] = &exynos5_clk_mout_mpll.clk,
+	[1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+	.sources        = exynos5_clkset_usbdrd30_list,
+	.nr_sources     = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
 /* Possible clock sources for aclk_266_gscl_sub Mux */
 static struct clk *clk_src_gscl_266_list[] = {
 	[0] = &clk_ext_xtal_mux,

@@ -1415,6 +1430,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
 			.parent		= &exynos5_clk_mout_cpll.clk,
 		},
 		.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+	}, {
+		.clk    = {
+			.name           = "sclk_usbdrd30",
+			.enable         = exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit        = (1 << 28),
+		},
+		.sources = &exynos5_clkset_usbdrd30,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 },
 	},
 };

arch/arm/mach-exynos/include/mach/map.h +1 -0

index 4bf6fd9..74470ca 100644
@@ -201,6 +201,7 @@
 #define EXYNOS4_PA_EHCI			0x12580000
 #define EXYNOS4_PA_OHCI			0x12590000
 #define EXYNOS4_PA_HSPHY		0x125B0000
+#define EXYNOS5_PA_DRD			0x12000000
 #define EXYNOS5_PA_EHCI			0x12110000
 #define EXYNOS5_PA_OHCI			0x12120000
 #define EXYNOS4_PA_MFC			0x13400000

arch/arm/mach-exynos/mach-exynos5-dt.c +2 -0

index 07aa586..26dd6c8 100644
@@ -114,6 +114,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 				"s5p-ehci", NULL),
 	OF_DEV_AUXDATA("samsung,exynos4210-ohci", EXYNOS5_PA_OHCI,
 				"exynos-ohci", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dwc3", EXYNOS5_PA_DRD,
+				"exynos-dwc3", NULL),
 	{},
 };

Signature · 1 line

1.7.6.5

Vivek Gautam

2012-12-19 13:52 UTC #6 lore raw

Re: [PATCH v3] ARM: Exynos5250: Enabling dwc3-exynos driver

CC Doug Anderson

Quoted 156 lines · Vivek Gautam

Adding DWC3 device tree node for Exynos5250 along with the device address and clock support needed for the controller.

Signed-off-by Vivek Gautam <[email protected]>

---
Changes from v2:
- Changed the compatible string to chip specific(samsung,exynos5250), since dwc3-exynos is being used from exynso5250 onwards.
- Based on changes for USB 2.0:

   https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-December/024413.html

Changes from v1:
- Changed the device node name from 'dwc3' to 'usb@12000000'.
- Added the documentation for device tree bindings for dwc3 controller.

 .../devicetree/bindings/usb/exynos-usb.txt         |   14 +++++++++++
 arch/arm/boot/dts/exynos5250.dtsi                  |    6 +++++
 arch/arm/mach-exynos/Kconfig                       |    1 +
 arch/arm/mach-exynos/clock-exynos5.c               |   24 ++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    2 +
 6 files changed, 48 insertions(+), 0 deletions(-)

Documentation/devicetree/bindings/usb/exynos-usb.txt +14 -0

index f66fcdd..d660410 100644
@@ -38,3 +38,17 @@ Example:
                reg = <0x12120000 0x100>;
                interrupts = <0 71 0>;
        };
+
+DWC3
+Required properties:
+ - compatible: should be "samsung,exynos5250-dwc3" for USB 3.0 DWC3 controller.
+ - reg: physical base address of the controller and length of memory mapped
+   region.
+ - interrupts: interrupt number to the cpu.
+
+Example:
+       usb@12000000 {
+               compatible = "samsung,exynos5250-dwc3";
+               reg = <0x12000000 0x10000>;
+               interrupts = <0 72 0>;
+       };

arch/arm/boot/dts/exynos5250.dtsi +6 -0

index 75510d1..001a31b 100644
@@ -299,6 +299,12 @@
                rx-dma-channel = <&pdma0 11>; /* preliminary */
        };
 
+       usb@12000000 {
+               compatible = "samsung,exynos5250-dwc3";
+               reg = <0x12000000 0x10000>;
+               interrupts = <0 72 0>;
+       };
+
        usb@12110000 {
                compatible = "samsung,exynos4210-ehci";
                reg = <0x12110000 0x100>;

arch/arm/mach-exynos/Kconfig +1 -0

index 91d5b6f..09f9587 100644
@@ -426,6 +426,7 @@ config MACH_EXYNOS5_DT
        depends on ARCH_EXYNOS5
        select ARM_AMBA
        select USE_OF
+       select USB_ARCH_HAS_XHCI
        help
          Machine support for Samsung EXYNOS5 machine with device tree enabled.
          Select this if a fdt blob is available for the EXYNOS5 SoC based board.

arch/arm/mach-exynos/clock-exynos5.c +24 -0

index 5c63bc7..f2214a0 100644
@@ -768,6 +768,11 @@ static struct clk exynos5_init_clocks_off[] = {
                .enable         = exynos5_clk_ip_fsys_ctrl ,
                .ctrlbit        = (1 << 18),
        }, {
+               .name           = "usbdrd30",
+               .parent         = &exynos5_clk_aclk_200.clk,
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 19),
+       }, {
                .name           = "usbotg",
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 7),

@@ -1121,6 +1126,16 @@ static struct clksrc_sources exynos5_clkset_group = {
        .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
 };
 
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+       [0] = &exynos5_clk_mout_mpll.clk,
+       [1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+       .sources        = exynos5_clkset_usbdrd30_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
 /* Possible clock sources for aclk_266_gscl_sub Mux */
 static struct clk *clk_src_gscl_266_list[] = {
        [0] = &clk_ext_xtal_mux,

@@ -1415,6 +1430,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
                        .parent         = &exynos5_clk_mout_cpll.clk,
                },
                .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_usbdrd30",
+                       .enable         = exynos5_clksrc_mask_fsys_ctrl,
+                       .ctrlbit        = (1 << 28),
+               },
+               .sources = &exynos5_clkset_usbdrd30,
+               .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 },
+               .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 },
        },
 };

arch/arm/mach-exynos/include/mach/map.h +1 -0

index 4bf6fd9..74470ca 100644
@@ -201,6 +201,7 @@
 #define EXYNOS4_PA_EHCI                        0x12580000
 #define EXYNOS4_PA_OHCI                        0x12590000
 #define EXYNOS4_PA_HSPHY               0x125B0000
+#define EXYNOS5_PA_DRD                 0x12000000
 #define EXYNOS5_PA_EHCI                        0x12110000
 #define EXYNOS5_PA_OHCI                        0x12120000
 #define EXYNOS4_PA_MFC                 0x13400000

arch/arm/mach-exynos/mach-exynos5-dt.c +2 -1

index 07aa586..26dd6c8 100644
@@ -114,6 +114,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                "s5p-ehci", NULL),
        OF_DEV_AUXDATA("samsung,exynos4210-ohci", EXYNOS5_PA_OHCI,
                                "exynos-ohci", NULL),
+       OF_DEV_AUXDATA("samsung,exynos5250-dwc3", EXYNOS5_PA_DRD,
+                               "exynos-dwc3", NULL),
        {},
 };
 
--

1.7.6.5

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Signature · 2 lines

Thanks & Regards
Vivek