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mx27: add a clock gate to activate SPLL clock

PATCH Superseded Gwenhael Goavec-Merou 4 participants 8 messages Dec 19, 2012 – Jan 8, 2013

Subsystems (5)
Arm (32-bit) USB Arm sub-architectures Arm i.MX and Layerscape +1 more subsystems

v1 of 2 Superseded Latest is v2 →

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Gwenhael Goavec-Merou

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#0 lore raw

PATCH 1/2 mx27: add a clock gate to activate SPLL clock

A clock gate is mandatory to activate SPLL clock needed, at least, for usb.

Signed-off-by Gwenhael Goavec-Merou <[email protected]>
---
 arch/arm/mach-imx/clk-imx27.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)
arch/arm/mach-imx/clk-imx27.c +4 -3
index 4c1d1e4..4f066d13 100644
@@ -62,7 +62,7 @@ static const char *clko_sel_clks[] = {
 	"32k", "usb_div", "dptc",
 };
 
-static const char *ssi_sel_clks[] = { "spll", "mpll", };
+static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
 
 enum mx27_clks {
 	dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,

@@ -82,7 +82,7 @@ enum mx27_clks {
 	csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
 	uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
 	uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
-	mpll_sel, clk_max
+	mpll_sel, spll_gate, clk_max
 };
 
 static struct clk *clk[clk_max];

@@ -104,6 +104,7 @@ int __init mx27_clocks_init(unsigned long fref)
 			ARRAY_SIZE(mpll_sel_clks));
 	clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
 	clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
+	clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
 	clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
 
 	if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {

@@ -121,7 +122,7 @@ int __init mx27_clocks_init(unsigned long fref)
 	clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
 	clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
 	clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
-	clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
+	clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
 	clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
 	clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
 	if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
Signature · 1 line
1.7.8.6
author
#1 lore raw

PATCH 2/2 mxc: enable EHCI PER clock

EHCI PER clock (aka usb_div) must be enabled to have EHCI driver working.

Signed-off-by Gwenhael Goavec-Merou <[email protected]>
---
 drivers/usb/host/ehci-mxc.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)
drivers/usb/host/ehci-mxc.c +11 -1
index ec7f5d2..8050631 100644
@@ -31,7 +31,7 @@
 #define ULPI_VIEWPORT_OFFSET	0x170
 
 struct ehci_mxc_priv {
-	struct clk *usbclk, *ahbclk, *phyclk;
+	struct clk *usbclk, *ahbclk, *perclk, *phyclk;
 	struct usb_hcd *hcd;
 };
 

@@ -150,6 +150,13 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
 	}
 	clk_prepare_enable(priv->ahbclk);
 
+	priv->perclk = devm_clk_get(&pdev->dev, "per");
+	if (IS_ERR(priv->perclk)) {
+		ret = PTR_ERR(priv->perclk);
+		goto err_clk_per;
+	}
+	clk_prepare_enable(priv->perclk);
+
 	/* "dr" device has its own clock on i.MX51 */
 	priv->phyclk = devm_clk_get(&pdev->dev, "phy");
 	if (IS_ERR(priv->phyclk))

@@ -233,6 +240,8 @@ err_init:
 	if (priv->phyclk)
 		clk_disable_unprepare(priv->phyclk);
 
+	clk_disable_unprepare(priv->perclk);
+err_clk_per:
 	clk_disable_unprepare(priv->ahbclk);
 err_clk_ahb:
 	clk_disable_unprepare(priv->usbclk);

@@ -259,6 +268,7 @@ static int __exit ehci_mxc_drv_remove(struct platform_device *pdev)
 
 	clk_disable_unprepare(priv->usbclk);
 	clk_disable_unprepare(priv->ahbclk);
+	clk_disable_unprepare(priv->perclk);
 
 	if (priv->phyclk)
 		clk_disable_unprepare(priv->phyclk);
Signature · 1 line
1.7.8.6
reviewer
#2 lore raw

PATCH 2/2 mxc: enable EHCI PER clock

Quoted 3 lines · Gwenhael Goavec-Merou

EHCI PER clock (aka usb_div) must be enabled to have EHCI driver working.

Signed-off-by Gwenhael Goavec-Merou <[email protected]>

Have you considered to use the chipidea usb driver in mx27 instead? mx28/mx6 are already converted to the chipidea usb driver.

Regards,

Fabio Estevm

#3 lore raw

PATCH 2/2 mxc: enable EHCI PER clock

Dear Fabio Estevam,

Quoted 9 lines

On Wed, Dec 19, 2012 at 4:29 PM, Gwenhael Goavec-Merou

Quoted 3 lines · <[email protected]> wrote:

EHCI PER clock (aka usb_div) must be enabled to have EHCI driver working.

Signed-off-by Gwenhael Goavec-Merou <[email protected]>

Have you considered to use the chipidea usb driver in mx27 instead? mx28/mx6 are already converted to the chipidea usb driver.

True, we should kill ehci-mxc ASAP. On the other hand, I'm not opposed to applying these, just bear in mind the driver might just disappear.

Best regards,
Marek Vasut

maintainer
#4 lore raw

PATCH 2/2 mxc: enable EHCI PER clock

In reply to Gwenhael Goavec-Merou
Quoted 21 lines · Gwenhael Goavec-Merou

EHCI PER clock (aka usb_div) must be enabled to have EHCI driver working.

Signed-off-by Gwenhael Goavec-Merou <[email protected]>
---
 drivers/usb/host/ehci-mxc.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)
drivers/usb/host/ehci-mxc.c +1 -1
index ec7f5d2..8050631 100644
@@ -31,7 +31,7 @@
 #define ULPI_VIEWPORT_OFFSET	0x170
 
 struct ehci_mxc_priv {
-	struct clk *usbclk, *ahbclk, *phyclk;
+	struct clk *usbclk, *ahbclk, *perclk, *phyclk;
 	struct usb_hcd *hcd;
 };

drivers/usb/host/ehci-mxc.c static int ehci_mxc_drv_probe(struct platform_device *pdev) · line 158

Quoted 9 lines
drivers/usb/host/ehci-mxc.c +6 -0
@@ -150,6 +150,13 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
 	}
 	clk_prepare_enable(priv->ahbclk);
 
+	priv->perclk = devm_clk_get(&pdev->dev, "per");
+	if (IS_ERR(priv->perclk)) {
+		ret = PTR_ERR(priv->perclk);
+		goto err_clk_per;
+	}
+	clk_prepare_enable(priv->perclk);

Have you checked this clock is present on all SoCs using this driver?

Other than that, +1 on using the chipidea driver as Fabio and Marek already noted.

Sascha

Signature · 4 lines
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author
#5 lore raw

PATCH 2/2 mxc: enable EHCI PER clock

Quoted 25 lines · On Wed, 19 Dec 2012 21:29:26 +0100 Sascha Hauer <[email protected]> wrote:
Quoted 24 lines · Gwenhael Goavec-Merou

EHCI PER clock (aka usb_div) must be enabled to have EHCI driver working.

Signed-off-by Gwenhael Goavec-Merou <[email protected]>
---
 drivers/usb/host/ehci-mxc.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)
drivers/usb/host/ehci-mxc.c +1 -1
index ec7f5d2..8050631 100644
@@ -31,7 +31,7 @@
 #define ULPI_VIEWPORT_OFFSET	0x170
 
 struct ehci_mxc_priv {
-	struct clk *usbclk, *ahbclk, *phyclk;
+	struct clk *usbclk, *ahbclk, *perclk, *phyclk;
 	struct usb_hcd *hcd;
 };
 

@@ -150,6 +150,13 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
 	}
 	clk_prepare_enable(priv->ahbclk);
Quoted 9 lines

drivers/usb/host/ehci-mxc.c static int ehci_mxc_drv_probe(struct platform_device *pdev) · line 158

Quoted 6 lines
drivers/usb/host/ehci-mxc.c +6 -0
+	priv->perclk = devm_clk_get(&pdev->dev, "per");
+	if (IS_ERR(priv->perclk)) {
+		ret = PTR_ERR(priv->perclk);
+		goto err_clk_per;
+	}
+	clk_prepare_enable(priv->perclk);

Have you checked this clock is present on all SoCs using this driver?

Yes

Quoted 4 lines

Other than that, +1 on using the chipidea driver as Fabio and Marek already noted.

True. But I need to use a non-dt board based on imx27. Chipidea is not working yet for this chip and I have currently not enough time to do that.

Gwenha?l

#6 lore raw

PATCH 2/2 mxc: enable EHCI PER clock

Dear gwenhael.goavec,

Quoted 45 lines

On Wed, 19 Dec 2012 21:29:26 +0100

Quoted 33 lines · Sascha Hauer
Quoted 32 lines · Gwenhael Goavec-Merou

EHCI PER clock (aka usb_div) must be enabled to have EHCI driver working.

Signed-off-by: Gwenhael Goavec-Merou
<[email protected]> ---

 drivers/usb/host/ehci-mxc.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)
drivers/usb/host/ehci-mxc.c +1 -1
index ec7f5d2..8050631 100644
@@ -31,7 +31,7 @@
 
 #define ULPI_VIEWPORT_OFFSET	0x170
 
 struct ehci_mxc_priv {
 
-	struct clk *usbclk, *ahbclk, *phyclk;
+	struct clk *usbclk, *ahbclk, *perclk, *phyclk;
drivers/usb/host/ehci-mxc.c +0 -0
 	struct usb_hcd *hcd;
 
 };

@@ -150,6 +150,13 @@ static int ehci_mxc_drv_probe(struct
 platform_device *pdev)
 
 	}
 	clk_prepare_enable(priv->ahbclk);
Quoted 8 lines

drivers/usb/host/ehci-mxc.c static int ehci_mxc_drv_probe(struct platform_device *pdev) · line 158

Quoted 6 lines
drivers/usb/host/ehci-mxc.c +6 -0
+	priv->perclk = devm_clk_get(&pdev->dev, "per");
+	if (IS_ERR(priv->perclk)) {
+		ret = PTR_ERR(priv->perclk);
+		goto err_clk_per;
+	}
+	clk_prepare_enable(priv->perclk);

Have you checked this clock is present on all SoCs using this driver?

Quoted 8 lines

Yes

Quoted 2 lines

Other than that, +1 on using the chipidea driver as Fabio and Marek already noted.

True. But I need to use a non-dt board based on imx27. Chipidea is not working yet for this chip and I have currently not enough time to do that.

You're on your own then, sorry :-(

Best regards,
Marek Vasut

author
#7 lore raw

PATCH 2/2 mxc: enable EHCI PER clock

Quoted 49 lines · On Tue, 8 Jan 2013 14:01:36 +0100 Marek Vasut <[email protected]> wrote:

Dear gwenhael.goavec,

Quoted 47 lines

On Wed, 19 Dec 2012 21:29:26 +0100

Quoted 33 lines · Sascha Hauer
Quoted 32 lines · Gwenhael Goavec-Merou

EHCI PER clock (aka usb_div) must be enabled to have EHCI driver working.

Signed-off-by: Gwenhael Goavec-Merou
<[email protected]> ---

 drivers/usb/host/ehci-mxc.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)
drivers/usb/host/ehci-mxc.c +1 -1
index ec7f5d2..8050631 100644
@@ -31,7 +31,7 @@
 
 #define ULPI_VIEWPORT_OFFSET	0x170
 
 struct ehci_mxc_priv {
 
-	struct clk *usbclk, *ahbclk, *phyclk;
+	struct clk *usbclk, *ahbclk, *perclk, *phyclk;
drivers/usb/host/ehci-mxc.c +0 -0
 	struct usb_hcd *hcd;
 
 };

@@ -150,6 +150,13 @@ static int ehci_mxc_drv_probe(struct
 platform_device *pdev)
 
 	}
 	clk_prepare_enable(priv->ahbclk);
Quoted 8 lines

drivers/usb/host/ehci-mxc.c static int ehci_mxc_drv_probe(struct platform_device *pdev) · line 158

Quoted 6 lines
drivers/usb/host/ehci-mxc.c +6 -0
+	priv->perclk = devm_clk_get(&pdev->dev, "per");
+	if (IS_ERR(priv->perclk)) {
+		ret = PTR_ERR(priv->perclk);
+		goto err_clk_per;
+	}
+	clk_prepare_enable(priv->perclk);

Have you checked this clock is present on all SoCs using this driver?

Yes

Quoted 9 lines
Quoted 6 lines
Quoted 2 lines

Other than that, +1 on using the chipidea driver as Fabio and Marek already noted.

True. But I need to use a non-dt board based on imx27. Chipidea is not working yet for this chip and I have currently not enough time to do that.

You're on your own then, sorry :-(

Yes i Know. But currently all i.MX27 based board without DT support have USB not working.
Gwenhael