pinctrl: support mmp silicon with single driver
Subsystems (5)
Haojian Zhuang
maintainerv6 cover pinctrl: support mmp silicon with single driver
Changelog:
v6:
1. Two configuration array will be created for each pin group. This first array is stored in pcs_function structure. The 32-bit configruation argument is stored in this array. Driver stores data while parsing DTS file, and loads these config array if function selector is indicated.
The second array is stored in pinctrl_map structure. Driver won't use it directly. So we could avoid to append lookup pinctrl map method that is introduced in v5.
v5:
1. Move the properties of pinconf into pin group. So those mask properties could be merged with other pinconf properties.
2. Append lookup pinctrl map method.
3. Append input schmitt disable config parameter.
4. Clean code.
v4:
1. Define gpio range as sub-node, not label. And remove pinctrl-single,gpio-ranges property.
2. Use new two properties in sub-node, reg & pinctrl-single,gpio. GPIO number & GPIO function are listed in the pinctrl-single,gpio property.
3. Reference the names like pinctrl-single,bias.
4. Add compatible name "pinconf-single". If the compatible name is "pinctrl-single", there's no pinconf. If the compatible name is "pinconf-single", there's the generic pinconf in pinctrl-single.
5. Update documents.
v3:
1. Add more comments in document.
2. Replace pcs_readl() & pcs_writel() by pcs->read() & pcs->write().
3. Clean code.
v2:
1. Remove "pinctrl-single,gpio-mask". Since GPIO function is one of the mux function in the pinmux register of both OMAP and PXA/MMP silicons. Use "pinctrl-single,function-mask" instead.
2. Remove "pinctrl-single,gpio-enable" & "pinctrl-single,gpio-disable". Use "pinctrl-single,gpio-func" instead. Because GPIO mode is only one of the mux functions in the pinmux register. Defining "gpio-enable" & "gpio-disable" are redundant.
3. Define register with __iomem, not u32 type.
4. Remove "pinctrl-single,input-schmit-shift", "pinctrl-single,power-source-shift", "pinctrl-single,bias-shift". All these properties could be calculated by mask fields.
5. Return -EPROBE_DEFER if pinmux could be got in device driver. And the device driver would be probed again deferred.
Haojian Zhuang
maintainerPATCH v6 1/8 pinctrl: single: support generic pinconf
Support the operation of generic pinconf. The supported config arguments are INPUT_SCHMITT, INPUT_SCHMITT_DISABLE, POWER_SOURCE, BIAS_DISABLE, BIAS_PULLUP, BIAS_PULLDOWN.
--- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/pinctrl-single.c | 292 +++++++++++++++++++++++++++++++++++++- 2 files changed, 287 insertions(+), 6 deletions(-)
drivers/pinctrl/Kconfig +1 -0
@@ -143,6 +143,7 @@ config PINCTRL_SINGLE depends on OF select PINMUX select PINCONF + select GENERIC_PINCONF help This selects the device tree based generic pinctrl driver.
drivers/pinctrl/pinctrl-single.c +286 -6
405 lines not on this page · raw message
Signature · 1 line
1.7.10.4
Tony Lindgren
maintainerPATCH v6 1/8 pinctrl: single: support generic pinconf
Hi,
Quoted 3 lines · Haojian Zhuang
Support the operation of generic pinconf. The supported config arguments are
INPUT_SCHMITT,INPUT_SCHMITT_DISABLE,POWER_SOURCE,BIAS_DISABLE,BIAS_PULLUP,BIAS_PULLDOWN.
FYI, I'm getting one warning with this:
drivers/pinctrl/pinctrl-single.c: In function ?pcs_pinconf_group_get?:drivers/pinctrl/pinctrl-single.c:580: warning: ?old? may be used uninitialized in this function
Will play with my bit-per-mux testcase and comment more after the holidays. Also posted some suggestions trying to unify the binding in the documentation patch.
Regards,
Tony
Tony Lindgren
maintainerPATCH v6 1/8 pinctrl: single: support generic pinconf
In reply to Haojian ZhuangQuoted 23 lines · Haojian Zhuang
drivers/pinctrl/pinctrl-single.c +13
-0@@ -60,6 +61,19 @@ struct pcs_func_vals { };/** +* struct pcs_conf_vals - pinconf parameter, pinconf register offset +* and value/mask pair +* @param: config parameter +* @val: register value +* @mask: mask of register value +*/ +struct pcs_conf_vals { +enum pin_config_param param; +unsigned val; +unsigned mask; +}; + +/** * struct pcs_function - pinctrl function * @name: pinctrl function name * @vals: register and vals array
drivers/pinctrl/pinctrl-single.c struct pcs_function { · line 94
Quoted 7 lines
drivers/pinctrl/pinctrl-single.c +2
-0@@ -74,6 +88,8 @@ struct pcs_function {unsigned nvals;const char **pgnames;int npgnames; +struct pcs_conf_vals *conf; +int nconfs;struct list_head node; };
That's nice, that will work much better than the earlier solution :)
Quoted 41 lines
drivers/pinctrl/pinctrl-single.c +37
-0@@ -448,25 +466,149 @@ static struct pinmux_ops pcs_pinmux_ops = {static int pcs_pinconf_get (struct pinctrl_dev *pctldev,unsigned pin,unsigned long *config) { +struct pcs_device *pcs =pinctrl_dev_get_drvdata (pctldev); +struct pin_desc *pdesc =pin_desc_get (pctldev, pin); +struct pcs_function *func; +const struct pinctrl_setting_mux *setting; +unsigned fselector, offset =0 , data =0 , i, j; + +/* If pin is not described in DTS & enabled, mux_setting is NULL. */ + setting = pdesc->mux_setting; +if (!setting) +return -ENOTSUPP ; + fselector = setting->func; + func =radix_tree_lookup (&pcs->ftree, fselector); +if (!func) { +dev_err (pcs->dev,"%s could not find function%i\n" , + __func__, fselector); +return -ENOTSUPP ; + } + +for (i =0 ; i < func->nconfs; i++) { +if (pinconf_to_config_param (*config) != func->conf[i].param) +continue ; + offset = pin * (pcs->width /BITS_PER_BYTE ); + data = pcs->read (pcs->base + offset); + data &= func->conf[i].mask; +switch (func->conf[i].param) { +case PIN_CONFIG_BIAS_DISABLE : +case PIN_CONFIG_BIAS_PULL_DOWN : +case PIN_CONFIG_BIAS_PULL_UP : +case PIN_CONFIG_INPUT_SCHMITT_DISABLE : +if (data != func->conf[i].val) +return -ENOTSUPP ; + *config = data; +break ; +case PIN_CONFIG_INPUT_SCHMITT : +/* either INPUT_SCHMITT or DISABLE */ +for (j =0 ; j < func->nconfs; j++) { +switch (func->conf[j].param) {
drivers/pinctrl/pinctrl-single.c static struct pinmux_ops pcs_pinmux_ops = { · line 515
Quoted 10 lines
drivers/pinctrl/pinctrl-single.c +10
-0+case PIN_CONFIG_INPUT_SCHMITT_DISABLE : +if (data == func->conf[j].val) +return -ENOTSUPP ; +break ; +default : +break ; + } + } + *config = data; +break ;
We should standardize on the binding format of <enableval disableval regmask> and then all these can be handled the same way I think. And that makes the binding more generic.
drivers/pinctrl/pinctrl-single.c static struct pinmux_ops pcs_pinmux_ops = { · line 521
Quoted 6 lines
drivers/pinctrl/pinctrl-single.c +6
-0+default : + *config = data; +break ; + } +return 0 ; + }
Should we set *config = 0 here too?
drivers/pinctrl/pinctrl-single.c static struct pinmux_ops pcs_pinmux_ops = { · line 523
Quoted 2 lines
drivers/pinctrl/pinctrl-single.c +0
-0return -ENOTSUPP ; }
And we should probably just return the raw pinfonf register value when PIN_CONFIG_END is passed. For write too, we should probably just write the raw register value when PIN_CONFIG_END is passed as there can be related pinconf settings that a client driver may need to use. An example I have for that is a simple USB transceiver that may provide multiple comparators to figure out the charger state.
drivers/pinctrl/pinctrl-single.c static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) · line 833
Quoted 13 lines
drivers/pinctrl/pinctrl-single.c +13
-0+static int pcs_config_match (unsigned data,unsigned match) +{ +int ret =0 ; + +if (!match) { +if (!data) + ret =1 ; + }else { +if ((data & match) == match) + ret =1 ; + } +return ret; +}
How about do the following here:
static int pcs_config_match(unsigned data, unsigned match)
{
if (!match && !data)
return 1; /* typo? do we really return 1 here? */
if ((data & match) == match)
return 1;
return 0;
}Regards,
Tony
Haojian Zhuang
maintainerPATCH v6 2/8 ARM: dts: support pinctrl single in pxa910
In reply to Haojian ZhuangAdd pinctrl-single support with device tree in pxa910 dkb platform.
--- arch/arm/boot/dts/pxa910-dkb.dts | 204 +++++++++++++++++++++++++++++++++++++- arch/arm/boot/dts/pxa910.dtsi | 68 +++++++++++++ 2 files changed, 271 insertions(+), 1 deletion(-)
arch/arm/boot/dts/pxa910-dkb.dts +203 -1
@@ -24,10 +24,212 @@ soc { apb at d4000000 { - uart1: uart at d4017000 { + pmx: pinmux at d401e000 { + pinctrl-names = "default"; + pinctrl-0 = <&board_pins>; + + board_pins: pinmux_board_pins { + /* pins not owned by device driver */ + /* w1 */ + pinctrl-single,pins = < + 0x0cc 0x2 /* CLK_REQ_W1 */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x198 0x6 /* GPIO47_UART1_RXD */ + 0x19c 0x6 /* GPIO48_UART1_TXD */ + >; + /* power source, mask */ + pinctrl-single,power-source = <0x1000 0x1800>; + /* bias, mask, disable, pull down, pull up */ + pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>; + /* input schmitt, mask, disable */ + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x150 0x4 /* GPIO29_UART2_CTS */ + 0x154 0x4 /* GPIO30_UART2_RTS */ + 0x158 0x4 /* GPIO31_UART2_TXD */ + 0x15c 0x4 /* GPIO32_UART2_RXD */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x188 0x7 /* GPIO43_UART3_RXD */ + 0x18c 0x7 /* GPIO44_UART3_TXD */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi1_pins: pinmux_twsi1_pins { + pinctrl-single,pins = < + 0x1b0 0x2 /* GPIO53_TWSI_SCL */ + 0x1b4 0x2 /* GPIO54_TWSI_SDA */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + nand_pins: pinmux_nand_pins { + pinctrl-single,pins = < + 0x040 0x0 /* ND_IO0 */ + 0x03c 0x0 /* ND_IO1 */ + 0x038 0x0 /* ND_IO2 */ + 0x034 0x0 /* ND_IO3 */ + 0x030 0x0 /* ND_IO4 */ + 0x02c 0x0 /* ND_IO5 */ + 0x028 0x0 /* ND_IO6 */ + 0x024 0x0 /* ND_IO7 */ + 0x020 0x0 /* ND_IO8 */ + 0x01c 0x0 /* ND_IO9 */ + 0x018 0x0 /* ND_IO10 */ + 0x014 0x0 /* ND_IO11 */ + 0x010 0x0 /* ND_IO12 */ + 0x00c 0x0 /* ND_IO13 */ + 0x008 0x0 /* ND_IO14 */ + 0x004 0x0 /* ND_IO15 */ + 0x044 0x0 /* ND_nCS0 */ + 0x060 0x1 /* ND_ALE */ + 0x05c 0x0 /* ND_CLE */ + 0x054 0x1 /* ND_nWE */ + 0x058 0x1 /* ND_nRE */ + 0x068 0x0 /* ND_RDY0 */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + mmc1_ldata_pins: pinmux_mmc1_ldata_pins { + pinctrl-single,pins = < + 0x0a0 0x0 /* MMC1_DATA0 */ + 0x09c 0x0 /* MMC1_DATA1 */ + 0x098 0x0 /* MMC1_DATA2 */ + 0x094 0x0 /* MMC1_DATA3 */ + >; + pinctrl-single,power-source = <0x1800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + mmc1_hdata_pins: pinmux_mmc1_hdata_pins { + pinctrl-single,pins = < + 0x090 0x0 /* MMC1_DATA4 */ + 0x08c 0x0 /* MMC1_DATA5 */ + 0x088 0x0 /* MMC1_DATA6 */ + 0x084 0x0 /* MMC1_DATA7 */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + mmc1_clk_pins: pinmux_mmc1_clk_pins { + pinctrl-single,pins = < + 0x0a4 0x0 /* MMC1_CMD */ + 0x0a8 0x0 /* MMC1_CLK */ + >; + pinctrl-single,power-source = <0x1800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + mmc1_cd_pins: pinmux_mmc1_cd_pins { + pinctrl-single,pins = < + 0x0ac 0x0 /* MMC1_CD */ + 0x0b0 0x0 /* MMC1_WP */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + 0x180 0x1 /* MMC2_CMD */ + 0x184 0x1 /* MMC2_CLK */ + 0x17c 0x1 /* MMC2_DATA0 */ + 0x178 0x1 /* MMC2_DATA1 */ + 0x174 0x1 /* MMC2_DATA2 */ + 0x170 0x1 /* MMC2_DATA3 */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + ssp1_pins: pinmux_ssp1_pins { + pinctrl-single,pins = < + 0x130 0x1 /* GPIO21_SSP1_SCLK */ + 0x134 0x1 /* GPIO22_SSP1_FRM */ + 0x138 0x1 /* GPIO23_SSP1_TXD */ + 0x13c 0x1 /* GPIO24_SSP1_RXD */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + keypad_pins: pinmux_keypad_pins { + pinctrl-single,pins = < + 0x0dc 0x1 /* GPIO0_MKIN0 */ + 0x0e0 0x1 /* GPIO1_MKOUT0 */ + 0x0e4 0x1 /* GPIO2_MKIN1 */ + 0x0e8 0x1 /* GPIO3_MKOUT1 */ + 0x0ec 0x1 /* GPIO4_MKIN2 */ + 0x0f0 0x1 /* GPIO5_MKOUT2 */ + 0x0f4 0x1 /* GPIO6_MKIN3 */ + 0x0f8 0x1 /* GPIO7_MKOUT3 */ + 0x0fc 0x1 /* GPIO8_MKIN4 */ + 0x100 0x1 /* GPIO9_MKOUT4 */ + 0x10c 0x1 /* GPIO12_MKIN6 */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + nfc_pins: pinmux_nfc_pins { + pinctrl-single,pins = < + 0x120 0x0 /* GPIO17 */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + wlan_pins: pinmux_wlan_pins { + pinctrl-single,pins = < + 0x114 0x0 /* GPIO14 */ + 0x12c 0x0 /* GPIO20 */ + 0x160 0x0 /* GPIO33 */ + 0x164 0x0 /* GPIO34 */ + 0x168 0x0 /* GPIO35 */ + 0x16c 0x0 /* GPIO36 */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + }; + uart1: uart at d4017000 { /* FFUART */ + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; + }; + uart2: uart at d4018000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; + }; + uart3: uart at d4036000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; status = "okay"; }; twsi1: i2c at d4011000 { + pinctrl-names = "default"; + pinctrl-0 = <&twsi1_pins>; status = "okay"; pmic: 88pm860x at 34 {
arch/arm/boot/dts/pxa910.dtsi +68 -0
74 lines not on this page · raw message
Signature · 1 line
1.7.10.4
Tony Lindgren
maintainerPATCH v6 2/8 ARM: dts: support pinctrl single in pxa910
Hi,
Quoted 13 lines · Haojian Zhuang
Add pinctrl-single support with device tree in pxa910 dkb platform.
Signed-off-by Haojian Zhuang <[email protected]>--- arch/arm/boot/dts/pxa910-dkb.dts | 204 +++++++++++++++++++++++++++++++++++++- arch/arm/boot/dts/pxa910.dtsi | 68 +++++++++++++ 2 files changed, 271 insertions(+), 1 deletion(-)arch/arm/boot/dts/pxa910-dkb.dts +0
-0
arch/arm/boot/dts/pxa910-dkb.dts line 29
Quoted 7 lines
arch/arm/boot/dts/pxa910-dkb.dts +3
-1@@ -24,10 +24,212 @@ soc { apb at d4000000 { - uart1: uart at d4017000 { + pmx: pinmux at d401e000 { + pinctrl-names = "default"; + pinctrl-0 = <&board_pins>;
Looking at this maybe we should allow specifying the pinconf values at the controller level too if the apply to all the registers:
pinctrl-single,power-source = <enableval disableval regmask>; pinctrl-single,bias = <enableval disableval regmask>; pinctrl-single,input-schmitt = <enableval disableval regmask>;
arch/arm/boot/dts/pxa910-dkb.dts line 39
Quoted 10 lines
arch/arm/boot/dts/pxa910-dkb.dts +10
-0+ + board_pins: pinmux_board_pins { + /* pins not owned by device driver */ + /* w1 */ + pinctrl-single,pins = < + 0x0cc 0x2 /* CLK_REQ_W1 */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
And then you could leave them out from here for your case, while I still need to specify them at the register level.
arch/arm/boot/dts/pxa910-dkb.dts line 51
Quoted 12 lines
arch/arm/boot/dts/pxa910-dkb.dts +12
-0+ }; + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x198 0x6 /* GPIO47_UART1_RXD */ + 0x19c 0x6 /* GPIO48_UART1_TXD */ + >; + /* power source, mask */ + pinctrl-single,power-source = <0x1000 0x1800>; + /* bias, mask, disable, pull down, pull up */ + pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>; + /* input schmitt, mask, disable */ + pinctrl-single,input-schmitt = <0x40 0x70 0x40>;
Regards,
Tony
Haojian Zhuang
maintainerPATCH v6 3/8 ARM: dts: support pinctrl single in aspenite
In reply to Haojian ZhuangFrom: Haojian Zhuang <[email protected]>
Support pinctrl-single driver in aspenite DTS file.
--- arch/arm/boot/dts/pxa168-aspenite.dts | 109 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/pxa168.dtsi | 109 +++++++++++++++++++++++++++++++++ 2 files changed, 218 insertions(+)
arch/arm/boot/dts/pxa168-aspenite.dts +109 -0
@@ -24,7 +24,116 @@ soc { apb at d4000000 { + pmx: pinmux at d401e000 { + pinctrl-names = "default"; + pinctrl-0 = <ðer_pins>; + + ether_pins: pinmux_ether_pins { + pinctrl-single,pins = < + 0x094 0x3 /* GPIO18_SMC_nCS0 */ + 0x0a8 0x0 /* GPIO23_SMC_nLUA */ + 0x0b0 0x0 /* GPIO25_SMC_nLLA */ + 0x0b8 0x0 /* GPIO27_GPIO as irq */ + 0x0bc 0x0 /* GPIO28_SMC_RDY */ + 0x0c0 0x0 /* GPIO29_SMC_SCLK */ + 0x0d4 0x2 /* GPIO34_SMC_nCS1 */ + 0x0d8 0x2 /* GPIO35_SMC_BE1 */ + 0x0dc 0x2 /* GPIO36_SMC_BE2 */ + >; + pinctrl-single,power-source = <0x0c00 0x0c00>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + }; + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x1ac 0x2 /* GPIO107_UART1_RXD */ + 0x1b0 0x2 /* GPIO108_UART1_TXD */ + >; + pinctrl-single,power-source = <0x0c00 0x0c00>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + }; + nand_pins: pinmux_nand_pins { + pinctrl-single,pins = < + 0x04c 0x0 /* ND_IO15 */ + 0x050 0x0 /* ND_IO14 */ + 0x054 0x0 /* ND_IO13 */ + 0x058 0x0 /* ND_IO12 */ + 0x05c 0x0 /* ND_IO11 */ + 0x060 0x0 /* ND_IO10 */ + 0x064 0x0 /* ND_IO9 */ + 0x068 0x0 /* ND_IO8 */ + 0x06c 0x0 /* ND_IO7 */ + 0x070 0x0 /* ND_IO6 */ + 0x074 0x0 /* ND_IO5 */ + 0x078 0x0 /* ND_IO4 */ + 0x07c 0x0 /* ND_IO3 */ + 0x080 0x0 /* ND_IO2 */ + 0x084 0x0 /* ND_IO1 */ + 0x088 0x0 /* ND_IO0 */ + >; + pinctrl-single,power-source = <0x0800 0x0c00>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + }; + ssp1_pins: pinmux_ssp1_pins { + pinctrl-single,pins = < + 0x1c4 0x6 /* GPIO113_I2S_MCLK */ + 0x1c8 0x1 /* GPIO114_I2S_FRM */ + 0x1cc 0x1 /* GPIO115_I2S_BCLK */ + 0x120 0x2 /* GPIO116_I2S_RXD */ + 0x124 0x2 /* GPIO117_I2S_TXD */ + >; + pinctrl-single,power-source = <0x0800 0x0c00>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + }; + keypad_pins: pinmux_keypad_pins { + pinctrl-single,pins = < + 0x1b4 0x7 /* GPIO109_KP_MKIN1 */ + 0x1b8 0x7 /* GPIO110_KP_MKIN0 */ + 0x1bc 0x7 /* GPIO111_KP_MKOUT7 */ + 0x1c0 0x7 /* GPIO112_KP_MKOUT6 */ + 0x1e4 0x7 /* GPIO121_MK_MKIN4 */ + >; + pinctrl-single,power-source = <0x0800 0x0c00>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + }; + lcd_pins: pinmux_lcd_pins { + pinctrl-single,pins = < + 0x0e0 0x1 /* GPIO56_LCD_FCLK_RD */ + 0x0e4 0x1 /* GPIO57_LCD_LCLK_A0 */ + 0x0e8 0x1 /* GPIO58_LCD_ACLK_WR */ + 0x0ec 0x1 /* GPIO59_LCD_DENA_BIAS */ + 0x0f0 0x1 /* GPIO60_LCD_DD0 */ + 0x0f4 0x1 /* GPIO60_LCD_DD1 */ + 0x0f8 0x1 /* GPIO60_LCD_DD2 */ + 0x0fc 0x1 /* GPIO60_LCD_DD3 */ + 0x100 0x1 /* GPIO60_LCD_DD4 */ + 0x104 0x1 /* GPIO60_LCD_DD5 */ + 0x108 0x1 /* GPIO60_LCD_DD6 */ + 0x10c 0x1 /* GPIO60_LCD_DD7 */ + 0x110 0x1 /* GPIO60_LCD_DD8 */ + 0x114 0x1 /* GPIO60_LCD_DD9 */ + 0x118 0x1 /* GPIO60_LCD_DD10 */ + 0x11c 0x1 /* GPIO60_LCD_DD11 */ + 0x120 0x1 /* GPIO60_LCD_DD12 */ + 0x124 0x1 /* GPIO60_LCD_DD13 */ + 0x128 0x1 /* GPIO60_LCD_DD14 */ + 0x12c 0x1 /* GPIO60_LCD_DD15 */ + 0x130 0x1 /* GPIO60_LCD_DD16 */ + 0x134 0x1 /* GPIO60_LCD_DD17 */ + 0x138 0x1 /* GPIO60_LCD_DD18 */ + 0x13c 0x1 /* GPIO60_LCD_DD19 */ + 0x140 0x1 /* GPIO60_LCD_DD20 */ + 0x144 0x1 /* GPIO60_LCD_DD21 */ + 0x148 0x1 /* GPIO60_LCD_DD22 */ + 0x14c 0x1 /* GPIO60_LCD_DD23 */ + >; + pinctrl-single,power-source = <0x0800 0x0c00>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + }; + }; + uart1: uart at d4017000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; status = "okay"; }; twsi1: i2c at d4011000 {
arch/arm/boot/dts/pxa168.dtsi +109 -0
115 lines not on this page · raw message
Signature · 1 line
1.7.10.4
Haojian Zhuang
maintainerPATCH v6 4/8 ARM: dts: support pinctrl single in brownstone
In reply to Haojian ZhuangFrom: Haojian Zhuang <[email protected]>
Support pinctrl-single driver in brownstone platform with DT.
--- arch/arm/boot/dts/mmp2-brownstone.dts | 171 +++++++++++++++++++++++++++ arch/arm/boot/dts/mmp2.dtsi | 204 +++++++++++++++++++++++++++++++++ 2 files changed, 375 insertions(+)
arch/arm/boot/dts/mmp2-brownstone.dts +171 -0
@@ -24,10 +24,181 @@ soc { apb at d4000000 { + pmx: pinmux at d401e000 { + pinctrl-names = "default"; + pinctrl-0 = <&board_pins>; + + board_pins: pinmux_board_pins { + pinctrl-single,pins = < + 0x010 0x0 /* GPIO125_GPIO as version:0 */ + 0x014 0x0 /* GPIO126_GPIO as version:1 */ + 0x018 0x0 /* GPIO127_GPIO as version:2 */ + 0x01c 0x0 /* GPIO128_GPIO as version:3 */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x0c8 0x1 /* GPIO29_UART1_RXD */ + 0x0cc 0x1 /* GPIO30_UART1_TXD */ + >; + /* power source, mask */ + pinctrl-single,power-source = <0x1000 0x1800>; + /* bias, mask, disable, pull down, pull up */ + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + /* input schmitt, mask, disable */ + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x110 0x1 /* GPIO47_UART2_RXD */ + 0x114 0x1 /* GPIO48_UART2_TXD */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x120 0x1 /* GPIO51_UART3_RXD */ + 0x124 0x1 /* GPIO52_UART3_TXD */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi1_pins: pinmux_twsi1_pins { + pinctrl-single,pins = < + 0x140 0x0 /* TWSI_SCL */ + 0x144 0x0 /* TWSI_SDA */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi2_pins: pinmux_twsi2_pins { + pinctrl-single,pins = < + 0x100 0x1 /* GPIO43_TWSI2_SCL */ + 0x104 0x1 /* GPIO44_TWSI2_SDA */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi3_pins: pinmux_twsi3_pins { + pinctrl-single,pins = < + 0x2b0 0x1 /* GPIO71_TWSI3_SCL */ + 0x2b4 0x1 /* GPIO72_TWSI3_SDA */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi4_pins: pinmux_twsi4_pins { + pinctrl-single,pins = < + 0x2bc 0x0 /* TWSI4_SCL */ + 0x2c0 0x0 /* TWSI4_SDA */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi5_pins: pinmux_twsi5_pins { + pinctrl-single,pins = < + 0x1d4 0x4 /* GPIO99_TWSI5_SCL */ + 0x1d8 0x4 /* GPIO100_TWSI5_SDA */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + twsi6_pins: pinmux_twsi6_pins { + pinctrl-single,pins = < + 0x1cc 0x2 /* GPIO97_TWSI6_SCL */ + 0x1d0 0x2 /* GPIO98_TWSI6_SDA */ + >; + pinctrl-single,power-source = <0x0800 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + sspa1_pins: pinmux_sspa1_pins { + pinctrl-single,pins = < + 0x0b0 0x0 /* GPIO23_GPIO */ + 0x0b4 0x1 /* GPIO24_I2S_SYSCLK */ + 0x0b8 0x1 /* GPIO25_I2S_BITCLK */ + 0x0bc 0x1 /* GPIO26_I2S_SYNC */ + 0x0c0 0x1 /* GPIO27_I2S_DATA_OUT */ + 0x0c4 0x1 /* GPIO28_I2S_SDATA_IN */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + sspa2_pins: pinmux_sspa2_pins { + pinctrl-single,pins = < + 0x0d8 0x1 /* GPIO33_SSPA2_CLK */ + 0x0dc 0x1 /* GPIO34_SSPA2_FRM */ + 0x0e0 0x1 /* GPIO35_SSPA2_TXD */ + 0x0e4 0x1 /* GPIO36_SSPA2_RXD */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + nand_pins: pinmux_nand_pins { + pinctrl-single,pins = < + 0x1e0 0x0 /* GPIO168_DFI_D0 */ + 0x1e4 0x0 /* GPIO167_DFI_D1 */ + 0x1e8 0x0 /* GPIO166_DFI_D2 */ + 0x1ec 0x0 /* GPIO165_DFI_D3 */ + 0x1f0 0x0 /* GPIO107_DFI_D4 */ + 0x1f4 0x0 /* GPIO106_DFI_D5 */ + 0x1f8 0x0 /* GPIO105_DFI_D6 */ + 0x1fc 0x0 /* GPIO104_DFI_D7 */ + 0x200 0x0 /* GPIO111_DFI_D8 */ + 0x204 0x0 /* GPIO164_DFI_D9 */ + 0x208 0x0 /* GPIO163_DFI_D10 */ + 0x20c 0x0 /* GPIO162_DFI_D11 */ + 0x210 0x0 /* GPIO161_DFI_D12 */ + 0x214 0x0 /* GPIO110_DFI_D13 */ + 0x218 0x0 /* GPIO109_DFI_D14 */ + 0x21c 0x0 /* GPIO108_DFI_D15 */ + 0x220 0x0 /* GPIO143_ND_nCS0 */ + 0x224 0X0 /* GPIO144_ND_nCS1 */ + 0x230 0x0 /* GPIO147_ND_nWE */ + 0x234 0x0 /* GPIO148_ND_nRE */ + 0x238 0x0 /* GPIO149_ND_CLE */ + 0x23c 0x0 /* GPIO150_ND_ALE */ + 0x244 0x0 /* GPIO112_ND_RDY0 */ + 0x250 0x0 /* GPIO160_ND_RDY1 */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + keypad_pins: pinmux_keypad_pins { + pinctrl-single,pins = < + 0x094 0x1 /* GPIO16_KP_DKIN0 */ + 0x098 0X1 /* GPIO17_KP_DKIN1 */ + 0x09c 0x1 /* GPIO18_KP_DKIN2 */ + 0x0a0 0x1 /* GPIO19_KP_DKIN3 */ + >; + pinctrl-single,power-source = <0x1000 0x1800>; + pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>; + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + }; uart3: uart at d4018000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; status = "okay"; }; twsi1: i2c at d4011000 { + pinctrl-names = "default"; + pinctrl-0 = <&twsi1_pins>; status = "okay"; }; rtc: rtc at d4010000 {
arch/arm/boot/dts/mmp2.dtsi +204 -0
210 lines not on this page · raw message
Signature · 1 line
1.7.10.4
Haojian Zhuang
maintainerPATCH v6 5/8 document: devicetree: bind pinconf with pin single
In reply to Haojian ZhuangFrom: Haojian Zhuang <[email protected]>
Add comments with pinconf & gpio range in the document of pinctrl-single.
--- .../devicetree/bindings/pinctrl/pinctrl-single.txt | 82 +++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +81 -1
@@ -1,7 +1,9 @@ One-register-per-pin type device tree based pinctrl driver Required properties: -- compatible : "pinctrl-single" +- compatible : "pinctrl-single" or "pinconf-single". + "pinctrl-single" means that pinconf isn't supported. + "pinconf-single" means that generic pinconf is supported. - reg : offset and length of the register set for the mux registers
@@ -14,9 +16,31 @@ Optional properties: - pinctrl-single,function-off : function off mode for disabled state if available and same for all registers; if not specified, disabling of pin functions is ignored + - pinctrl-single,bit-per-mux : boolean to indicate that one register controls more than one pin +- pinctrl-single,power-source : array of value that are used to configure + power source in the pinmux register. They're value of power source field + and power source mask. + + /* power source, mask */ + pinctrl-single,power-source = <0x1000 0x1800>; + +- pinctrl-single,bias : array of value that are used to configure the input + bias in the pinmux register. They're value of bias field, bias mask, + bias disable value, bias pull down value & bias pull up value. + + /* bias, mask, disable, pull down, pull up */ + pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>; + +- pinctrl-single,input-schmitt : array of value that are used to configure + input schmitt in the pinmux register. They're value of input schmitt field, + mask, & disable value. + + /* input schmitt value, mask, disable */ + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + This driver assumes that there is only one register for each pin (unless the pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt document in this directory.
@@ -42,6 +66,24 @@ Where 0xdc is the offset from the pinctrl register base address for the device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to be used when applying this change to the register. + +Optional sub-node: In case some pins could be configured as GPIO in the pinmux +register, those pins could be defined as a GPIO range. The sub-node should +be defined in .dtsi files of those silicons. + +Required properties in sub-node: +- reg : offset and length of the GPIO range sub-node. + +- pinctrl-single,gpio : array of GPIO base number in the range and the GPIO + function in the pinmux register. + + range0: { + /* GPIO0 ~ GPIO54 */ + reg = <0xd401e0dc 55>; + pinctrl-single,gpio = <0 0>; + }; + + Example: /* SoC common file */
@@ -76,6 +118,26 @@ control_devconf0: pinmux at 48002274 { pinctrl-single,function-mask = <0x5F>; }; +/* third controller instance for pins in gpio domain */ +pmx_gpio: pinmux at d401e000 { + compatible = "pinconf-single"; + reg = <0xd401e000 0x0330>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + + range0: range at d401e0dc { + /* GPIO0 ~ GPIO54 */ + reg = <0xd401e0dc 0xdc>; + /* gpio base & gpio func */ + pinctrl-single,gpio = <0 0>; + }; +}; + + /* board specific .dts file */ &pmx_core {
@@ -96,6 +158,19 @@ control_devconf0: pinmux at 48002274 { >; }; + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x198 0x6 /* GPIO47_UART1_RXD */ + 0x19c 0x6 /* GPIO48_UART1_TXD */ + >; + /* power source, mask */ + pinctrl-single,power-source = <0x1000 0x1800>; + /* bias, mask, disable, pull down, pull up */ + pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>; + /* input schmitt, mask, disable */ + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; + }; + /* map uart2 pins */ uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = <
@@ -122,6 +197,11 @@ control_devconf0: pinmux@48002274 { }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>;
Signature · 1 line
1.7.10.4
Tony Lindgren
maintainerPATCH v6 5/8 document: devicetree: bind pinconf with pin single
Hi,
Quoted 12 lines · Haojian Zhuang
+- pinctrl-single,power-source : array of value that are used to configure
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +10
-0+ power source in the pinmux register. They're value of power source field + and power source mask. + + /* power source, mask */ + pinctrl-single,power-source = <0x1000 0x1800>; + +- pinctrl-single,bias : array of value that are used to configure the input + bias in the pinmux register. They're value of bias field, bias mask, + bias disable value, bias pull down value & bias pull up value. +
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt Optional properties: · line 43
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +10
-0+ /* bias, mask, disable, pull down, pull up */ + pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>; + +- pinctrl-single,input-schmitt : array of value that are used to configure + input schmitt in the pinmux register. They're value of input schmitt field, + mask, & disable value. + + /* input schmitt value, mask, disable */ + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; +
Hmm we might be able to standardize on just few bindings if we break the bias into enable, pullup and pulldown. Then we should have the defval, enable and disable for each of them to allow setting the board specific config, and to enable and disable things using the generic pinconf api.
So how about something like this:
pinctrl-single,power-source = <defval regmask enableval disableval>;
pinctrl-single,bias-enable = <defval regmask enableval disableval>;
pinctrl-single,bias-pullup = <defval regmask enableval disableval>;
pinctrl-single,bias-pulldown = <defval regmask enableval disableval>;
pinctrl-single,input-schmitt = <defval regmask enableval disableval>;
And then we can add support for other things like comparators too:
pinctrl-single,comparator-enable = <defval regmask enableval disableval>;
pinctrl-single,comparator-status = <regmask>; /* read only status bits */
I'll do some experiments on this with my bit-per-mux testcase, but please let me know if you see any issues using the format above meanwhile.
Regards,
Tony
Haojian Zhuang
maintainerPATCH v6 5/8 document: devicetree: bind pinconf with pin single
Quoted 32 lines · Tony Lindgren
Hi,
Quoted 12 lines · Haojian Zhuang
+- pinctrl-single,power-source : array of value that are used to configure
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +10
-0+ power source in the pinmux register. They're value of power source field + and power source mask. + + /* power source, mask */ + pinctrl-single,power-source = <0x1000 0x1800>; + +- pinctrl-single,bias : array of value that are used to configure the input + bias in the pinmux register. They're value of bias field, bias mask, + bias disable value, bias pull down value & bias pull up value. +Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt Optional properties: · line 43
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +10
-0+ /* bias, mask, disable, pull down, pull up */ + pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>; + +- pinctrl-single,input-schmitt : array of value that are used to configure + input schmitt in the pinmux register. They're value of input schmitt field, + mask, & disable value. + + /* input schmitt value, mask, disable */ + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; +Hmm we might be able to standardize on just few bindings if we break the bias into enable, pullup and pulldown. Then we should have the defval, enable and disable for each of them to allow setting the board specific config, and to enable and disable things using the generic pinconf api.
Quoted 3 lines
So how about something like this:
pinctrl-single,power-source = <defval regmask enableval disableval>;
It seems that there's no requirement on disable power source. Is there any silicon that need
to disable power source? I think that power source means drive strength at here.
Quoted 3 lines
pinctrl-single,bias-enable = <defval regmask enableval disableval>; pinctrl-single,bias-pullup = <defval regmask enableval disableval>; pinctrl-single,bias-pulldown = <defval regmask enableval disableval>;
If bias-pullup or bias-pulldown, it means that bias-enable also. As my understanding, pin could be in any state of bias-disable, bias-pullup, bias-pulldown.
In my v5 patches, pin couldn't switch state among these states. Now it's fixed in v6 patches.
Quoted 1 line
pinctrl-single,input-schmitt = <defval regmask enableval disableval>;
In Marvell silicons, input-schmitt trigger could be configured as high-edge, low-edge or both
detect. So enableval can't cover this usage.
Quoted 6 lines
And then we can add support for other things like comparators too:
pinctrl-single,comparator-enable = <defval regmask enableval disableval>;
pinctrl-single,comparator-status = <regmask>; /* read only status bits */
I'm OK on appending these properties. I would also add slew rate property later.
Regards
Haojian
Tony Lindgren
maintainerPATCH v6 5/8 document: devicetree: bind pinconf with pin single
Quoted 33 lines · Haojian Zhuang
Quoted 32 lines · Tony Lindgren
Hi,
Quoted 12 lines · Haojian Zhuang
+- pinctrl-single,power-source : array of value that are used to configure
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +10
-0+ power source in the pinmux register. They're value of power source field + and power source mask. + + /* power source, mask */ + pinctrl-single,power-source = <0x1000 0x1800>; + +- pinctrl-single,bias : array of value that are used to configure the input + bias in the pinmux register. They're value of bias field, bias mask, + bias disable value, bias pull down value & bias pull up value. +Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt Optional properties: · line 43
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +10
-0+ /* bias, mask, disable, pull down, pull up */ + pinctrl-single,bias = <0xc000 0xe000 0 0xa000 0xc000>; + +- pinctrl-single,input-schmitt : array of value that are used to configure + input schmitt in the pinmux register. They're value of input schmitt field, + mask, & disable value. + + /* input schmitt value, mask, disable */ + pinctrl-single,input-schmitt = <0x40 0x70 0x40>; +Hmm we might be able to standardize on just few bindings if we break the bias into enable, pullup and pulldown. Then we should have the defval, enable and disable for each of them to allow setting the board specific config, and to enable and disable things using the generic pinconf api.
Quoted 7 lines
Quoted 3 lines
So how about something like this:
pinctrl-single,power-source = <defval regmask enableval disableval>;
It seems that there's no requirement on disable power source. Is there any silicon that need
to disable power source? I think that power source means drive strength at here.
Yes at least I have cases where the bias disable needs to be set when changing bias voltage between 1.8V and 3V.
Quoted 9 lines
Quoted 3 lines
pinctrl-single,bias-enable = <defval regmask enableval disableval>; pinctrl-single,bias-pullup = <defval regmask enableval disableval>; pinctrl-single,bias-pulldown = <defval regmask enableval disableval>;If bias-pullup or bias-pulldown, it means that bias-enable also. As my understanding, pin could be in any state of bias-disable, bias-pullup, bias-pulldown.
In my v5 patches, pin couldn't switch state among these states. Now it's fixed in v6 patches.
Yes that's cool. I'm just worried that if we try to stuff all the bias settings into one array, it won't work for additional bias states. Looks like we have at least bias disable, bias voltage and bias high impedance mode in addition to what you're describing.
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pinctrl-single,input-schmitt = <defval regmask enableval disableval>;
In Marvell silicons, input-schmitt trigger could be configured as high-edge, low-edge or both
detect. So enableval can't cover this usage.
Hmm there too trying to stuff them into one array may not be flexible enough to cover all the cases. So that's why I'm suggesting we describe them separately.
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And then we can add support for other things like comparators too:
pinctrl-single,comparator-enable = <defval regmask enableval disableval>;
pinctrl-single,comparator-status = <regmask>; /* read only status bits */I'm OK on appending these properties. I would also add slew rate property later.
OK thanks.
BTW, we may not need the board configured "defval" in the array examples I posted above, we may have it already in the pinmux binding.
Regards,
Tony
Tony Lindgren
maintainerPATCH v6 5/8 document: devicetree: bind pinconf with pin single
Quoted 5 lines · Tony Lindgren
Quoted 4 lines · Haojian Zhuang
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pinctrl-single,input-schmitt = <defval regmask enableval disableval>;
In Marvell silicons, input-schmitt trigger could be configured as high-edge, low-edge or both
detect. So enableval can't cover this usage.
Hmm assuming that's two bits for configuring it, can you make both detect same as:
pinctrl-single,input-schmitt-high-edge = <enableval disableval regmask>;
pinctrl-single,input-schmitt-low-edge = <enableval disableval regmask>;
Or does that not work for you?
To me it looks like we should just standarize on the following:
pinctrl-single,bias-enable = <enableval disableval regmask>; pinctrl-single,bias-pullup = <enableval disableval regmask>; pinctrl-single,bias-pulldown = <enableval disableval regmask>;
pinctrl-single,input-schmitt = <enableval disableval regmask>;
pinctrl-single,input-schmitt-high-edge = <enableval disableval regmask>;
pinctrl-single,input-schmitt-low-edge = <enableval disableval regmask>;
...
pinctrl-single,comparator-enable = <enableval disableval regmask>;
pinctrl-single,comparator-status = <regmask>; /* read only status bits */
So no need to stuff the defval there AFAIK.
Regards,
Tony
Haojian Zhuang
maintainerPATCH v6 6/8 tty: pxa: configure pin
In reply to Haojian ZhuangFrom: Haojian Zhuang <[email protected]>
Configure pins by pinctrl driver.
--- drivers/tty/serial/pxa.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/tty/serial/pxa.c +7 -1
@@ -37,6 +37,7 @@#include <linux/delay.h> #include <linux/interrupt.h> #include <linux/of.h> +#include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <linux/tty.h> #include <linux/tty_flip.h>
@@ -864,6 +865,7 @@ static int serial_pxa_probe_dt(struct platform_device *pdev, struct uart_pxa_port *sport) {struct device_node *np = pdev->dev.of_node; +struct pinctrl *pinctrl;int ret;if (!np)
@@ -874,6 +876,10 @@ static int serial_pxa_probe_dt(struct platform_device *pdev,dev_err (&pdev->dev,"failed to get alias id, errno %d\n" , ret);return ret; } + pinctrl =devm_pinctrl_get_select_default (&pdev->dev); +if (IS_ERR (pinctrl)) +return -EPROBE_DEFER ; + sport->port.line = ret;return 0 ; }
@@ -912,7 +918,7 @@ static int serial_pxa_probe(struct platform_device *dev) ret =serial_pxa_probe_dt (dev, sport);if (ret >0 ) sport->port.line = dev->id; -else if (ret <0 ) +if (ret <0 ) goto err_clk;snprintf (sport->name,PXA_NAME_LEN -1 ,"UART%d" , sport->port.line +1 );
Signature · 1 line
1.7.10.4
PATCH v6 6/8 tty: pxa: configure pin
Quoted 6 lines · Haojian Zhuang
From: Haojian Zhuang <[email protected]>
Configure pins by pinctrl driver.
Signed-off-by Haojian Zhuang <[email protected]>Acked-by Linus Walleij <[email protected]>
I think this will not be needed if Greg ACKs my patch entitled "drivers/pinctrl: grab default handles from device core"
No such simple grabbers will be needed anymore.
Yours,
Linus Walleij
Haojian Zhuang
maintainerPATCH v6 7/8 i2c: pxa: use devm_kzalloc
In reply to Haojian ZhuangFrom: Haojian Zhuang <[email protected]>
Use devm_kzalloc & add checking in probe() function.
--- drivers/i2c/busses/i2c-pxa.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-)
drivers/i2c/busses/i2c-pxa.c +10 -16
@@ -1078,6 +1078,8 @@ static int i2c_pxa_probe_pdata(struct platform_device *pdev,struct i2c_pxa_platform_data *plat = pdev->dev.platform_data;const struct platform_device_id *id =platform_get_device_id (pdev); +if (!id) +return -EINVAL ; *i2c_types = id->driver_data;if (plat) { i2c->use_pio = plat->use_pio;
@@ -1094,29 +1096,23 @@ static int i2c_pxa_probe(struct platform_device *dev)struct resource *res =NULL ;int ret, irq; - i2c =kzalloc (sizeof (struct pxa_i2c ),GFP_KERNEL ); -if (!i2c) { - ret = -ENOMEM ; - goto emalloc; - } + i2c =devm_kzalloc (&dev->dev,sizeof (struct pxa_i2c ),GFP_KERNEL ); +if (!i2c) +return -ENOMEM ; ret =i2c_pxa_probe_dt (dev, i2c, &i2c_type);if (ret >0 ) ret =i2c_pxa_probe_pdata (dev, i2c, &i2c_type);if (ret <0 ) - goto eclk; +return ret; res =platform_get_resource (dev,IORESOURCE_MEM ,0 ); irq =platform_get_irq (dev,0 ); -if (res ==NULL || irq <0 ) { - ret = -ENODEV ; - goto eclk; - } +if (res ==NULL || irq <0 ) +return -ENODEV ; -if (!request_mem_region (res->start,resource_size (res), res->name)) { - ret = -ENOMEM ; - goto eclk; - } +if (!request_mem_region (res->start,resource_size (res), res->name)) +return -ENOMEM ; i2c->adap.owner =THIS_MODULE ; i2c->adap.retries =5 ;
@@ -1209,8 +1205,6 @@ ereqirq: eremap:clk_put (i2c->clk); eclk: -kfree (i2c); -emalloc:release_mem_region (res->start,resource_size (res));return ret; }
Signature · 1 line
1.7.10.4
Haojian Zhuang
maintainerPATCH v6 8/8 i2c: pxa: configure pinmux
In reply to Haojian ZhuangFrom: Haojian Zhuang <[email protected]>
Configure pins by pinctrl driver.
--- drivers/i2c/busses/i2c-pxa.c | 5 +++++ 1 file changed, 5 insertions(+)
drivers/i2c/busses/i2c-pxa.c +5 -0
@@ -32,6 +32,7 @@#include <linux/of.h> #include <linux/of_device.h> #include <linux/of_i2c.h> +#include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <linux/err.h> #include <linux/clk.h>
@@ -1051,6 +1052,7 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c, enum pxa_i2c_types *i2c_types) {struct device_node *np = pdev->dev.of_node; +struct pinctrl *pinctrl;const struct of_device_id *of_id =of_match_device (i2c_pxa_dt_ids, &pdev->dev);int ret;
@@ -1063,6 +1065,9 @@ static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,return ret; } pdev->id = ret; + pinctrl =devm_pinctrl_get_select_default (&pdev->dev); +if (IS_ERR (pinctrl)) +return -EPROBE_DEFER ;if (of_get_property (np,"mrvl,i2c-polling" ,NULL )) i2c->use_pio =1 ;if (of_get_property (np,"mrvl,i2c-fast-mode" ,NULL ))
Signature · 1 line
1.7.10.4
PATCH v6 8/8 i2c: pxa: configure pinmux
Quoted 7 lines · Haojian Zhuang
From: Haojian Zhuang <[email protected]>
Configure pins by pinctrl driver.
Signed-off-by Haojian Zhuang <[email protected]>Cc Ben Dooks <[email protected]>Acked-by Linus Walleij <[email protected]>
Same comment as on the other patch.
And it's important that you send I2C patches to Wolfram Sang these days.
Yours,
Linus Walleij