at91: cleanup and switch core driver to device/driver
Subsystems (4)
cover at91: cleanup and switch core driver to device/driver
HI,
cleanup base addresses and start to drop AT91_BASE_SYS to allow multiple arch at a time
switch code drivers to device/drivers
detect soc a at run time
The following changes since commit adbdc7cd87971b126838950e2dc5eaedfff943d7:
spi: atmel: request cs pin via gpiolib (2012-12-29 00:35:08 +0800)
are available in the git repository at:
git://git.jcrosoft.org/barebox.git delivery/at91_cleanup
for you to fetch changes up to 9f7f67ca887b26a4488edf5fa171a78e142e0a5b:
at91: drop AT91_BASE_PIOx for soc specific one for none boot code (2012-12-29 01:37:47 +0800)
----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (13):
at91: factorise dbgu address
at91: enable clock via clock framework
at91: factoryse PMC address as it's the same on every soc
at91: pmc: drop AT91_BASE_SYS
at91: introduce Kconfig to select the dbgu for lowlevel debug
at91: sync with the kernel address base
at91: at91sam9: provide its own clkdev for pit
at91: PIT: switch to platfrom_driver
at91: autodetect the soc one time at postcore_initcall
at91: SMC: switch to platfrom_driver
at91: wdt: drop AT91_SYS_BASE
at91: introduce AT91SAM9_SMC and AT91SAM9_TIMER
at91: drop AT91_BASE_PIOx for soc specific one for none boot code
arch/arm/boards/at91sam9260ek/init.c | 5 +- arch/arm/boards/at91sam9261ek/init.c | 5 +- arch/arm/boards/at91sam9263ek/init.c | 3 +- arch/arm/boards/at91sam9m10g45ek/init.c | 3 +- arch/arm/boards/at91sam9n12ek/init.c | 5 +- arch/arm/boards/at91sam9x5ek/init.c | 3 +- arch/arm/boards/dss11/init.c | 9 ++- arch/arm/boards/pm9261/init.c | 5 +- arch/arm/boards/pm9263/init.c | 3 +- arch/arm/boards/pm9g45/init.c | 3 +- arch/arm/boards/qil-a9260/init.c | 3 +- arch/arm/boards/tny-a926x/init.c | 5 +- arch/arm/boards/usb-a926x/init.c | 5 +- arch/arm/mach-at91/Kconfig | 114 ++++++++++++++++++++++------ arch/arm/mach-at91/Makefile | 21 +++--- arch/arm/mach-at91/at91rm9200.c | 25 +++--- arch/arm/mach-at91/at91rm9200_lowlevel_init.c | 18 +++-- arch/arm/mach-at91/at91sam9260.c | 24 +++--- arch/arm/mach-at91/at91sam9261.c | 24 +++--- arch/arm/mach-at91/at91sam9263.c | 29 +++---- arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 28 +++---- arch/arm/mach-at91/at91sam926x_time.c | 68 +++++++++++++---- arch/arm/mach-at91/at91sam9g45.c | 29 ++++--- arch/arm/mach-at91/at91sam9n12.c | 26 +++---- arch/arm/mach-at91/at91sam9x5.c | 26 +++---- arch/arm/mach-at91/clock.c | 50 ++++++------ arch/arm/mach-at91/generic.h | 13 ++++ arch/arm/mach-at91/include/mach/at91_dbgu.h | 26 +++---- arch/arm/mach-at91/include/mach/at91_pit.h | 8 +- arch/arm/mach-at91/include/mach/at91_pmc.h | 48 ++++++------ arch/arm/mach-at91/include/mach/at91_wdt.h | 6 +- arch/arm/mach-at91/include/mach/at91rm9200.h | 22 ++++-- arch/arm/mach-at91/include/mach/at91sam9260.h | 37 ++++++--- arch/arm/mach-at91/include/mach/at91sam9261.h | 34 ++++++--- arch/arm/mach-at91/include/mach/at91sam9263.h | 52 ++++++++----- arch/arm/mach-at91/include/mach/at91sam9_smc.h | 50 +++++++++--- arch/arm/mach-at91/include/mach/at91sam9g45.h | 44 +++++++---- arch/arm/mach-at91/include/mach/at91sam9n12.h | 43 +++++++---- arch/arm/mach-at91/include/mach/at91sam9x5.h | 43 +++++++---- arch/arm/mach-at91/include/mach/cpu.h | 190 ++++++++++++++++++++++------------------------ arch/arm/mach-at91/include/mach/debug_ll.h | 6 +- arch/arm/mach-at91/include/mach/hardware.h | 8 ++ arch/arm/mach-at91/include/mach/sam9_smc.h | 33 -------- arch/arm/mach-at91/sam9_smc.c | 146 +++++++++++++++++++++++++++++------ arch/arm/mach-at91/setup.c | 226 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-at91/soc.h | 66 ++++++++++++++++ 46 files changed, 1127 insertions(+), 513 deletions(-) delete mode 100644 arch/arm/mach-at91/include/mach/sam9_smc.h create mode 100644 arch/arm/mach-at91/setup.c create mode 100644 arch/arm/mach-at91/soc.h
Best Regards,
J.
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PATCH 1/13 at91: factorise dbgu address
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/mach-at91/include/mach/hardware.h | 6 ++++++ 1 file changed, 6 insertions(+)
arch/arm/mach-at91/include/mach/hardware.h +6 -0
@@ -14,6 +14,12 @@#ifndef __ASM_ARCH_HARDWARE_H#define __ASM_ARCH_HARDWARE_H +/* DBGU base */ +/* rm9200, 9260/9g20, 9261/9g10, 9rl */ +#define AT91_BASE_DBGU0 0xfffff200 +/* 9263, 9g45 */ +#define AT91_BASE_DBGU1 0xffffee00 +#if defined(CONFIG_ARCH_AT91RM9200 )#include <mach/at91rm9200.h> #elif defined(CONFIG_ARCH_AT91SAM9260 ) || defined(CONFIG_ARCH_AT91SAM9G20 )
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PATCH 2/13 at91: enable clock via clock framework
fix at91sam926x timer and dss11
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/boards/dss11/init.c | 6 ++++-- arch/arm/mach-at91/at91sam926x_time.c | 23 ++++++++++++++++------- 2 files changed, 20 insertions(+), 9 deletions(-)
arch/arm/boards/dss11/init.c +4 -2
@@ -32,8 +32,8 @@#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> -#include <mach/at91_pmc.h> #include <mach/at91_rstc.h> +#include <linux/clk.h> static struct atmel_nand_data nand_pdata = { .ale =21 ,
@@ -82,7 +82,9 @@ static struct at91_ether_platform_data macb_pdata = {static void dss11_phy_reset (void ) {unsigned long rstc; -at91_sys_write (AT91_PMC_PCER ,1 <<AT91SAM9260_ID_EMAC ); +struct clk *clk =clk_get (NULL ,"macb_clk" ); + +clk_enable (clk);at91_set_gpio_input (AT91_PIN_PA14 ,0 );at91_set_gpio_input (AT91_PIN_PA15 ,0 );
arch/arm/mach-at91/at91sam926x_time.c +16 -7
@@ -30,11 +30,11 @@#include <clock.h> #include <asm/hardware.h> #include <mach/at91_pit.h> -#include <mach/at91_pmc.h> #include <mach/at91_rstc.h> #include <mach/io.h> #include <io.h> #include <linux/clk.h> +#include <linux/err.h> uint64_t at91sam9_clocksource_read (void ) {
@@ -49,15 +49,24 @@ static struct clocksource cs = {static int clocksource_init (void ) { +struct clk *clk;u32 pit_rate; -/* -* Enable PITC Clock -* The clock is already enabled for system controller in boot -*/ -at91_sys_write (AT91_PMC_PCER ,1 <<AT91_ID_SYS ); + clk =clk_get (NULL ,"mck" ); +if (IS_ERR (clk)) { + ret =PTR_ERR (clk); +dev_err (dev,"clock not found: %d\n" , ret); +return ret; + } - pit_rate =clk_get_rate (clk_get (NULL ,"mck" )) /16 ; + ret =clk_enable (clk); +if (ret <0 ) { +dev_err (dev,"clock failed to enable: %d\n" , ret); +clk_put (clk); +return ret; + } + + pit_rate =clk_get_rate (clk) /16 ;/* Enable PITC */ at91_sys_write (AT91_PIT_MR ,0xfffff |AT91_PIT_PITEN );
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Re: [PATCH 02/13] at91: enable clock via clock framework
Quoted 58 lines · Jean-Christophe PLAGNIOL-VILLARD
fix at91sam926x timer and dss11
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>--- arch/arm/boards/dss11/init.c | 6 ++++-- arch/arm/mach-at91/at91sam926x_time.c | 23 ++++++++++++++++------- 2 files changed, 20 insertions(+), 9 deletions(-)arch/arm/boards/dss11/init.c +4
-2@@ -32,8 +32,8 @@#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> -#include <mach/at91_pmc.h> #include <mach/at91_rstc.h> +#include <linux/clk.h> static struct atmel_nand_data nand_pdata = { .ale =21 ,@@ -82,7 +82,9 @@ static struct at91_ether_platform_data macb_pdata = {static void dss11_phy_reset (void ) {unsigned long rstc; -at91_sys_write (AT91_PMC_PCER ,1 <<AT91SAM9260_ID_EMAC ); +struct clk *clk =clk_get (NULL ,"macb_clk" ); + +clk_enable (clk);at91_set_gpio_input (AT91_PIN_PA14 ,0 );at91_set_gpio_input (AT91_PIN_PA15 ,0 );arch/arm/mach-at91/at91sam926x_time.c +2
-2@@ -30,11 +30,11 @@#include <clock.h> #include <asm/hardware.h> #include <mach/at91_pit.h> -#include <mach/at91_pmc.h> #include <mach/at91_rstc.h> #include <mach/io.h> #include <io.h> #include <linux/clk.h> +#include <linux/err.h> uint64_t at91sam9_clocksource_read (void ) {@@ -49,15 +49,24 @@ static struct clocksource cs = {static int clocksource_init (void ) { +struct clk *clk;u32 pit_rate; -/*
arch/arm/mach-at91/at91sam926x_time.c static struct clocksource cs = { · line 60
Quoted 10 lines
arch/arm/mach-at91/at91sam926x_time.c +6
-4-* Enable PITC Clock -* The clock is already enabled for system controller in boot -*/ -at91_sys_write (AT91_PMC_PCER ,1 <<AT91_ID_SYS ); + clk =clk_get (NULL ,"mck" ); +if (IS_ERR (clk)) { + ret =PTR_ERR (clk); +dev_err (dev,"clock not found: %d\n" , ret); +return ret; + }
This breaks compilation:
arch/arm/mach-at91/at91sam926x_time.c: In function 'clocksource_init':arch/arm/mach-at91/at91sam926x_time.c:57:3: error: 'ret' undeclared (first use in this function) arch/arm/mach-at91/at91sam926x_time.c:57:3: note: each undeclared identifier is reported only once for each function it appears in arch/arm/mach-at91/at91sam926x_time.c:58:3: error: 'dev' undeclared (first use in this function)
I guess the patch order is wrong.
Sascha
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PATCH 3/13 at91: factoryse PMC address as it's the same on every soc
In reply to Jean-Christophe PLAGNIOL-VILLARDSigned-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/mach-at91/include/mach/at91rm9200.h | 1 - arch/arm/mach-at91/include/mach/at91sam9260.h | 1 - arch/arm/mach-at91/include/mach/at91sam9261.h | 1 - arch/arm/mach-at91/include/mach/at91sam9263.h | 1 - arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 - arch/arm/mach-at91/include/mach/at91sam9n12.h | 1 - arch/arm/mach-at91/include/mach/at91sam9x5.h | 1 - arch/arm/mach-at91/include/mach/hardware.h | 2 ++ 8 files changed, 2 insertions(+), 7 deletions(-)
arch/arm/mach-at91/include/mach/at91rm9200.h +0 -1
@@ -84,7 +84,6 @@*/ #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)/* Advanced Interrupt Controller */ #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)/* Debug Unit */ -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)/* Power Management Controller */ #define AT91_ST (0xfffffd00 - AT91_BASE_SYS)/* System Timer */ #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)/* Real-Time Clock */ #define AT91_MC (0xffffff00 - AT91_BASE_SYS)/* Memory Controllers */
arch/arm/mach-at91/include/mach/at91sam9260.h +0 -1
@@ -87,7 +87,6 @@#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
arch/arm/mach-at91/include/mach/at91sam9261.h +0 -1
@@ -73,7 +73,6 @@#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
arch/arm/mach-at91/include/mach/at91sam9263.h +0 -1
@@ -87,7 +87,6 @@#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
arch/arm/mach-at91/include/mach/at91sam9g45.h +0 -1
@@ -97,7 +97,6 @@#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
arch/arm/mach-at91/include/mach/at91sam9n12.h +0 -1
@@ -93,7 +93,6 @@#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
arch/arm/mach-at91/include/mach/at91sam9x5.h +0 -1
@@ -100,7 +100,6 @@#define AT91_DMA1 (0xffffee00 - AT91_BASE_SYS)#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
arch/arm/mach-at91/include/mach/hardware.h +2 -0
@@ -20,6 +20,8 @@/* 9263, 9g45 */ #define AT91_BASE_DBGU1 0xffffee00 +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#if defined(CONFIG_ARCH_AT91RM9200 )#include <mach/at91rm9200.h> #elif defined(CONFIG_ARCH_AT91SAM9260 ) || defined(CONFIG_ARCH_AT91SAM9G20 )
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Re: [PATCH 03/13] at91: factoryse PMC address as it's the same on every soc
subject: s/factoryse/factorise/
Sascha
Quoted 118 lines · Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>--- arch/arm/mach-at91/include/mach/at91rm9200.h | 1 - arch/arm/mach-at91/include/mach/at91sam9260.h | 1 - arch/arm/mach-at91/include/mach/at91sam9261.h | 1 - arch/arm/mach-at91/include/mach/at91sam9263.h | 1 - arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 - arch/arm/mach-at91/include/mach/at91sam9n12.h | 1 - arch/arm/mach-at91/include/mach/at91sam9x5.h | 1 - arch/arm/mach-at91/include/mach/hardware.h | 2 ++ 8 files changed, 2 insertions(+), 7 deletions(-)arch/arm/mach-at91/include/mach/at91rm9200.h +0
-1@@ -84,7 +84,6 @@*/ #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)/* Advanced Interrupt Controller */ #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)/* Debug Unit */ -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)/* Power Management Controller */ #define AT91_ST (0xfffffd00 - AT91_BASE_SYS)/* System Timer */ #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)/* Real-Time Clock */ #define AT91_MC (0xffffff00 - AT91_BASE_SYS)/* Memory Controllers */ arch/arm/mach-at91/include/mach/at91sam9260.h +0
-1@@ -87,7 +87,6 @@#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)arch/arm/mach-at91/include/mach/at91sam9261.h +0
-1@@ -73,7 +73,6 @@#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)arch/arm/mach-at91/include/mach/at91sam9263.h +0
-1@@ -87,7 +87,6 @@#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)arch/arm/mach-at91/include/mach/at91sam9g45.h +0
-1@@ -97,7 +97,6 @@#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)arch/arm/mach-at91/include/mach/at91sam9n12.h +0
-1@@ -93,7 +93,6 @@#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)arch/arm/mach-at91/include/mach/at91sam9x5.h +0
-1@@ -100,7 +100,6 @@#define AT91_DMA1 (0xffffee00 - AT91_BASE_SYS)#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)arch/arm/mach-at91/include/mach/hardware.h +2
-0@@ -20,6 +20,8 @@/* 9263, 9g45 */ #define AT91_BASE_DBGU1 0xffffee00 +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#if defined(CONFIG_ARCH_AT91RM9200 )#include <mach/at91rm9200.h> #elif defined(CONFIG_ARCH_AT91SAM9260 ) || defined(CONFIG_ARCH_AT91SAM9G20 )Signature · 7 lines
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PATCH 4/13 at91: pmc: drop AT91_BASE_SYS
In reply to Jean-Christophe PLAGNIOL-VILLARDSigned-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/boards/at91sam9260ek/init.c | 2 +- arch/arm/mach-at91/at91rm9200_lowlevel_init.c | 18 +++++---- arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 18 +++++---- arch/arm/mach-at91/clock.c | 50 ++++++++++++------------ arch/arm/mach-at91/include/mach/at91_pmc.h | 48 +++++++++++++---------- arch/arm/mach-at91/include/mach/cpu.h | 2 +- arch/arm/mach-at91/include/mach/hardware.h | 2 +- 7 files changed, 76 insertions(+), 64 deletions(-)
arch/arm/boards/at91sam9260ek/init.c +1 -1
@@ -135,7 +135,7 @@ static struct at91_ether_platform_data macb_pdata = {static void at91sam9260ek_phy_reset (void ) {unsigned long rstc; -at91_sys_write (AT91_PMC_PCER ,1 <<AT91SAM9260_ID_EMAC ); +at91_pmc_write (AT91_PMC_PCER ,1 <<AT91SAM9260_ID_EMAC );at91_set_gpio_input (AT91_PIN_PA14 ,0 );at91_set_gpio_input (AT91_PIN_PA15 ,0 );
arch/arm/mach-at91/at91rm9200_lowlevel_init.c +10 -8
@@ -4,6 +4,8 @@* Under GPLv2 */ +#define __LOWLEVEL_INIT__ +#include <common.h> #include <asm/system.h> #include <asm/barebox-arm.h>
@@ -31,17 +33,17 @@ void __naked __bare_init reset(void)/* * PMC Check if the PLL is already initialized */ - r =at91_sys_read (AT91_PMC_MCKR ); + r =at91_pmc_read (AT91_PMC_MCKR );if (r &AT91_PMC_CSS ) goto end;/* * Enable the Main Oscillator */ -at91_sys_write (AT91_CKGR_MOR ,CONFIG_SYS_MOR_VAL ); +at91_pmc_write (AT91_CKGR_MOR ,CONFIG_SYS_MOR_VAL );do { - r =at91_sys_read (AT91_PMC_SR ); + r =at91_pmc_read (AT91_PMC_SR ); }while (!(r &AT91_PMC_MOSCS ));/*
@@ -61,24 +63,24 @@ void __naked __bare_init reset(void)/* * PLLAR: x MHz for PCK */ -at91_sys_write (AT91_CKGR_PLLAR ,CONFIG_SYS_PLLAR_VAL ); +at91_pmc_write (AT91_CKGR_PLLAR ,CONFIG_SYS_PLLAR_VAL );do { - r =at91_sys_read (AT91_PMC_SR ); + r =at91_pmc_read (AT91_PMC_SR ); }while (!(r &AT91_PMC_LOCKA ));/* * PCK/x = MCK Master Clock from SLOW */ -at91_sys_write (AT91_PMC_MCKR ,CONFIG_SYS_MCKR2_VAL1 ); +at91_pmc_write (AT91_PMC_MCKR ,CONFIG_SYS_MCKR2_VAL1 );/* * PCK/x = MCK Master Clock from PLLA */ -at91_sys_write (AT91_PMC_MCKR ,CONFIG_SYS_MCKR2_VAL2 ); +at91_pmc_write (AT91_PMC_MCKR ,CONFIG_SYS_MCKR2_VAL2 );do { - r =at91_sys_read (AT91_PMC_SR ); + r =at91_pmc_read (AT91_PMC_SR ); }while (!(r &AT91_PMC_MCKRDY ));/*
arch/arm/mach-at91/at91sam926x_lowlevel_init.c +10 -8
@@ -5,6 +5,8 @@* Under GPLv2 */ +#define __LOWLEVEL_INIT__ +#include <common.h> #include <asm/system.h> #include <asm/barebox-arm.h>
@@ -30,7 +32,7 @@ static void inline pmc_check_mckrdy(void)u32 r;do { - r =at91_sys_read (AT91_PMC_SR ); + r =at91_pmc_read (AT91_PMC_SR ); }while (!(r &AT91_PMC_MCKRDY )); }
@@ -71,39 +73,39 @@ void __naked __bare_init reset(void)/* * PMC Check if the PLL is already initialized */ - r =at91_sys_read (AT91_PMC_MCKR ); + r =at91_pmc_read (AT91_PMC_MCKR );if (r &AT91_PMC_CSS ) goto end;/* * Enable the Main Oscillator */ -at91_sys_write (AT91_CKGR_MOR ,CONFIG_SYS_MOR_VAL ); +at91_pmc_write (AT91_CKGR_MOR ,CONFIG_SYS_MOR_VAL );do { - r =at91_sys_read (AT91_PMC_SR ); + r =at91_pmc_read (AT91_PMC_SR ); }while (!(r &AT91_PMC_MOSCS ));/* * PLLAR: x MHz for PCK */ -at91_sys_write (AT91_CKGR_PLLAR ,CONFIG_SYS_PLLAR_VAL ); +at91_pmc_write (AT91_CKGR_PLLAR ,CONFIG_SYS_PLLAR_VAL );do { - r =at91_sys_read (AT91_PMC_SR ); + r =at91_pmc_read (AT91_PMC_SR ); }while (!(r &AT91_PMC_LOCKA ));/* * PCK/x = MCK Master Clock from SLOW */ -at91_sys_write (AT91_PMC_MCKR ,CONFIG_SYS_MCKR1_VAL ); +at91_pmc_write (AT91_PMC_MCKR ,CONFIG_SYS_MCKR1_VAL );pmc_check_mckrdy ();/* * PCK/x = MCK Master Clock from PLLA */ -at91_sys_write (AT91_PMC_MCKR ,CONFIG_SYS_MCKR2_VAL ); +at91_pmc_write (AT91_PMC_MCKR ,CONFIG_SYS_MCKR2_VAL );pmc_check_mckrdy ();
arch/arm/mach-at91/clock.c +26 -24
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arch/arm/mach-at91/include/mach/at91_pmc.h +27 -21
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arch/arm/mach-at91/include/mach/cpu.h +1 -1
@@ -86,7 +86,7 @@ static inline unsigned long at91_arch_identify(void)static inline unsigned long at91cap9_rev_identify (void ) { -return (at91_sys_read (AT91_PMC_VER )); +return (at91_pmc_read (AT91_PMC_VER )); }#endif
arch/arm/mach-at91/include/mach/hardware.h +1 -1
@@ -20,7 +20,7 @@/* 9263, 9g45 */ #define AT91_BASE_DBGU1 0xffffee00 -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_PMC 0xfffffc00#if defined(CONFIG_ARCH_AT91RM9200 )#include <mach/at91rm9200.h>
Signature · 7 lines
1.7.10.4 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 5/13 at91: introduce Kconfig to select the dbgu for lowlevel debug
In reply to Jean-Christophe PLAGNIOL-VILLARDso we can drop AT91_BASE_SYS too
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/mach-at91/Kconfig | 15 +++++++++++++++ arch/arm/mach-at91/include/mach/debug_ll.h | 6 +++++- 2 files changed, 20 insertions(+), 1 deletion(-)
arch/arm/mach-at91/Kconfig +15 -0
@@ -1,5 +1,11 @@ if ARCH_AT91 +config HAVE_AT91_DBGU0 + bool + +config HAVE_AT91_DBGU1 + bool + config ARCH_TEXT_BASE hex default 0x73f00000 if ARCH_AT91SAM9G45
@@ -49,6 +55,7 @@ choice config ARCH_AT91RM9200 bool "AT91RM9200" select CPU_ARM920T + select HAVE_AT91_DBGU0 select HAS_AT91_ETHER select MACH_HAS_LOWLEVEL_INIT select MACH_DO_LOWLEVEL_INIT
@@ -56,46 +63,54 @@ config ARCH_AT91RM9200 config ARCH_AT91SAM9260 bool "AT91SAM9260" select CPU_ARM926T + select HAVE_AT91_DBGU0 select HAS_MACB select AT91SAM9_RESET config ARCH_AT91SAM9261 bool "AT91SAM9261" select CPU_ARM926T + select HAVE_AT91_DBGU0 select AT91SAM9_RESET config ARCH_AT91SAM9263 bool "AT91SAM9263" select CPU_ARM926T + select HAVE_AT91_DBGU1 select HAS_MACB select AT91SAM9_RESET config ARCH_AT91SAM9G10 bool "AT91SAM9G10" select CPU_ARM926T + select HAVE_AT91_DBGU0 select AT91SAM9_RESET config ARCH_AT91SAM9G20 bool "AT91SAM9G20" select CPU_ARM926T + select HAVE_AT91_DBGU0 select HAS_MACB select AT91SAM9_RESET config ARCH_AT91SAM9G45 bool "AT91SAM9G45 or AT91SAM9M10" select CPU_ARM926T + select HAVE_AT91_DBGU1 select HAS_MACB select AT91SAM9G45_RESET config ARCH_AT91SAM9X5 bool "AT91SAM9X5" select CPU_ARM926T + select HAVE_AT91_DBGU0 select HAS_MACB select AT91SAM9G45_RESET config ARCH_AT91SAM9N12 bool "AT91SAM9N12" select CPU_ARM926T + select HAVE_AT91_DBGU0 select AT91SAM9G45_RESET endchoice
arch/arm/mach-at91/include/mach/debug_ll.h +5 -1
@@ -11,7 +11,11 @@#include <asm/io.h> #include <mach/hardware.h> -#define UART_BASE (AT91_BASE_SYS + AT91_DBGU) +#ifdef COFNIG_HAVE_AT91_DBGU0 +#define UART_BASE AT91_BASE_DBGU0 +#else +#define UART_BASE AT91_BASE_DBGU1 +#endif #define ATMEL_US_CSR 0x0014#define ATMEL_US_THR 0x001c
Signature · 7 lines
1.7.10.4 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 6/13 at91: sync with the kernel address base
In reply to Jean-Christophe PLAGNIOL-VILLARDadd non AT91_SYS_BASE offset base address define
This will prepare for multi arch support
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/mach-at91/include/mach/at91rm9200.h | 21 +++++++++--- arch/arm/mach-at91/include/mach/at91sam9260.h | 28 +++++++++++---- arch/arm/mach-at91/include/mach/at91sam9261.h | 26 ++++++++++---- arch/arm/mach-at91/include/mach/at91sam9263.h | 45 +++++++++++++++++-------- arch/arm/mach-at91/include/mach/at91sam9g45.h | 38 +++++++++++++++------ arch/arm/mach-at91/include/mach/at91sam9n12.h | 37 +++++++++++++++----- arch/arm/mach-at91/include/mach/at91sam9x5.h | 37 +++++++++++++++----- 7 files changed, 172 insertions(+), 60 deletions(-)
arch/arm/mach-at91/include/mach/at91rm9200.h +16 -5
@@ -78,20 +78,31 @@#define AT91RM9200_BASE_SPI 0xfffe0000#define AT91_BASE_SYS 0xfffff000 +/* +* System Peripherals +*/ +#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0/* Debug Unit */ +#define AT91RM9200_BASE_PIOA 0xfffff400/* PIO Controller A */ +#define AT91RM9200_BASE_PIOB 0xfffff600/* PIO Controller B */ +#define AT91RM9200_BASE_PIOC 0xfffff800/* PIO Controller C */ +#define AT91RM9200_BASE_PIOD 0xfffffa00/* PIO Controller D */ +#define AT91RM9200_BASE_ST 0xfffffd00/* System Timer */ +#define AT91RM9200_BASE_RTC 0xfffffe00/* Real-Time Clock */ +#define AT91RM9200_BASE_MC 0xffffff00/* Memory Controllers */ +/* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)/* Advanced Interrupt Controller */ #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)/* Debug Unit */ #define AT91_ST (0xfffffd00 - AT91_BASE_SYS)/* System Timer */ #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)/* Real-Time Clock */ #define AT91_MC (0xffffff00 - AT91_BASE_SYS)/* Memory Controllers */ -#define AT91_BASE_PIOA 0xfffff400/* PIO Controller A */ -#define AT91_BASE_PIOB 0xfffff600/* PIO Controller B */ -#define AT91_BASE_PIOC 0xfffff800/* PIO Controller C */ -#define AT91_BASE_PIOD 0xfffffa00/* PIO Controller D */ +#define AT91_BASE_PIOA AT91RM9200_BASE_PIOA/* PIO Controller A */ +#define AT91_BASE_PIOB AT91RM9200_BASE_PIOB/* PIO Controller B */ +#define AT91_BASE_PIOC AT91RM9200_BASE_PIOC/* PIO Controller C */ +#define AT91_BASE_PIOD AT91RM9200_BASE_PIOD/* PIO Controller D */ #define AT91_USART0 AT91RM9200_BASE_US0#define AT91_USART1 AT91RM9200_BASE_US1
arch/arm/mach-at91/include/mach/at91sam9260.h +21 -7
@@ -78,25 +78,39 @@#define AT91_BASE_SYS 0xffffe800/* +* System Peripherals +*/ +#define AT91SAM9260_BASE_ECC 0xffffe800 +#define AT91SAM9260_BASE_SDRAMC 0xffffea00 +#define AT91SAM9260_BASE_SMC 0xffffec00 +#define AT91SAM9260_BASE_MATRIX 0xffffee00 +#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0 +#define AT91SAM9260_BASE_PIOA 0xfffff400 +#define AT91SAM9260_BASE_PIOB 0xfffff600 +#define AT91SAM9260_BASE_PIOC 0xfffff800 +#define AT91SAM9260_BASE_RSTC 0xfffffd00 +#define AT91SAM9260_BASE_SHDWC 0xfffffd10 +#define AT91SAM9260_BASE_RTT 0xfffffd20 +#define AT91SAM9260_BASE_PIT 0xfffffd30 +#define AT91SAM9260_BASE_WDT 0xfffffd40 +#define AT91SAM9260_BASE_GPBR 0xfffffd50 + +/* * System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_ECC (0xffffe800 - AT91_BASE_SYS)#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) -#define AT91_BASE_PIOA 0xfffff400 -#define AT91_BASE_PIOB 0xfffff600 -#define AT91_BASE_PIOC 0xfffff800 +#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA +#define AT91_BASE_PIOB AT91SAM9260_BASE_PIOB +#define AT91_BASE_PIOC AT91SAM9260_BASE_PIOC#define AT91_USART0 AT91SAM9260_BASE_US0#define AT91_USART1 AT91SAM9260_BASE_US1
arch/arm/mach-at91/include/mach/at91sam9261.h +20 -6
@@ -66,23 +66,37 @@/* +* System Peripherals +*/ +#define AT91SAM9261_BASE_SMC 0xffffec00 +#define AT91SAM9261_BASE_MATRIX 0xffffee00 +#define AT91SAM9261_BASE_SDRAMC 0xffffea00 +#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 +#define AT91SAM9261_BASE_PIOA 0xfffff400 +#define AT91SAM9261_BASE_PIOB 0xfffff600 +#define AT91SAM9261_BASE_PIOC 0xfffff800 +#define AT91SAM9261_BASE_RSTC 0xfffffd00 +#define AT91SAM9261_BASE_SHDWC 0xfffffd10 +#define AT91SAM9261_BASE_RTT 0xfffffd20 +#define AT91SAM9261_BASE_PIT 0xfffffd30 +#define AT91SAM9261_BASE_WDT 0xfffffd40 +#define AT91SAM9261_BASE_GPBR 0xfffffd50 + +/* * System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) -#define AT91_BASE_PIOA 0xfffff400 -#define AT91_BASE_PIOB 0xfffff600 -#define AT91_BASE_PIOC 0xfffff800 +#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA +#define AT91_BASE_PIOB AT91SAM9261_BASE_PIOB +#define AT91_BASE_PIOC AT91SAM9261_BASE_PIOC#define AT91_USART0 AT91SAM9261_BASE_US0#define AT91_USART1 AT91SAM9261_BASE_US1
arch/arm/mach-at91/include/mach/at91sam9263.h +31 -14
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arch/arm/mach-at91/include/mach/at91sam9g45.h +28 -10
@@ -87,6 +87,29 @@#define AT91_BASE_SYS 0xffffe200/* +* System Peripherals +*/ +#define AT91SAM9G45_BASE_ECC 0xffffe200 +#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400 +#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600 +#define AT91SAM9G45_BASE_DMA 0xffffec00 +#define AT91SAM9G45_BASE_SMC 0xffffe800 +#define AT91SAM9G45_BASE_MATRIX 0xffffea00 +#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 +#define AT91SAM9G45_BASE_PIOA 0xfffff200 +#define AT91SAM9G45_BASE_PIOB 0xfffff400 +#define AT91SAM9G45_BASE_PIOC 0xfffff600 +#define AT91SAM9G45_BASE_PIOD 0xfffff800 +#define AT91SAM9G45_BASE_PIOE 0xfffffa00 +#define AT91SAM9G45_BASE_RSTC 0xfffffd00 +#define AT91SAM9G45_BASE_SHDWC 0xfffffd10 +#define AT91SAM9G45_BASE_RTT 0xfffffd20 +#define AT91SAM9G45_BASE_PIT 0xfffffd30 +#define AT91SAM9G45_BASE_WDT 0xfffffd40 +#define AT91SAM9G45_BASE_RTC 0xfffffdb0 +#define AT91SAM9G45_BASE_GPBR 0xfffffd60 + +/* * System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
@@ -94,22 +117,17 @@#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) -#define AT91_BASE_PIOA 0xfffff200 -#define AT91_BASE_PIOB 0xfffff400 -#define AT91_BASE_PIOC 0xfffff600 -#define AT91_BASE_PIOD 0xfffff800 -#define AT91_BASE_PIOE 0xfffffa00 +#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA +#define AT91_BASE_PIOB AT91SAM9G45_BASE_PIOB +#define AT91_BASE_PIOC AT91SAM9G45_BASE_PIOC +#define AT91_BASE_PIOD AT91SAM9G45_BASE_PIOD +#define AT91_BASE_PIOE AT91SAM9G45_BASE_PIOE#define AT91_USART0 AT91SAM9G45_BASE_US0#define AT91_USART1 AT91SAM9G45_BASE_US1
arch/arm/mach-at91/include/mach/at91sam9n12.h +28 -9
@@ -82,28 +82,47 @@#define AT91_BASE_SYS 0xffffc000/* +* System Peripherals +*/ +#define AT91SAM9N12_BASE_FUSE 0xffffdc00 +#define AT91SAM9N12_BASE_MATRIX 0xffffde00 +#define AT91SAM9N12_BASE_PMECC 0xffffe000 +#define AT91SAM9N12_BASE_PMERRLOC 0xffffe600 +#define AT91SAM9N12_BASE_DDRSDRC0 0xffffe800 +#define AT91SAM9N12_BASE_SMC 0xffffea00 +#define AT91SAM9N12_BASE_DMA 0xffffec00 +#define AT91SAM9N12_BASE_AIC 0xfffff000 +#define AT91SAM9N12_BASE_DBGU 0xfffff200 +#define AT91SAM9N12_BASE_PIOA 0xfffff400 +#define AT91SAM9N12_BASE_PIOB 0xfffff600 +#define AT91SAM9N12_BASE_PIOC 0xfffff800 +#define AT91SAM9N12_BASE_PIOD 0xfffffa00 +#define AT91SAM9N12_BASE_PMC 0xfffffc00 +#define AT91SAM9N12_BASE_RSTC 0xfffffe00 +#define AT91SAM9N12_BASE_SHDWC 0xfffffe10 +#define AT91SAM9N12_BASE_PIT 0xfffffe30 +#define AT91SAM9N12_BASE_WDT 0xfffffe40 +#define AT91SAM9N12_BASE_GPBR 0xfffffe60 +#define AT91SAM9N12_BASE_RTC 0xfffffeb0 + +/* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_FUSE (0xffffdc00 - AT91_BASE_SYS)#define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS)#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)#define AT91_SMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffe60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffeb0 - AT91_BASE_SYS) -#define AT91_BASE_PIOA 0xfffff400 -#define AT91_BASE_PIOB 0xfffff600 -#define AT91_BASE_PIOC 0xfffff800 -#define AT91_BASE_PIOD 0xfffffa00 +#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA +#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB +#define AT91_BASE_PIOC AT91SAM9N12_BASE_PIOC +#define AT91_BASE_PIOD AT91SAM9N12_BASE_PIOD#define AT91_USART0 AT91SAM9X5_BASE_US0#define AT91_USART1 AT91SAM9X5_BASE_US1
arch/arm/mach-at91/include/mach/at91sam9x5.h +28 -9
@@ -89,6 +89,30 @@#define AT91_BASE_SYS 0xffffc000/* +* System Peripherals +*/ +#define AT91SAM9X5_BASE_MATRIX 0xffffde00 +#define AT9SAM9X5_BASE1_PMECC 0xffffe000 +#define AT91SAM9X5_BASE_PMERRLOC 0xffffe600 +#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800 +#define AT91SAM9X5_BASE_SMC 0xffffea00 +#define AT91SAM9X5_BASE_DMA0 0xffffec00 +#define AT91SAM9X5_BASE_DMA1 0xffffee00 +#define AT91SAM9X5_BASE_AIC 0xfffff000 +#define AT91SAM9X5_BASE_DBGU 0xfffff200 +#define AT91SAM9X5_BASE_PIOA 0xfffff400 +#define AT91SAM9X5_BASE_PIOB 0xfffff600 +#define AT91SAM9X5_BASE_PIOC 0xfffff800 +#define AT91SAM9X5_BASE_PIOD 0xfffffa00 +#define AT91SAM9X5_BASE_PMC 0xfffffc00 +#define AT91SAM9X5_BASE_RSTC 0xfffffe00 +#define AT91SAM9X5_BASE_SHDWC 0xfffffe10 +#define AT91SAM9X5_BASE_PIT 0xfffffe30 +#define AT91SAM9X5_BASE_WDT 0xfffffe40 +#define AT91SAM9X5_BASE_GPBR 0xfffffe60 +#define AT91SAM9X5_BASE_RTC 0xfffffeb0 + +/* * System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS)
@@ -96,21 +120,16 @@#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)#define AT91_SMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_DMA0 (0xffffec00 - AT91_BASE_SYS) -#define AT91_DMA1 (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffe60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffeb0 - AT91_BASE_SYS) -#define AT91_BASE_PIOA 0xfffff400 -#define AT91_BASE_PIOB 0xfffff600 -#define AT91_BASE_PIOC 0xfffff800 -#define AT91_BASE_PIOD 0xfffffa00 +#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA +#define AT91_BASE_PIOB AT91SAM9X5_BASE_PIOB +#define AT91_BASE_PIOC AT91SAM9X5_BASE_PIOC +#define AT91_BASE_PIOD AT91SAM9X5_BASE_PIOD#define AT91_USART0 AT91SAM9X5_BASE_US0#define AT91_USART1 AT91SAM9X5_BASE_US1
Signature · 7 lines
1.7.10.4 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 7/13 at91: at91sam9: provide its own clkdev for pit
In reply to Jean-Christophe PLAGNIOL-VILLARDSigned-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/mach-at91/at91sam9260.c | 1 + arch/arm/mach-at91/at91sam9261.c | 1 + arch/arm/mach-at91/at91sam9263.c | 1 + arch/arm/mach-at91/at91sam9g45.c | 1 + arch/arm/mach-at91/at91sam9n12.c | 1 + arch/arm/mach-at91/at91sam9x5.c | 1 + 6 files changed, 6 insertions(+)
arch/arm/mach-at91/at91sam9260.c +1 -0
@@ -175,6 +175,7 @@ static struct clk_lookup periph_clocks_lookups[] = {CLKDEV_DEV_ID ("at91rm9200-gpio0" , &pioA_clk),CLKDEV_DEV_ID ("at91rm9200-gpio1" , &pioB_clk),CLKDEV_DEV_ID ("at91rm9200-gpio2" , &pioC_clk), + CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = {
arch/arm/mach-at91/at91sam9261.c +1 -0
@@ -139,6 +139,7 @@ static struct clk_lookup periph_clocks_lookups[] = {CLKDEV_DEV_ID ("at91rm9200-gpio0" , &pioA_clk),CLKDEV_DEV_ID ("at91rm9200-gpio1" , &pioB_clk),CLKDEV_DEV_ID ("at91rm9200-gpio2" , &pioC_clk), + CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = {
arch/arm/mach-at91/at91sam9263.c +1 -0
@@ -173,6 +173,7 @@ static struct clk_lookup periph_clocks_lookups[] = {CLKDEV_DEV_ID ("at91rm9200-gpio2" , &pioCDE_clk),CLKDEV_DEV_ID ("at91rm9200-gpio3" , &pioCDE_clk),CLKDEV_DEV_ID ("at91rm9200-gpio4" , &pioCDE_clk), + CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = {
arch/arm/mach-at91/at91sam9g45.c +1 -0
@@ -195,6 +195,7 @@ static struct clk_lookup periph_clocks_lookups[] = {CLKDEV_DEV_ID ("at91rm9200-gpio2" , &pioC_clk),CLKDEV_DEV_ID ("at91rm9200-gpio3" , &pioDE_clk),CLKDEV_DEV_ID ("at91rm9200-gpio4" , &pioDE_clk), + CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = {
arch/arm/mach-at91/at91sam9n12.c +1 -0
@@ -154,6 +154,7 @@ static struct clk_lookup periph_clocks_lookups[] = {CLKDEV_DEV_ID ("at91sam9x5-gpio1" , &pioAB_clk),CLKDEV_DEV_ID ("at91sam9x5-gpio2" , &pioCD_clk),CLKDEV_DEV_ID ("at91sam9x5-gpio3" , &pioCD_clk), + CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = {
arch/arm/mach-at91/at91sam9x5.c +1 -0
@@ -213,6 +213,7 @@ static struct clk_lookup periph_clocks_lookups[] = {CLKDEV_DEV_ID ("at91sam9x5-gpio1" , &pioAB_clk),CLKDEV_DEV_ID ("at91sam9x5-gpio2" , &pioCD_clk),CLKDEV_DEV_ID ("at91sam9x5-gpio3" , &pioCD_clk), + CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = {
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1.7.10.4 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 8/13 at91: PIT: switch to platfrom_driver
In reply to Jean-Christophe PLAGNIOL-VILLARDSigned-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/mach-at91/at91sam9260.c | 1 + arch/arm/mach-at91/at91sam9261.c | 1 + arch/arm/mach-at91/at91sam9263.c | 1 + arch/arm/mach-at91/at91sam926x_time.c | 47 +++++++++++++++++++++---- arch/arm/mach-at91/at91sam9g45.c | 1 + arch/arm/mach-at91/at91sam9n12.c | 1 + arch/arm/mach-at91/at91sam9x5.c | 1 + arch/arm/mach-at91/generic.h | 6 ++++ arch/arm/mach-at91/include/mach/at91_pit.h | 8 ++--- arch/arm/mach-at91/include/mach/at91sam9260.h | 1 - arch/arm/mach-at91/include/mach/at91sam9261.h | 1 - arch/arm/mach-at91/include/mach/at91sam9263.h | 1 - arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 - arch/arm/mach-at91/include/mach/at91sam9n12.h | 1 - arch/arm/mach-at91/include/mach/at91sam9x5.h | 1 - 15 files changed, 56 insertions(+), 17 deletions(-)
arch/arm/mach-at91/at91sam9260.c +1 -0
@@ -239,6 +239,7 @@ static int at91sam9260_gpio_init(void)at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA );at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB );at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC ); +at91_add_pit (AT91SAM9260_BASE_PIT );return 0 ; }
arch/arm/mach-at91/at91sam9261.c +1 -0
@@ -231,6 +231,7 @@ static int at91sam9261_gpio_init(void)at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA );at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB );at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC ); +at91_add_pit (AT91SAM9261_BASE_PIT );return 0 ; }
arch/arm/mach-at91/at91sam9263.c +1 -0
@@ -250,6 +250,7 @@ static int at91sam9263_gpio_init(void)at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC );at91_add_rm9200_gpio (3 ,AT91_BASE_PIOD );at91_add_rm9200_gpio (4 ,AT91_BASE_PIOE ); +at91_add_pit (AT91SAM9263_BASE_PIT );return 0 ; }
arch/arm/mach-at91/at91sam926x_time.c +40 -7
81 lines not on this page · raw message
arch/arm/mach-at91/at91sam9g45.c +1 -0
@@ -263,6 +263,7 @@ static int at91sam9g45_gpio_init(void)at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC );at91_add_rm9200_gpio (3 ,AT91_BASE_PIOD );at91_add_rm9200_gpio (4 ,AT91_BASE_PIOE ); +at91_add_pit (AT91SAM9G45_BASE_PIT );return 0 ; }
arch/arm/mach-at91/at91sam9n12.c +1 -0
@@ -222,6 +222,7 @@ static int at91sam9n12_gpio_init(void)at91_add_sam9x5_gpio (1 ,AT91_BASE_PIOB );at91_add_sam9x5_gpio (2 ,AT91_BASE_PIOC );at91_add_sam9x5_gpio (3 ,AT91_BASE_PIOD ); +at91_add_pit (AT91SAM9N12_BASE_PIT );return 0 ; }
arch/arm/mach-at91/at91sam9x5.c +1 -0
@@ -307,6 +307,7 @@ static int at91sam9x5_gpio_init(void)at91_add_sam9x5_gpio (1 ,AT91_BASE_PIOB );at91_add_sam9x5_gpio (2 ,AT91_BASE_PIOC );at91_add_sam9x5_gpio (3 ,AT91_BASE_PIOD ); +at91_add_pit (AT91SAM9X5_BASE_PIT );return 0 ; }
arch/arm/mach-at91/generic.h +6 -0
@@ -22,3 +22,9 @@ static inline struct device_d *at91_add_sam9x5_gpio(int id, resource_size_t starreturn add_generic_device ("at91sam9x5-gpio" , id,NULL , start,512 ,IORESOURCE_MEM ,NULL ); } + +static inline struct device_d *at91_add_pit (resource_size_t start) +{ +return add_generic_device ("at91-pit" ,DEVICE_ID_SINGLE ,NULL , start,16 , +IORESOURCE_MEM ,NULL ); +}
arch/arm/mach-at91/include/mach/at91_pit.h +4 -4
@@ -16,16 +16,16 @@#ifndef AT91_PIT_H #define AT91_PIT_H -#define AT91_PIT_MR (AT91_PIT + 0x00)/* Mode Register */ +#define AT91_PIT_MR 0x00/* Mode Register */ #define AT91_PIT_PITIEN (1 << 25)/* Timer Interrupt Enable */ #define AT91_PIT_PITEN (1 << 24)/* Timer Enabled */ #define AT91_PIT_PIV (0xfffff)/* Periodic Interval Value */ -#define AT91_PIT_SR (AT91_PIT + 0x04)/* Status Register */ +#define AT91_PIT_SR 0x04/* Status Register */ #define AT91_PIT_PITS (1 << 0)/* Timer Status */ -#define AT91_PIT_PIVR (AT91_PIT + 0x08)/* Periodic Interval Value Register */ -#define AT91_PIT_PIIR (AT91_PIT + 0x0c)/* Periodic Interval Image Register */ +#define AT91_PIT_PIVR 0x08/* Periodic Interval Value Register */ +#define AT91_PIT_PIIR 0x0c/* Periodic Interval Image Register */ #define AT91_PIT_PICNT (0xfff << 20)/* Interval Counter */ #define AT91_PIT_CPIV (0xfffff)/* Inverval Value */
arch/arm/mach-at91/include/mach/at91sam9260.h +0 -1
@@ -105,7 +105,6 @@#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
arch/arm/mach-at91/include/mach/at91sam9261.h +0 -1
@@ -91,7 +91,6 @@#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA
arch/arm/mach-at91/include/mach/at91sam9263.h +0 -1
@@ -109,7 +109,6 @@#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA
arch/arm/mach-at91/include/mach/at91sam9g45.h +0 -1
@@ -120,7 +120,6 @@#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA
arch/arm/mach-at91/include/mach/at91sam9n12.h +0 -1
@@ -116,7 +116,6 @@#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA
arch/arm/mach-at91/include/mach/at91sam9x5.h +0 -1
@@ -123,7 +123,6 @@#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA
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1.7.10.4 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 08/13] at91: PIT: switch to platfrom_driver
subject: s/platfrom_driver/platform_driver/
Sascha
Quoted 300 lines · Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>--- arch/arm/mach-at91/at91sam9260.c | 1 + arch/arm/mach-at91/at91sam9261.c | 1 + arch/arm/mach-at91/at91sam9263.c | 1 + arch/arm/mach-at91/at91sam926x_time.c | 47 +++++++++++++++++++++---- arch/arm/mach-at91/at91sam9g45.c | 1 + arch/arm/mach-at91/at91sam9n12.c | 1 + arch/arm/mach-at91/at91sam9x5.c | 1 + arch/arm/mach-at91/generic.h | 6 ++++ arch/arm/mach-at91/include/mach/at91_pit.h | 8 ++--- arch/arm/mach-at91/include/mach/at91sam9260.h | 1 - arch/arm/mach-at91/include/mach/at91sam9261.h | 1 - arch/arm/mach-at91/include/mach/at91sam9263.h | 1 - arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 - arch/arm/mach-at91/include/mach/at91sam9n12.h | 1 - arch/arm/mach-at91/include/mach/at91sam9x5.h | 1 - 15 files changed, 56 insertions(+), 17 deletions(-)arch/arm/mach-at91/at91sam9260.c +1
-0@@ -239,6 +239,7 @@ static int at91sam9260_gpio_init(void)at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA );at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB );at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC ); +at91_add_pit (AT91SAM9260_BASE_PIT );return 0 ; }arch/arm/mach-at91/at91sam9261.c +1
-0@@ -231,6 +231,7 @@ static int at91sam9261_gpio_init(void)at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA );at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB );at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC ); +at91_add_pit (AT91SAM9261_BASE_PIT );return 0 ; }arch/arm/mach-at91/at91sam9263.c +1
-0@@ -250,6 +250,7 @@ static int at91sam9263_gpio_init(void)at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC );at91_add_rm9200_gpio (3 ,AT91_BASE_PIOD );at91_add_rm9200_gpio (4 ,AT91_BASE_PIOE ); +at91_add_pit (AT91SAM9263_BASE_PIT );return 0 ; }arch/arm/mach-at91/at91sam926x_time.c +40
-7@@ -30,15 +30,20 @@#include <clock.h> #include <asm/hardware.h> #include <mach/at91_pit.h> -#include <mach/at91_rstc.h> #include <mach/io.h> #include <io.h> #include <linux/clk.h> #include <linux/err.h> +#define PIT_CPIV (x) ((x) & AT91_PIT_CPIV) +#define pit_write (reg, val) __raw_writel(val, pit_base + reg) +#define pit_read (reg) __raw_readl(pit_base + reg) + +static __iomem void *pit_base; +uint64_t at91sam9_clocksource_read (void ) { -return at91_sys_read (AT91_PIT_PIIR ); +return pit_read (AT91_PIT_PIIR ); }static struct clocksource cs = {@@ -47,12 +52,30 @@ static struct clocksource cs = { .shift = 10, }; -static int clocksource_init (void ) +static void at91_pit_stop (void ) +{ +/* Disable timer and irqs */ +pit_write (AT91_PIT_MR ,0 ); + +/* Clear any pending interrupts, wait for PIT to stop counting */ +while (PIT_CPIV (pit_read (AT91_PIT_PIVR )) !=0 ); +} + +static void at91sam926x_pit_reset (void ) +{ +at91_pit_stop (); + +/* Start PIT but don't enable IRQ */ +pit_write (AT91_PIT_MR ,0xfffff |AT91_PIT_PITEN ); +} + +static int at91_pit_probe (struct device_d *dev) {struct clk *clk;u32 pit_rate; +int ret; - clk =clk_get (NULL ,"mck" ); + clk =clk_get (dev,NULL );if (IS_ERR (clk)) { ret =PTR_ERR (clk);dev_err (dev,"clock not found: %d\n" , ret);@@ -66,10 +89,11 @@ static int clocksource_init (void)return ret; } + pit_base =dev_request_mem_region (dev,0 ); + pit_rate =clk_get_rate (clk) /16 ; -/* Enable PITC */ -at91_sys_write (AT91_PIT_MR ,0xfffff |AT91_PIT_PITEN ); +at91sam926x_pit_reset (); cs.mult =clocksource_hz2mult (pit_rate, cs.shift);@@ -78,4 +102,13 @@ static int clocksource_init (void)return 0 ; } -core_initcall (clocksource_init); +static struct driver_d at91_pit_driver = { + .name ="at91-pit" , + .probe = at91_pit_probe, +}; + +static int at91_pit_init (void ) +{ +return platform_driver_register (&at91_pit_driver); +} +postcore_initcall (at91_pit_init);arch/arm/mach-at91/at91sam9g45.c +1
-0@@ -263,6 +263,7 @@ static int at91sam9g45_gpio_init(void)at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC );at91_add_rm9200_gpio (3 ,AT91_BASE_PIOD );at91_add_rm9200_gpio (4 ,AT91_BASE_PIOE ); +at91_add_pit (AT91SAM9G45_BASE_PIT );return 0 ; }arch/arm/mach-at91/at91sam9n12.c +1
-0@@ -222,6 +222,7 @@ static int at91sam9n12_gpio_init(void)at91_add_sam9x5_gpio (1 ,AT91_BASE_PIOB );at91_add_sam9x5_gpio (2 ,AT91_BASE_PIOC );at91_add_sam9x5_gpio (3 ,AT91_BASE_PIOD ); +at91_add_pit (AT91SAM9N12_BASE_PIT );return 0 ; }arch/arm/mach-at91/at91sam9x5.c +1
-0@@ -307,6 +307,7 @@ static int at91sam9x5_gpio_init(void)at91_add_sam9x5_gpio (1 ,AT91_BASE_PIOB );at91_add_sam9x5_gpio (2 ,AT91_BASE_PIOC );at91_add_sam9x5_gpio (3 ,AT91_BASE_PIOD ); +at91_add_pit (AT91SAM9X5_BASE_PIT );return 0 ; }arch/arm/mach-at91/generic.h +6
-0@@ -22,3 +22,9 @@ static inline struct device_d *at91_add_sam9x5_gpio(int id, resource_size_t starreturn add_generic_device ("at91sam9x5-gpio" , id,NULL , start,512 ,IORESOURCE_MEM ,NULL ); } + +static inline struct device_d *at91_add_pit (resource_size_t start) +{ +return add_generic_device ("at91-pit" ,DEVICE_ID_SINGLE ,NULL , start,16 , +IORESOURCE_MEM ,NULL ); +}arch/arm/mach-at91/include/mach/at91_pit.h +4
-4@@ -16,16 +16,16 @@#ifndef AT91_PIT_H #define AT91_PIT_H -#define AT91_PIT_MR (AT91_PIT + 0x00)/* Mode Register */ +#define AT91_PIT_MR 0x00/* Mode Register */ #define AT91_PIT_PITIEN (1 << 25)/* Timer Interrupt Enable */ #define AT91_PIT_PITEN (1 << 24)/* Timer Enabled */ #define AT91_PIT_PIV (0xfffff)/* Periodic Interval Value */ -#define AT91_PIT_SR (AT91_PIT + 0x04)/* Status Register */ +#define AT91_PIT_SR 0x04/* Status Register */ #define AT91_PIT_PITS (1 << 0)/* Timer Status */ -#define AT91_PIT_PIVR (AT91_PIT + 0x08)/* Periodic Interval Value Register */ -#define AT91_PIT_PIIR (AT91_PIT + 0x0c)/* Periodic Interval Image Register */ +#define AT91_PIT_PIVR 0x08/* Periodic Interval Value Register */ +#define AT91_PIT_PIIR 0x0c/* Periodic Interval Image Register */ #define AT91_PIT_PICNT (0xfff << 20)/* Interval Counter */ #define AT91_PIT_CPIV (0xfffff)/* Inverval Value */ arch/arm/mach-at91/include/mach/at91sam9260.h +0
-1@@ -105,7 +105,6 @@#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOAarch/arm/mach-at91/include/mach/at91sam9261.h +0
-1@@ -91,7 +91,6 @@#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOAarch/arm/mach-at91/include/mach/at91sam9263.h +0
-1@@ -109,7 +109,6 @@#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOAarch/arm/mach-at91/include/mach/at91sam9g45.h +0
-1@@ -120,7 +120,6 @@#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOAarch/arm/mach-at91/include/mach/at91sam9n12.h +0
-1@@ -116,7 +116,6 @@#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOAarch/arm/mach-at91/include/mach/at91sam9x5.h +0
-1@@ -123,7 +123,6 @@#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOASignature · 7 lines
1.7.10.4 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Signature · 9 lines
Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 9/13 at91: autodetect the soc one time at postcore_initcall
In reply to Jean-Christophe PLAGNIOL-VILLARDand then register a device
The code is take from linux
drop AT91_BASE_SYS for dbgu
factorise the soc type in the Kconfig but keep the ARCH_ so far as the device code have the same function accross soc which for now does not allow us to compile soc together
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/mach-at91/Kconfig | 99 ++++++++---- arch/arm/mach-at91/Makefile | 2 +- arch/arm/mach-at91/at91rm9200.c | 17 +- arch/arm/mach-at91/at91sam9260.c | 17 +- arch/arm/mach-at91/at91sam9261.c | 17 +- arch/arm/mach-at91/at91sam9263.c | 17 +- arch/arm/mach-at91/at91sam9g45.c | 18 +-- arch/arm/mach-at91/at91sam9n12.c | 17 +- arch/arm/mach-at91/at91sam9x5.c | 17 +- arch/arm/mach-at91/include/mach/at91_dbgu.h | 26 +-- arch/arm/mach-at91/include/mach/cpu.h | 190 +++++++++++----------- arch/arm/mach-at91/setup.c | 226 +++++++++++++++++++++++++++ arch/arm/mach-at91/soc.h | 66 ++++++++ 13 files changed, 515 insertions(+), 214 deletions(-) create mode 100644 arch/arm/mach-at91/setup.c create mode 100644 arch/arm/mach-at91/soc.h
arch/arm/mach-at91/Kconfig +69 -30
@@ -49,69 +49,108 @@ config AT91SAM9G45_RESET comment "Atmel AT91 System-on-Chip" -choice - prompt "Atmel AT91 Processor" - -config ARCH_AT91RM9200 - bool "AT91RM9200" +config SOC_AT91RM9200 + bool select CPU_ARM920T select HAVE_AT91_DBGU0 select HAS_AT91_ETHER select MACH_HAS_LOWLEVEL_INIT - select MACH_DO_LOWLEVEL_INIT -config ARCH_AT91SAM9260 - bool "AT91SAM9260" +config SOC_AT91SAM9260 + bool select CPU_ARM926T select HAVE_AT91_DBGU0 select HAS_MACB select AT91SAM9_RESET + help + Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE + or AT91SAM9G20 SoC. -config ARCH_AT91SAM9261 - bool "AT91SAM9261" +config SOC_AT91SAM9261 + bool select CPU_ARM926T select HAVE_AT91_DBGU0 select AT91SAM9_RESET + help + Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. -config ARCH_AT91SAM9263 - bool "AT91SAM9263" +config SOC_AT91SAM9263 + bool select CPU_ARM926T select HAVE_AT91_DBGU1 select HAS_MACB select AT91SAM9_RESET -config ARCH_AT91SAM9G10 - bool "AT91SAM9G10" +config SOC_AT91SAM9G45 + bool select CPU_ARM926T - select HAVE_AT91_DBGU0 - select AT91SAM9_RESET + select HAVE_AT91_DBGU1 + select HAS_MACB + select AT91SAM9G45_RESET + help + Select this if you are using one of Atmel's AT91SAM9G45 family SoC. + This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. -config ARCH_AT91SAM9G20 - bool "AT91SAM9G20" +config SOC_AT91SAM9X5 + bool select CPU_ARM926T select HAVE_AT91_DBGU0 select HAS_MACB - select AT91SAM9_RESET + select AT91SAM9G45_RESET + help + Select this if you are using one of Atmel's AT91SAM9x5 family SoC. + This means that your SAM9 name finishes with a '5' (except if it is + AT91SAM9G45!). + This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35 + and AT91SAM9X35. -config ARCH_AT91SAM9G45 - bool "AT91SAM9G45 or AT91SAM9M10" +config SOC_AT91SAM9N12 + bool select CPU_ARM926T - select HAVE_AT91_DBGU1 - select HAS_MACB + select HAVE_AT91_DBGU0 select AT91SAM9G45_RESET + help + Select this if you are using Atmel's AT91SAM9N12 SoC. + +choice + prompt "Atmel AT91 Processor" + +config ARCH_AT91RM9200 + bool "AT91RM9200" + select MACH_DO_LOWLEVEL_INIT + select SOC_AT91RM9200 + +config ARCH_AT91SAM9260 + bool "AT91SAM9260" + select SOC_AT91SAM9260 + +config ARCH_AT91SAM9261 + bool "AT91SAM9261" + select SOC_AT91SAM9261 + +config ARCH_AT91SAM9263 + bool "AT91SAM9263" + select SOC_AT91SAM9263 + +config ARCH_AT91SAM9G10 + bool "AT91SAM9G10" + select SOC_AT91SAM9261 + +config ARCH_AT91SAM9G20 + bool "AT91SAM9G20" + select SOC_AT91SAM9260 + +config ARCH_AT91SAM9G45 + bool "AT91SAM9G45 or AT91SAM9M10" + select SOC_AT91SAM9G45 config ARCH_AT91SAM9X5 bool "AT91SAM9X5" - select CPU_ARM926T - select HAVE_AT91_DBGU0 - select HAS_MACB - select AT91SAM9G45_RESET + select SOC_AT91SAM9X5 config ARCH_AT91SAM9N12 bool "AT91SAM9N12" - select CPU_ARM926T - select HAVE_AT91_DBGU0 - select AT91SAM9G45_RESET + select SOC_AT91SAM9N12 endchoice
arch/arm/mach-at91/Makefile +1 -1
@@ -1,4 +1,4 @@ -obj-y += clock.o gpio.o +obj-y += setup.o clock.o gpio.o lowlevel_init-y = at91sam926x_lowlevel_init.o lowlevel_init-$(CONFIG_ARCH_AT91RM9200) = at91rm9200_lowlevel_init.o
arch/arm/mach-at91/at91rm9200.c +6 -11
@@ -4,6 +4,7 @@#include <asm/hardware.h> #include <mach/at91_pmc.h> +#include "soc.h" #include "clock.h" #include "generic.h"
@@ -222,27 +223,21 @@ static void __init at91rm9200_register_clocks(void)/* -------------------------------------------------------------------- * AT91RM9200 processor initialization * -------------------------------------------------------------------- */ -static int __init at91rm9200_initialize (void ) +static void __init at91rm9200_initialize (void ) { -/* Init clock subsystem */ at91_clock_init (AT91_MAIN_CLOCK );/* Register the processor-specific clocks */ at91rm9200_register_clocks (); -return 0 ; -} -core_initcall (at91rm9200_initialize); - -static int at91rm9200_gpio_init (void ) -{/* Register GPIO subsystem */ at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA );at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB );at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC );at91_add_rm9200_gpio (3 ,AT91_BASE_PIOD ); - -return 0 ; } -postcore_initcall (at91rm9200_gpio_init); + +AT91_SOC_START (rm9200) + .init = at91rm9200_initialize, +AT91_SOC_END
arch/arm/mach-at91/at91sam9260.c +7 -10
@@ -4,6 +4,7 @@#include <asm/hardware.h> #include <mach/at91_pmc.h> +#include "soc.h" #include "generic.h" #include "clock.h"
@@ -221,7 +222,7 @@ static void __init at91sam9260_register_clocks(void)clk_register (&pck1); } -static int at91sam9260_initialize (void ) +static void at91sam9260_initialize (void ) {/* Init clock subsystem */ at91_clock_init (AT91_MAIN_CLOCK );
@@ -229,18 +230,14 @@ static int at91sam9260_initialize(void)/* Register the processor-specific clocks */ at91sam9260_register_clocks (); -return 0 ; -} -core_initcall (at91sam9260_initialize); - -static int at91sam9260_gpio_init (void ) -{/* Register GPIO subsystem */ at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA );at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB );at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC ); -at91_add_pit (AT91SAM9260_BASE_PIT ); -return 0 ; +at91_add_pit (AT91SAM9260_BASE_PIT ); } -postcore_initcall (at91sam9260_gpio_init); + +AT91_SOC_START (sam9260) + .init = at91sam9260_initialize, +AT91_SOC_END
arch/arm/mach-at91/at91sam9261.c +7 -10
@@ -4,6 +4,7 @@#include <asm/hardware.h> #include <mach/at91_pmc.h> +#include "soc.h" #include "generic.h" #include "clock.h"
@@ -213,7 +214,7 @@ static void at91sam9261_register_clocks(void)clk_register (&hck1); } -static int at91sam9261_initialize (void ) +static void at91sam9261_initialize (void ) {/* Init clock subsystem */ at91_clock_init (AT91_MAIN_CLOCK );
@@ -221,18 +222,14 @@ static int at91sam9261_initialize(void)/* Register the processor-specific clocks */ at91sam9261_register_clocks (); -return 0 ; -} -core_initcall (at91sam9261_initialize); - -static int at91sam9261_gpio_init (void ) -{/* Register GPIO subsystem */ at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA );at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB );at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC ); -at91_add_pit (AT91SAM9261_BASE_PIT ); -return 0 ; +at91_add_pit (AT91SAM9261_BASE_PIT ); } -postcore_initcall (at91sam9261_gpio_init); + +AT91_SOC_START (sam9261) + .init = at91sam9261_initialize, +AT91_SOC_END
arch/arm/mach-at91/at91sam9263.c +7 -10
@@ -4,6 +4,7 @@#include <asm/hardware.h> #include <mach/at91_pmc.h> +#include "soc.h" #include "clock.h" #include "generic.h"
@@ -230,7 +231,7 @@ static void __init at91sam9263_register_clocks(void)clk_register (&pck3); } -static int at91sam9263_initialize (void ) +static void at91sam9263_initialize (void ) {/* Init clock subsystem */ at91_clock_init (AT91_MAIN_CLOCK );
@@ -238,20 +239,16 @@ static int at91sam9263_initialize(void)/* Register the processor-specific clocks */ at91sam9263_register_clocks (); -return 0 ; -} -core_initcall (at91sam9263_initialize); - -static int at91sam9263_gpio_init (void ) -{/* Register GPIO subsystem */ at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA );at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB );at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC );at91_add_rm9200_gpio (3 ,AT91_BASE_PIOD );at91_add_rm9200_gpio (4 ,AT91_BASE_PIOE ); -at91_add_pit (AT91SAM9263_BASE_PIT ); -return 0 ; +at91_add_pit (AT91SAM9263_BASE_PIT ); } -postcore_initcall (at91sam9263_gpio_init); + +AT91_SOC_START (sam9263) + .init = at91sam9263_initialize, +AT91_SOC_END
arch/arm/mach-at91/at91sam9g45.c +7 -11
@@ -6,6 +6,7 @@#include <mach/at91_pmc.h> #include <mach/cpu.h> +#include "soc.h" #include "generic.h" #include "clock.h"
@@ -242,7 +243,7 @@ static void __init at91sam9g45_register_clocks(void)clk_register (&pck1); } -static int at91sam9g45_initialize (void ) +static void at91sam9g45_initialize (void ) {/* Init clock subsystem */ at91_clock_init (AT91_MAIN_CLOCK );
@@ -250,21 +251,16 @@ static int at91sam9g45_initialize(void)/* Register the processor-specific clocks */ at91sam9g45_register_clocks (); -return 0 ; -} - -core_initcall (at91sam9g45_initialize); - -static int at91sam9g45_gpio_init (void ) -{/* Register GPIO subsystem */ at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA );at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB );at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC );at91_add_rm9200_gpio (3 ,AT91_BASE_PIOD );at91_add_rm9200_gpio (4 ,AT91_BASE_PIOE ); -at91_add_pit (AT91SAM9G45_BASE_PIT ); -return 0 ; +at91_add_pit (AT91SAM9G45_BASE_PIT ); } -postcore_initcall (at91sam9g45_gpio_init); + +AT91_SOC_START (sam9g45) + .init = at91sam9g45_initialize, +AT91_SOC_END
arch/arm/mach-at91/at91sam9n12.c +7 -10
@@ -6,6 +6,7 @@#include <mach/io.h> #include <mach/cpu.h> +#include "soc.h" #include "generic.h" #include "clock.h"
@@ -203,7 +204,7 @@ static void __init at91sam9n12_register_clocks(void)* AT91SAM9N12 processor initialization * -------------------------------------------------------------------- */ -static int at91sam9n12_initialize (void ) +static void at91sam9n12_initialize (void ) {/* Init clock subsystem */ at91_clock_init (AT91_MAIN_CLOCK );
@@ -211,19 +212,15 @@ static int at91sam9n12_initialize(void)/* Register the processor-specific clocks */ at91sam9n12_register_clocks (); -return 0 ; -} -core_initcall (at91sam9n12_initialize); - -static int at91sam9n12_gpio_init (void ) -{/* Register GPIO subsystem */ at91_add_sam9x5_gpio (0 ,AT91_BASE_PIOA );at91_add_sam9x5_gpio (1 ,AT91_BASE_PIOB );at91_add_sam9x5_gpio (2 ,AT91_BASE_PIOC );at91_add_sam9x5_gpio (3 ,AT91_BASE_PIOD ); -at91_add_pit (AT91SAM9N12_BASE_PIT ); -return 0 ; +at91_add_pit (AT91SAM9N12_BASE_PIT ); } -postcore_initcall (at91sam9n12_gpio_init); + +AT91_SOC_START (sam9n12) + .init = at91sam9n12_initialize, +AT91_SOC_END
arch/arm/mach-at91/at91sam9x5.c +7 -10
@@ -6,6 +6,7 @@#include <mach/io.h> #include <mach/cpu.h> +#include "soc.h" #include "generic.h" #include "clock.h"
@@ -288,7 +289,7 @@ static void __init at91sam9x5_register_clocks(void)* AT91SAM9x5 processor initialization * -------------------------------------------------------------------- */ -static int at91sam9x5_initialize (void ) +static void at91sam9x5_initialize (void ) {/* Init clock subsystem */ at91_clock_init (AT91_MAIN_CLOCK );
@@ -296,19 +297,15 @@ static int at91sam9x5_initialize(void)/* Register the processor-specific clocks */ at91sam9x5_register_clocks (); -return 0 ; -} -core_initcall (at91sam9x5_initialize); - -static int at91sam9x5_gpio_init (void ) -{/* Register GPIO subsystem */ at91_add_sam9x5_gpio (0 ,AT91_BASE_PIOA );at91_add_sam9x5_gpio (1 ,AT91_BASE_PIOB );at91_add_sam9x5_gpio (2 ,AT91_BASE_PIOC );at91_add_sam9x5_gpio (3 ,AT91_BASE_PIOD ); -at91_add_pit (AT91SAM9X5_BASE_PIT ); -return 0 ; +at91_add_pit (AT91SAM9X5_BASE_PIT ); } -postcore_initcall (at91sam9x5_gpio_init); + +AT91_SOC_START (sam9x5) + .init = at91sam9x5_initialize, +AT91_SOC_END
arch/arm/mach-at91/include/mach/at91_dbgu.h +13 -13
@@ -16,22 +16,22 @@#ifndef AT91_DBGU_H #define AT91_DBGU_H -#ifdef AT91_DBGU -#define AT91_DBGU_CR (AT91_DBGU + 0x00)/* Control Register */ -#define AT91_DBGU_MR (AT91_DBGU + 0x04)/* Mode Register */ -#define AT91_DBGU_IER (AT91_DBGU + 0x08)/* Interrupt Enable Register */ +#if !defined(CONFIG_ARCH_AT91X40 ) +#define AT91_DBGU_CR (0x00)/* Control Register */ +#define AT91_DBGU_MR (0x04)/* Mode Register */ +#define AT91_DBGU_IER (0x08)/* Interrupt Enable Register */ #define AT91_DBGU_TXRDY (1 << 1)/* Transmitter Ready */ #define AT91_DBGU_TXEMPTY (1 << 9)/* Transmitter Empty */ -#define AT91_DBGU_IDR (AT91_DBGU + 0x0c)/* Interrupt Disable Register */ -#define AT91_DBGU_IMR (AT91_DBGU + 0x10)/* Interrupt Mask Register */ -#define AT91_DBGU_SR (AT91_DBGU + 0x14)/* Status Register */ -#define AT91_DBGU_RHR (AT91_DBGU + 0x18)/* Receiver Holding Register */ -#define AT91_DBGU_THR (AT91_DBGU + 0x1c)/* Transmitter Holding Register */ -#define AT91_DBGU_BRGR (AT91_DBGU + 0x20)/* Baud Rate Generator Register */ +#define AT91_DBGU_IDR (0x0c)/* Interrupt Disable Register */ +#define AT91_DBGU_IMR (0x10)/* Interrupt Mask Register */ +#define AT91_DBGU_SR (0x14)/* Status Register */ +#define AT91_DBGU_RHR (0x18)/* Receiver Holding Register */ +#define AT91_DBGU_THR (0x1c)/* Transmitter Holding Register */ +#define AT91_DBGU_BRGR (0x20)/* Baud Rate Generator Register */ -#define AT91_DBGU_CIDR (AT91_DBGU + 0x40)/* Chip ID Register */ -#define AT91_DBGU_EXID (AT91_DBGU + 0x44)/* Chip ID Extension Register */ -#define AT91_DBGU_FNR (AT91_DBGU + 0x48)/* Force NTRST Register [SAM9 only] */ +#define AT91_DBGU_CIDR (0x40)/* Chip ID Register */ +#define AT91_DBGU_EXID (0x44)/* Chip ID Extension Register */ +#define AT91_DBGU_FNR (0x48)/* Force NTRST Register [SAM9 only] */ #define AT91_DBGU_FNTRST (1 << 0)/* Force NTRST */ #endif /* AT91_DBGU */
arch/arm/mach-at91/include/mach/cpu.h +92 -98
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arch/arm/mach-at91/setup.c new file +226 -0
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arch/arm/mach-at91/soc.h new file +66 -0
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1.7.10.4 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 10/13 at91: SMC: switch to platfrom_driver
In reply to Jean-Christophe PLAGNIOL-VILLARDThis will allow to support multiple arch
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/boards/at91sam9260ek/init.c | 3 +- arch/arm/boards/at91sam9261ek/init.c | 5 +- arch/arm/boards/at91sam9263ek/init.c | 3 +- arch/arm/boards/at91sam9m10g45ek/init.c | 3 +- arch/arm/boards/at91sam9n12ek/init.c | 5 +- arch/arm/boards/at91sam9x5ek/init.c | 3 +- arch/arm/boards/dss11/init.c | 3 +- arch/arm/boards/pm9261/init.c | 5 +- arch/arm/boards/pm9263/init.c | 3 +- arch/arm/boards/pm9g45/init.c | 3 +- arch/arm/boards/qil-a9260/init.c | 3 +- arch/arm/boards/tny-a926x/init.c | 5 +- arch/arm/boards/usb-a926x/init.c | 5 +- arch/arm/mach-at91/at91sam9260.c | 1 + arch/arm/mach-at91/at91sam9261.c | 1 + arch/arm/mach-at91/at91sam9263.c | 2 + arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 8 +- arch/arm/mach-at91/at91sam9g45.c | 1 + arch/arm/mach-at91/at91sam9n12.c | 1 + arch/arm/mach-at91/at91sam9x5.c | 1 + arch/arm/mach-at91/generic.h | 7 ++ arch/arm/mach-at91/include/mach/at91sam9260.h | 3 +- arch/arm/mach-at91/include/mach/at91sam9261.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9263.h | 3 +- arch/arm/mach-at91/include/mach/at91sam9_smc.h | 50 ++++++-- arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9n12.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 +- arch/arm/mach-at91/include/mach/sam9_smc.h | 33 ------ arch/arm/mach-at91/sam9_smc.c | 146 ++++++++++++++++++++---- 30 files changed, 206 insertions(+), 108 deletions(-) delete mode 100644 arch/arm/mach-at91/include/mach/sam9_smc.h
arch/arm/boards/at91sam9260ek/init.c +1 -2
@@ -31,7 +31,6 @@#include <linux/mtd/nand.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_pmc.h>
@@ -122,7 +121,7 @@ static void ek_add_device_nand(void) smc->mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , smc); +sam9_smc_configure (0 ,3 , smc);at91_add_device_nand (&nand_pdata); }
arch/arm/boards/at91sam9261ek/init.c +2 -3
@@ -33,7 +33,6 @@#include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <dm9000.h> #include <gpio_keys.h> #include <readkey.h>
@@ -80,7 +79,7 @@ static void ek_add_device_nand(void) ek_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &ek_nand_smc_config); +sam9_smc_configure (0 ,3 , &ek_nand_smc_config);at91_add_device_nand (&nand_pdata); }
@@ -118,7 +117,7 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {static void __init ek_add_device_dm9000 (void ) {/* Configure chip-select 2 (DM9000) */ -sam9_smc_configure (2 , &dm9000_smc_config); +sam9_smc_configure (0 ,2 , &dm9000_smc_config);/* Configure Reset signal as output */ at91_set_gpio_output (AT91_PIN_PC10 ,0 );
arch/arm/boards/at91sam9263ek/init.c +1 -2
@@ -35,7 +35,6 @@#include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> static struct atmel_nand_data nand_pdata = { .ale =21 ,
@@ -78,7 +77,7 @@ static void ek_add_device_nand(void) ek_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &ek_nand_smc_config); +sam9_smc_configure (0 ,3 , &ek_nand_smc_config);at91_add_device_nand (&nand_pdata); }
arch/arm/boards/at91sam9m10g45ek/init.c +1 -2
@@ -36,7 +36,6 @@#include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio_keys.h> #include <readkey.h>
@@ -101,7 +100,7 @@ static void ek_add_device_nand(void) ek_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &ek_nand_smc_config); +sam9_smc_configure (0 ,3 , &ek_nand_smc_config);at91_add_device_nand (&nand_pdata); }
arch/arm/boards/at91sam9n12ek/init.c +2 -3
@@ -31,7 +31,6 @@#include <linux/mtd/nand.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_pmc.h>
@@ -77,7 +76,7 @@ static void ek_add_device_nand(void) ek_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &ek_nand_smc_config); +sam9_smc_configure (0 ,3 , &ek_nand_smc_config);at91_add_device_nand (&nand_pdata); }
@@ -112,7 +111,7 @@ static struct sam9_smc_config __initdata ks8851_smc_config = {static void __init ek_add_device_ks8851 (void ) {/* Configure chip-select 2 (KS8851) */ -sam9_smc_configure (2 , &ks8851_smc_config); +sam9_smc_configure (0 ,2 , &ks8851_smc_config);/* Configure NCS signal */ at91_set_B_periph (AT91_PIN_PD19 ,0 );/* Configure Interrupt pin as input, no pull-up */
arch/arm/boards/at91sam9x5ek/init.c +1 -2
@@ -31,7 +31,6 @@#include <linux/mtd/nand.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_pmc.h>
@@ -93,7 +92,7 @@ static void ek_add_device_nand(void) cm_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &cm_nand_smc_config); +sam9_smc_configure (0 ,3 , &cm_nand_smc_config);if (at91sam9x5ek_cm_is_vendor (VENDOR_COGENT )) {unsigned long csa;
arch/arm/boards/dss11/init.c +1 -2
@@ -29,7 +29,6 @@#include <linux/mtd/nand.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_rstc.h>
@@ -69,7 +68,7 @@ static void dss11_add_device_nand(void) dss11_nand_smc_config.mode |=AT91_SMC_DBW_16 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &dss11_nand_smc_config); +sam9_smc_configure (0 ,3 , &dss11_nand_smc_config);at91_add_device_nand (&nand_pdata); }
arch/arm/boards/pm9261/init.c +2 -3
@@ -34,7 +34,6 @@#include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <dm9000.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h>
@@ -84,7 +83,7 @@ static void pm_add_device_nand(void) pm_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &pm_nand_smc_config); +sam9_smc_configure (0 ,3 , &pm_nand_smc_config);at91_add_device_nand (&nand_pdata); }
@@ -123,7 +122,7 @@ static void __init pm_add_device_dm9000(void) {w1_local_mac_address_register (0 ,"ron" ,"w1-1-0" );/* Configure chip-select 2 (DM9000) */ -sam9_smc_configure (2 , &dm9000_smc_config); +sam9_smc_configure (0 ,2 , &dm9000_smc_config);add_dm9000_device (0 ,AT91_CHIPSELECT_2 ,AT91_CHIPSELECT_2 +4 ,IORESOURCE_MEM_16BIT , &dm9000_data);
arch/arm/boards/pm9263/init.c +1 -2
@@ -35,7 +35,6 @@#include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h>
@@ -84,7 +83,7 @@ static void pm_add_device_nand(void) pm_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &pm_nand_smc_config); +sam9_smc_configure (0 ,3 , &pm_nand_smc_config);at91_add_device_nand (&nand_pdata); }
arch/arm/boards/pm9g45/init.c +1 -2
@@ -34,7 +34,6 @@#include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h>
@@ -76,7 +75,7 @@ static void pm_add_device_nand(void) pm_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &pm_nand_smc_config); +sam9_smc_configure (0 ,3 , &pm_nand_smc_config);at91_add_device_nand (&nand_pdata); }
arch/arm/boards/qil-a9260/init.c +1 -2
@@ -22,7 +22,6 @@#include <linux/clk.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <led.h> #include <mach/io.h>
@@ -59,7 +58,7 @@ static struct sam9_smc_config nand_smc_config = {static void qil_a9260_add_device_nand (void ) {/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &nand_smc_config); +sam9_smc_configure (0 ,3 , &nand_smc_config);at91_add_device_nand (&nand_pdata); }
arch/arm/boards/tny-a926x/init.c +2 -3
@@ -32,7 +32,6 @@#include <mach/board.h> #include <mach/at91sam9_smc.h> #include <mach/at91sam9_sdramc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_pmc.h>
@@ -100,9 +99,9 @@ static void tny_a9260_add_device_nand(void) {/* configure chip-select 3 (NAND) */ if (machine_is_tny_a9g20 ()) -sam9_smc_configure (3 , &tny_a9g20_nand_smc_config); +sam9_smc_configure (0 ,3 , &tny_a9g20_nand_smc_config);else -sam9_smc_configure (3 , &tny_a9260_nand_smc_config); +sam9_smc_configure (0 ,3 , &tny_a9260_nand_smc_config);if (machine_is_tny_a9263 ()) { nand_pdata.rdy_pin =AT91_PIN_PA22 ;
arch/arm/boards/usb-a926x/init.c +2 -3
@@ -32,7 +32,6 @@#include <mach/board.h> #include <mach/at91sam9_smc.h> #include <mach/at91sam9_sdramc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <led.h> #include <mach/io.h>
@@ -101,9 +100,9 @@ static void usb_a9260_add_device_nand(void) {/* configure chip-select 3 (NAND) */ if (machine_is_usb_a9g20 ()) -sam9_smc_configure (3 , &usb_a9g20_nand_smc_config); +sam9_smc_configure (0 ,3 , &usb_a9g20_nand_smc_config);else -sam9_smc_configure (3 , &usb_a9260_nand_smc_config); +sam9_smc_configure (0 ,3 , &usb_a9260_nand_smc_config);if (machine_is_usb_a9263 ()) { nand_pdata.rdy_pin =AT91_PIN_PA22 ;
arch/arm/mach-at91/at91sam9260.c +1 -0
@@ -236,6 +236,7 @@ static void at91sam9260_initialize(void)at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC );at91_add_pit (AT91SAM9260_BASE_PIT ); +at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9260_BASE_SMC ,0x200 ); }AT91_SOC_START (sam9260)
arch/arm/mach-at91/at91sam9261.c +1 -0
@@ -228,6 +228,7 @@ static void at91sam9261_initialize(void)at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC );at91_add_pit (AT91SAM9261_BASE_PIT ); +at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9261_BASE_SMC ,0x200 ); }AT91_SOC_START (sam9261)
arch/arm/mach-at91/at91sam9263.c +2 -0
@@ -247,6 +247,8 @@ static void at91sam9263_initialize(void)at91_add_rm9200_gpio (4 ,AT91_BASE_PIOE );at91_add_pit (AT91SAM9263_BASE_PIT ); +at91_add_sam9_smc (0 ,AT91SAM9263_BASE_SMC0 ,0x200 ); +at91_add_sam9_smc (1 ,AT91SAM9263_BASE_SMC1 ,0x200 ); }AT91_SOC_START (sam9263)
arch/arm/mach-at91/at91sam926x_lowlevel_init.c +4 -4
@@ -62,13 +62,13 @@ void __naked __bare_init reset(void)#endif /* flash */ -at91_sys_write (AT91_SMC_MODE (CONFIG_SYS_SMC_CS ),CONFIG_SYS_SMC_MODE_VAL ); +at91_smc_write (CONFIG_SYS_SMC_CS ,AT91_SMC_MODE ,CONFIG_SYS_SMC_MODE_VAL ); -at91_sys_write (AT91_SMC_CYCLE (CONFIG_SYS_SMC_CS ),CONFIG_SYS_SMC_CYCLE_VAL ); +at91_smc_write (CONFIG_SYS_SMC_CS ,AT91_SMC_CYCLE ,CONFIG_SYS_SMC_CYCLE_VAL ); -at91_sys_write (AT91_SMC_PULSE (CONFIG_SYS_SMC_CS ),CONFIG_SYS_SMC_PULSE_VAL ); +at91_smc_write (CONFIG_SYS_SMC_CS ,AT91_SMC_PULSE ,CONFIG_SYS_SMC_PULSE_VAL ); -at91_sys_write (AT91_SMC_SETUP (CONFIG_SYS_SMC_CS ),CONFIG_SYS_SMC_SETUP_VAL ); +at91_smc_write (CONFIG_SYS_SMC_CS ,AT91_SMC_SETUP ,CONFIG_SYS_SMC_SETUP_VAL );/* * PMC Check if the PLL is already initialized
arch/arm/mach-at91/at91sam9g45.c +1 -0
@@ -259,6 +259,7 @@ static void at91sam9g45_initialize(void)at91_add_rm9200_gpio (4 ,AT91_BASE_PIOE );at91_add_pit (AT91SAM9G45_BASE_PIT ); +at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9G45_BASE_SMC ,0x200 ); }AT91_SOC_START (sam9g45)
arch/arm/mach-at91/at91sam9n12.c +1 -0
@@ -219,6 +219,7 @@ static void at91sam9n12_initialize(void)at91_add_sam9x5_gpio (3 ,AT91_BASE_PIOD );at91_add_pit (AT91SAM9N12_BASE_PIT ); +at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9N12_BASE_SMC ,0x200 ); }AT91_SOC_START (sam9n12)
arch/arm/mach-at91/at91sam9x5.c +1 -0
@@ -304,6 +304,7 @@ static void at91sam9x5_initialize(void)at91_add_sam9x5_gpio (3 ,AT91_BASE_PIOD );at91_add_pit (AT91SAM9X5_BASE_PIT ); +at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9X5_BASE_SMC ,0x200 ); }AT91_SOC_START (sam9x5)
arch/arm/mach-at91/generic.h +7 -0
@@ -28,3 +28,10 @@ static inline struct device_d *at91_add_pit(resource_size_t start)return add_generic_device ("at91-pit" ,DEVICE_ID_SINGLE ,NULL , start,16 ,IORESOURCE_MEM ,NULL ); } + +static inline struct device_d *at91_add_sam9_smc (int id,resource_size_t start, +resource_size_t size) +{ +return add_generic_device ("at91sam9-smc" , id,NULL , start, size, +IORESOURCE_MEM ,NULL ); +}
arch/arm/mach-at91/include/mach/at91sam9260.h +2 -1
@@ -100,13 +100,14 @@*/ #define AT91_ECC (0xffffe800 - AT91_BASE_SYS)#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_BASE_SMC AT91SAM9260_BASE_SMC +#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9260_BASE_PIOB#define AT91_BASE_PIOC AT91SAM9260_BASE_PIOC
arch/arm/mach-at91/include/mach/at91sam9261.h +1 -1
@@ -86,13 +86,13 @@* System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_BASE_SMC AT91SAM9261_BASE_SMC#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9261_BASE_PIOB#define AT91_BASE_PIOC AT91SAM9261_BASE_PIOC
arch/arm/mach-at91/include/mach/at91sam9263.h +1 -2
@@ -104,13 +104,13 @@*/ #define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) -#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_BASE_SMC AT91SAM9263_BASE_SMC0#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9263_BASE_PIOB#define AT91_BASE_PIOC AT91SAM9263_BASE_PIOC
@@ -122,7 +122,6 @@#define AT91_USART2 AT91SAM9263_BASE_US2#define AT91_NB_USART 4 -#define AT91_SMC AT91_SMC0#define AT91_SDRAMC AT91_SDRAMC0#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0
arch/arm/mach-at91/include/mach/at91sam9_smc.h +39 -11
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arch/arm/mach-at91/include/mach/at91sam9g45.h +1 -1
@@ -115,13 +115,13 @@#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_BASE_SMC AT91SAM9G45_BASE_SMC#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9G45_BASE_PIOB#define AT91_BASE_PIOC AT91SAM9G45_BASE_PIOC
arch/arm/mach-at91/include/mach/at91sam9n12.h +1 -1
@@ -112,12 +112,12 @@#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC (0xffffea00 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS) +#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB#define AT91_BASE_PIOC AT91SAM9N12_BASE_PIOC
arch/arm/mach-at91/include/mach/at91sam9x5.h +1 -1
@@ -119,12 +119,12 @@#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC (0xffffea00 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS) +#define AT91_BASE_SMC AT91SAM9X5_BASE_SMC#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9X5_BASE_PIOB#define AT91_BASE_PIOC AT91SAM9X5_BASE_PIOC
arch/arm/mach-at91/include/mach/sam9_smc.h deleted +0 -33
@@ -1,33 +0,0 @@ -/* -* linux/arch/arm/mach-at91/sam9_smc. -* -* Copyright (C) 2008 Andrew Victor -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -*/ - -struct sam9_smc_config { -/* Setup register */ -u8 ncs_read_setup; -u8 nrd_setup; -u8 ncs_write_setup; -u8 nwe_setup; - -/* Pulse register */ -u8 ncs_read_pulse; -u8 nrd_pulse; -u8 ncs_write_pulse; -u8 nwe_pulse; - -/* Cycle register */ -u16 read_cycle; -u16 write_cycle; - -/* Mode register */ -u32 mode; -u8 tdf_cycles:4 ; -}; - -extern void __init sam9_smc_configure (int cs,struct sam9_smc_config * config);
arch/arm/mach-at91/sam9_smc.c +124 -22
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Signature · 7 lines
1.7.10.4 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 10/13] at91: SMC: switch to platfrom_driver
subject: s/platfrom_driver/platform_driver
Sascha
Quoted 876 lines · Jean-Christophe PLAGNIOL-VILLARD
This will allow to support multiple arch
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>--- arch/arm/boards/at91sam9260ek/init.c | 3 +- arch/arm/boards/at91sam9261ek/init.c | 5 +- arch/arm/boards/at91sam9263ek/init.c | 3 +- arch/arm/boards/at91sam9m10g45ek/init.c | 3 +- arch/arm/boards/at91sam9n12ek/init.c | 5 +- arch/arm/boards/at91sam9x5ek/init.c | 3 +- arch/arm/boards/dss11/init.c | 3 +- arch/arm/boards/pm9261/init.c | 5 +- arch/arm/boards/pm9263/init.c | 3 +- arch/arm/boards/pm9g45/init.c | 3 +- arch/arm/boards/qil-a9260/init.c | 3 +- arch/arm/boards/tny-a926x/init.c | 5 +- arch/arm/boards/usb-a926x/init.c | 5 +- arch/arm/mach-at91/at91sam9260.c | 1 + arch/arm/mach-at91/at91sam9261.c | 1 + arch/arm/mach-at91/at91sam9263.c | 2 + arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 8 +- arch/arm/mach-at91/at91sam9g45.c | 1 + arch/arm/mach-at91/at91sam9n12.c | 1 + arch/arm/mach-at91/at91sam9x5.c | 1 + arch/arm/mach-at91/generic.h | 7 ++ arch/arm/mach-at91/include/mach/at91sam9260.h | 3 +- arch/arm/mach-at91/include/mach/at91sam9261.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9263.h | 3 +- arch/arm/mach-at91/include/mach/at91sam9_smc.h | 50 ++++++-- arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9n12.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 +- arch/arm/mach-at91/include/mach/sam9_smc.h | 33 ------ arch/arm/mach-at91/sam9_smc.c | 146 ++++++++++++++++++++---- 30 files changed, 206 insertions(+), 108 deletions(-) delete mode 100644 arch/arm/mach-at91/include/mach/sam9_smc.harch/arm/boards/at91sam9260ek/init.c +1
-2@@ -31,7 +31,6 @@#include <linux/mtd/nand.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_pmc.h> @@ -122,7 +121,7 @@ static void ek_add_device_nand(void) smc->mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , smc); +sam9_smc_configure (0 ,3 , smc);at91_add_device_nand (&nand_pdata); }arch/arm/boards/at91sam9261ek/init.c +2
-3@@ -33,7 +33,6 @@#include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <dm9000.h> #include <gpio_keys.h> #include <readkey.h> @@ -80,7 +79,7 @@ static void ek_add_device_nand(void) ek_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &ek_nand_smc_config); +sam9_smc_configure (0 ,3 , &ek_nand_smc_config);at91_add_device_nand (&nand_pdata); }@@ -118,7 +117,7 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {static void __init ek_add_device_dm9000 (void ) {/* Configure chip-select 2 (DM9000) */ -sam9_smc_configure (2 , &dm9000_smc_config); +sam9_smc_configure (0 ,2 , &dm9000_smc_config);/* Configure Reset signal as output */ at91_set_gpio_output (AT91_PIN_PC10 ,0 );arch/arm/boards/at91sam9263ek/init.c +1
-2@@ -35,7 +35,6 @@#include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> static struct atmel_nand_data nand_pdata = { .ale =21 ,@@ -78,7 +77,7 @@ static void ek_add_device_nand(void) ek_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &ek_nand_smc_config); +sam9_smc_configure (0 ,3 , &ek_nand_smc_config);at91_add_device_nand (&nand_pdata); }arch/arm/boards/at91sam9m10g45ek/init.c +1
-2@@ -36,7 +36,6 @@#include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio_keys.h> #include <readkey.h> @@ -101,7 +100,7 @@ static void ek_add_device_nand(void) ek_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &ek_nand_smc_config); +sam9_smc_configure (0 ,3 , &ek_nand_smc_config);at91_add_device_nand (&nand_pdata); }arch/arm/boards/at91sam9n12ek/init.c +2
-3@@ -31,7 +31,6 @@#include <linux/mtd/nand.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_pmc.h> @@ -77,7 +76,7 @@ static void ek_add_device_nand(void) ek_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &ek_nand_smc_config); +sam9_smc_configure (0 ,3 , &ek_nand_smc_config);at91_add_device_nand (&nand_pdata); }@@ -112,7 +111,7 @@ static struct sam9_smc_config __initdata ks8851_smc_config = {static void __init ek_add_device_ks8851 (void ) {/* Configure chip-select 2 (KS8851) */ -sam9_smc_configure (2 , &ks8851_smc_config); +sam9_smc_configure (0 ,2 , &ks8851_smc_config);/* Configure NCS signal */ at91_set_B_periph (AT91_PIN_PD19 ,0 );/* Configure Interrupt pin as input, no pull-up */ arch/arm/boards/at91sam9x5ek/init.c +1
-2@@ -31,7 +31,6 @@#include <linux/mtd/nand.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_pmc.h> @@ -93,7 +92,7 @@ static void ek_add_device_nand(void) cm_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &cm_nand_smc_config); +sam9_smc_configure (0 ,3 , &cm_nand_smc_config);if (at91sam9x5ek_cm_is_vendor (VENDOR_COGENT )) {unsigned long csa;arch/arm/boards/dss11/init.c +1
-2@@ -29,7 +29,6 @@#include <linux/mtd/nand.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_rstc.h> @@ -69,7 +68,7 @@ static void dss11_add_device_nand(void) dss11_nand_smc_config.mode |=AT91_SMC_DBW_16 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &dss11_nand_smc_config); +sam9_smc_configure (0 ,3 , &dss11_nand_smc_config);at91_add_device_nand (&nand_pdata); }arch/arm/boards/pm9261/init.c +2
-3@@ -34,7 +34,6 @@#include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <dm9000.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h> @@ -84,7 +83,7 @@ static void pm_add_device_nand(void) pm_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &pm_nand_smc_config); +sam9_smc_configure (0 ,3 , &pm_nand_smc_config);at91_add_device_nand (&nand_pdata); }@@ -123,7 +122,7 @@ static void __init pm_add_device_dm9000(void) {w1_local_mac_address_register (0 ,"ron" ,"w1-1-0" );/* Configure chip-select 2 (DM9000) */ -sam9_smc_configure (2 , &dm9000_smc_config); +sam9_smc_configure (0 ,2 , &dm9000_smc_config);add_dm9000_device (0 ,AT91_CHIPSELECT_2 ,AT91_CHIPSELECT_2 +4 ,IORESOURCE_MEM_16BIT , &dm9000_data);arch/arm/boards/pm9263/init.c +1
-2@@ -35,7 +35,6 @@#include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h> @@ -84,7 +83,7 @@ static void pm_add_device_nand(void) pm_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &pm_nand_smc_config); +sam9_smc_configure (0 ,3 , &pm_nand_smc_config);at91_add_device_nand (&nand_pdata); }arch/arm/boards/pm9g45/init.c +1
-2@@ -34,7 +34,6 @@#include <mach/gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h> @@ -76,7 +75,7 @@ static void pm_add_device_nand(void) pm_nand_smc_config.mode |=AT91_SMC_DBW_8 ;/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &pm_nand_smc_config); +sam9_smc_configure (0 ,3 , &pm_nand_smc_config);at91_add_device_nand (&nand_pdata); }arch/arm/boards/qil-a9260/init.c +1
-2@@ -22,7 +22,6 @@#include <linux/clk.h> #include <mach/board.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <led.h> #include <mach/io.h> @@ -59,7 +58,7 @@ static struct sam9_smc_config nand_smc_config = {static void qil_a9260_add_device_nand (void ) {/* configure chip-select 3 (NAND) */ -sam9_smc_configure (3 , &nand_smc_config); +sam9_smc_configure (0 ,3 , &nand_smc_config);at91_add_device_nand (&nand_pdata); }arch/arm/boards/tny-a926x/init.c +2
-3@@ -32,7 +32,6 @@#include <mach/board.h> #include <mach/at91sam9_smc.h> #include <mach/at91sam9_sdramc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <mach/io.h> #include <mach/at91_pmc.h> @@ -100,9 +99,9 @@ static void tny_a9260_add_device_nand(void) {/* configure chip-select 3 (NAND) */ if (machine_is_tny_a9g20 ()) -sam9_smc_configure (3 , &tny_a9g20_nand_smc_config); +sam9_smc_configure (0 ,3 , &tny_a9g20_nand_smc_config);else -sam9_smc_configure (3 , &tny_a9260_nand_smc_config); +sam9_smc_configure (0 ,3 , &tny_a9260_nand_smc_config);if (machine_is_tny_a9263 ()) { nand_pdata.rdy_pin =AT91_PIN_PA22 ;arch/arm/boards/usb-a926x/init.c +2
-3@@ -32,7 +32,6 @@#include <mach/board.h> #include <mach/at91sam9_smc.h> #include <mach/at91sam9_sdramc.h> -#include <mach/sam9_smc.h> #include <gpio.h> #include <led.h> #include <mach/io.h> @@ -101,9 +100,9 @@ static void usb_a9260_add_device_nand(void) {/* configure chip-select 3 (NAND) */ if (machine_is_usb_a9g20 ()) -sam9_smc_configure (3 , &usb_a9g20_nand_smc_config); +sam9_smc_configure (0 ,3 , &usb_a9g20_nand_smc_config);else -sam9_smc_configure (3 , &usb_a9260_nand_smc_config); +sam9_smc_configure (0 ,3 , &usb_a9260_nand_smc_config);if (machine_is_usb_a9263 ()) { nand_pdata.rdy_pin =AT91_PIN_PA22 ;arch/arm/mach-at91/at91sam9260.c +1
-0@@ -236,6 +236,7 @@ static void at91sam9260_initialize(void)at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC );at91_add_pit (AT91SAM9260_BASE_PIT ); +at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9260_BASE_SMC ,0x200 ); }AT91_SOC_START (sam9260)arch/arm/mach-at91/at91sam9261.c +1
-0@@ -228,6 +228,7 @@ static void at91sam9261_initialize(void)at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC );at91_add_pit (AT91SAM9261_BASE_PIT ); +at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9261_BASE_SMC ,0x200 ); }AT91_SOC_START (sam9261)arch/arm/mach-at91/at91sam9263.c +2
-0@@ -247,6 +247,8 @@ static void at91sam9263_initialize(void)at91_add_rm9200_gpio (4 ,AT91_BASE_PIOE );at91_add_pit (AT91SAM9263_BASE_PIT ); +at91_add_sam9_smc (0 ,AT91SAM9263_BASE_SMC0 ,0x200 ); +at91_add_sam9_smc (1 ,AT91SAM9263_BASE_SMC1 ,0x200 ); }AT91_SOC_START (sam9263)arch/arm/mach-at91/at91sam926x_lowlevel_init.c +4
-4@@ -62,13 +62,13 @@ void __naked __bare_init reset(void)#endif /* flash */ -at91_sys_write (AT91_SMC_MODE (CONFIG_SYS_SMC_CS ),CONFIG_SYS_SMC_MODE_VAL ); +at91_smc_write (CONFIG_SYS_SMC_CS ,AT91_SMC_MODE ,CONFIG_SYS_SMC_MODE_VAL ); -at91_sys_write (AT91_SMC_CYCLE (CONFIG_SYS_SMC_CS ),CONFIG_SYS_SMC_CYCLE_VAL ); +at91_smc_write (CONFIG_SYS_SMC_CS ,AT91_SMC_CYCLE ,CONFIG_SYS_SMC_CYCLE_VAL ); -at91_sys_write (AT91_SMC_PULSE (CONFIG_SYS_SMC_CS ),CONFIG_SYS_SMC_PULSE_VAL ); +at91_smc_write (CONFIG_SYS_SMC_CS ,AT91_SMC_PULSE ,CONFIG_SYS_SMC_PULSE_VAL ); -at91_sys_write (AT91_SMC_SETUP (CONFIG_SYS_SMC_CS ),CONFIG_SYS_SMC_SETUP_VAL ); +at91_smc_write (CONFIG_SYS_SMC_CS ,AT91_SMC_SETUP ,CONFIG_SYS_SMC_SETUP_VAL );/* * PMC Check if the PLL is already initialized arch/arm/mach-at91/at91sam9g45.c +1
-0@@ -259,6 +259,7 @@ static void at91sam9g45_initialize(void)at91_add_rm9200_gpio (4 ,AT91_BASE_PIOE );at91_add_pit (AT91SAM9G45_BASE_PIT ); +at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9G45_BASE_SMC ,0x200 ); }AT91_SOC_START (sam9g45)arch/arm/mach-at91/at91sam9n12.c +1
-0@@ -219,6 +219,7 @@ static void at91sam9n12_initialize(void)at91_add_sam9x5_gpio (3 ,AT91_BASE_PIOD );at91_add_pit (AT91SAM9N12_BASE_PIT ); +at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9N12_BASE_SMC ,0x200 ); }AT91_SOC_START (sam9n12)arch/arm/mach-at91/at91sam9x5.c +1
-0@@ -304,6 +304,7 @@ static void at91sam9x5_initialize(void)at91_add_sam9x5_gpio (3 ,AT91_BASE_PIOD );at91_add_pit (AT91SAM9X5_BASE_PIT ); +at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9X5_BASE_SMC ,0x200 ); }AT91_SOC_START (sam9x5)arch/arm/mach-at91/generic.h +7
-0@@ -28,3 +28,10 @@ static inline struct device_d *at91_add_pit(resource_size_t start)return add_generic_device ("at91-pit" ,DEVICE_ID_SINGLE ,NULL , start,16 ,IORESOURCE_MEM ,NULL ); } + +static inline struct device_d *at91_add_sam9_smc (int id,resource_size_t start, +resource_size_t size) +{ +return add_generic_device ("at91sam9-smc" , id,NULL , start, size, +IORESOURCE_MEM ,NULL ); +}arch/arm/mach-at91/include/mach/at91sam9260.h +2
-1@@ -100,13 +100,14 @@*/ #define AT91_ECC (0xffffe800 - AT91_BASE_SYS)#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_BASE_SMC AT91SAM9260_BASE_SMC +#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9260_BASE_PIOB#define AT91_BASE_PIOC AT91SAM9260_BASE_PIOCarch/arm/mach-at91/include/mach/at91sam9261.h +1
-1@@ -86,13 +86,13 @@* System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_BASE_SMC AT91SAM9261_BASE_SMC#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9261_BASE_PIOB#define AT91_BASE_PIOC AT91SAM9261_BASE_PIOCarch/arm/mach-at91/include/mach/at91sam9263.h +1
-2@@ -104,13 +104,13 @@*/ #define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) -#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_BASE_SMC AT91SAM9263_BASE_SMC0#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9263_BASE_PIOB#define AT91_BASE_PIOC AT91SAM9263_BASE_PIOC@@ -122,7 +122,6 @@#define AT91_USART2 AT91SAM9263_BASE_US2#define AT91_NB_USART 4 -#define AT91_SMC AT91_SMC0#define AT91_SDRAMC AT91_SDRAMC0#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0arch/arm/mach-at91/include/mach/at91sam9_smc.h +39
-11@@ -16,7 +16,42 @@#ifndef AT91SAM9_SMC_H #define AT91SAM9_SMC_H -#define AT91_SMC_SETUP (n) (AT91_SMC + 0x00 + ((n)*0x10))/* Setup Register for CS n */ +#define at91_smc_read (id, field) \ + __raw_readl(AT91_BASE_SMC + ((id) * 0x10) + field) + +#define at91_smc_write (id, field, value) \ + __raw_writel(value, AT91_BASE_SMC + ((id) * 0x10) + field) + +#ifndef __ASSEMBLY__ +struct sam9_smc_config { +/* Setup register */ +u8 ncs_read_setup; +u8 nrd_setup; +u8 ncs_write_setup; +u8 nwe_setup; + +/* Pulse register */ +u8 ncs_read_pulse; +u8 nrd_pulse; +u8 ncs_write_pulse; +u8 nwe_pulse; + +/* Cycle register */ +u16 read_cycle; +u16 write_cycle; + +/* Mode register */ +u32 mode; +u8 tdf_cycles:4 ; +}; + +extern void sam9_smc_configure (int id,int cs,struct sam9_smc_config *config); +extern void sam9_smc_read (int id,int cs,struct sam9_smc_config *config); +extern void sam9_smc_read_mode (int id,int cs,struct sam9_smc_config *config); +extern void sam9_smc_write_mode (int id,int cs,struct sam9_smc_config *config); +#endif + +#define AT91_SMC_SETUP 0x00/* Setup Register for CS n */ #define AT91_SMC_NWESETUP (0x3f << 0)/* NWE Setup Length */ #define AT91_SMC_NWESETUP_ (x) ((x) << 0)#define AT91_SMC_NCS_WRSETUP (0x3f << 8)/* NCS Setup Length in Write Access */ @@ -26,7 +61,7 @@#define AT91_SMC_NCS_RDSETUP (0x3f << 24)/* NCS Setup Length in Read Access */ #define AT91_SMC_NCS_RDSETUP_ (x) ((x) << 24) -#define AT91_SMC_PULSE (n) (AT91_SMC + 0x04 + ((n)*0x10))/* Pulse Register for CS n */ +#define AT91_SMC_PULSE 0x04/* Pulse Register for CS n */ #define AT91_SMC_NWEPULSE (0x7f << 0)/* NWE Pulse Length */ #define AT91_SMC_NWEPULSE_ (x) ((x) << 0)#define AT91_SMC_NCS_WRPULSE (0x7f << 8)/* NCS Pulse Length in Write Access */ @@ -36,13 +71,13 @@#define AT91_SMC_NCS_RDPULSE (0x7f << 24)/* NCS Pulse Length in Read Access */ #define AT91_SMC_NCS_RDPULSE_ (x)((x) << 24) -#define AT91_SMC_CYCLE (n) (AT91_SMC + 0x08 + ((n)*0x10))/* Cycle Register for CS n */ +#define AT91_SMC_CYCLE 0x08/* Cycle Register for CS n */ #define AT91_SMC_NWECYCLE (0x1ff << 0 )/* Total Write Cycle Length */ #define AT91_SMC_NWECYCLE_ (x) ((x) << 0)#define AT91_SMC_NRDCYCLE (0x1ff << 16)/* Total Read Cycle Length */ #define AT91_SMC_NRDCYCLE_ (x) ((x) << 16) -#define AT91_SMC_MODE (n) (AT91_SMC + 0x0c + ((n)*0x10))/* Mode Register for CS n */ +#define AT91_SMC_MODE 0x0c/* Mode Register for CS n */ #define AT91_SMC_READMODE (1 << 0)/* Read Mode */ #define AT91_SMC_WRITEMODE (1 << 1)/* Write Mode */ #define AT91_SMC_EXNWMODE (3 << 4)/* NWAIT Mode */ @@ -66,11 +101,4 @@#define AT91_SMC_PS_16 (2 << 28)#define AT91_SMC_PS_32 (3 << 28) -#if defined(AT91_SMC1 )/* The AT91SAM9263 has 2 Static Memory contollers */ -#define AT91_SMC1_SETUP (n) (AT91_SMC1 + 0x00 + ((n)*0x10))/* Setup Register for CS n */ -#define AT91_SMC1_PULSE (n) (AT91_SMC1 + 0x04 + ((n)*0x10))/* Pulse Register for CS n */ -#define AT91_SMC1_CYCLE (n) (AT91_SMC1 + 0x08 + ((n)*0x10))/* Cycle Register for CS n */ -#define AT91_SMC1_MODE (n) (AT91_SMC1 + 0x0c + ((n)*0x10))/* Mode Register for CS n */ -#endif -#endif arch/arm/mach-at91/include/mach/at91sam9g45.h +1
-1@@ -115,13 +115,13 @@#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_BASE_SMC AT91SAM9G45_BASE_SMC#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9G45_BASE_PIOB#define AT91_BASE_PIOC AT91SAM9G45_BASE_PIOCarch/arm/mach-at91/include/mach/at91sam9n12.h +1
-1@@ -112,12 +112,12 @@#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC (0xffffea00 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS) +#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB#define AT91_BASE_PIOC AT91SAM9N12_BASE_PIOCarch/arm/mach-at91/include/mach/at91sam9x5.h +1
-1@@ -119,12 +119,12 @@#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC (0xffffea00 - AT91_BASE_SYS)#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS) +#define AT91_BASE_SMC AT91SAM9X5_BASE_SMC#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9X5_BASE_PIOB#define AT91_BASE_PIOC AT91SAM9X5_BASE_PIOCarch/arm/mach-at91/include/mach/sam9_smc.h deleted +0
-33@@ -1,33 +0,0 @@ -/* -* linux/arch/arm/mach-at91/sam9_smc. -* -* Copyright (C) 2008 Andrew Victor -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -*/ - -struct sam9_smc_config { -/* Setup register */ -u8 ncs_read_setup; -u8 nrd_setup; -u8 ncs_write_setup; -u8 nwe_setup; - -/* Pulse register */ -u8 ncs_read_pulse; -u8 nrd_pulse; -u8 ncs_write_pulse; -u8 nwe_pulse; - -/* Cycle register */ -u16 read_cycle; -u16 write_cycle; - -/* Mode register */ -u32 mode; -u8 tdf_cycles:4 ; -}; - -extern void __init sam9_smc_configure (int cs,struct sam9_smc_config * config);arch/arm/mach-at91/sam9_smc.c +124
-22@@ -9,40 +9,142 @@*/ #include <common.h> +#include <init.h> #include <io.h> #include <mach/hardware.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <mach/sam9_smc.h> -void sam9_smc_configure (int cs,struct sam9_smc_config * config) +#define AT91_SMC_CS (id, n) (smc_base_addr[id] + ((n) * 0x10)) + +static void __iomem *smc_base_addr[2 ]; + +static void sam9_smc_cs_write_mode (void __iomem *base, +struct sam9_smc_config *config) +{ +__raw_writel (config->mode + |AT91_SMC_TDF_ (config->tdf_cycles), + base +AT91_SMC_MODE ); +} + +void sam9_smc_write_mode (int id,int cs, +struct sam9_smc_config *config) +{ +sam9_smc_cs_write_mode (AT91_SMC_CS (id, cs), config); +} + +static void sam9_smc_cs_configure (void __iomem *base, +struct sam9_smc_config *config) +{ + +/* Setup register */ +__raw_writel (AT91_SMC_NWESETUP_ (config->nwe_setup) + |AT91_SMC_NCS_WRSETUP_ (config->ncs_write_setup) + |AT91_SMC_NRDSETUP_ (config->nrd_setup) + |AT91_SMC_NCS_RDSETUP_ (config->ncs_read_setup), + base +AT91_SMC_SETUP ); + +/* Pulse register */ +__raw_writel (AT91_SMC_NWEPULSE_ (config->nwe_pulse) + |AT91_SMC_NCS_WRPULSE_ (config->ncs_write_pulse) + |AT91_SMC_NRDPULSE_ (config->nrd_pulse) + |AT91_SMC_NCS_RDPULSE_ (config->ncs_read_pulse), + base +AT91_SMC_PULSE ); + +/* Cycle register */ +__raw_writel (AT91_SMC_NWECYCLE_ (config->write_cycle) + |AT91_SMC_NRDCYCLE_ (config->read_cycle), + base +AT91_SMC_CYCLE ); + +/* Mode register */ +sam9_smc_cs_write_mode (base, config); +} + +void sam9_smc_configure (int id,int cs, +struct sam9_smc_config *config) +{ +sam9_smc_cs_configure (AT91_SMC_CS (id, cs), config); +} + +static void sam9_smc_cs_read_mode (void __iomem *base, +struct sam9_smc_config *config) +{ +u32 val =__raw_readl (base +AT91_SMC_MODE ); + + config->mode = (val & ~AT91_SMC_NWECYCLE ); + config->tdf_cycles = (val &AT91_SMC_NWECYCLE ) >>16 ; +} + +void sam9_smc_read_mode (int id,int cs, +struct sam9_smc_config *config) +{ +sam9_smc_cs_read_mode (AT91_SMC_CS (id, cs), config); +} + +static void sam9_smc_cs_read (void __iomem *base, +struct sam9_smc_config *config) { +u32 val; +/* Setup register */ -at91_sys_write (AT91_SMC_SETUP (cs), -AT91_SMC_NWESETUP_ (config->nwe_setup) - |AT91_SMC_NCS_WRSETUP_ (config->ncs_write_setup) - |AT91_SMC_NRDSETUP_ (config->nrd_setup) - |AT91_SMC_NCS_RDSETUP_ (config->ncs_read_setup) - ); + val =__raw_readl (base +AT91_SMC_SETUP ); + + config->nwe_setup = val &AT91_SMC_NWESETUP ; + config->ncs_write_setup = (val &AT91_SMC_NCS_WRSETUP ) >>8 ; + config->nrd_setup = (val &AT91_SMC_NRDSETUP ) >>16 ; + config->ncs_read_setup = (val &AT91_SMC_NCS_RDSETUP ) >>24 ;/* Pulse register */ -at91_sys_write (AT91_SMC_PULSE (cs), -AT91_SMC_NWEPULSE_ (config->nwe_pulse) - |AT91_SMC_NCS_WRPULSE_ (config->ncs_write_pulse) - |AT91_SMC_NRDPULSE_ (config->nrd_pulse) - |AT91_SMC_NCS_RDPULSE_ (config->ncs_read_pulse) - ); + val =__raw_readl (base +AT91_SMC_PULSE ); + + config->nwe_setup = val &AT91_SMC_NWEPULSE ; + config->ncs_write_pulse = (val &AT91_SMC_NCS_WRPULSE ) >>8 ; + config->nrd_pulse = (val &AT91_SMC_NRDPULSE ) >>16 ; + config->ncs_read_pulse = (val &AT91_SMC_NCS_RDPULSE ) >>24 ;/* Cycle register */ -at91_sys_write (AT91_SMC_CYCLE (cs), -AT91_SMC_NWECYCLE_ (config->write_cycle) - |AT91_SMC_NRDCYCLE_ (config->read_cycle) - ); + val =__raw_readl (base +AT91_SMC_CYCLE ); + + config->write_cycle = val &AT91_SMC_NWECYCLE ; + config->read_cycle = (val &AT91_SMC_NRDCYCLE ) >>16 ;/* Mode register */ -at91_sys_write (AT91_SMC_MODE (cs), - config->mode - |AT91_SMC_TDF_ (config->tdf_cycles) - ); +sam9_smc_cs_read_mode (base, config); +} + +void sam9_smc_read (int id,int cs,struct sam9_smc_config *config) +{ +sam9_smc_cs_read (AT91_SMC_CS (id, cs), config); +} + +static int at91sam9_smc_probe (struct device_d *dev) +{ +int id; + +if (dev->id <0 ) { + id =0 ; + }else if (dev->id >1 ) { +dev_warn (dev,": id > 2\n" ); +return -EIO ; + } + + smc_base_addr[id] =dev_request_mem_region (dev,0 ); +if (!smc_base_addr[id]) { +dev_err (dev,"Impossible to request smc.%d\n" , id); +return -ENOMEM ; + } + +return 0 ; +} + +static struct driver_d at91sam9_smc_driver = { + .name ="at91sam9-smc" , + .probe = at91sam9_smc_probe, +}; + +static int at91sam9_smc_init (void ) +{ +return platform_driver_register (&at91sam9_smc_driver); } +coredevice_initcall (at91sam9_smc_init);Signature · 7 lines
1.7.10.4 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
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Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 11/13 at91: wdt: drop AT91_SYS_BASE
In reply to Jean-Christophe PLAGNIOL-VILLARDSigned-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 2 +- arch/arm/mach-at91/include/mach/at91_wdt.h | 6 +++--- arch/arm/mach-at91/include/mach/at91sam9260.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9261.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9263.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9n12.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 +- 8 files changed, 10 insertions(+), 10 deletions(-)
arch/arm/mach-at91/at91sam926x_lowlevel_init.c +1 -1
@@ -43,7 +43,7 @@ void __naked __bare_init reset(void)common_reset (); -at91_sys_write (AT91_WDT_MR ,CONFIG_SYS_WDTC_WDMR_VAL ); +__raw_writel (CONFIG_SYS_WDTC_WDMR_VAL ,AT91_BASE_WDT +AT91_WDT_MR );/* configure PIOx as EBI0 D[16-31] */ #ifdef CONFIG_ARCH_AT91SAM9263
arch/arm/mach-at91/include/mach/at91_wdt.h +3 -3
@@ -17,11 +17,11 @@#ifndef AT91_WDT_H #define AT91_WDT_H -#define AT91_WDT_CR (AT91_WDT + 0x00)/* Watchdog Control Register */ +#define AT91_WDT_CR 0x00/* Watchdog Control Register */ #define AT91_WDT_WDRSTT (1 << 0)/* Restart */ #define AT91_WDT_KEY (0xa5 << 24)/* KEY Password */ -#define AT91_WDT_MR (AT91_WDT + 0x04)/* Watchdog Mode Register */ +#define AT91_WDT_MR 0x04/* Watchdog Mode Register */ #define AT91_WDT_WDV (0xfff << 0)/* Counter Value */ #define AT91_WDT_WDFIEN (1 << 12)/* Fault Interrupt Enable */ #define AT91_WDT_WDRSTEN (1 << 13)/* Reset Processor */
@@ -31,7 +31,7 @@#define AT91_WDT_WDDBGHLT (1 << 28)/* Debug Halt */ #define AT91_WDT_WDIDLEHLT (1 << 29)/* Idle Halt */ -#define AT91_WDT_SR (AT91_WDT + 0x08)/* Watchdog Status Register */ +#define AT91_WDT_SR 0x08/* Watchdog Status Register */ #define AT91_WDT_WDUNF (1 << 0)/* Watchdog Underflow */ #define AT91_WDT_WDERR (1 << 1)/* Watchdog Error */
arch/arm/mach-at91/include/mach/at91sam9260.h +1 -1
@@ -104,8 +104,8 @@#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_BASE_WDT AT91SAM9260_BASE_WDT#define AT91_BASE_SMC AT91SAM9260_BASE_SMC#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
arch/arm/mach-at91/include/mach/at91sam9261.h +1 -1
@@ -90,8 +90,8 @@#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_BASE_WDT AT91SAM9261_BASE_WDT#define AT91_BASE_SMC AT91SAM9261_BASE_SMC#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9261_BASE_PIOB
arch/arm/mach-at91/include/mach/at91sam9263.h +1 -1
@@ -108,8 +108,8 @@#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_BASE_WDT AT91SAM9263_BASE_WDT#define AT91_BASE_SMC AT91SAM9263_BASE_SMC0#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9263_BASE_PIOB
arch/arm/mach-at91/include/mach/at91sam9g45.h +1 -1
@@ -119,8 +119,8 @@#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_BASE_WDT AT91SAM9G45_BASE_WDT#define AT91_BASE_SMC AT91SAM9G45_BASE_SMC#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9G45_BASE_PIOB
arch/arm/mach-at91/include/mach/at91sam9n12.h +1 -1
@@ -115,8 +115,8 @@#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS) +#define AT91_BASE_WDT AT91SAM9N12_BASE_WDT#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB
arch/arm/mach-at91/include/mach/at91sam9x5.h +1 -1
@@ -122,8 +122,8 @@#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS) +#define AT91_BASE_WDT AT91SAM9X5_BASE_WDT#define AT91_BASE_SMC AT91SAM9X5_BASE_SMC#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA#define AT91_BASE_PIOB AT91SAM9X5_BASE_PIOB
Signature · 7 lines
1.7.10.4 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 12/13 at91: introduce AT91SAM9_SMC and AT91SAM9_TIMER
In reply to Jean-Christophe PLAGNIOL-VILLARDto select the smc and timer for at91sam9 soc
This will allow to simplify the Makefile
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/mach-at91/Kconfig | 24 ++++++++++++++++++------ arch/arm/mach-at91/Makefile | 19 +++++++++++-------- 2 files changed, 29 insertions(+), 14 deletions(-)
arch/arm/mach-at91/Kconfig +18 -6
@@ -6,6 +6,18 @@ config HAVE_AT91_DBGU0 config HAVE_AT91_DBGU1 bool +config AT91SAM9_SMC + bool + +config AT91SAM9_TIMER + bool + +config SOC_AT91SAM9 + bool + select CPU_ARM926T + select AT91SAM9_SMC + select AT91SAM9_TIMER + config ARCH_TEXT_BASE hex default 0x73f00000 if ARCH_AT91SAM9G45
@@ -58,7 +70,7 @@ config SOC_AT91RM9200 config SOC_AT91SAM9260 bool - select CPU_ARM926T + select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select HAS_MACB select AT91SAM9_RESET
@@ -68,7 +80,7 @@ config SOC_AT91SAM9260 config SOC_AT91SAM9261 bool - select CPU_ARM926T + select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select AT91SAM9_RESET help
@@ -76,14 +88,14 @@ config SOC_AT91SAM9261 config SOC_AT91SAM9263 bool - select CPU_ARM926T + select SOC_AT91SAM9 select HAVE_AT91_DBGU1 select HAS_MACB select AT91SAM9_RESET config SOC_AT91SAM9G45 bool - select CPU_ARM926T + select SOC_AT91SAM9 select HAVE_AT91_DBGU1 select HAS_MACB select AT91SAM9G45_RESET
@@ -93,7 +105,7 @@ config SOC_AT91SAM9G45 config SOC_AT91SAM9X5 bool - select CPU_ARM926T + select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select HAS_MACB select AT91SAM9G45_RESET
@@ -106,7 +118,7 @@ config SOC_AT91SAM9X5 config SOC_AT91SAM9N12 bool - select CPU_ARM926T + select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select AT91SAM9G45_RESET help
arch/arm/mach-at91/Makefile +11 -8
@@ -9,13 +9,16 @@ pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y) obj-$(CONFIG_AT91SAM9_RESET) += at91sam9_reset.o obj-$(CONFIG_AT91SAM9G45_RESET) += at91sam9g45_reset.o +obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o +obj-$(CONFIG_AT91SAM9_TIMER) += at91sam926x_time.o + # CPU-specific support obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o -obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o at91sam9x5_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam926x_time.o at91sam9n12_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o +obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o +obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o +obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam9261_devices.o +obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o +obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o +obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o +obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam9n12_devices.o
Signature · 7 lines
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PATCH 13/13 at91: drop AT91_BASE_PIOx for soc specific one for none boot code
In reply to Jean-Christophe PLAGNIOL-VILLARDSigned-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
--- arch/arm/mach-at91/at91rm9200.c | 8 ++++---- arch/arm/mach-at91/at91sam9260.c | 6 +++--- arch/arm/mach-at91/at91sam9261.c | 6 +++--- arch/arm/mach-at91/at91sam9263.c | 10 +++++----- arch/arm/mach-at91/at91sam9g45.c | 10 +++++----- arch/arm/mach-at91/at91sam9n12.c | 8 ++++---- arch/arm/mach-at91/at91sam9x5.c | 8 ++++---- 7 files changed, 28 insertions(+), 28 deletions(-)
arch/arm/mach-at91/at91rm9200.c +4 -4
@@ -232,10 +232,10 @@ static void __init at91rm9200_initialize(void)at91rm9200_register_clocks ();/* Register GPIO subsystem */ -at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA ); -at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB ); -at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC ); -at91_add_rm9200_gpio (3 ,AT91_BASE_PIOD ); +at91_add_rm9200_gpio (0 ,AT91RM9200_BASE_PIOA ); +at91_add_rm9200_gpio (1 ,AT91RM9200_BASE_PIOB ); +at91_add_rm9200_gpio (2 ,AT91RM9200_BASE_PIOC ); +at91_add_rm9200_gpio (3 ,AT91RM9200_BASE_PIOD ); }AT91_SOC_START (rm9200)
arch/arm/mach-at91/at91sam9260.c +3 -3
@@ -231,9 +231,9 @@ static void at91sam9260_initialize(void)at91sam9260_register_clocks ();/* Register GPIO subsystem */ -at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA ); -at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB ); -at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC ); +at91_add_rm9200_gpio (0 ,AT91SAM9260_BASE_PIOA ); +at91_add_rm9200_gpio (1 ,AT91SAM9260_BASE_PIOB ); +at91_add_rm9200_gpio (2 ,AT91SAM9260_BASE_PIOC );at91_add_pit (AT91SAM9260_BASE_PIT );at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9260_BASE_SMC ,0x200 );
arch/arm/mach-at91/at91sam9261.c +3 -3
@@ -223,9 +223,9 @@ static void at91sam9261_initialize(void)at91sam9261_register_clocks ();/* Register GPIO subsystem */ -at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA ); -at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB ); -at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC ); +at91_add_rm9200_gpio (0 ,AT91SAM9261_BASE_PIOA ); +at91_add_rm9200_gpio (1 ,AT91SAM9261_BASE_PIOB ); +at91_add_rm9200_gpio (2 ,AT91SAM9261_BASE_PIOC );at91_add_pit (AT91SAM9261_BASE_PIT );at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9261_BASE_SMC ,0x200 );
arch/arm/mach-at91/at91sam9263.c +5 -5
@@ -240,11 +240,11 @@ static void at91sam9263_initialize(void)at91sam9263_register_clocks ();/* Register GPIO subsystem */ -at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA ); -at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB ); -at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC ); -at91_add_rm9200_gpio (3 ,AT91_BASE_PIOD ); -at91_add_rm9200_gpio (4 ,AT91_BASE_PIOE ); +at91_add_rm9200_gpio (0 ,AT91SAM9263_BASE_PIOA ); +at91_add_rm9200_gpio (1 ,AT91SAM9263_BASE_PIOB ); +at91_add_rm9200_gpio (2 ,AT91SAM9263_BASE_PIOC ); +at91_add_rm9200_gpio (3 ,AT91SAM9263_BASE_PIOD ); +at91_add_rm9200_gpio (4 ,AT91SAM9263_BASE_PIOE );at91_add_pit (AT91SAM9263_BASE_PIT );at91_add_sam9_smc (0 ,AT91SAM9263_BASE_SMC0 ,0x200 );
arch/arm/mach-at91/at91sam9g45.c +5 -5
@@ -252,11 +252,11 @@ static void at91sam9g45_initialize(void)at91sam9g45_register_clocks ();/* Register GPIO subsystem */ -at91_add_rm9200_gpio (0 ,AT91_BASE_PIOA ); -at91_add_rm9200_gpio (1 ,AT91_BASE_PIOB ); -at91_add_rm9200_gpio (2 ,AT91_BASE_PIOC ); -at91_add_rm9200_gpio (3 ,AT91_BASE_PIOD ); -at91_add_rm9200_gpio (4 ,AT91_BASE_PIOE ); +at91_add_rm9200_gpio (0 ,AT91SAM9G45_BASE_PIOA ); +at91_add_rm9200_gpio (1 ,AT91SAM9G45_BASE_PIOB ); +at91_add_rm9200_gpio (2 ,AT91SAM9G45_BASE_PIOC ); +at91_add_rm9200_gpio (3 ,AT91SAM9G45_BASE_PIOD ); +at91_add_rm9200_gpio (4 ,AT91SAM9G45_BASE_PIOE );at91_add_pit (AT91SAM9G45_BASE_PIT );at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9G45_BASE_SMC ,0x200 );
arch/arm/mach-at91/at91sam9n12.c +4 -4
@@ -213,10 +213,10 @@ static void at91sam9n12_initialize(void)at91sam9n12_register_clocks ();/* Register GPIO subsystem */ -at91_add_sam9x5_gpio (0 ,AT91_BASE_PIOA ); -at91_add_sam9x5_gpio (1 ,AT91_BASE_PIOB ); -at91_add_sam9x5_gpio (2 ,AT91_BASE_PIOC ); -at91_add_sam9x5_gpio (3 ,AT91_BASE_PIOD ); +at91_add_sam9x5_gpio (0 ,AT91SAM9N12_BASE_PIOA ); +at91_add_sam9x5_gpio (1 ,AT91SAM9N12_BASE_PIOB ); +at91_add_sam9x5_gpio (2 ,AT91SAM9N12_BASE_PIOC ); +at91_add_sam9x5_gpio (3 ,AT91SAM9N12_BASE_PIOD );at91_add_pit (AT91SAM9N12_BASE_PIT );at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9N12_BASE_SMC ,0x200 );
arch/arm/mach-at91/at91sam9x5.c +4 -4
@@ -298,10 +298,10 @@ static void at91sam9x5_initialize(void)at91sam9x5_register_clocks ();/* Register GPIO subsystem */ -at91_add_sam9x5_gpio (0 ,AT91_BASE_PIOA ); -at91_add_sam9x5_gpio (1 ,AT91_BASE_PIOB ); -at91_add_sam9x5_gpio (2 ,AT91_BASE_PIOC ); -at91_add_sam9x5_gpio (3 ,AT91_BASE_PIOD ); +at91_add_sam9x5_gpio (0 ,AT91SAM9X5_BASE_PIOA ); +at91_add_sam9x5_gpio (1 ,AT91SAM9X5_BASE_PIOB ); +at91_add_sam9x5_gpio (2 ,AT91SAM9X5_BASE_PIOC ); +at91_add_sam9x5_gpio (3 ,AT91SAM9X5_BASE_PIOD );at91_add_pit (AT91SAM9X5_BASE_PIT );at91_add_sam9_smc (DEVICE_ID_SINGLE ,AT91SAM9X5_BASE_SMC ,0x200 );
Signature · 7 lines
1.7.10.4 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Sascha Hauer
AppliedQuoted 9 lines · Jean-Christophe PLAGNIOL-VILLARD
HI,
cleanup base addresses and start to drop
AT91_BASE_SYSto allow multiple arch at a timeswitch code drivers to device/drivers
detect soc a at run time
Quoted 8 lines
The following changes since commit
adbdc7cd87971b126838950e2dc5eaedfff943d7:spi: atmel: request cs pin via gpiolib (2012-12-29 00:35:08 +0800)
are available in the git repository at:
git://git.jcrosoft.org/barebox.gitdelivery/at91_cleanup
Applied, thanks
Sascha
Quoted 79 lines
for you to fetch changes up to
9f7f67ca887b26a4488edf5fa171a78e142e0a5b:at91: drop
AT91_BASE_PIOxfor soc specific one for none boot code (2012-12-29 01:37:47 +0800)----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (13):
at91: factorise dbgu address
at91: enable clock via clock framework
at91: factoryse PMC address as it's the same on every soc
at91: pmc: dropAT91_BASE_SYS
at91: introduceKconfigto select the dbgu for lowlevel debug
at91: sync with the kernel address base
at91: at91sam9: provide its own clkdev for pit
at91: PIT: switch toplatfrom_driver
at91: autodetect the soc one time atpostcore_initcall
at91: SMC: switch toplatfrom_driver
at91: wdt: dropAT91_SYS_BASE
at91: introduceAT91SAM9_SMCandAT91SAM9_TIMER
at91: dropAT91_BASE_PIOxfor soc specific one for none boot codearch/arm/boards/at91sam9260ek/init.c | 5 +- arch/arm/boards/at91sam9261ek/init.c | 5 +- arch/arm/boards/at91sam9263ek/init.c | 3 +- arch/arm/boards/at91sam9m10g45ek/init.c | 3 +- arch/arm/boards/at91sam9n12ek/init.c | 5 +- arch/arm/boards/at91sam9x5ek/init.c | 3 +- arch/arm/boards/dss11/init.c | 9 ++- arch/arm/boards/pm9261/init.c | 5 +- arch/arm/boards/pm9263/init.c | 3 +- arch/arm/boards/pm9g45/init.c | 3 +- arch/arm/boards/qil-a9260/init.c | 3 +- arch/arm/boards/tny-a926x/init.c | 5 +- arch/arm/boards/usb-a926x/init.c | 5 +- arch/arm/mach-at91/Kconfig | 114 ++++++++++++++++++++++------ arch/arm/mach-at91/Makefile | 21 +++--- arch/arm/mach-at91/at91rm9200.c | 25 +++--- arch/arm/mach-at91/at91rm9200_lowlevel_init.c | 18 +++-- arch/arm/mach-at91/at91sam9260.c | 24 +++--- arch/arm/mach-at91/at91sam9261.c | 24 +++--- arch/arm/mach-at91/at91sam9263.c | 29 +++---- arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 28 +++---- arch/arm/mach-at91/at91sam926x_time.c | 68 +++++++++++++---- arch/arm/mach-at91/at91sam9g45.c | 29 ++++--- arch/arm/mach-at91/at91sam9n12.c | 26 +++---- arch/arm/mach-at91/at91sam9x5.c | 26 +++---- arch/arm/mach-at91/clock.c | 50 ++++++------ arch/arm/mach-at91/generic.h | 13 ++++ arch/arm/mach-at91/include/mach/at91_dbgu.h | 26 +++---- arch/arm/mach-at91/include/mach/at91_pit.h | 8 +- arch/arm/mach-at91/include/mach/at91_pmc.h | 48 ++++++------ arch/arm/mach-at91/include/mach/at91_wdt.h | 6 +- arch/arm/mach-at91/include/mach/at91rm9200.h | 22 ++++-- arch/arm/mach-at91/include/mach/at91sam9260.h | 37 ++++++--- arch/arm/mach-at91/include/mach/at91sam9261.h | 34 ++++++--- arch/arm/mach-at91/include/mach/at91sam9263.h | 52 ++++++++----- arch/arm/mach-at91/include/mach/at91sam9_smc.h | 50 +++++++++--- arch/arm/mach-at91/include/mach/at91sam9g45.h | 44 +++++++---- arch/arm/mach-at91/include/mach/at91sam9n12.h | 43 +++++++---- arch/arm/mach-at91/include/mach/at91sam9x5.h | 43 +++++++---- arch/arm/mach-at91/include/mach/cpu.h | 190 ++++++++++++++++++++++------------------------ arch/arm/mach-at91/include/mach/debug_ll.h | 6 +- arch/arm/mach-at91/include/mach/hardware.h | 8 ++ arch/arm/mach-at91/include/mach/sam9_smc.h | 33 -------- arch/arm/mach-at91/sam9_smc.c | 146 +++++++++++++++++++++++++++++------ arch/arm/mach-at91/setup.c | 226 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-at91/soc.h | 66 ++++++++++++++++ 46 files changed, 1127 insertions(+), 513 deletions(-) delete mode 100644 arch/arm/mach-at91/include/mach/sam9_smc.h create mode 100644 arch/arm/mach-at91/setup.c create mode 100644 arch/arm/mach-at91/soc.hBest Regards,
J._______________________________________________
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