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arm: cache-l2x0: aurora: Various bug fixes

PATCH New Gregory CLEMENT 2 participants 5 messages Dec 19, 2012 – Jan 6, 2013 Arm (32-bit)

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Gregory CLEMENT

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#0 lore raw

cover arm: cache-l2x0: aurora: Various bug fixes

Hi,

Now that we have more devices and more boards supported, bugs shows up. Here are a couple of fixes that have been tested on Aramda XP based boards such as DB-78460-BP and DB-MV784MP-GP, and on Armada 370 based boards such as DB-88F6710-BP-DDR3 and Mirabox. They are 3.8 materials.

Thanks,

Gregory CLEMENT (2):
arm: cache-l2x0: aurora: Invalidate during clean operation with WT
enable
arm: cache-l2x0: aurora: Use writel_relaxed instead of writel

 arch/arm/mm/cache-l2x0.c |   31 +++++++++++++++++++------------
 1 file changed, 19 insertions(+), 12 deletions(-)
Signature · 1 line
1.7.9.5
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#1 lore raw

PATCH 1/2 arm: cache-l2x0: aurora: Invalidate during clean operation with WT enable

This patch fixes a bug for Aurora L2 cache controller when the write-through mode is enable. For the clean operation even if we don't have to flush the lines we still need to invalidate them.

Signed-off-by Gregory CLEMENT <[email protected]>
Tested-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mm/cache-l2x0.c |   22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)
arch/arm/mm/cache-l2x0.c +14 -8
index 6911b8b..7ffe943 100644
@@ -505,15 +505,21 @@ static void aurora_clean_range(unsigned long start, unsigned long end)
 
 static void aurora_flush_range(unsigned long start, unsigned long end)
 {
-	if (!l2_wt_override) {
-		start &= ~(CACHE_LINE_SIZE - 1);
-		end = ALIGN(end, CACHE_LINE_SIZE);
-		while (start != end) {
-			unsigned long range_end = calc_range_end(start, end);
+	start &= ~(CACHE_LINE_SIZE - 1);
+	end = ALIGN(end, CACHE_LINE_SIZE);
+	while (start != end) {
+		unsigned long range_end = calc_range_end(start, end);
+		/*
+		 * If L2 is forced to WT, the L2 will always be clean and we
+		 * just need to invalidate.
+		 */
+		if (l2_wt_override)
 			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
-					AURORA_FLUSH_RANGE_REG);
-			start = range_end;
-		}
+							AURORA_INVAL_RANGE_REG);
+		else
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+							AURORA_FLUSH_RANGE_REG);
+		start = range_end;
 	}
 }
Signature · 1 line
1.7.9.5
author
#2 lore raw

PATCH 2/2 arm: cache-l2x0: aurora: Use writel_relaxed instead of writel

In reply to Gregory CLEMENT

The use of writel instead of writel_relaxed lead to deadlock in some situation (SMP on Armada 370 for instance). The use of writel_relaxed as it was done in the rest of this driver fixes this bug.

Signed-off-by Gregory CLEMENT <[email protected]>
Tested-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mm/cache-l2x0.c |    9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)
arch/arm/mm/cache-l2x0.c +5 -4
index 7ffe943..96a1ae4 100644
@@ -459,8 +459,8 @@ static void aurora_pa_range(unsigned long start, unsigned long end,
 	unsigned long flags;
 
 	raw_spin_lock_irqsave(&l2x0_lock, flags);
-	writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
-	writel(end, l2x0_base + offset);
+	writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+	writel_relaxed(end, l2x0_base + offset);
 	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 
 	cache_sync();

@@ -674,8 +674,9 @@ static void pl310_resume(void)
 static void aurora_resume(void)
 {
 	if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
-		writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
-		writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+		writel_relaxed(l2x0_saved_regs.aux_ctrl,
+				l2x0_base + L2X0_AUX_CTRL);
+		writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
 	}
 }
Signature · 1 line
1.7.9.5
#3 lore raw

cover arm: cache-l2x0: aurora: Various bug fixes

In reply to Gregory CLEMENT
Quoted 10 lines · Gregory CLEMENT

Hi,

Now that we have more devices and more boards supported, bugs shows up. Here are a couple of fixes that have been tested on Aramda XP based boards such as DB-78460-BP and DB-MV784MP-GP, and on Armada 370 based boards such as DB-88F6710-BP-DDR3 and Mirabox. They are 3.8 materials.

Thanks,

Quoted 7 lines

Gregory CLEMENT (2):
arm: cache-l2x0: aurora: Invalidate during clean operation with WT
enable
arm: cache-l2x0: aurora: Use writel_relaxed instead of writel

 arch/arm/mm/cache-l2x0.c |   31 +++++++++++++++++++------------
 1 file changed, 19 insertions(+), 12 deletions(-)

Series:

Acked-by Jason Cooper <[email protected]>

thx,

Jason.

author
#4 lore raw

cover arm: cache-l2x0: aurora: Various bug fixes

Quoted 16 lines · Jason Cooper
Quoted 15 lines · Gregory CLEMENT

Hi,

Now that we have more devices and more boards supported, bugs shows up. Here are a couple of fixes that have been tested on Aramda XP based boards such as DB-78460-BP and DB-MV784MP-GP, and on Armada 370 based boards such as DB-88F6710-BP-DDR3 and Mirabox. They are 3.8 materials.

Thanks,

Gregory CLEMENT (2):
arm: cache-l2x0: aurora: Invalidate during clean operation with WT
enable
arm: cache-l2x0: aurora: Use writel_relaxed instead of writel

Quoted 7 lines
Quoted 2 lines
 arch/arm/mm/cache-l2x0.c |   31 +++++++++++++++++++------------
 1 file changed, 19 insertions(+), 12 deletions(-)

Series:

Acked-by Jason Cooper <[email protected]>

Thanks I will add them to Russell patch system

Quoted 9 lines

thx,

Jason.

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Signature · 4 lines
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com