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ARM: shmobile: pinctrl and DT extensions

PATCH Superseded Guennadi Liakhovetski 4 participants 18 messages Jan 16, 2013 – Jan 23, 2013

Subsystems (6)
Device tree bindings Arm (32-bit) Arm sub-architectures SuperH +2 more subsystems

v1 of 3 Superseded Latest is v3 →

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Guennadi Liakhovetski

author
#0 lore raw

cover ARM: shmobile: pinctrl and DT extensions

These patches extend sh7372 and r8a7740 pinctrl support and use it to add SDHI and MMCIF to armadillo800eva and mackerel reference DT implementations. GPIO-based pin configuration is removed from board files. Additionally, MMC interfaces on armadillo800eva support run-time power-switching, which is also supported in DT with these patches.

This series is based on recent work by Laurent and Simon. sh7372 and r8a7740 pinctrl support seems to be stable and, probably, won't change, so, also the base for these patches seems solid. Since the current pinctrl implementation for sh73a0 is likely to change, support for kzm9g isn't included in this series.

Guennadi Liakhovetski (8):
pinctrl: add SDHI and MMCIF pin groups to r8a7740
pinctrl: add SDHI and MMCIF pin groups to sh7372
ARM: shmobile: simplify armadillo800eva and kzm9g Kconfig
dependencies
ARM: shmobile: add MMCIF and SDHI DT clock aliases to sh73a0 and

    r8a7740

ARM: shmobile: add a GPIO controller DT node for sh7372
ARM: shmobile: use GPIO SD-card detection on armadillo800eva
ARM: shmobile: completely switch MMC interfaces on mackerel-reference
to DT
ARM: shmobile: completely switch MMC interfaces on
armadillo800eva-reference to DT

 .../boot/dts/r8a7740-armadillo800eva-reference.dts |  101 ++++++++++
 arch/arm/boot/dts/sh7372-mackerel-reference.dts    |   42 +++-
 arch/arm/boot/dts/sh7372.dtsi                      |    8 +
 arch/arm/mach-shmobile/Kconfig                     |   12 +-
 .../board-armadillo800eva-reference.c              |    5 +-
 arch/arm/mach-shmobile/board-armadillo800eva.c     |   10 +-
 arch/arm/mach-shmobile/board-mackerel-reference.c  |   46 -----
 arch/arm/mach-shmobile/clock-r8a7740.c             |    4 +
 arch/arm/mach-shmobile/clock-sh73a0.c              |    3 +
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c               |  180 +++++++++++++++++
 drivers/pinctrl/sh-pfc/pfc-sh7372.c                |  205 ++++++++++++++++++++
 11 files changed, 552 insertions(+), 64 deletions(-)
Signature · 8 lines
1.7.2.5

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
author
#1 lore raw

PATCH 1/8 pinctrl: add SDHI and MMCIF pin groups to r8a7740

Add pin groups for the first two SDHI interfaces and two alternative pin groups for the MMCIF interface on the r8a7740 SoC.

Signed-off-by Guennadi Liakhovetski <[email protected]>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c |  180 ++++++++++++++++++++++++++++++++++
 1 files changed, 180 insertions(+), 0 deletions(-)
drivers/pinctrl/sh-pfc/pfc-r8a7740.c +180 -0
index d0b7165..5e9a671 100644
@@ -1870,6 +1870,138 @@ static const unsigned int lcd1_sys_mux[] = {
 	LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
 };
 
+static const unsigned int sdhi0_data1_pins[] = {
+	/* D0 */
+	77,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+	SDHI0_D0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+	/* D[0:3] */
+	77, 78, 79, 80,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+	SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+	/* CMD, CLK */
+	76, 82,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+	SDHI0_CMD_MARK, SDHI0_CLK_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+	/* CD */
+	81,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+	SDHI0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+	/* WP */
+	83,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+	SDHI0_WP_MARK,
+};
+
+static const unsigned int sdhi1_data1_pins[] = {
+	/* D0 */
+	68,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+	SDHI1_D0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+	/* D[0:3] */
+	68, 69, 70, 71,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+	SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+	/* CMD, CLK */
+	67, 66,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+	SDHI1_CMD_MARK, SDHI1_CLK_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+	/* CD */
+	72,
+};
+static const unsigned int sdhi1_cd_mux[] = {
+	SDHI1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+	/* WP */
+	73,
+};
+static const unsigned int sdhi1_wp_mux[] = {
+	SDHI1_WP_MARK,
+};
+
+static const unsigned int mmc0_data1_0_pins[] = {
+	/* D[0] */
+	68,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+	MMC0_D0_PORT68_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+	/* D[0:3] */
+	68, 69, 70, 71,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+	MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+	/* D[0:7] */
+	68, 69, 70, 71, 72, 73, 74, 75,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+	MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
+	MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+	/* CMD, CLK */
+	66, 67,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+	MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
+};
+
+static const unsigned int mmc0_data1_1_pins[] = {
+	/* D[0] */
+	149,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+	MMC1_D0_PORT149_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+	/* D[0:3] */
+	149, 148, 147, 146,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+	MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+	/* D[0:7] */
+	149, 148, 147, 146, 145, 144, 143, 142,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+	MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
+	MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+	/* CMD, CLK */
+	104, 103,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+	MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
+};
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(lcd0_data8),
 	SH_PFC_PIN_GROUP(lcd0_data9),

@@ -1893,6 +2025,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(lcd1_lclk),
 	SH_PFC_PIN_GROUP(lcd1_sync),
 	SH_PFC_PIN_GROUP(lcd1_sys),
+	SH_PFC_PIN_GROUP(sdhi0_data1),
+	SH_PFC_PIN_GROUP(sdhi0_data4),
+	SH_PFC_PIN_GROUP(sdhi0_ctrl),
+	SH_PFC_PIN_GROUP(sdhi0_cd),
+	SH_PFC_PIN_GROUP(sdhi0_wp),
+	SH_PFC_PIN_GROUP(sdhi1_data1),
+	SH_PFC_PIN_GROUP(sdhi1_data4),
+	SH_PFC_PIN_GROUP(sdhi1_ctrl),
+	SH_PFC_PIN_GROUP(sdhi1_cd),
+	SH_PFC_PIN_GROUP(sdhi1_wp),
+	SH_PFC_PIN_GROUP(mmc0_data1_0),
+	SH_PFC_PIN_GROUP(mmc0_data4_0),
+	SH_PFC_PIN_GROUP(mmc0_data8_0),
+	SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+	SH_PFC_PIN_GROUP(mmc0_data1_1),
+	SH_PFC_PIN_GROUP(mmc0_data4_1),
+	SH_PFC_PIN_GROUP(mmc0_data8_1),
+	SH_PFC_PIN_GROUP(mmc0_ctrl_1),
 };
 
 static const char * const lcd0_groups[] = {

@@ -1923,9 +2073,39 @@ static const char * const lcd1_groups[] = {
 	"lcd1_sys",
 };
 
+static const char * const sdhi0_groups[] = {
+	"sdhi0_data1",
+	"sdhi0_data4",
+	"sdhi0_ctrl",
+	"sdhi0_cd",
+	"sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+	"sdhi1_data1",
+	"sdhi1_data4",
+	"sdhi1_ctrl",
+	"sdhi1_cd",
+	"sdhi1_wp",
+};
+
+static const char * const mmc0_groups[] = {
+	"mmc0_data1_0",
+	"mmc0_data4_0",
+	"mmc0_data8_0",
+	"mmc0_ctrl_0",
+	"mmc0_data1_1",
+	"mmc0_data4_1",
+	"mmc0_data8_1",
+	"mmc0_ctrl_1",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(lcd0),
 	SH_PFC_FUNCTION(lcd1),
+	SH_PFC_FUNCTION(sdhi0),
+	SH_PFC_FUNCTION(sdhi1),
+	SH_PFC_FUNCTION(mmc0),
 };
 
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
Signature · 1 line
1.7.2.5
author
#2 lore raw

PATCH v2 1/8 pinctrl: add SDHI and MMCIF pin groups to r8a7740

Add pin groups for all three SDHI interfaces and two alternative pin groups for the MMCIF interface on the r8a7740 SoC.

Signed-off-by Guennadi Liakhovetski <[email protected]>

---

v2: add SDHI2 pins

 drivers/pinctrl/sh-pfc/pfc-r8a7740.c |  248 ++++++++++++++++++++++++++++++++++
 1 files changed, 248 insertions(+), 0 deletions(-)
drivers/pinctrl/sh-pfc/pfc-r8a7740.c +248 -0
index d0b7165..57d9e25 100644
@@ -1870,6 +1870,188 @@ static const unsigned int lcd1_sys_mux[] = {
 	LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
 };
 
+static const unsigned int sdhi0_data1_pins[] = {
+	/* D0 */
+	77,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+	SDHI0_D0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+	/* D[0:3] */
+	77, 78, 79, 80,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+	SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+	/* CMD, CLK */
+	76, 82,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+	SDHI0_CMD_MARK, SDHI0_CLK_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+	/* CD */
+	81,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+	SDHI0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+	/* WP */
+	83,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+	SDHI0_WP_MARK,
+};
+
+static const unsigned int sdhi1_data1_pins[] = {
+	/* D0 */
+	68,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+	SDHI1_D0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+	/* D[0:3] */
+	68, 69, 70, 71,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+	SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+	/* CMD, CLK */
+	67, 66,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+	SDHI1_CMD_MARK, SDHI1_CLK_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+	/* CD */
+	72,
+};
+static const unsigned int sdhi1_cd_mux[] = {
+	SDHI1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+	/* WP */
+	73,
+};
+static const unsigned int sdhi1_wp_mux[] = {
+	SDHI1_WP_MARK,
+};
+
+static const unsigned int sdhi2_data1_pins[] = {
+	/* D0 */
+	205,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+	SDHI2_D0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+	/* D[0:3] */
+	205, 206, 207, 208,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+	SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+	/* CMD, CLK */
+	204, 203,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+	SDHI2_CMD_MARK, SDHI2_CLK_MARK,
+};
+static const unsigned int sdhi2_cd_0_pins[] = {
+	/* CD */
+	202,
+};
+static const unsigned int sdhi2_cd_0_mux[] = {
+	SDHI2_CD_PORT202_MARK,
+};
+static const unsigned int sdhi2_wp_0_pins[] = {
+	/* WP */
+	177,
+};
+static const unsigned int sdhi2_wp_0_mux[] = {
+	SDHI2_WP_PORT177_MARK,
+};
+static const unsigned int sdhi2_cd_1_pins[] = {
+	/* CD */
+	24,
+};
+static const unsigned int sdhi2_cd_1_mux[] = {
+	SDHI2_CD_PORT24_MARK,
+};
+static const unsigned int sdhi2_wp_1_pins[] = {
+	/* WP */
+	25,
+};
+static const unsigned int sdhi2_wp_1_mux[] = {
+	SDHI2_WP_PORT25_MARK,
+};
+
+static const unsigned int mmc0_data1_0_pins[] = {
+	/* D[0] */
+	68,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+	MMC0_D0_PORT68_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+	/* D[0:3] */
+	68, 69, 70, 71,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+	MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+	/* D[0:7] */
+	68, 69, 70, 71, 72, 73, 74, 75,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+	MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
+	MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+	/* CMD, CLK */
+	66, 67,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+	MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
+};
+
+static const unsigned int mmc0_data1_1_pins[] = {
+	/* D[0] */
+	149,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+	MMC1_D0_PORT149_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+	/* D[0:3] */
+	149, 148, 147, 146,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+	MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+	/* D[0:7] */
+	149, 148, 147, 146, 145, 144, 143, 142,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+	MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
+	MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+	/* CMD, CLK */
+	104, 103,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+	MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
+};
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(lcd0_data8),
 	SH_PFC_PIN_GROUP(lcd0_data9),

@@ -1893,6 +2075,31 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(lcd1_lclk),
 	SH_PFC_PIN_GROUP(lcd1_sync),
 	SH_PFC_PIN_GROUP(lcd1_sys),
+	SH_PFC_PIN_GROUP(sdhi0_data1),
+	SH_PFC_PIN_GROUP(sdhi0_data4),
+	SH_PFC_PIN_GROUP(sdhi0_ctrl),
+	SH_PFC_PIN_GROUP(sdhi0_cd),
+	SH_PFC_PIN_GROUP(sdhi0_wp),
+	SH_PFC_PIN_GROUP(sdhi1_data1),
+	SH_PFC_PIN_GROUP(sdhi1_data4),
+	SH_PFC_PIN_GROUP(sdhi1_ctrl),
+	SH_PFC_PIN_GROUP(sdhi1_cd),
+	SH_PFC_PIN_GROUP(sdhi1_wp),
+	SH_PFC_PIN_GROUP(sdhi2_data1),
+	SH_PFC_PIN_GROUP(sdhi2_data4),
+	SH_PFC_PIN_GROUP(sdhi2_ctrl),
+	SH_PFC_PIN_GROUP(sdhi2_cd_0),
+	SH_PFC_PIN_GROUP(sdhi2_wp_0),
+	SH_PFC_PIN_GROUP(sdhi2_cd_1),
+	SH_PFC_PIN_GROUP(sdhi2_wp_1),
+	SH_PFC_PIN_GROUP(mmc0_data1_0),
+	SH_PFC_PIN_GROUP(mmc0_data4_0),
+	SH_PFC_PIN_GROUP(mmc0_data8_0),
+	SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+	SH_PFC_PIN_GROUP(mmc0_data1_1),
+	SH_PFC_PIN_GROUP(mmc0_data4_1),
+	SH_PFC_PIN_GROUP(mmc0_data8_1),
+	SH_PFC_PIN_GROUP(mmc0_ctrl_1),
 };
 
 static const char * const lcd0_groups[] = {

@@ -1923,9 +2130,50 @@ static const char * const lcd1_groups[] = {
 	"lcd1_sys",
 };
 
+static const char * const sdhi0_groups[] = {
+	"sdhi0_data1",
+	"sdhi0_data4",
+	"sdhi0_ctrl",
+	"sdhi0_cd",
+	"sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+	"sdhi1_data1",
+	"sdhi1_data4",
+	"sdhi1_ctrl",
+	"sdhi1_cd",
+	"sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+	"sdhi2_data1",
+	"sdhi2_data4",
+	"sdhi2_ctrl",
+	"sdhi2_cd_0",
+	"sdhi2_wp_0",
+	"sdhi2_cd_1",
+	"sdhi2_wp_1",
+};
+
+static const char * const mmc0_groups[] = {
+	"mmc0_data1_0",
+	"mmc0_data4_0",
+	"mmc0_data8_0",
+	"mmc0_ctrl_0",
+	"mmc0_data1_1",
+	"mmc0_data4_1",
+	"mmc0_data8_1",
+	"mmc0_ctrl_1",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(lcd0),
 	SH_PFC_FUNCTION(lcd1),
+	SH_PFC_FUNCTION(sdhi0),
+	SH_PFC_FUNCTION(sdhi1),
+	SH_PFC_FUNCTION(sdhi2),
+	SH_PFC_FUNCTION(mmc0),
 };
 
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
Signature · 1 line
1.7.2.5
#3 lore raw

PATCH v2 1/8 pinctrl: add SDHI and MMCIF pin groups to r8a7740

Hi Guennadi,

Thanks for the patch.

Quoted 16 lines · On Thursday 17 January 2013 11:04:26 Guennadi Liakhovetski wrote:

Add pin groups for all three SDHI interfaces and two alternative pin groups for the MMCIF interface on the r8a7740 SoC.

Signed-off-by Guennadi Liakhovetski <[email protected]>

---

v2: add SDHI2 pins

 drivers/pinctrl/sh-pfc/pfc-r8a7740.c |  248 +++++++++++++++++++++++++++++++
 1 files changed, 248 insertions(+), 0 deletions(-)
(quoted diff) +0 -0

b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index d0b7165..57d9e25 100644

drivers/pinctrl/sh-pfc/pfc-r8a7740.c +0 -0
@@ -1870,6 +1870,188 @@ static const unsigned int lcd1_sys_mux[] = {

[snip]

drivers/pinctrl/sh-pfc/pfc-r8a7740.c static const unsigned int lcd1_sys_mux[] = { · line 2019

Quoted 3 lines
drivers/pinctrl/sh-pfc/pfc-r8a7740.c +3 -0
+static const unsigned int mmc0_ctrl_0_pins[] = {
+	/* CMD, CLK */
+	66, 67,

Shouldn't this be 67, 66 ?

Quoted 4 lines
drivers/pinctrl/sh-pfc/pfc-r8a7740.c +4 -0
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+	MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
+};
Signature · 3 lines
Regards,

Laurent Pinchart
author
#5 lore raw

PATCH 2/8 pinctrl: add SDHI and MMCIF pin groups to sh7372

In reply to Guennadi Liakhovetski

Add pin groups for all three SDHI interfaces and two alternative pin groups for the MMCIF interface on the sh7372 SoC.

Signed-off-by Guennadi Liakhovetski <[email protected]>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c |  205 +++++++++++++++++++++++++++++++++++
 1 files changed, 205 insertions(+), 0 deletions(-)
drivers/pinctrl/sh-pfc/pfc-sh7372.c +205 -0
index 847e0cd..78444a0 100644
@@ -933,6 +933,206 @@ static struct sh_pfc_pin pinmux_pins[] = {
 	GPIO_PORT_ALL(),
 };
 
+static const unsigned int sdhi0_data1_pins[] = {
+	/* D0 */
+	173,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+	SDHID0_0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+	/* D[0:3] */
+	173, 174, 175, 176,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+	SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+	/* CMD, CLK */
+	177, 171,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+	SDHICMD0_MARK, SDHICLK0_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+	/* CD */
+	172,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+	SDHICD0_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+	/* WP */
+	178,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+	SDHIWP0_MARK,
+};
+
+static const unsigned int sdhi1_data1_pins[] = {
+	/* D0 */
+	180,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+	SDHID1_0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+	/* D[0:3] */
+	180, 181, 182, 183,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+	SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+	/* CMD, CLK */
+	184, 179,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+	SDHICMD1_MARK, SDHICLK1_MARK,
+};
+
+static const unsigned int sdhi2_data1_pins[] = {
+	/* D0 */
+	186,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+	SDHID2_0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+	/* D[0:3] */
+	186, 187, 188, 189,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+	SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+	/* CMD, CLK */
+	190, 185,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+	SDHICMD2_MARK, SDHICLK2_MARK,
+};
+
+static const unsigned int mmc0_data1_0_pins[] = {
+	/* D[0] */
+	84,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+	MMCD0_0_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+	/* D[0:3] */
+	84, 85, 86, 87,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+	/* D[0:7] */
+	84, 85, 86, 87, 88, 89, 90, 91,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+	MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+	/* CMD, CLK */
+	92, 99,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+	MMCCMD0_MARK, MMCCLK0_MARK,
+};
+
+static const unsigned int mmc0_data1_1_pins[] = {
+	/* D[0] */
+	54,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+	MMCD1_0_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+	/* D[0:3] */
+	54, 55, 56, 57,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+	/* D[0:7] */
+	54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+	MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+	/* CMD, CLK */
+	67, 66,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+	MMCCMD1_MARK, MMCCLK1_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(sdhi0_data1),
+	SH_PFC_PIN_GROUP(sdhi0_data4),
+	SH_PFC_PIN_GROUP(sdhi0_ctrl),
+	SH_PFC_PIN_GROUP(sdhi0_cd),
+	SH_PFC_PIN_GROUP(sdhi0_wp),
+	SH_PFC_PIN_GROUP(sdhi1_data1),
+	SH_PFC_PIN_GROUP(sdhi1_data4),
+	SH_PFC_PIN_GROUP(sdhi1_ctrl),
+	SH_PFC_PIN_GROUP(sdhi2_data1),
+	SH_PFC_PIN_GROUP(sdhi2_data4),
+	SH_PFC_PIN_GROUP(sdhi2_ctrl),
+	SH_PFC_PIN_GROUP(mmc0_data1_0),
+	SH_PFC_PIN_GROUP(mmc0_data4_0),
+	SH_PFC_PIN_GROUP(mmc0_data8_0),
+	SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+	SH_PFC_PIN_GROUP(mmc0_data1_1),
+	SH_PFC_PIN_GROUP(mmc0_data4_1),
+	SH_PFC_PIN_GROUP(mmc0_data8_1),
+	SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+};
+
+static const char * const sdhi0_groups[] = {
+	"sdhi0_data1",
+	"sdhi0_data4",
+	"sdhi0_ctrl",
+	"sdhi0_cd",
+	"sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+	"sdhi1_data1",
+	"sdhi1_data4",
+	"sdhi1_ctrl",
+};
+
+static const char * const sdhi2_groups[] = {
+	"sdhi2_data1",
+	"sdhi2_data4",
+	"sdhi2_ctrl",
+};
+
+static const char * const mmc0_groups[] = {
+	"mmc0_data1_0",
+	"mmc0_data4_0",
+	"mmc0_data8_0",
+	"mmc0_ctrl_0",
+	"mmc0_data1_1",
+	"mmc0_data4_1",
+	"mmc0_data8_1",
+	"mmc0_ctrl_1",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(sdhi0),
+	SH_PFC_FUNCTION(sdhi1),
+	SH_PFC_FUNCTION(sdhi2),
+	SH_PFC_FUNCTION(mmc0),
+};
+
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
 
 static struct pinmux_func pinmux_func_gpios[] = {

@@ -1644,6 +1844,11 @@ struct sh_pfc_soc_info sh7372_pinmux_info = {
 
 	.pins = pinmux_pins,
 	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.groups		= pinmux_groups,
+	.nr_groups	= ARRAY_SIZE(pinmux_groups),
+	.functions	= pinmux_functions,
+	.nr_functions	= ARRAY_SIZE(pinmux_functions),
+
 	.func_gpios = pinmux_func_gpios,
 	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
Signature · 1 line
1.7.2.5
author
#7 lore raw

PATCH 2/8 pinctrl: add SDHI and MMCIF pin groups to sh7372

Quoted 11 lines · Linus Walleij
Quoted 4 lines · Guennadi Liakhovetski

Add pin groups for all three SDHI interfaces and two alternative pin groups for the MMCIF interface on the sh7372 SoC.

Signed-off-by Guennadi Liakhovetski <[email protected]>
Acked-by Linus Walleij <[email protected]>

I guess this needs to go on top of Laurent's patch set?

Sure, quoting patch 0/8:

<quote>
This series is based on recent work by Laurent and Simon. sh7372 and r8a7740 pinctrl support seems to be stable and, probably, won't change, so, also the base for these patches seems solid. Since the current pinctrl implementation for sh73a0 is likely to change, support for kzm9g isn't included in this series.
</quote>

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/

#8 lore raw

PATCH 2/8 pinctrl: add SDHI and MMCIF pin groups to sh7372

In reply to Guennadi Liakhovetski

Hi Guennadi,

Thanks for the patch.

Quoted 12 lines · On Wednesday 16 January 2013 18:08:11 Guennadi Liakhovetski wrote:

Add pin groups for all three SDHI interfaces and two alternative pin groups for the MMCIF interface on the sh7372 SoC.

Signed-off-by Guennadi Liakhovetski <[email protected]>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c |  205 ++++++++++++++++++++++++++++++++
 1 files changed, 205 insertions(+), 0 deletions(-)
(quoted diff) +0 -0

b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index 847e0cd..78444a0 100644

drivers/pinctrl/sh-pfc/pfc-sh7372.c +0 -0

[snip]

drivers/pinctrl/sh-pfc/pfc-sh7372.c struct sh_pfc_soc_info sh7372_pinmux_info = { · line 1851

Quoted 9 lines
drivers/pinctrl/sh-pfc/pfc-sh7372.c +5 -0
@@ -1644,6 +1844,11 @@ struct sh_pfc_soc_info sh7372_pinmux_info = {
 
 	.pins = pinmux_pins,
 	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.groups		= pinmux_groups,
+	.nr_groups	= ARRAY_SIZE(pinmux_groups),
+	.functions	= pinmux_functions,
+	.nr_functions	= ARRAY_SIZE(pinmux_functions),
+

Just a little bit of nitpicking here. I don't have a strong preference on whether the = signs should be aligned. Both options were used in the PFC code, so I've tried to keep whatever was there. It might be better to do so here as well.

Quoted 2 lines
drivers/pinctrl/sh-pfc/pfc-sh7372.c +0 -0
 	.func_gpios = pinmux_func_gpios,
 	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
Signature · 3 lines
Regards,

Laurent Pinchart
author
#9 lore raw

PATCH 3/8 ARM: shmobile: simplify armadillo800eva and kzm9g Kconfig dependencies

In reply to Guennadi Liakhovetski

Reference kernel configurations for armadillo800eva and kzm9g boards do not have to depend on their respective "legacy" configurations, doing device instantiation in .c, they can be configured and built independently.

Signed-off-by Guennadi Liakhovetski <[email protected]>
---
 arch/arm/mach-shmobile/Kconfig |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)
arch/arm/mach-shmobile/Kconfig +10 -2
index 5f61e8f..927eecc 100644
@@ -106,7 +106,11 @@ config MACH_ARMADILLO800EVA
 
 config MACH_ARMADILLO800EVA_REFERENCE
 	bool "Armadillo-800 EVA board - Reference Device Tree Implementation"
-	depends on MACH_ARMADILLO800EVA
+	depends on ARCH_R8A7740
+	select ARCH_REQUIRE_GPIOLIB
+	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+	select SND_SOC_WM8978 if SND_SIMPLE_CARD
+	select USE_OF
 	---help---
 	  Use reference implementation of Aramdillo800 EVA board support
 	  which makes a greater use of device tree at the expense

@@ -136,7 +140,11 @@ config MACH_KZM9G
 
 config MACH_KZM9G_REFERENCE
 	bool "KZM-A9-GT board - Reference Device Tree Implementation"
-	depends on MACH_KZM9G
+	depends on ARCH_SH73A0
+	select ARCH_REQUIRE_GPIOLIB
+	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+	select SND_SOC_AK4642 if SND_SIMPLE_CARD
+	select USE_OF
 	---help---
 	   Use reference implementation of KZM-A9-GT board support
 	   which makes as greater use of device tree at the expense
Signature · 1 line
1.7.2.5
author
#10 lore raw

PATCH 4/8 ARM: shmobile: add MMCIF and SDHI DT clock aliases to sh73a0 and r8a7740

In reply to Guennadi Liakhovetski

Add clock lookup entries for SDHI and MMCIF device names, for the FDT case.

Signed-off-by Guennadi Liakhovetski <[email protected]>
---
 arch/arm/mach-shmobile/clock-r8a7740.c |    4 ++++
 arch/arm/mach-shmobile/clock-sh73a0.c  |    3 +++
 2 files changed, 7 insertions(+), 0 deletions(-)
arch/arm/mach-shmobile/clock-r8a7740.c +4 -0
index 8765a76..83209bf 100644
@@ -611,12 +611,16 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("i2c-sh_mobile.1",	&mstp_clks[MSTP323]),
 	CLKDEV_DEV_ID("renesas_usbhs",		&mstp_clks[MSTP320]),
 	CLKDEV_DEV_ID("sh_mobile_sdhi.0",	&mstp_clks[MSTP314]),
+	CLKDEV_DEV_ID("e6850000.sdhi",		&mstp_clks[MSTP314]),
 	CLKDEV_DEV_ID("sh_mobile_sdhi.1",	&mstp_clks[MSTP313]),
+	CLKDEV_DEV_ID("e6860000.sdhi",		&mstp_clks[MSTP313]),
 	CLKDEV_DEV_ID("sh_mmcif",		&mstp_clks[MSTP312]),
+	CLKDEV_DEV_ID("e6bd0000.mmcif",		&mstp_clks[MSTP312]),
 	CLKDEV_DEV_ID("sh-eth",			&mstp_clks[MSTP309]),
 	CLKDEV_DEV_ID("e9a00000.sh-eth",	&mstp_clks[MSTP309]),
 
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2",	&mstp_clks[MSTP415]),
+	CLKDEV_DEV_ID("e6870000.sdhi",		&mstp_clks[MSTP415]),
 
 	/* ICK */
 	CLKDEV_ICK_ID("host",	"renesas_usbhs",	&mstp_clks[MSTP416]),
arch/arm/mach-shmobile/clock-sh73a0.c +3 -0
index afa5423..5fa106b 100644
@@ -581,10 +581,13 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
 	CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+	CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+	CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
 	CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
 	CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
+	CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
 	CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
 	CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
 	CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
Signature · 1 line
1.7.2.5
author
#11 lore raw

PATCH 5/8 ARM: shmobile: add a GPIO controller DT node for sh7372

In reply to Guennadi Liakhovetski

Add a missing GPIO controller node to sh7372.

Signed-off-by Guennadi Liakhovetski <[email protected]>
---
 arch/arm/boot/dts/sh7372.dtsi |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
arch/arm/boot/dts/sh7372.dtsi +8 -0
index 582fdec..7ca9322 100644
@@ -19,6 +19,14 @@
 		};
 	};
 
+	gpio: pfc at e6050000 {
+		compatible = "renesas,pfc-sh7372";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605800c 0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
Signature · 1 line
1.7.2.5
#12 lore raw

PATCH 5/8 ARM: shmobile: add a GPIO controller DT node for sh7372

Hi Guennadi,

Thanks for the patch.

Quoted 12 lines · On Wednesday 16 January 2013 18:08:14 Guennadi Liakhovetski wrote:

Add a missing GPIO controller node to sh7372.

Signed-off-by Guennadi Liakhovetski <[email protected]>
---
 arch/arm/boot/dts/sh7372.dtsi |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
arch/arm/boot/dts/sh7372.dtsi +0 -0
index 582fdec..7ca9322 100644

arch/arm/boot/dts/sh7372.dtsi line 25

Quoted 7 lines
arch/arm/boot/dts/sh7372.dtsi +4 -0
@@ -19,6 +19,14 @@
 		};
 	};
 
+	gpio: pfc at e6050000 {
+		compatible = "renesas,pfc-sh7372";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605800c 0x20>;

Shouldn't the second one be

		      <0xe605800c 0x1c>;

arch/arm/boot/dts/sh7372.dtsi line 29

Quoted 4 lines
arch/arm/boot/dts/sh7372.dtsi +4 -0
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+

I haven't checked the board files, have you made sure that the PFC device won't be instantiated twice, once from DT and once from board code ?

Quoted 3 lines
arch/arm/boot/dts/sh7372.dtsi +0 -0
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
Signature · 3 lines
Regards,

Laurent Pinchart
author
#13 lore raw

PATCH 5/8 ARM: shmobile: add a GPIO controller DT node for sh7372

Hi Laurent

Thanks for your comments. All will be addressed except for this one:

Quoted 29 lines · Laurent Pinchart

Hi Guennadi,

Thanks for the patch.

Quoted 12 lines · On Wednesday 16 January 2013 18:08:14 Guennadi Liakhovetski wrote:

Add a missing GPIO controller node to sh7372.

Signed-off-by Guennadi Liakhovetski <[email protected]>
---
 arch/arm/boot/dts/sh7372.dtsi |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
arch/arm/boot/dts/sh7372.dtsi +0 -0
index 582fdec..7ca9322 100644

arch/arm/boot/dts/sh7372.dtsi line 25

Quoted 7 lines
arch/arm/boot/dts/sh7372.dtsi +4 -0
@@ -19,6 +19,14 @@
 		};
 	};
 
+	gpio: pfc at e6050000 {
+		compatible = "renesas,pfc-sh7372";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605800c 0x20>;

Shouldn't the second one be

		      <0xe605800c 0x1c>;
Quoted 7 lines

arch/arm/boot/dts/sh7372.dtsi line 29

Quoted 4 lines
arch/arm/boot/dts/sh7372.dtsi +4 -0
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+

I haven't checked the board files, have you made sure that the PFC device won't be instantiated twice, once from DT and once from board code ?

Don't think so. board-mackerel.c uses DT in a really dull way - it doesn't call of_platform_populate(). It also initialises interrupts by calling sh7372_init_irq(), which would conflict with intc instances in sh7372.dtsi too, if the latter were used. And board-mackerel-reference.c doesn't register PFC internally.

Thanks
Guennadi

Quoted 10 lines
Quoted 4 lines
arch/arm/boot/dts/sh7372.dtsi +0 -0
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
Signature · 3 lines
Regards,

Laurent Pinchart

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/

author
#14 lore raw

PATCH 6/8 ARM: shmobile: use GPIO SD-card detection on armadillo800eva

In reply to Guennadi Liakhovetski

Switch SDHI0 and SDHI1 SD-card interfaces on armadillo800eva to using GPIO card detection, which provides maximum power saving and automatically selects IRQ or polling mode, depending on the CD GPIO capability.

Signed-off-by Guennadi Liakhovetski <[email protected]>
---
 arch/arm/mach-shmobile/board-armadillo800eva.c |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)
arch/arm/mach-shmobile/board-armadillo800eva.c +6 -4
index e657a7a..1cf1157 100644
@@ -580,10 +580,10 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] =
 static struct sh_mobile_sdhi_info sdhi0_info = {
 	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
 	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
-	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |\
-			  MMC_CAP_NEEDS_POLL,
+	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
 	.tmio_ocr_mask	= MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
-	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT,
+	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
+	.cd_gpio	= GPIO_PORT167,
 };
 
 static struct resource sdhi0_resources[] = {

@@ -624,7 +624,9 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
 	.dma_slave_rx	= SHDMA_SLAVE_SDHI1_RX,
 	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
 	.tmio_ocr_mask	= MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
-	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT,
+	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
+	/* Port72 cannot generate IRQs, will be used in polling mode. */
+	.cd_gpio	= GPIO_PORT72,
 };
 
 static struct resource sdhi1_resources[] = {
Signature · 1 line
1.7.2.5
author
#15 lore raw

PATCH 7/8 ARM: shmobile: completely switch MMC interfaces on mackerel-reference to DT

In reply to Guennadi Liakhovetski

Switch MMCIF, SDHI0 and SDHI2 to complete DT initialisation: use DT bindings to configure interface pins, card-detect GPIOs, various interface configuration parameters. Notice, since MMCIF and SDHI1 share the same card slot, both devices cannot be successfully probed
simultaneously: they both would try to get the card-detection GPIO and only one would succeed. Ideally it should be possible to let the user decide which device to enable by, possibly, patching the DT at run-time. As long as this is unsupported, we choose to enable MMCIF and remove SDHI1 from DT completely.

Signed-off-by Guennadi Liakhovetski <[email protected]>
---
 arch/arm/boot/dts/sh7372-mackerel-reference.dts   |   42 +++++++++++++++----
 arch/arm/mach-shmobile/board-mackerel-reference.c |   46 ---------------------
 2 files changed, 33 insertions(+), 55 deletions(-)
arch/arm/boot/dts/sh7372-mackerel-reference.dts +33 -9
index 2fd1eff..aa72309 100644
@@ -75,6 +75,11 @@
 		interrupt-parent = <&intca>;
 		interrupts = <0x1ac0 0x1ae0>;
 		vmmc-supply = <&reg_1p8v>;
+		bus-width = <8>;
+		cd-gpios = <&gpio 41 1>;
+		broken-cd;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mmc0_pins>;
 	};
 
 	sdhi0: sdhi at 0xe6850000 {

@@ -83,22 +88,26 @@
 		interrupt-parent = <&intca>;
 		interrupts = <0x0e00 0x0e20 0x0e40>;
 		vmmc-supply = <&reg_3p3v>;
-	};
-
-	sdhi1: sdhi at 0xe6860000 {
-		compatible = "renesas,shmobile-sdhi";
-		reg = <0xe6860000 0x100>;
-		interrupt-parent = <&intca>;
-		interrupts = <0x0e80 0x0ea0 0x0ec0>;
-		vmmc-supply = <&reg_1p8v>;
+		bus-width = <4>;
+		cd-gpios = <&gpio 172 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdhi0_pins>;
+		toshiba,mmc-cap-sdio-irq;
 	};
 
 	sdhi2: sdhi at 0xe6870000 {
 		compatible = "renesas,shmobile-sdhi";
 		reg = <0xe6870000 0x100>;
 		interrupt-parent = <&intca>;
-		interrupts = <0x1200 0x1220 0x1240>;
+		interrupts = <0x1220 0x1240>;
 		vmmc-supply = <&reg_3p3v>;
+		bus-width = <4>;
+		cd-gpios = <&gpio 162 1>;
+		broken-cd;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdhi2_pins>;
+		toshiba,mmc-wrprotect-disable;
+		toshiba,mmc-cap-sdio-irq;
 	};
 
 	flash at 2000000 {

@@ -129,3 +138,18 @@
 		};
 	};
 };
+
+&gpio {
+	sdhi0_pins: pfc_sdhi0_pins {
+		renesas,pins = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
+		renesas,function = "sdhi0";
+	};
+	sdhi2_pins: pfc_sdhi2_pins {
+		renesas,pins = "sdhi2_data4", "sdhi2_ctrl";
+		renesas,function = "sdhi2";
+	};
+	mmc0_pins: pfc_mmc0_pins {
+		renesas,pins = "mmc0_data8_0", "mmc0_ctrl_0";
+		renesas,function = "mmc0";
+	};
+};
arch/arm/mach-shmobile/board-mackerel-reference.c +0 -46

58 lines not on this page · raw message

Signature · 1 line
1.7.2.5
author
#16 lore raw

PATCH 8/8 ARM: shmobile: completely switch MMC interfaces on armadillo800eva-reference to DT

In reply to Guennadi Liakhovetski

Switch MMCIF, SDHI0 and SDHI1 to complete DT initialisation: use DT bindings to configure regulators, interface pins, card-detect GPIOs, various interface configuration parameters.

Signed-off-by Guennadi Liakhovetski <[email protected]>
---
 .../boot/dts/r8a7740-armadillo800eva-reference.dts |  101 ++++++++++++++++++++
 .../board-armadillo800eva-reference.c              |    5 +-
 2 files changed, 103 insertions(+), 3 deletions(-)
arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +101 -0
index 319af9b..27774eb 100644
@@ -30,4 +30,105 @@
 		sh-eth,register-type = "gigabit";
 		sh-eth,phy-id = <0>;
 	};
+
+	reg_3p3v: regulator at 0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	mmcif0: mmcif at 0xe6bd0000 {
+		compatible = "renesas,sh-mmcif", "renesas,sh7372-mmcif";
+		reg = <0xe6bd0000 0x100>;
+		interrupt-parent = <&intca>;
+		interrupts = <0x1ac0 0x1ae0>;
+		vmmc-supply = <&reg_3p3v>;
+		bus-width = <8>;
+		non-removable;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mmc0_pins>;
+	};
+
+	vcc_sdhi0: regulator at 1 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vcc-sdhi0";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio 75 0>;
+		enable-active-high;
+	};
+
+	vcc_sdhi1: regulator at 2 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vcc-sdhi1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio 16 0>;
+		enable-active-high;
+	};
+
+	vccq_sdhi0: gpio-regulator at 0 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "vccq-sdhi0";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sdhi0>;
+
+		enable-gpio = <&gpio 74 0>;
+		gpios = <&gpio 17 0>;
+		states = <3300000 0
+			  1800000 1>;
+
+		enable-active-high;
+	};
+
+	sdhi0: sdhi at 0xe6850000 {
+		compatible = "renesas,shmobile-sdhi";
+		reg = <0xe6850000 0x100>;
+		interrupt-parent = <&intca>;
+		interrupts = <0xe20 0xe40>;
+		vmmc-supply = <&vcc_sdhi0>;
+		vqmmc-supply = <&vccq_sdhi0>;
+		bus-width = <4>;
+		cd-gpios = <&gpio 167 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdhi0_pins>;
+		toshiba,mmc-has-idle-wait;
+		toshiba,mmc-cap-sdio-irq;
+	};
+
+	sdhi1: sdhi at 0xe6860000 {
+		compatible = "renesas,shmobile-sdhi";
+		reg = <0xe6860000 0x100>;
+		interrupt-parent = <&intca>;
+		interrupts = <0xea0 0xec0>;
+		vmmc-supply = <&vcc_sdhi1>;
+		bus-width = <4>;
+		cd-gpios = <&gpio 72 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdhi1_pins>;
+		toshiba,mmc-has-idle-wait;
+		toshiba,mmc-cap-sdio-irq;
+	};
+};
+
+&gpio {
+	sdhi0_pins: pfc_sdhi0_pins {
+		renesas,pins = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
+		renesas,function = "sdhi0";
+	};
+	sdhi1_pins: pfc_sdhi1_pins {
+		renesas,pins = "sdhi1_data4", "sdhi1_ctrl", "sdhi1_wp";
+		renesas,function = "sdhi1";
+	};
+	mmc0_pins: pfc_mmc0_pins {
+		renesas,pins = "mmc0_data8_1", "mmc0_ctrl_1";
+		renesas,function = "mmc0";
+	};
 };
arch/arm/mach-shmobile/board-armadillo800eva-reference.c +2 -3
index c206612..f929931 100644
@@ -107,9 +107,10 @@
  */
 static void __init eva_init(void)
 {
-	r8a7740_pinmux_init();
 	r8a7740_meram_workaround();
 
+	r8a7740_add_standard_devices_dt();
+
 	/* SCIFA1 */
 	gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
 	gpio_request(GPIO_FN_SCIFA1_TXD, NULL);

@@ -142,8 +143,6 @@ static void __init eva_init(void)
 	/* Early BRESP enable, Shared attribute override enable, 32K*8way */
 	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
 #endif
-
-	r8a7740_add_standard_devices_dt();
 }
 
 #define RESCNT2 IOMEM(0xe6188020)
Signature · 1 line
1.7.2.5
#17 lore raw

cover ARM: shmobile: pinctrl and DT extensions

In reply to Guennadi Liakhovetski
Quoted 11 lines · Guennadi Liakhovetski

These patches extend sh7372 and r8a7740 pinctrl support and use it to add SDHI and MMCIF to armadillo800eva and mackerel reference DT implementations. GPIO-based pin configuration is removed from board files. Additionally, MMC interfaces on armadillo800eva support run-time power-switching, which is also supported in DT with these patches.

This series is based on recent work by Laurent and Simon. sh7372 and r8a7740 pinctrl support seems to be stable and, probably, won't change, so, also the base for these patches seems solid. Since the current pinctrl implementation for sh73a0 is likely to change, support for kzm9g isn't included in this series.

Thanks.

As these depend on at least one outstanding series from Laurent, I'm going to wait for some fresh patches from him before applying this.