ARM: shmobile: DT initialisation of INTC

new file mode 100644
index 0000000..eb605ce
@@ -0,0 +1,191 @@
+* Renesas SuperH / SH-MOBILE Interrupt Controller
+
+The SH/INTC driver is used by SuperH and ARM/SH-MOBILE.
+At the moment, SuperH does not have the plan corresponding to DT.
+DT of SH/INTC has taken the form where the table data of the C
+is managed by DT, in order to maintain compatibility.
+
+The main node requires the following properties:
+
+- compatible : "renesas,sh-intc"
+
+- interrupt-controller  : Identifies the node as an interrupt controller
+- #interrupt-cells      : Must be 1
+- #address-cells        : Must be 1
+- #size-cells           : Must be 1
+- ranges                : Empty as we have a 1-1 mapping to parent's
+                          address space
+- reg                   : Specifies base physical address(s) and size of
+                          the INTC registers
+- intsrc*               : Interrupt source
+                          Associate an interrupt source with its vector
+
+- *_registers           : These describe the vector table, mask, priority, ack,
+                          and sense registers. It must contain the following:
+
+ -- intc_vectors	: This describes the interrupt sources
+    This node requires the following property:
+	*vector_table	: List of interrupt sources
+
+ -- intc_mask_registers : This specifies the contents of the mask registers
+    This node requires the following properties:
+        * address-cells : Must be 1
+        * size-cells    : Must be 1
+        * ranges        : Empty as we have a 1-1 mapping to parent's
+                          address space
+        * intc_mask*    : A mask register
+	  This node requires the following properties:
+          ** reg        : This specifies the address of mask registers.
+                          The first entry specifies the mask register and
+                          the second entry specifies the mask clear
+                          register.  The first cell is the register's
+                          address, and the second cell is the register's size
+                          which must be 1, 2 or 4 bytes.
+          ** reginfo    : This specifies the interrupt sources controlled by
+                          the mask. The list entries correspond to bits of
+                          the mask from most to least significant.  A value
+                          of 0 may be used for unused bits in the mask.
+                          Trailing list entries may be omitted in which
+                          case they will be treated as 0.
+
+ -- intc_prio_registers : This sets up the contents of the priority registers
+    This node requires the following properties:
+        * address-cells : Must be 1
+        * size-cells    : Must be 1
+        * ranges        : Empty as we have a 1-1 mapping to parent's
+                          address space
+        * intc_prio*	: A sense register
+	  This node requires the following properties:
+          ** reg        : This specifies the address of the priority register.
+                          The first entry specifies the priority set
+                          register and the second entry specifies priority
+                          clear register.  The first cell is the register's
+                          address, and the second cell is the register's
+                          size which must be 1, 2 or 4 bytes.  If there is
+                          not priority clear register then they entry may
+                          be omitted or 0 used as the register's address.
+          ** field-width: Width of each group in the register in bits.
+                          A group contains the priority for a single
+                          interrupt vector. Thus a 16 bit register with
+                          a field-width of 4 may control the priority for
+                          4 (16 / 4) interrupt sources.
+          ** reginfo    : This specifies the interrupt sources or interrupt
+                          source groups controlled by the priority register.
+                          The list entries correspond to the groups of the
+                          priority register from least to most significant.
+                          A value of 0 may be used for unused groups.
+                          Trailing list entries may be omitted in which
+                          case they will be treated as 0.
+
+ -- intc_sense_registers : This sets up the contents of the sense registers
+    This node requires the following properties:
+        * address-cells : Must be 1
+        * size-cells    : Must be 1
+        * ranges        : Empty as we have a 1-1 mapping to parent's
+                          address space
+        * intc_prio*	: A sense register
+	  This node requires the following properties:
+          ** reg        : This specifies the address of the sense register.
+                          The first cell is the register's address, and the
+                          second cell is the register's size which must be
+                          1, 2 or 4 bytes.
+          ** field-width: Width of each group in the register in bits.
+                          A group contains the priority for a single
+                          interrupt vector. Thus a 16 bit register with
+                          a field-width of 4 may control the priority for
+                          4 (16 / 4) interrupt sources.
+          ** reginfo    : This specifies the interrupt sources controlled by
+                          the sense register.  The list entries correspond
+                          to the groups of the priority register from least
+                          to most significant.  A value of 0 may be used
+                          for unused groups.  Trailing list entries may be
+                          omitted in which case they will be treated as 0.
+
+ -- intc_ack_registers   : This sets up the contents of the ACK registers
+    This node requires the following properties:
+        * address-cells : Must be 1
+        * size-cells    : Must be 1
+        * ranges        : Empty as we have a 1-1 mapping to parent's
+                          address space
+        * intc_ack*	: An ACK registers
+	  This node requires the following properties:
+          ** reg        : This specifies the address of the ACK register.
+                          The first cell is the register's address, and the
+                          second cell is the register's size which must be
+                          1, 2 or 4 bytes.
+          ** reginfo    : This specifies the interrupt sources controlled by
+                          the ACK register. The list entries correspond to
+                          bits of the ACK register from most to least
+                          significant.  A value of 0 may be used for unused
+                          bits in the mask.  Trailing list entries may be
+                          omitted in which case they will be treated as 0.
+
+Optional:
+
+- intc_groups		: The interrupt source groups
+                          Interrupt sources may be grouped with a group
+                          sharing the same bits of an interrupt priority
+                          register.
+    This node requires the following property:
+	* intc_group*   : An interrupt source group
+	  This node requires the following property:
+          ** group      : The list of interrupt sources that
+                          belong to the group.
+
+- intc_intevtsa	: This sets up the contents of INTEVTSA.
+	This node requires the following properties:
+	  * vector : This specifies the interrupt source
+
+Example:
+
+	intca: interrupt-controller at 0 {
+		compatible = "renesas,sh_intc";
+		interrupt-controller;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		#interrupt-cells = <1>;
+		ranges;
+
+		reg = <0xe6940000 0x200>, <0xe6950000 0x200>;
+		group_size = <19>;
+
+		DIRC: intsrc1 { vector = <0x0560>; };
+		ATAPI: intsrc2 { vector = <0x05E0>; };
+		....
+
+		DMAC1_1: intc_group0 { group = <&DMAC1_1_DEI0 &DMAC1_1_DEI1
+				&DMAC1_1_DEI2 &DMAC1_1_DEI3>; };
+		DMAC1_2: intc_group1 { group = <&DMAC1_2_DEI4 &DMAC1_2_DEI5
+						 &DMAC1_2_DADERR>; };
+		....
+		intc_vectors {
+			vector_table = <&DIRC &ATAPI &IIC1_ALI &IIC1_TACKI &IIC1_WAITI,
+		....
+		};
+
+		intc_mask_registers {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			intc_mask0 {
+				reg = <0xe6940080 1>, <0xe69400c0 1>;
+				reginfo = <&DMAC2_1_DEI3 &DMAC2_1_DEI2 &DMAC2_1_DEI1
+					&DMAC2_1_DEI0 0 0 &AP_ARM_COMMTX &AP_ARM_COMMRX>;
+			};
+			....
+		};
+
+		intc_prio_registers {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			intc_prio0 {
+				reg = <0xe6940000 2>;
+				field-width = <4>;
+				reginfo = <&DMAC3_1 &DMAC3_2 &CMT2 &ICBS0>;
+			};
+			....
+		};
+	};

index 54ec2a0..b53ab7e 100644
@@ -3,3 +3,4 @@ obj-y 	:= access.o chip.o core.o handle.o irqdomain.o virq.o
 obj-$(CONFIG_INTC_BALANCING)		+= balancing.o
 obj-$(CONFIG_INTC_USERIMASK)		+= userimask.o
 obj-$(CONFIG_INTC_MAPPING_DEBUG)	+= virq-debugfs.o
+obj-$(CONFIG_OF)			+= of_intc.o

index e44da40..7fb4696 100644
@@ -123,7 +123,8 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
 dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
 	r8a7740-armadillo800eva.dtb \
 	sh73a0-kzm9g.dtb \
-	sh7372-mackerel.dtb
+	sh7372-mackerel.dtb \
+	sh7372-mackerel-reference.dtb
 dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
 	spear1340-evb.dtb
 dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \

131 lines not on this page · raw message

index 9255546..c25784b 100644
@@ -76,6 +76,14 @@ config MACH_MACKEREL
 	select SND_SOC_AK4642 if SND_SIMPLE_CARD
 	select USE_OF
 
+config MACH_MACKEREL_REFERENCE
+	bool "mackerel board - Reference Device Tree Implementation"
+	depends on ARCH_SH7372
+	select ARCH_REQUIRE_GPIOLIB
+	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+	select SND_SOC_AK4642 if SND_SIMPLE_CARD
+	select USE_OF
+
 config MACH_KOTA2
 	bool "KOTA2 board"
 	depends on ARCH_SH73A0

index e1fac57..7723a8f 100644
@@ -36,6 +36,7 @@ obj-$(CONFIG_ARCH_SH73A0)	+= pm-sh73a0.o
 obj-$(CONFIG_MACH_AP4EVB)	+= board-ap4evb.o
 obj-$(CONFIG_MACH_AG5EVM)	+= board-ag5evm.o
 obj-$(CONFIG_MACH_MACKEREL)	+= board-mackerel.o
+obj-$(CONFIG_MACH_MACKEREL_REFERENCE)	+= board-mackerel-reference.o
 obj-$(CONFIG_MACH_KOTA2)	+= board-kota2.o
 obj-$(CONFIG_MACH_BONITO)	+= board-bonito.o
 obj-$(CONFIG_MACH_MARZEN)	+= board-marzen.o

index 677fc60..582fdec 100644
@@ -18,4 +18,787 @@
 			compatible = "arm,cortex-a8";
 		};
 	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		intca: interrupt-controller at 0 {
+			compatible = "renesas,sh-intc";
+			interrupt-controller;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#interrupt-cells = <1>;
+			ranges;
+
+			reg = <0xe6940000 0x200>, <0xe6950000 0x200>;
+
+			DIRC:		intsrc1 { vector = <0x0560>; };
+			CRYPT_STD:	intsrc2 { vector = <0x0700>; };
+			IIC1_ALI1:	intsrc3 { vector = <0x0780>; };
+			IIC1_TACKI1:intsrc4 { vector = <0x07a0>; };
+			IIC1_WAITI1:intsrc5 { vector = <0x07c0>; };
+			IIC1_DTEI1:	intsrc6 { vector = <0x07e0>; };
+			AP_ARM_IRQPMU:	intsrc7 { vector = <0x0800>; };
+			AP_ARM_COMMTX:	intsrc8 { vector = <0x0840>; };
+			AP_ARM_COMMRX:	intsrc9 { vector = <0x0860>; };
+			MFI_MFIM:	intsrc10 { vector = <0x0900>; };
+			MFI_MFIS:	intsrc11 { vector = <0x0920>; };
+			BBIF1:		intsrc12 { vector = <0x0940>; };
+			BBIF2:		intsrc13 { vector = <0x0960>; };
+			USBHSDMAC0_USHDMI:	intsrc14 { vector = <0x0a00>; };
+			_3DG_SGX540:	intsrc15 { vector = <0x0a60>; };
+			CMT1_CMT10:	intsrc16 { vector = <0x0b00>; };
+			CMT1_CMT11:	intsrc17 { vector = <0x0b20>; };
+			CMT1_CMT12:	intsrc18 { vector = <0x0b40>; };
+			CMT1_CMT13:	intsrc19 { vector = <0x0b60>; };
+			CMT2:		intsrc20 { vector = <0x0b80>; };
+			CMT3:		intsrc21 { vector = <0x0ba0>; };
+			KEYSC_KEY:	intsrc22 { vector = <0x0be0>; };
+			SCIFA0:		intsrc23 { vector = <0x0c00>; };
+			SCIFA1:		intsrc24 { vector = <0x0c20>; };
+			SCIFA2:		intsrc25 { vector = <0x0c40>; };
+			SCIFA3:		intsrc26 { vector = <0x0c60>; };
+			MSIOF2:		intsrc27 { vector = <0x0c80>; };
+			MSIOF1:		intsrc28 { vector = <0x0d00>; };
+			SCIFA4:		intsrc29 { vector = <0x0d20>; };
+			SCIFA5:		intsrc30 { vector = <0x0d40>; };
+			SCIFB:		intsrc31 { vector = <0x0d60>; };
+			FLCTL_FLSTEI:	intsrc32 { vector = <0x0d80>; };
+			FLCTL_FLTENDI:	intsrc33 { vector = <0x0da0>; };
+			FLCTL_FLTREQ0I:	intsrc34 { vector = <0x0dc0>; };
+			FLCTL_FLTREQ1I:	intsrc35 { vector = <0x0de0>; };
+			SDHI0_SDHI0I0:	intsrc36 { vector = <0x0e00>; };
+			SDHI0_SDHI0I1:	intsrc37 { vector = <0x0e20>; };
+			SDHI0_SDHI0I2:	intsrc38 { vector = <0x0e40>; };
+			SDHI0_SDHI0I3:	intsrc39 { vector = <0x0e60>; };
+			SDHI1_SDHI1I0:	intsrc40 { vector = <0x0e80>; };
+			SDHI1_SDHI1I1:	intsrc41 { vector = <0x0ea0>; };
+			SDHI1_SDHI1I2:	intsrc42 { vector = <0x0ec0>; };
+			IRREM:	intsrc43 { vector = <0x0f60>; };
+			IRDA:	intsrc44 { vector = <0x0480>; };
+			TPU0:	intsrc45 { vector = <0x04a0>; };
+			TTI20:	intsrc46 { vector = <0x1100>; };
+			DDM:	intsrc47 { vector = <0x1140>; };
+			SDHI2_SDHI2I0:	intsrc48 { vector = <0x1200>; };
+			SDHI2_SDHI2I1:	intsrc49 { vector = <0x1220>; };
+			SDHI2_SDHI2I2:	intsrc50 { vector = <0x1240>; };
+			SDHI2_SDHI2I3:	intsrc51 { vector = <0x1260>; };
+			RWDT0:	intsrc52 { vector = <0x1280>; };
+			DMAC1_1_DEI0:	intsrc53 { vector = <0x2000>; };
+			DMAC1_1_DEI1:	intsrc54 { vector = <0x2020>; };
+			DMAC1_1_DEI2:	intsrc55 { vector = <0x2040>; };
+			DMAC1_1_DEI3:	intsrc56 { vector = <0x2060>; };
+			DMAC1_2_DEI4:	intsrc57 { vector = <0x2080>; };
+			DMAC1_2_DEI5:	intsrc58 { vector = <0x20a0>; };
+			DMAC1_2_DADERR:	intsrc59 { vector = <0x20c0>; };
+			DMAC2_1_DEI0:	intsrc60 { vector = <0x2100>; };
+			DMAC2_1_DEI1:	intsrc61 { vector = <0x2120>; };
+			DMAC2_1_DEI2:	intsrc62 { vector = <0x2140>; };
+			DMAC2_1_DEI3:	intsrc63 { vector = <0x2160>; };
+			DMAC2_2_DEI4:	intsrc64 { vector = <0x2180>; };
+			DMAC2_2_DEI5:	intsrc65 { vector = <0x21a0>; };
+			DMAC2_2_DADERR:	intsrc66 { vector = <0x21c0>; };
+			DMAC3_1_DEI0:	intsrc67 { vector = <0x2200>; };
+			DMAC3_1_DEI1:	intsrc68 { vector = <0x2220>; };
+			DMAC3_1_DEI2:	intsrc69 { vector = <0x2240>; };
+			DMAC3_1_DEI3:	intsrc70 { vector = <0x2260>; };
+			DMAC3_2_DEI4:	intsrc71 { vector = <0x2280>; };
+			DMAC3_2_DEI5:	intsrc72 { vector = <0x22a0>; };
+			DMAC3_2_DADERR:	intsrc73 { vector = <0x22c0>; };
+			SHWYSTAT_RT:	intsrc74 { vector = <0x1300>; };
+			SHWYSTAT_HS:	intsrc75 { vector = <0x1320>; };
+			SHWYSTAT_COM:	intsrc76 { vector = <0x1340>; };
+			HDMI:	intsrc77 { vector = <0x17e0>; };
+			SPU2_SPU0:	intsrc78 { vector = <0x1800>; };
+			SPU2_SPU1:	intsrc79 { vector = <0x1820>; };
+			FSI:	intsrc80 { vector = <0x1840>; };
+			FMSI:	intsrc81 { vector = <0x1860>; };
+			MIPI_HSI:	intsrc82 { vector = <0x18e0>; };
+			IPMMU_IPMMUD:	intsrc83 { vector = <0x1920>; };
+			CEC_1:	intsrc84 { vector = <0x1940>; };
+			CEC_2:	intsrc85 { vector = <0x1960>; };
+			AP_ARM_CTIIRQ:	intsrc86 { vector = <0x1980>; };
+			AP_ARM_DMAEXTERRIRQ:	intsrc87 { vector = <0x19a0>; };
+			AP_ARM_DMAIRQ:	intsrc88 { vector = <0x19c0>; };
+			AP_ARM_DMASIRQ:	intsrc89 { vector = <0x19e0>; };
+			MFIS2:	intsrc90 { vector = <0x1a00>; };
+			CPORTR2S:	intsrc91 { vector = <0x1a20>; };
+			CMT14:	intsrc92 { vector = <0x1a40>; };
+			CMT15:	intsrc93 { vector = <0x1a60>; };
+			MMC_MMC_ERR:	intsrc94 { vector = <0x1ac0>; };
+			MMC_MMC_NOR:	intsrc95 { vector = <0x1ae0>; };
+			IIC4_ALI4:		intsrc96 { vector = <0x1b00>; };
+			IIC4_TACKI4:	intsrc97 { vector = <0x1b20>; };
+			IIC4_WAITI4:	intsrc98 { vector = <0x1b40>; };
+			IIC4_DTEI4:		intsrc99 { vector = <0x1b60>; };
+			IIC3_ALI3:		intsrc100 { vector = <0x1b80>; };
+			IIC3_TACKI3:	intsrc101 { vector = <0x1ba0>; };
+			IIC3_WAITI3:	intsrc102 { vector = <0x1bc0>; };
+			IIC3_DTEI3:		intsrc103 { vector = <0x1be0>; };
+			USB0_USB0I1:	intsrc104 { vector = <0x1c80>; };
+			USB0_USB0I0:	intsrc105 { vector = <0x1ca0>; };
+			USB1_USB1I1:	intsrc106 { vector = <0x1cc0>; };
+			USB1_USB1I0:	intsrc107 { vector = <0x1ce0>; };
+			USBHSDMAC1_USHDMI:	intsrc108 { vector = <0x1d00>; };
+
+			intc_groups {
+				DMAC1_1: intc_group0 {
+					group = <&DMAC1_1_DEI0 &DMAC1_1_DEI1
+							&DMAC1_1_DEI2 &DMAC1_1_DEI3>;
+				};
+
+				DMAC1_2: intc_group1 {
+					group = <&DMAC1_2_DEI4 &DMAC1_2_DEI5
+							&DMAC1_2_DADERR>;
+				};
+
+				DMAC2_1: intc_group2 {
+					group = <&DMAC2_1_DEI0 &DMAC2_1_DEI1
+							&DMAC2_1_DEI2 &DMAC2_1_DEI3>;
+				};
+
+				DMAC2_2: intc_group3 {
+					group = <&DMAC2_2_DEI4 &DMAC2_2_DEI5
+							&DMAC2_2_DADERR>;
+				};
+
+				DMAC3_1: intc_group4 {
+					group = <&DMAC3_1_DEI0 &DMAC3_1_DEI1
+							&DMAC3_1_DEI2 &DMAC3_1_DEI3>;
+				};
+
+				DMAC3_2: intc_group5 {
+					group = <&DMAC3_2_DEI4 &DMAC3_2_DEI5
+							&DMAC3_2_DADERR>;
+				};
+
+				AP_ARM1: intc_group6 {
+					group = <&AP_ARM_IRQPMU &AP_ARM_COMMTX
+							&AP_ARM_COMMRX>;
+				};
+
+				AP_ARM2: intc_group7 {
+					group = <&AP_ARM_CTIIRQ &AP_ARM_DMAEXTERRIRQ
+							&AP_ARM_DMAIRQ &AP_ARM_DMASIRQ>;
+				};
+
+				SPU2: intc_group8 {
+					group = <&SPU2_SPU0 &SPU2_SPU1>;
+				};
+
+				FLCTL: intc_group9 {
+					group = <&FLCTL_FLSTEI &FLCTL_FLTENDI
+							&FLCTL_FLTREQ0I &FLCTL_FLTREQ1I>;
+				};
+
+				IIC1: intc_group10 {
+					group = <&IIC1_ALI1 &IIC1_TACKI1 &IIC1_WAITI1
+							&IIC1_DTEI1>;
+				};
+
+				SDHI0: intc_group11 {
+					group = <&SDHI0_SDHI0I0 &SDHI0_SDHI0I1
+							&SDHI0_SDHI0I2 &SDHI0_SDHI0I3>;
+				};
+
+				SDHI1: intc_group12 {
+					group = <&SDHI1_SDHI1I0 &SDHI1_SDHI1I1
+							&SDHI1_SDHI1I2>;
+				};
+
+				SDHI2: intc_group13 {
+					group = <&SDHI2_SDHI2I0 &SDHI2_SDHI2I1
+							&SDHI2_SDHI2I2 &SDHI2_SDHI2I3>;
+				};
+
+				SHWYSTAT: intc_group14 {
+					group = <&SHWYSTAT_RT &SHWYSTAT_HS &SHWYSTAT_COM>;
+				};
+			};
+
+			intc_vectors {
+				vector_table = <&DIRC &CRYPT_STD
+						&IIC1_ALI1 &IIC1_TACKI1 &IIC1_WAITI1 &IIC1_DTEI1
+						&AP_ARM_IRQPMU &AP_ARM_COMMTX &AP_ARM_COMMRX
+						&MFI_MFIM &MFI_MFIS &BBIF1 &BBIF2
+						&USBHSDMAC0_USHDMI
+						&_3DG_SGX540
+						&CMT1_CMT10 &CMT1_CMT11 &CMT1_CMT12
+						&CMT1_CMT13 &CMT2 &CMT3
+						&KEYSC_KEY
+						&SCIFA0 &SCIFA1 &SCIFA2 &SCIFA3
+						&MSIOF2 &MSIOF1
+						&SCIFA4 &SCIFA5 &SCIFB
+						&FLCTL_FLSTEI &FLCTL_FLTENDI &FLCTL_FLTREQ0I
+						&FLCTL_FLTREQ1I
+						&SDHI0_SDHI0I0 &SDHI0_SDHI0I1 &SDHI0_SDHI0I2
+						&SDHI0_SDHI0I3
+						&SDHI1_SDHI1I0 &SDHI1_SDHI1I1 &SDHI1_SDHI1I2
+						&IRREM &IRDA &TPU0 &TTI20 &DDM
+						&SDHI2_SDHI2I0 &SDHI2_SDHI2I1 &SDHI2_SDHI2I2
+						&SDHI2_SDHI2I3
+						&RWDT0
+						&DMAC1_1_DEI0 &DMAC1_1_DEI1 &DMAC1_1_DEI2
+						&DMAC1_1_DEI3
+						&DMAC1_2_DEI4 &DMAC1_2_DEI5 &DMAC1_2_DADERR
+						&DMAC2_1_DEI0 &DMAC2_1_DEI1 &DMAC2_1_DEI2
+						&DMAC2_1_DEI3
+						&DMAC2_2_DEI4 &DMAC2_2_DEI5 &DMAC2_2_DADERR
+						&DMAC3_1_DEI0 &DMAC3_1_DEI1 &DMAC3_1_DEI2
+						&DMAC3_1_DEI3
+						&DMAC3_2_DEI4 &DMAC3_2_DEI5 &DMAC3_2_DADERR
+						&SHWYSTAT_RT &SHWYSTAT_HS &SHWYSTAT_COM
+						&HDMI
+						&SPU2_SPU0 &SPU2_SPU1
+						&FSI &FMSI
+						&MIPI_HSI
+						&IPMMU_IPMMUD
+						&CEC_1 &CEC_2
+						&AP_ARM_CTIIRQ &AP_ARM_DMAEXTERRIRQ &AP_ARM_DMAIRQ
+						&AP_ARM_DMASIRQ
+						&MFIS2
+						&CPORTR2S
+						&CMT14 &CMT15
+						&MMC_MMC_ERR &MMC_MMC_NOR
+						&IIC4_ALI4 &IIC4_TACKI4 &IIC4_WAITI4 &IIC4_DTEI4
+						&IIC3_ALI3 &IIC3_TACKI3 &IIC3_WAITI3 &IIC3_DTEI3
+						&USB0_USB0I1 &USB0_USB0I0
+						&USB1_USB1I1 &USB1_USB1I0
+						&USBHSDMAC1_USHDMI>;
+			};
+
+			intc_mask_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_mask0 {
+					reg = <0xe6940080 1>, <0xe69400c0 1>;
+					reginfo = <&DMAC2_1_DEI3 &DMAC2_1_DEI2 &DMAC2_1_DEI1
+							&DMAC2_1_DEI0 &AP_ARM_IRQPMU 0 &AP_ARM_COMMTX
+							&AP_ARM_COMMRX>;
+				};
+
+				intc_mask1 {
+					reg = <0xe6940084 1>, <0xe69400c4 1>;
+					reginfo = <0 &CRYPT_STD &DIRC 0 &DMAC1_1_DEI3 &DMAC1_1_DEI2
+							&DMAC1_1_DEI1 &DMAC1_1_DEI0>;
+				};
+
+				intc_mask2 {
+					reg = <0xe6940088 1>, <0xe69400c8 1>;
+					reginfo = <0 0 0 0 &BBIF1 &BBIF2 &MFI_MFIS &MFI_MFIM>;
+				};
+
+				intc_mask3 {
+					reg = <0xe694008c 1>, <0xe69400cc 1>;
+					reginfo = <&DMAC3_1_DEI3 &DMAC3_1_DEI2 &DMAC3_1_DEI1
+							&DMAC3_1_DEI0 &DMAC3_2_DADERR &DMAC3_2_DEI5
+							&DMAC3_2_DEI4 &IRDA>;
+				};
+
+				intc_mask4 {
+					reg = <0xe6940090 1>, <0xe69400d0 1>;
+					reginfo = <&DDM>;
+				};
+
+				intc_mask5 {
+					reg = <0xe6940094 1>, <0xe69400d4 1>;
+					reginfo = <&KEYSC_KEY &DMAC1_2_DADERR &DMAC1_2_DEI5
+							&DMAC1_2_DEI4 &SCIFA3 &SCIFA2 &SCIFA1 &SCIFA0>;
+				};
+
+				intc_mask6 {
+					reg = <0xe6940098 1>, <0xe69400d8 1>;
+					reginfo = <&SCIFB &SCIFA5 &SCIFA4 &MSIOF1 0 0 &MSIOF2>;
+				};
+
+				intc_mask7 {
+					reg = <0xe694009c 1>, <0xe69400dc 1>;
+					reginfo = <&SDHI0_SDHI0I3 &SDHI0_SDHI0I2 &SDHI0_SDHI0I1
+							&SDHI0_SDHI0I0 &FLCTL_FLTREQ1I &FLCTL_FLTREQ0I
+							&FLCTL_FLTENDI &FLCTL_FLSTEI>;
+				};
+
+				intc_mask8 {
+					reg = <0xe69400a0 1>, <0xe69400e0 1>;
+					reginfo = <0 &SDHI1_SDHI1I2 &SDHI1_SDHI1I1 &SDHI1_SDHI1I0
+							&TTI20 &USBHSDMAC0_USHDMI>;
+				};
+
+				intc_mask9 {
+					reg = <0xe69400a4 1>, <0xe69400e4 1>;
+					reginfo = <&CMT1_CMT13 &CMT1_CMT12 &CMT1_CMT11 &CMT1_CMT10
+							&CMT2 0 0 &_3DG_SGX540>;
+				};
+
+				intc_mask10 {
+					reg = <0xe69400a8 1>, <0xe69400e8 1>;
+					reginfo = <0 &DMAC2_2_DADERR &DMAC2_2_DEI5 &DMAC2_2_DEI4>;
+				};
+
+				intc_mask11 {
+					reg = <0xe69400ac 1>, <0xe69400ec 1>;
+					reginfo = <&IIC1_DTEI1 &IIC1_WAITI1 &IIC1_TACKI1
+							&IIC1_ALI1 0 0 &IRREM>;
+				};
+
+				intc_mask12 {
+					reg = <0xe69400b0 1>, <0xe69400f0 1>;
+					reginfo = <0 0 &TPU0>;
+				};
+
+				intc_mask13 {
+					reg = <0xe69400b4 1>, <0xe69400f4 1>;
+					reginfo = <&SDHI2_SDHI2I3 &SDHI2_SDHI2I2 &SDHI2_SDHI2I1
+							&SDHI2_SDHI2I0 0 &CMT3 0 &RWDT0>;
+				};
+
+				intc_mask14 {
+					reg = <0xe6950080 1>, <0xe69500c0 1>;
+					reginfo = <&SHWYSTAT_RT &SHWYSTAT_HS &SHWYSTAT_COM>;
+				};
+
+				intc_mask15 {
+					reg = <0xe6950090 1>, <0xe69500d0 1>;
+					reginfo = <0 0 0 0 0 0 0 &HDMI>;
+				};
+
+				intc_mask16 {
+					reg = <0xe6950094 1>, <0xe69500d4 1>;
+					reginfo = <&SPU2_SPU0 &SPU2_SPU1 &FSI &FMSI
+							0 0 0 &MIPI_HSI>;
+				};
+
+				intc_mask17 {
+					reg = <0xe6950098 1>, <0xe69500d8 1>;
+					reginfo = <0 &IPMMU_IPMMUD &CEC_1 &CEC_2
+							&AP_ARM_CTIIRQ &AP_ARM_DMAEXTERRIRQ
+							&AP_ARM_DMAIRQ &AP_ARM_DMASIRQ>;
+				};
+
+				intc_mask18 {
+					reg = <0xe695009c 1>, <0xe69500dc 1>;
+					reginfo = <&MFIS2 &CPORTR2S &CMT14 &CMT15
+							0 0 &MMC_MMC_ERR &MMC_MMC_NOR>;
+				};
+
+				intc_mask19 {
+					reg = <0xe69500a0 1>, <0xe69500e0 1>;
+					reginfo = <&IIC4_ALI4 &IIC4_TACKI4 &IIC4_WAITI4
+							&IIC4_DTEI4 &IIC3_ALI3 &IIC3_TACKI3
+							&IIC3_WAITI3 &IIC3_DTEI3>;
+				};
+
+				intc_mask20 {
+					reg = <0xe69500a4 1>, <0xe69500e4 1>;
+					reginfo = <0 0 0 0 &USB0_USB0I1 &USB0_USB0I0
+							&USB1_USB1I1 &USB1_USB1I0>;
+				};
+
+				intc_mask21 {
+					reg = <0xe69500a8 1>, <0xe69500e8 1>;
+					reginfo = <&USBHSDMAC1_USHDMI>;
+				};
+			};
+
+			intc_prio_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_prio0 {
+					reg = <0xe6940000 2>;
+					field-width = <4>;
+					reginfo = <&DMAC3_1 &DMAC3_2 &CMT2>;
+				};
+
+				intc_prio1 {
+					reg = <0xe6940004 2>;
+					field-width = <4>;
+					reginfo = <&IRDA 0 &BBIF1 &BBIF2>;
+				};
+
+				intc_prio2 {
+					reg = <0xe6940008 2>;
+					field-width = <4>;
+					reginfo = <0 &CRYPT_STD &CMT1_CMT11 &AP_ARM1>;
+				};
+
+				intc_prio3 {
+					reg = <0xe694000c 2>;
+					field-width = <4>;
+					reginfo = <0 0 &CMT1_CMT12>;
+				};
+
+				intc_prio4 {
+					reg = <0xe6940010 2>;
+					field-width = <4>;
+					reginfo = <&DMAC1_1 &MFI_MFIS &MFI_MFIM>;
+				};
+
+				intc_prio5 {
+					reg = <0xe6940014 2>;
+					field-width = <4>;
+					reginfo = <&KEYSC_KEY &DMAC1_2 &_3DG_SGX540 &CMT1_CMT10>;
+				};
+
+				intc_prio6 {
+					reg = <0xe6940018 2>;
+					field-width = <4>;
+					reginfo = <&SCIFA0 &SCIFA1 &SCIFA2 &SCIFA3>;
+				};
+
+				intc_prio7 {
+					reg = <0xe694001c 2>;
+					field-width = <4>;
+					reginfo = <&MSIOF2 &USBHSDMAC0_USHDMI &FLCTL &SDHI0>;
+				};
+
+				intc_prio8 {
+					reg = <0xe6940020 2>;
+					field-width = <4>;
+					reginfo = <&MSIOF1 &SCIFA4 0  &IIC1>;
+				};
+
+				intc_prio9 {
+					reg = <0xe6940024 2>;
+					field-width = <4>;
+					reginfo = <&DMAC2_1 &DMAC2_2 0  &TTI20>;
+				};
+
+				intc_prio10 {
+					reg = <0xe6940028 2>;
+					field-width = <4>;
+					reginfo = <0 &CMT1_CMT13 &IRREM &SDHI1>;
+				};
+
+				intc_prio11 {
+					reg = <0xe694002c 2>;
+					field-width = <4>;
+					reginfo = <&TPU0>;
+				};
+
+				intc_prio12 {
+					reg = <0xe6940030 2>;
+					field-width = <4>;
+					reginfo = <0 &CMT3 0 &RWDT0>;
+				};
+
+				intc_prio13 {
+					reg = <0xe6940034 2>;
+					field-width = <4>;
+					reginfo = <&SCIFB &SCIFA5 0 &DDM>;
+				};
+
+				intc_prio14 {
+					reg = <0xe6940038 2>;
+					field-width = <4>;
+					reginfo = <0 0 &DIRC &SDHI2>;
+				};
+
+				intc_prio15 {
+					reg = <0xe6950000 2>;
+					field-width = <4>;
+					reginfo = <&SHWYSTAT>;
+				};
+
+				intc_prio16 {
+					reg = <0xe6950024 2>;
+					field-width = <4>;
+					reginfo = <0 0 0 &HDMI>;
+				};
+
+				intc_prio17 {
+					reg = <0xe6950028 2>;
+					field-width = <4>;
+					reginfo = <&SPU2 0 &FSI &FMSI>;
+				};
+
+				intc_prio18 {
+					reg = <0xe695002c 2>;
+					field-width = <4>;
+					reginfo = <0 0 0 &MIPI_HSI>;
+				};
+
+				intc_prio19 {
+					reg = <0xe6950030 2>;
+					field-width = <4>;
+					reginfo = <&IPMMU_IPMMUD 0 &CEC_1 &CEC_2>;
+				};
+
+				intc_prio20 {
+					reg = <0xe6950034 2>;
+					field-width = <4>;
+					reginfo = <&AP_ARM2>;
+				};
+
+				intc_prio21 {
+					reg = <0xe6950038 2>;
+					field-width = <4>;
+					reginfo = <&MFIS2 &CPORTR2S &CMT14 &CMT15>;
+				};
+
+				intc_prio22 {
+					reg = <0xe695003c 2>;
+					field-width = <4>;
+					reginfo = <0 0 &MMC_MMC_ERR &MMC_MMC_NOR>;
+				};
+
+				intc_prio23 {
+					reg = <0xe6950040 2>;
+					field-width = <4>;
+					reginfo = <&IIC4_ALI4 &IIC4_TACKI4 &IIC4_WAITI4 &IIC4_DTEI4>;
+				};
+
+				intc_prio24 {
+					reg = <0xe6950044 2>;
+					field-width = <4>;
+					reginfo = <&IIC3_ALI3 &IIC3_TACKI3 &IIC3_WAITI3 &IIC3_DTEI3>;
+				};
+
+				intc_prio25 {
+					reg = <0xe6950048 2>;
+					field-width = <4>;
+					reginfo = <>;
+				};
+
+				intc_prio26 {
+					reg = <0xe695004c 2>;
+					field-width = <4>;
+					reginfo = <&USB0_USB0I1 &USB0_USB0I0 &USB1_USB1I1 &USB1_USB1I0>;
+				};
+
+				intc_prio27 {
+					reg = <0xe6950050 2>;
+					field-width = <4>;
+					reginfo = <&USBHSDMAC1_USHDMI>;
+				};
+
+			};
+		};
+
+		intca_irq_pins_lo: interrupt-controller at 1 {
+			compatible = "renesas,sh-intc";
+			interrupt-controller;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#interrupt-cells = <1>;
+			ranges;
+
+			reg = <0xe6900000 0x70>;
+
+			IRQ0:	intsrc1 { vector = <0x200>; };
+			IRQ1:	intsrc2 { vector = <0x220>; };
+			IRQ2:	intsrc3 { vector = <0x240>; };
+			IRQ3:	intsrc4 { vector = <0x260>; };
+			IRQ4:	intsrc5 { vector = <0x280>; };
+			IRQ5:	intsrc6 { vector = <0x2a0>; };
+			IRQ6:	intsrc7 { vector = <0x2c0>; };
+			IRQ7:	intsrc8 { vector = <0x2e0>; };
+			IRQ8:	intsrc9 { vector = <0x300>; };
+			IRQ9:	intsrc10 { vector = <0x320>; };
+			IRQ10:	intsrc11 { vector = <0x340>; };
+			IRQ11:	intsrc12 { vector = <0x360>; };
+			IRQ12:	intsrc13 { vector = <0x380>; };
+			IRQ13:	intsrc14 { vector = <0x3a0>; };
+			IRQ14:	intsrc15 { vector = <0x3c0>; };
+			IRQ15:	intsrc16 { vector = <0x3e0>; };
+
+			intc_vectors {
+				vector_table = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 &IRQ5
+								&IRQ6 &IRQ7 &IRQ8 &IRQ9 &IRQ10
+								&IRQ11 &IRQ12 &IRQ13 &IRQ14 &IRQ15>;
+			};
+
+			intc_mask_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_mask0 {
+					reg = <0xe6900040 1>, <0xe6900060 1>;
+					reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4
+							&IRQ5 &IRQ6 &IRQ7>;
+				};
+
+				intc_mask1 {
+					reg = <0xe6900044 1>, <0xe6900064 1>;
+					reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11
+							&IRQ12 &IRQ13 &IRQ14 &IRQ15>;
+				};
+			};
+
+			intc_prio_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_prio0 {
+					reg = <0xe6900010 4>;
+					field-width = <4>;
+					reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4
+							&IRQ5 &IRQ6 &IRQ7>;
+				};
+
+				intc_prio1 {
+					reg = <0xe6900014 4>;
+					field-width = <4>;
+					reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11
+							&IRQ12 &IRQ13 &IRQ14 &IRQ15>;
+				};
+			};
+
+			intc_sense_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_sense0 {
+					reg = <0xe6900000 4>;
+					field-width = <4>;
+					reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4
+							&IRQ5 &IRQ6 &IRQ7>;
+				};
+
+				intc_sense1 {
+					reg = <0xe6900004 4>;
+					field-width = <4>;
+					reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11
+							&IRQ12 &IRQ13 &IRQ14 &IRQ15>;
+				};
+			};
+
+			intc_ack_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_ack0 {
+					reg = <0xe6900020 1>;
+					reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4
+							&IRQ5 &IRQ6 &IRQ7>;
+				};
+
+				intc_ack1 {
+					reg = <0xe6900024 1>;
+					reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11
+							&IRQ12 &IRQ13 &IRQ14 &IRQ15>;
+				};
+			};
+		};
+
+		intca_irq_pins_hi: interrupt-controller at 2 {
+			compatible = "renesas,sh-intc";
+			interrupt-controller;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#interrupt-cells = <1>;
+			ranges;
+
+			reg = <0xe6900008 0x70>;
+
+			IRQ16:	intsrc1 { vector = <0x3200>; };
+			IRQ17:	intsrc2 { vector = <0x3220>; };
+			IRQ18:	intsrc3 { vector = <0x3240>; };
+			IRQ19:	intsrc4 { vector = <0x3260>; };
+			IRQ20:	intsrc5 { vector = <0x3280>; };
+			IRQ21:	intsrc6 { vector = <0x32a0>; };
+			IRQ22:	intsrc7 { vector = <0x32c0>; };
+			IRQ23:	intsrc8 { vector = <0x32e0>; };
+			IRQ24:	intsrc9 { vector = <0x3300>; };
+			IRQ25:	intsrc10 { vector = <0x3320>; };
+			IRQ26:	intsrc11 { vector = <0x3340>; };
+			IRQ27:	intsrc12 { vector = <0x3360>; };
+			IRQ28:	intsrc13 { vector = <0x3380>; };
+			IRQ29:	intsrc14 { vector = <0x33a0>; };
+			IRQ30:	intsrc15 { vector = <0x33c0>; };
+			IRQ31:	intsrc16 { vector = <0x33e0>; };
+
+			intc_vectors {
+				vector_table = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 &IRQ20 &IRQ21
+								&IRQ22 &IRQ23 &IRQ24 &IRQ25 &IRQ26
+								&IRQ27 &IRQ28 &IRQ29 &IRQ30 &IRQ31>;
+			};
+
+			intc_mask_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_mask0 {
+					reg = <0xe6900048 1>, <0xe6900068 1>;
+					reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 &IRQ20
+							&IRQ21 &IRQ22 &IRQ23>;
+				};
+
+				intc_mask1 {
+					reg = <0xe690004c 1>, <0xe690006c 1>;
+					reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27
+							&IRQ28 &IRQ29 &IRQ30 &IRQ31>;
+				};
+			};
+
+			intc_prio_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_prio0 {
+					reg = <0xe6900018 4>;
+					field-width = <4>;
+					reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 &IRQ20
+							&IRQ21 &IRQ22 &IRQ23>;
+				};
+
+				intc_prio1 {
+					reg = <0xe690001c 4>;
+					field-width = <4>;
+					reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27
+							&IRQ28 &IRQ29 &IRQ30 &IRQ31>;
+				};
+			};
+
+			intc_sense_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_sense0 {
+					reg = <0xe6900008 4>;
+					field-width = <4>;
+					reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 &IRQ20
+							&IRQ21 &IRQ22 &IRQ23>;
+				};
+
+				intc_sense1 {
+					reg = <0xe690000c 4>;
+					field-width = <4>;
+					reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27
+							&IRQ28 &IRQ29 &IRQ30 &IRQ31>;
+				};
+			};
+
+			intc_ack_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_ack0 {
+					reg = <0xe6900028 1>;
+					reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19 &IRQ20
+							&IRQ21 &IRQ22 &IRQ23>;
+				};
+
+				intc_ack1 {
+					reg = <0xe690002c 1>;
+					reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27
+							&IRQ28 &IRQ29 &IRQ30 &IRQ31>;
+				};
+			};
+		};
+	};
 };

index 2418278..9efc4f3 100644
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for the r8a7740 SoC
+ * Device Tree Source for Renesas r8a7740
  *
  * Copyright (C) 2012 Renesas Solutions Corp.
  *

@@ -25,4 +25,745 @@
 		      <0xe605800c 0x20>;
 		#gpio-cells = <2>;
 	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		intca: interrupt-controller at 0 {
+			compatible = "renesas,sh-intc";
+			interrupt-controller;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#interrupt-cells = <1>;
+			ranges;
+
+			reg = <0xe6940000 0x200>, <0xe6950000 0x200>;
+
+			DIRC: intsrc1 { vector = <0x0560>; };
+			ATAPI: intsrc2 { vector = <0x05E0>; };
+			IIC1_ALI: intsrc3 { vector = <0x0780>; };
+			IIC1_TACKI: intsrc4 { vector = <0x07A0>; };
+			IIC1_WAITI: intsrc5 { vector = <0x07C0>; };
+			IIC1_DTEI: intsrc6 { vector = <0x07E0>; };
+			AP_ARM_COMMTX: intsrc7 { vector = <0x0840>; };
+			AP_ARM_COMMRX: intsrc8 { vector = <0x0860>; };
+			MFI: intsrc9 { vector = <0x0900>; };
+			MFIS: intsrc10 { vector = <0x0920>; };
+			BBIF1: intsrc11 { vector = <0x0940>; };
+			BBIF2: intsrc12 { vector = <0x0960>; };
+			USBHSDMAC: intsrc13 { vector = <0x0A00>; };
+			USBF_OUL_SOF: intsrc14 { vector = <0x0A20>; };
+			USBF_IXL_INT: intsrc15 { vector = <0x0A40>; };
+			SGX540: intsrc16 { vector = <0x0A60>; };
+			CMT1_0: intsrc17 { vector = <0x0B00>; };
+			CMT1_1: intsrc18 { vector = <0x0B20>; };
+			CMT1_2: intsrc19 { vector = <0x0B40>; };
+			CMT1_3: intsrc20 { vector = <0x0B60>; };
+			CMT2: intsrc21 { vector = <0x0B80>; };
+			CMT3: intsrc22 { vector = <0x0BA0>; };
+			KEYSC: intsrc23 { vector = <0x0BE0>; };
+			SCIFA0: intsrc24 { vector = <0x0C00>; };
+			SCIFA1: intsrc25 { vector = <0x0C20>; };
+			SCIFA2: intsrc26 { vector = <0x0C40>; };
+			SCIFA3: intsrc27 { vector = <0x0C60>; };
+			MSIOF2: intsrc28 { vector = <0x0C80>; };
+			MSIOF1: intsrc29 { vector = <0x0D00>; };
+			SCIFA4: intsrc30 { vector = <0x0D20>; };
+			SCIFA5: intsrc31 { vector = <0x0D40>; };
+			SCIFB: intsrc32 { vector = <0x0D60>; };
+			FLCTL_FLSTEI: intsrc33 { vector = <0x0D80>; };
+			FLCTL_FLTENDI: intsrc34 { vector = <0x0DA0>; };
+			FLCTL_FLTREQ0I: intsrc35 { vector = <0x0DC0>; };
+			FLCTL_FLTREQ1I: intsrc36 { vector = <0x0DE0>; };
+			SDHI0_0: intsrc37 { vector = <0x0E00>; };
+			SDHI0_1: intsrc38 { vector = <0x0E20>; };
+			SDHI0_2: intsrc39 { vector = <0x0E40>; };
+			SDHI0_3: intsrc40 { vector = <0x0E60>; };
+			SDHI1_0: intsrc41 { vector = <0x0E80>; };
+			SDHI1_1: intsrc42 { vector = <0x0EA0>; };
+			SDHI1_2: intsrc43 { vector = <0x0EC0>; };
+			SDHI1_3: intsrc44 { vector = <0x0EE0>; };
+			AP_ARM_L2CINT: intsrc45 { vector = <0x0FA0>; };
+			IRDA: intsrc46 { vector = <0x0480>; };
+			TPU0: intsrc47 { vector = <0x04A0>; };
+			SCIFA6: intsrc48 { vector = <0x04C0>; };
+			SCIFA7: intsrc49 { vector = <0x04E0>; };
+			GETHER: intsrc50 { vector = <0x0500>; };
+			ICBS0: intsrc51 { vector = <0x0540>; };
+			DDM: intsrc52 { vector = <0x1140>; };
+			SDHI2_0: intsrc53 { vector = <0x1200>; };
+			SDHI2_1: intsrc54 { vector = <0x1220>; };
+			SDHI2_2: intsrc55 { vector = <0x1240>; };
+			SDHI2_3: intsrc56 { vector = <0x1260>; };
+			RWDT0: intsrc57 { vector = <0x1280>; };
+			DMAC1_1_DEI0: intsrc58 { vector = <0x2000>; };
+			DMAC1_1_DEI1: intsrc59 { vector = <0x2020>; };
+			DMAC1_1_DEI2: intsrc60 { vector = <0x2040>; };
+			DMAC1_1_DEI3: intsrc61 { vector = <0x2060>; };
+			DMAC1_2_DEI4: intsrc62 { vector = <0x2080>; };
+			DMAC1_2_DEI5: intsrc63 { vector = <0x20A0>; };
+			DMAC1_2_DADERR: intsrc64 { vector = <0x20C0>; };
+			DMAC2_1_DEI0: intsrc65 { vector = <0x2100>; };
+			DMAC2_1_DEI1: intsrc66 { vector = <0x2120>; };
+			DMAC2_1_DEI2: intsrc67 { vector = <0x2140>; };
+			DMAC2_1_DEI3: intsrc68 { vector = <0x2160>; };
+			DMAC2_2_DEI4: intsrc69 { vector = <0x2180>; };
+			DMAC2_2_DEI5: intsrc70 { vector = <0x21A0>; };
+			DMAC2_2_DADERR: intsrc71 { vector = <0x21C0>; };
+			DMAC3_1_DEI0: intsrc72 { vector = <0x2200>; };
+			DMAC3_1_DEI1: intsrc73 { vector = <0x2220>; };
+			DMAC3_1_DEI2: intsrc74 { vector = <0x2240>; };
+			DMAC3_1_DEI3: intsrc75 { vector = <0x2260>; };
+			DMAC3_2_DEI4: intsrc76 { vector = <0x2280>; };
+			DMAC3_2_DEI5: intsrc77 { vector = <0x22A0>; };
+			DMAC3_2_DADERR: intsrc78 { vector = <0x22C0>; };
+			SHWYSTAT_RT: intsrc79 { vector = <0x1300>; };
+			SHWYSTAT_HS: intsrc80 { vector = <0x1320>; };
+			SHWYSTAT_COM: intsrc81 { vector = <0x1340>; };
+			HDMI: intsrc82 { vector = <0x1700>; };
+			USBH_INT: intsrc83 { vector = <0x1540>; };
+			USBH_OHCI: intsrc84 { vector = <0x1560>; };
+			USBH_EHCI: intsrc85 { vector = <0x1580>; };
+			USBH_PME: intsrc86 { vector = <0x15A0>; };
+			USBH_BIND: intsrc87 { vector = <0x15C0>; };
+			RSPI_OVRF: intsrc88 { vector = <0x1780>; };
+			RSPI_SPTEF: intsrc89 { vector = <0x17A0>; };
+			RSPI_SPRF: intsrc90 { vector = <0x17C0>; };
+			SPU2_0: intsrc91 { vector = <0x1800>; };
+			SPU2_1: intsrc92 { vector = <0x1820>; };
+			FSI: intsrc93 { vector = <0x1840>; };
+			FMSI: intsrc94 { vector = <0x1860>; };
+			HDMI_SSS: intsrc95 { vector = <0x18A0>; };
+			HDMI_KEY: intsrc96 { vector = <0x18C0>; };
+			IPMMU: intsrc97 { vector = <0x1920>; };
+			AP_ARM_CTIIRQ: intsrc98 { vector = <0x1980>; };
+			AP_ARM_PMURQ: intsrc99 { vector = <0x19A0>; };
+			MFIS2: intsrc100 { vector = <0x1A00>; };
+			CPORTR2S: intsrc101 { vector = <0x1A20>; };
+			CMT14: intsrc102 { vector = <0x1A40>; };
+			CMT15: intsrc103 { vector = <0x1A60>; };
+			MMCIF_0: intsrc104 { vector = <0x1AA0>; };
+			MMCIF_1: intsrc105 { vector = <0x1AC0>; };
+			MMCIF_2: intsrc106 { vector = <0x1AE0>; };
+			SIM_ERI: intsrc107 { vector = <0x1C00>; };
+			SIM_RXI: intsrc108 { vector = <0x1C20>; };
+			SIM_TXI: intsrc109 { vector = <0x1C40>; };
+			SIM_TEI: intsrc110 { vector = <0x1C60>; };
+			STPRO_0: intsrc111 { vector = <0x1C80>; };
+			STPRO_1: intsrc112 { vector = <0x1CA0>; };
+			STPRO_2: intsrc113 { vector = <0x1CC0>; };
+			STPRO_3: intsrc114 { vector = <0x1CE0>; };
+			STPRO_4: intsrc115 { vector = <0x1D00>; };
+
+			intc_groups {
+				DMAC1_1: intc_group0 {
+					group = <&DMAC1_1_DEI0 &DMAC1_1_DEI1
+							&DMAC1_1_DEI2 &DMAC1_1_DEI3>;
+				};
+
+				DMAC1_2: intc_group1 {
+					group = <&DMAC1_2_DEI4 &DMAC1_2_DEI5
+							&DMAC1_2_DADERR>;
+				};
+
+				DMAC2_1: intc_group2 {
+					group = <&DMAC2_1_DEI0 &DMAC2_1_DEI1
+							&DMAC2_1_DEI2 &DMAC2_1_DEI3>;
+				};
+
+				DMAC2_2: intc_group3 {
+					group = <&DMAC2_2_DEI4 &DMAC2_2_DEI5
+							&DMAC2_2_DADERR>;
+				};
+
+				DMAC3_1: intc_group4 {
+					group = <&DMAC3_1_DEI0 &DMAC3_1_DEI1
+							&DMAC3_1_DEI2 &DMAC3_1_DEI3>;
+				};
+
+				DMAC3_2: intc_group5 {
+					group = <&DMAC3_2_DEI4 &DMAC3_2_DEI5
+							&DMAC3_2_DADERR>;
+				};
+
+				AP_ARM1: intc_group6 {
+					group = <&AP_ARM_COMMTX &AP_ARM_COMMRX>;
+				};
+
+				AP_ARM2: intc_group7 {
+					group = <&AP_ARM_CTIIRQ &AP_ARM_PMURQ>;
+				};
+
+				USBF: intc_group8 {
+					group = <&USBF_OUL_SOF &USBF_IXL_INT>;
+				};
+
+				SDHI0: intc_group9 {
+					group = <&SDHI0_0 &SDHI0_1 &SDHI0_2 &SDHI0_3>;
+				};
+
+				SDHI1: intc_group10 {
+					group = <&SDHI1_0 &SDHI1_1 &SDHI1_2 &SDHI1_3>;
+				};
+
+				SDHI2: intc_group11 {
+					group = <&SDHI2_0 &SDHI2_1 &SDHI2_2 &SDHI2_3>;
+				};
+
+				SHWYSTAT: intc_group12 {
+					group = <&SHWYSTAT_RT &SHWYSTAT_HS &SHWYSTAT_COM>;
+				};
+
+				USBH1: intc_group13 {
+					group = <&USBH_INT &USBH_OHCI>;
+				};
+
+				USBH2: intc_group14 {
+					group = <&USBH_EHCI &USBH_PME &USBH_BIND>;
+				};
+
+				RSPI: intc_group15 {
+					group = <&RSPI_OVRF &RSPI_SPTEF &RSPI_SPRF>;
+				};
+
+				SPU2: intc_group16 {
+					group = <&SPU2_0 &SPU2_1>;
+				};
+
+				FLCTL: intc_group17 {
+					group = <&FLCTL_FLSTEI &FLCTL_FLTENDI &FLCTL_FLTREQ0I
+							&FLCTL_FLTREQ1I>;
+				};
+
+				IIC1: intc_group18 {
+					group = <&IIC1_ALI &IIC1_TACKI &IIC1_WAITI &IIC1_DTEI>;
+				};
+			};
+
+			intc_vectors {
+				vector_table = <&DIRC &ATAPI &IIC1_ALI &IIC1_TACKI &IIC1_WAITI
+					&IIC1_DTEI &AP_ARM_COMMTX &AP_ARM_COMMRX &MFI &MFIS &BBIF1
+					&BBIF2 &USBHSDMAC &USBF_OUL_SOF &USBF_IXL_INT &SGX540 &CMT1_0
+					&CMT1_1 &CMT1_2 &CMT1_3 &CMT2 &CMT3 &KEYSC &SCIFA0 &SCIFA1
+					&SCIFA2 &SCIFA3 &MSIOF2 &MSIOF1 &SCIFA4 &SCIFA5 &SCIFB
+					&FLCTL_FLSTEI &FLCTL_FLTENDI &FLCTL_FLTREQ0I &FLCTL_FLTREQ1I
+					&SDHI0_0 &SDHI0_1 &SDHI0_2 &SDHI0_3
+					&SDHI1_0 &SDHI1_1 &SDHI1_2 &SDHI1_3
+					&AP_ARM_L2CINT &IRDA &TPU0 &SCIFA6 &SCIFA7
+					&GETHER &ICBS0 &DDM &SDHI2_0 &SDHI2_1 &SDHI2_2 &SDHI2_3
+					&RWDT0
+					&DMAC1_1_DEI0 &DMAC1_1_DEI1 &DMAC1_1_DEI2 &DMAC1_1_DEI3
+					&DMAC1_2_DEI4 &DMAC1_2_DEI5 &DMAC1_2_DADERR
+					&DMAC2_1_DEI0 &DMAC2_1_DEI1 &DMAC2_1_DEI2 &DMAC2_1_DEI3
+					&DMAC2_2_DEI4 &DMAC2_2_DEI5 &DMAC2_2_DADERR
+					&DMAC3_1_DEI0 &DMAC3_1_DEI1 &DMAC3_1_DEI2 &DMAC3_1_DEI3
+					&DMAC3_2_DEI4 &DMAC3_2_DEI5 &DMAC3_2_DADERR
+					&SHWYSTAT_RT &SHWYSTAT_HS &SHWYSTAT_COM
+					&USBH_INT &USBH_OHCI &USBH_EHCI &USBH_PME &USBH_BIND
+					&HDMI
+					&RSPI_OVRF &RSPI_SPTEF &RSPI_SPRF
+					&SPU2_0 &SPU2_1 &FSI &FMSI &HDMI_SSS &HDMI_KEY
+					&IPMMU &AP_ARM_CTIIRQ &AP_ARM_PMURQ &MFIS2
+					&CPORTR2S
+					&CMT14 &CMT15 &MMCIF_0 &MMCIF_1 &MMCIF_2
+					&SIM_ERI &SIM_RXI &SIM_TXI &SIM_TEI
+					&STPRO_0 &STPRO_1 &STPRO_2 &STPRO_3 &STPRO_4>;
+			};
+
+			intc_mask_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_mask0 {
+					reg = <0xe6940080 1>, <0xe69400c0 1>;
+					reginfo = <&DMAC2_1_DEI3 &DMAC2_1_DEI2 &DMAC2_1_DEI1
+						&DMAC2_1_DEI0 0 0 &AP_ARM_COMMTX &AP_ARM_COMMRX>;
+				};
+
+				intc_mask1 {
+					reg = <0xe6940084 1>, <0xe69400c4 1>;
+					reginfo = <&ATAPI 0 &DIRC 0 &DMAC1_1_DEI3 &DMAC1_1_DEI2
+						&DMAC1_1_DEI1 &DMAC1_1_DEI0>;
+				};
+
+				intc_mask2 {
+					reg = <0xe6940088 1>, <0xe69400c8 1>;
+					reginfo = <0 0 0 0 &BBIF1 &BBIF2 &MFIS &MFI>;
+				};
+
+				intc_mask3 {
+					reg = <0xe694008c 1>, <0xe69400cc 1>;
+					reginfo = <&DMAC3_1_DEI3 &DMAC3_1_DEI2 &DMAC3_1_DEI1
+						&DMAC3_1_DEI0 &DMAC3_2_DADERR &DMAC3_2_DEI5
+						&DMAC3_2_DEI4 &IRDA>;
+				};
+
+				intc_mask4 {
+					reg = <0xe6940090 1>, <0xe69400d0 1>;
+					reginfo = <&DDM>;
+				};
+
+				intc_mask5 {
+					reg = <0xe6940094 1>, <0xe69400d4 1>;
+					reginfo = <&KEYSC &DMAC1_2_DADERR &DMAC1_2_DEI5 &DMAC1_2_DEI4
+							&SCIFA3 &SCIFA2 &SCIFA1 &SCIFA0>;
+				};
+
+				intc_mask6 {
+					reg = <0xe6940098 1>, <0xe69400d8 1>;
+					reginfo = <&SCIFB &SCIFA5 &SCIFA4 &MSIOF1 0 0 &MSIOF2>;
+				};
+
+				intc_mask7 {
+					reg = <0xe694009c 1>, <0xe69400dc 1>;
+					reginfo = <&SDHI0_3 &SDHI0_2 &SDHI0_1 &SDHI0_0 &FLCTL_FLTREQ1I
+						&FLCTL_FLTREQ0I &FLCTL_FLTENDI &FLCTL_FLSTEI>;
+				};
+
+				intc_mask8 {
+					reg = <0xe69400a0 1>, <0xe69400e0 1>;
+					reginfo = <&SDHI1_3 &SDHI1_2 &SDHI1_1 &SDHI1_0 0
+						&USBHSDMAC 0 &AP_ARM_L2CINT>;
+				};
+
+				intc_mask9 {
+					reg = <0xe69400a4 1>, <0xe69400e4 1>;
+					reginfo = <&CMT1_3 &CMT1_2 &CMT1_1
+						&CMT1_0 &CMT2 &USBF_IXL_INT &USBF_OUL_SOF &SGX540>;
+				};
+
+				intc_mask10 {
+					reg = <0xe69400a8 1>, <0xe69400e8 1>;
+					reginfo = <0 &DMAC2_2_DADERR &DMAC2_2_DEI5 &DMAC2_2_DEI4>;
+				};
+
+				intc_mask11 {
+					reg = <0xe69400ac 1>, <0xe69400ec 1>;
+					reginfo = <&IIC1_DTEI &IIC1_WAITI
+						&IIC1_TACKI &IIC1_ALI &ICBS0>;
+				};
+
+				intc_mask12 {
+					reg = <0xe69400b0 1>, <0xe69400f0 1>;
+					reginfo = <0 0 &TPU0 &SCIFA6 &SCIFA7 &GETHER>;
+				};
+
+				intc_mask13 {
+					reg = <0xe69400b4 1>, <0xe69400f4 1>;
+					reginfo = <&SDHI2_3 &SDHI2_2 &SDHI2_1
+						&SDHI2_0 0 &CMT3 0 &RWDT0>;
+				};
+
+				intc_mask14 {
+					reg = <0xe6950080 1>, <0xe69500c0 1>;
+					reginfo = <&SHWYSTAT_RT &SHWYSTAT_HS
+						&SHWYSTAT_COM>;
+				};
+
+				intc_mask15 {
+					reg = <0xe6950088 1>, <0xe69500c8 1>;
+					reginfo = <0 0 &USBH_INT &USBH_OHCI
+						&USBH_EHCI &USBH_PME &USBH_BIND>;
+				};
+
+				intc_mask16 {
+					reg = <0xe6950090 1>, <0xe69500d0 1>;
+					reginfo = <&HDMI 0 0 0 &RSPI_OVRF
+						&RSPI_SPTEF &RSPI_SPRF>;
+				};
+
+				intc_mask17 {
+					reg = <0xe6950094 1>, <0xe69500d4 1>;
+					reginfo = <&SPU2_0 &SPU2_1 &FSI &FMSI 0
+						&HDMI_SSS &HDMI_KEY>;
+				};
+
+				intc_mask18 {
+					reg = <0xe6950098 1>, <0xe69500d8 1>;
+					reginfo = <0 &IPMMU 0 0 &AP_ARM_CTIIRQ
+						&AP_ARM_PMURQ>;
+				};
+
+				intc_mask19 {
+					reg = <0xe695009c 1>, <0xe69500dc 1>;
+					reginfo = <&MFIS2 &CPORTR2S &CMT14 &CMT15
+						0 &MMCIF_0 &MMCIF_1 &MMCIF_2>;
+				};
+
+				intc_mask20 {
+					reg = <0xe69500a4 1>, <0xe69500e4 1>;
+					reginfo = <&SIM_ERI &SIM_RXI &SIM_TXI
+						&SIM_TEI &STPRO_0 &STPRO_1 &STPRO_2 &STPRO_3>;
+				};
+
+				intc_mask21 {
+					reg = <0xe69500a8 1>, <0xe69500e8 1>;
+					reginfo = <&STPRO_4>;
+				};
+			};
+
+			intc_prio_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_prio0 {
+					reg = <0xe6940000 2>;
+					field-width = <4>;
+					reginfo = <&DMAC3_1 &DMAC3_2 &CMT2 &ICBS0>;
+				};
+
+				intc_prio1 {
+					reg = <0xe6940004 2>;
+					field-width = <4>;
+					reginfo =<&IRDA 0 &BBIF1 &BBIF2>;
+				};
+
+				intc_prio2 {
+					reg = <0xe6940008 2>;
+					field-width = <4>;
+					reginfo = <&ATAPI 0 &CMT1_1 &AP_ARM1>;
+				};
+
+				intc_prio3 {
+					reg = <0xe694000c 2>;
+					field-width = <4>;
+					reginfo = <0 0 &CMT1_2>;
+				};
+
+				intc_prio4 {
+					reg = <0xe6940010 2>;
+					field-width = <4>;
+					reginfo = <&DMAC1_1 &MFIS &MFI &USBF>;
+				};
+
+				intc_prio5 {
+					reg = <0xe6940014 2>;
+					field-width = <4>;
+					reginfo = <&KEYSC &DMAC1_2 &SGX540 &CMT1_0>;
+				};
+
+				intc_prio6 {
+					reg = <0xe6940018 2>;
+					field-width = <4>;
+					reginfo = <&SCIFA0 &SCIFA1 &SCIFA2 &SCIFA3>;
+				};
+
+				intc_prio7 {
+					reg = <0xe694001c 2>;
+					field-width = <4>;
+					reginfo = <&MSIOF2 &USBHSDMAC &FLCTL &SDHI0>;
+				};
+
+				intc_prio8 {
+					reg = <0xe6940020 2>;
+					field-width = <4>;
+					reginfo = <&MSIOF1 &SCIFA4 0 &IIC1>;
+				};
+
+				intc_prio9 {
+					reg = <0xe6940024 2>;
+					field-width = <4>;
+					reginfo = <&DMAC2_1 &DMAC2_2 &AP_ARM_L2CINT>;
+				};
+
+				intc_prio10 {
+					reg = <0xe6940028 2>;
+					field-width = <4>;
+					reginfo = <0 &CMT1_3 0 &SDHI1>;
+				};
+
+				intc_prio11 {
+					reg = <0xe694002c 2>;
+					field-width = <4>;
+					reginfo = <&TPU0 &SCIFA6 &SCIFA7 &GETHER>;
+				};
+
+				intc_prio12 {
+					reg = <0xe6940030 2>;
+					field-width = <4>;
+					reginfo = <0 &CMT3 0 &RWDT0>;
+				};
+
+				intc_prio13 {
+					reg = <0xe6940034 2>;
+					field-width = <4>;
+					reginfo = <&SCIFB &SCIFA5 0 &DDM>;
+				};
+
+				intc_prio14 {
+					reg = <0xe6940038 2>;
+					field-width = <4>;
+					reginfo = <0 0 &DIRC &SDHI2>;
+				};
+
+				intc_prio15 {
+					reg = <0xe6950000 2>;
+					field-width = <4>;
+					reginfo = <&SHWYSTAT>;
+				};
+
+				intc_prio16 {
+					reg = <0xe6950010 2>;
+					field-width = <4>;
+					reginfo = <&USBH1>;
+				};
+
+				intc_prio17 {
+					reg = <0xe6950014 2>;
+					field-width = <4>;
+					reginfo = <&USBH2>;
+				};
+
+				intc_prio18 {
+					reg = <0xe6950020 2>;
+					field-width = <4>;
+					reginfo = <&HDMI>;
+				};
+
+				intc_prio19 {
+					reg = <0xe6950024 2>;
+					field-width = <4>;
+					reginfo = <&RSPI>;
+				};
+
+				intc_prio20 {
+					reg = <0xe6950028 2>;
+					field-width = <4>;
+					reginfo = <&SPU2 0 &FSI &FMSI>;
+				};
+
+				intc_prio21 {
+					reg = <0xe695002c 2>;
+					field-width = <4>;
+					reginfo = <0 &HDMI_SSS &HDMI_KEY>;
+				};
+
+				intc_prio22 {
+					reg = <0xe6950030 2>;
+					field-width = <4>;
+					reginfo = <&IPMMU>;
+				};
+
+				intc_prio23 {
+					reg = <0xe6950034 2>;
+					field-width = <4>;
+					reginfo = <&AP_ARM2>;
+				};
+
+				intc_prio24 {
+					reg = <0xe6950038 2>;
+					field-width = <4>;
+					reginfo = <&MFIS2 &CPORTR2S &CMT14 &CMT15>;
+				};
+
+				intc_prio25 {
+					reg = <0xe695003c 2>;
+					field-width = <4>;
+					reginfo = <0 &MMCIF_0 &MMCIF_1 &MMCIF_2>;
+				};
+
+				intc_prio26 {
+					reg = <0xe6950048 2>;
+					field-width = <4>;
+					reginfo = <&SIM_ERI &SIM_RXI &SIM_TXI &SIM_TEI>;
+				};
+
+				intc_prio27 {
+					reg = <0xe695004c 2>;
+					field-width = <4>;
+					reginfo = <&STPRO_0 &STPRO_1 &STPRO_2 &STPRO_3>;
+				};
+
+				intc_prio28 {
+					reg = <0xe6950050 2>;
+					field-width = <4>;
+					reginfo = <&STPRO_4>;
+				};
+			};
+		};
+
+		intca_irq_pins: interrupt-controller at 1{
+			compatible = "renesas,sh-intc";
+			interrupt-controller;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#interrupt-cells = <1>;
+			ranges;
+
+			reg = <0xe6900000 0x6c>;
+
+			IRQ0:	intsrc1 { vector = <0x200>; };
+			IRQ1:	intsrc2 { vector = <0x220>; };
+			IRQ2:	intsrc3 { vector = <0x240>; };
+			IRQ3:	intsrc4 { vector = <0x260>; };
+			IRQ4:	intsrc5 { vector = <0x280>; };
+			IRQ5:	intsrc6 { vector = <0x2a0>; };
+			IRQ6:	intsrc7 { vector = <0x2c0>; };
+			IRQ7:	intsrc8 { vector = <0x2e0>; };
+			IRQ8:	intsrc9 { vector = <0x300>; };
+			IRQ9:	intsrc10 { vector = <0x320>; };
+			IRQ10:	intsrc11 { vector = <0x340>; };
+			IRQ11:	intsrc12 { vector = <0x360>; };
+			IRQ12:	intsrc13 { vector = <0x380>; };
+			IRQ13:	intsrc14 { vector = <0x3a0>; };
+			IRQ14:	intsrc15 { vector = <0x3c0>; };
+			IRQ15:	intsrc16 { vector = <0x3e0>; };
+			IRQ16:	intsrc17 { vector = <0x3200>; };
+			IRQ17:	intsrc18 { vector = <0x3220>; };
+			IRQ18:	intsrc19 { vector = <0x3240>; };
+			IRQ19:	intsrc20 { vector = <0x3260>; };
+			IRQ20:	intsrc21 { vector = <0x3280>; };
+			IRQ21:	intsrc22 { vector = <0x32a0>; };
+			IRQ22:	intsrc23 { vector = <0x32c0>; };
+			IRQ23:	intsrc24 { vector = <0x32e0>; };
+			IRQ24:	intsrc25 { vector = <0x3300>; };
+			IRQ25:	intsrc26 { vector = <0x3320>; };
+			IRQ26:	intsrc27 { vector = <0x3340>; };
+			IRQ27:	intsrc28 { vector = <0x3360>; };
+			IRQ28:	intsrc29 { vector = <0x3380>; };
+			IRQ29:	intsrc30 { vector = <0x33a0>; };
+			IRQ30:	intsrc31 { vector = <0x33c0>; };
+			IRQ31:	intsrc32 { vector = <0x33e0>; };
+
+			intc_vectors {
+				vector_table = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 &IRQ5
+								&IRQ6 &IRQ7 &IRQ8 &IRQ9 &IRQ10
+								&IRQ11 &IRQ12 &IRQ13 &IRQ14 &IRQ15
+								&IRQ16 &IRQ17 &IRQ18 &IRQ19 &IRQ20
+								&IRQ21 &IRQ22 &IRQ23 &IRQ24 &IRQ25
+								&IRQ26 &IRQ27 &IRQ28 &IRQ29 &IRQ30
+								&IRQ31>;
+			};
+
+			intc_mask_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_mask0 {
+					reg = <0xe6900040 1>, <0xe6900060 1>;
+					reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4
+							&IRQ5 &IRQ6 &IRQ7>;
+				};
+
+				intc_mask1 {
+					reg = <0xe6900044 1>, <0xe6900064 1>;
+					reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11
+							&IRQ12 &IRQ13 &IRQ14 &IRQ15>;
+				};
+
+				intc_mask2 {
+					reg = <0xe6900048 1>, <0xe6900068 1>;
+					reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19
+							&IRQ20 &IRQ21 &IRQ22 &IRQ23>;
+				};
+
+				intc_mask3 {
+					reg = <0xe690004C 1>, <0xe690006C 1>;
+					reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27
+							&IRQ28 &IRQ29 &IRQ30 &IRQ31>;
+				};
+			};
+
+			intc_prio_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_prio0 {
+					reg = <0xe6900010 4>;
+					field-width = <4>;
+					reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 &IRQ5 &IRQ6 &IRQ7>;
+				};
+
+				intc_prio1 {
+					reg = <0xe6900014 4>;
+					field-width = <4>;
+					reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11
+							&IRQ12 &IRQ13 &IRQ14 &IRQ15>;
+				};
+
+				intc_prio2 {
+					reg = <0xe6900018 4>;
+					field-width = <4>;
+					reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19
+							&IRQ20 &IRQ21 &IRQ22 &IRQ23>;
+				};
+
+				intc_prio3 {
+					reg = <0xe690001C 4>;
+					field-width = <4>;
+					reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27
+							&IRQ28 &IRQ29 &IRQ30 &IRQ31>;
+				};
+			};
+
+			intc_sense_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_sense0 {
+					reg = <0xe6900000 4>;
+					field-width = <4>;
+					reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 &IRQ5 &IRQ6 &IRQ7>;
+				};
+
+				intc_sense1 {
+					reg = <0xe6900004 4>;
+					field-width = <4>;
+					reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11
+							&IRQ12 &IRQ13 &IRQ14 &IRQ15>;
+				};
+
+				intc_sense2 {
+					reg = <0xe6900008 4>;
+					field-width = <4>;
+					reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19
+							&IRQ20 &IRQ21 &IRQ22 &IRQ23>;
+				};
+
+				intc_sense3 {
+					reg = <0xe690000C 4>;
+					field-width = <4>;
+					reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27
+							&IRQ28 &IRQ29 &IRQ30 &IRQ31>;
+				};
+			};
+
+			intc_ack_registers {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				intc_ack0 {
+					reg = <0xe6900020 1>;
+					reginfo = <&IRQ0 &IRQ1 &IRQ2 &IRQ3 &IRQ4 &IRQ5 &IRQ6 &IRQ7>;
+				};
+
+				intc_ack1 {
+					reg = <0xe6900024 1>;
+					reginfo = <&IRQ8 &IRQ9 &IRQ10 &IRQ11
+							&IRQ12 &IRQ13 &IRQ14 &IRQ15>;
+				};
+
+				intc_ack2 {
+					reg = <0xe6900028 1>;
+					reginfo = <&IRQ16 &IRQ17 &IRQ18 &IRQ19
+							&IRQ20 &IRQ21 &IRQ22 &IRQ23>;
+				};
+
+				intc_ack3 {
+					reg = <0xe690002C 1>;
+					reginfo = <&IRQ24 &IRQ25 &IRQ26 &IRQ27
+							&IRQ28 &IRQ29 &IRQ30 &IRQ31>;
+				};
+			};
+		};
+	};
 };