ARM: OMAP5: hwmod, clock and prm data files
Subsystems (7)
cover ARM: OMAP5: hwmod, clock and prm data files
Series contains the hwmod, clock and prm data files for OMAP54xx SOCs. This data was kept out of tree to be validated on es2.0 silicon version and also to avoid the es1.0/es2.0 differences which are many.
Benoit Cousson, Rajendra Nayak, Paul Walmesly and Mike have all contributed to get the autogen scripts in shape for OMAP5.
Quoted 1 line
From various discussion on the list, the clock data files are suppose
to be moved to drivers/clk/. Once the direction is clear, patch 8 can be updated accordingly.
Patches are tested on OMAP5 sEVM and uEVM. For testing few additional patches are needed. Same tree can be fetched from here [1]
The following changes since commit 7d1f9aeff1ee4a20b1aeb377dd0f579fe9647619:
Linux 3.8-rc4 (2013-01-17 19:25:45 -0800)
are available in the git repository at:
git://github.com/SantoshShilimkar/linux.git for_3.9/omap5_data_files
for you to fetch changes up to 7f534e1ebeb2bc64250b56fe00eb7d4dfa585e8e:
ARM: OMAP5: Enable build and frameowrk initialisations (2013-01-18 19:45:48 +0530)
----------------------------------------------------------------
Benoit Cousson (7):
ARM: OMAP5: PRM: Add OMAP54XX register and bitfield files
ARM: OMAP5: CM: Add OMAP54XX register and bitfield files
ARM: OMAP5: PRCM: Add OMAP54XX local MPU PRCM registers
ARM: OMAP5: SCRM: Add OMAP54XX header file.
ARM: OMAP2+: clockdomain data: Add OMAP54XX data and update the
header
ARM: OMAP5: powerdomain data: Add OMAP54XX data and update the header
ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Rajendra Nayak (1):
ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
Santosh Shilimkar (2):
ARM: OMAP5: voltagedomain data: Add OMAP5 voltage domain data
ARM: OMAP5: Enable build and frameowrk initialisations
arch/arm/mach-omap2/Makefile | 6 +- arch/arm/mach-omap2/cclock54xx_data.c | 1794 ++++++++ arch/arm/mach-omap2/clock.h | 23 +- arch/arm/mach-omap2/clock54xx.h | 12 + arch/arm/mach-omap2/clock_common_data.c | 139 +- arch/arm/mach-omap2/clockdomain.h | 1 + arch/arm/mach-omap2/clockdomains54xx_data.c | 464 ++ arch/arm/mach-omap2/cm-regbits-54xx.h | 1737 +++++++ arch/arm/mach-omap2/cm1_54xx.h | 216 + arch/arm/mach-omap2/cm2_54xx.h | 392 ++ arch/arm/mach-omap2/io.c | 9 + arch/arm/mach-omap2/omap_hwmod.h | 1 + arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 5988 +++++++++++++++++++++++++ arch/arm/mach-omap2/powerdomain.h | 1 + arch/arm/mach-omap2/powerdomains54xx_data.c | 331 ++ arch/arm/mach-omap2/prcm44xx.h | 6 + arch/arm/mach-omap2/prcm_mpu54xx.h | 92 + arch/arm/mach-omap2/prm-regbits-54xx.h | 2701 +++++++++++ arch/arm/mach-omap2/prm54xx.h | 447 ++ arch/arm/mach-omap2/scrm54xx.h | 231 + arch/arm/mach-omap2/voltage.h | 1 + arch/arm/mach-omap2/voltagedomains54xx_data.c | 102 + 22 files changed, 14656 insertions(+), 38 deletions(-) create mode 100644 arch/arm/mach-omap2/cclock54xx_data.c create mode 100644 arch/arm/mach-omap2/clock54xx.h create mode 100644 arch/arm/mach-omap2/clockdomains54xx_data.c create mode 100644 arch/arm/mach-omap2/cm-regbits-54xx.h create mode 100644 arch/arm/mach-omap2/cm1_54xx.h create mode 100644 arch/arm/mach-omap2/cm2_54xx.h create mode 100644 arch/arm/mach-omap2/omap_hwmod_54xx_data.c create mode 100644 arch/arm/mach-omap2/powerdomains54xx_data.c create mode 100644 arch/arm/mach-omap2/prcm_mpu54xx.h create mode 100644 arch/arm/mach-omap2/prm-regbits-54xx.h create mode 100644 arch/arm/mach-omap2/prm54xx.h create mode 100644 arch/arm/mach-omap2/scrm54xx.h create mode 100644 arch/arm/mach-omap2/voltagedomains54xx_data.c
Regards,
Santosh
[1] OMAP5-Test brachgit://github.com/SantoshShilimkar/linux.git 3.9/omap5-testing
Signature · 1 line
1.7.9.5
PATCH 1/10 ARM: OMAP5: PRM: Add OMAP54XX register and bitfield files
From: Benoit Cousson <[email protected]>
Add the new defines for OMAP54XX prm module registers.
Cc Paul Walmsley <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
Signed-off-by Benoit Cousson <[email protected]>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by Santosh Shilimkar <[email protected]>
--- arch/arm/mach-omap2/prm-regbits-54xx.h | 2701 ++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/prm54xx.h | 447 ++++++ 2 files changed, 3148 insertions(+) create mode 100644 arch/arm/mach-omap2/prm-regbits-54xx.h create mode 100644 arch/arm/mach-omap2/prm54xx.h
arch/arm/mach-omap2/prm-regbits-54xx.h new file +2701 -0
@@ -0,0 +1,2701 @@ +/* +* OMAP54xx Power Management register bits +* +* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com +* +* Paul Walmsley (paul at pwsan.com) +* Rajendra Nayak (rnayak at ti.com) +* Benoit Cousson (b-cousson at ti.com) +* +* This file is automatically generated from the OMAP hardware databases. +* We respectfully ask that any modifications to this file be coordinated +* with the public linux-omap at vger.kernel.org mailing list and the +* authors above to ensure that the autogeneration scripts are kept +* up-to-date with the file contents. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ABBOFF_ACT_SHIFT 1 +#define OMAP54XX_ABBOFF_ACT_WIDTH 0x1 +#define OMAP54XX_ABBOFF_ACT_MASK (1 << 1) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ABBOFF_SLEEP_SHIFT 2 +#define OMAP54XX_ABBOFF_SLEEP_WIDTH 0x1 +#define OMAP54XX_ABBOFF_SLEEP_MASK (1 << 2) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_ABB_MM_DONE_EN_SHIFT 31 +#define OMAP54XX_ABB_MM_DONE_EN_WIDTH 0x1 +#define OMAP54XX_ABB_MM_DONE_EN_MASK (1 << 31) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_ABB_MM_DONE_ST_SHIFT 31 +#define OMAP54XX_ABB_MM_DONE_ST_WIDTH 0x1 +#define OMAP54XX_ABB_MM_DONE_ST_MASK (1 << 31) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_ABB_MPU_DONE_EN_SHIFT 7 +#define OMAP54XX_ABB_MPU_DONE_EN_WIDTH 0x1 +#define OMAP54XX_ABB_MPU_DONE_EN_MASK (1 << 7) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_ABB_MPU_DONE_ST_SHIFT 7 +#define OMAP54XX_ABB_MPU_DONE_ST_WIDTH 0x1 +#define OMAP54XX_ABB_MPU_DONE_ST_MASK (1 << 7) + +/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ +#define OMAP54XX_ACTIVE_FBB_SEL_SHIFT 2 +#define OMAP54XX_ACTIVE_FBB_SEL_WIDTH 0x1 +#define OMAP54XX_ACTIVE_FBB_SEL_MASK (1 << 2) + +/* Used by PM_ABE_PWRSTCTRL */ +#define OMAP54XX_AESSMEM_ONSTATE_SHIFT 16 +#define OMAP54XX_AESSMEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_AESSMEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_ABE_PWRSTCTRL */ +#define OMAP54XX_AESSMEM_RETSTATE_SHIFT 8 +#define OMAP54XX_AESSMEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_AESSMEM_RETSTATE_MASK (1 << 8) + +/* Used by PM_ABE_PWRSTST */ +#define OMAP54XX_AESSMEM_STATEST_SHIFT 4 +#define OMAP54XX_AESSMEM_STATEST_WIDTH 0x2 +#define OMAP54XX_AESSMEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_AIPOFF_SHIFT 8 +#define OMAP54XX_AIPOFF_WIDTH 0x1 +#define OMAP54XX_AIPOFF_MASK (1 << 8) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT 0 +#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH 0x2 +#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT 4 +#define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH 0x2 +#define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK (0x3 << 4) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT 2 +#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH 0x2 +#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) + +/* Used by PRM_VC_BYPASS_ERRST */ +#define OMAP54XX_BYPS_RA_ERR_SHIFT 1 +#define OMAP54XX_BYPS_RA_ERR_WIDTH 0x1 +#define OMAP54XX_BYPS_RA_ERR_MASK (1 << 1) + +/* Used by PRM_VC_BYPASS_ERRST */ +#define OMAP54XX_BYPS_SA_ERR_SHIFT 0 +#define OMAP54XX_BYPS_SA_ERR_WIDTH 0x1 +#define OMAP54XX_BYPS_SA_ERR_MASK (1 << 0) + +/* Used by PRM_VC_BYPASS_ERRST */ +#define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT 2 +#define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH 0x1 +#define OMAP54XX_BYPS_TIMEOUT_ERR_MASK (1 << 2) + +/* Used by PRM_RSTST */ +#define OMAP54XX_C2C_RST_SHIFT 10 +#define OMAP54XX_C2C_RST_WIDTH 0x1 +#define OMAP54XX_C2C_RST_MASK (1 << 10) + +/* Used by PM_CAM_PWRSTCTRL */ +#define OMAP54XX_CAM_MEM_ONSTATE_SHIFT 16 +#define OMAP54XX_CAM_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_CAM_MEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_CAM_PWRSTST */ +#define OMAP54XX_CAM_MEM_STATEST_SHIFT 4 +#define OMAP54XX_CAM_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_CAM_MEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_CLKREQCTRL */ +#define OMAP54XX_CLKREQ_COND_SHIFT 0 +#define OMAP54XX_CLKREQ_COND_WIDTH 0x3 +#define OMAP54XX_CLKREQ_COND_MASK (0x7 << 0) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT 16 +#define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH 0x8 +#define OMAP54XX_CMDRA_VDD_CORE_L_MASK (0xff << 16) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_CMDRA_VDD_MM_L_SHIFT 16 +#define OMAP54XX_CMDRA_VDD_MM_L_WIDTH 0x8 +#define OMAP54XX_CMDRA_VDD_MM_L_MASK (0xff << 16) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT 16 +#define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH 0x8 +#define OMAP54XX_CMDRA_VDD_MPU_L_MASK (0xff << 16) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_CMD_VDD_CORE_L_SHIFT 28 +#define OMAP54XX_CMD_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_CMD_VDD_CORE_L_MASK (1 << 28) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_CMD_VDD_MM_L_SHIFT 28 +#define OMAP54XX_CMD_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_CMD_VDD_MM_L_MASK (1 << 28) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_CMD_VDD_MPU_L_SHIFT 28 +#define OMAP54XX_CMD_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_CMD_VDD_MPU_L_MASK (1 << 28) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT 18 +#define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT 9 +#define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK (1 << 9) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT 6 +#define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH 0x2 +#define OMAP54XX_CORE_OCMRAM_STATEST_MASK (0x3 << 6) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT 16 +#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH 0x2 +#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT 8 +#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH 0x1 +#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT 4 +#define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH 0x2 +#define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) + +/* Used by REVISION_PRM */ +#define OMAP54XX_CUSTOM_SHIFT 6 +#define OMAP54XX_CUSTOM_WIDTH 0x2 +#define OMAP54XX_CUSTOM_MASK (0x3 << 6) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_DATA_SHIFT 16 +#define OMAP54XX_DATA_WIDTH 0x8 +#define OMAP54XX_DATA_MASK (0xff << 16) + +/* Used by PRM_DEBUG_CORE_RET_TRANS */ +#define OMAP54XX_PRM_DEBUG_OUT_SHIFT 0 +#define OMAP54XX_PRM_DEBUG_OUT_WIDTH 0x1c +#define OMAP54XX_PRM_DEBUG_OUT_MASK (0xfffffff << 0) + +/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa +#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) + +/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 +#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) + +/* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 +#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) + +/* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_11_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_11_WIDTH 0xc +#define OMAP54XX_DEBUG_OUT_0_11_MASK (0xfff << 0) + +/* Used by PRM_DEVICE_OFF_CTRL */ +#define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT 0 +#define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH 0x1 +#define OMAP54XX_DEVICE_OFF_ENABLE_MASK (1 << 0) + +/* Used by PRM_VC_CFG_I2C_MODE */ +#define OMAP54XX_DFILTEREN_SHIFT 6 +#define OMAP54XX_DFILTEREN_WIDTH 0x1 +#define OMAP54XX_DFILTEREN_MASK (1 << 6) + +/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT 4 +#define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_ABE_RECAL_EN_MASK (1 << 4) + +/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT 4 +#define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_ABE_RECAL_ST_MASK (1 << 4) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT 0 +#define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_CORE_RECAL_EN_MASK (1 << 0) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT 0 +#define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_CORE_RECAL_ST_MASK (1 << 0) + +/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT 2 +#define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_IVA_RECAL_EN_MASK (1 << 2) + +/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT 2 +#define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_IVA_RECAL_ST_MASK (1 << 2) + +/* Used by PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT 1 +#define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_MPU_RECAL_EN_MASK (1 << 1) + +/* Used by PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT 1 +#define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_MPU_RECAL_ST_MASK (1 << 1) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT 3 +#define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_PER_RECAL_EN_MASK (1 << 3) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT 3 +#define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_PER_RECAL_ST_MASK (1 << 3) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT 20 +#define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH 0x2 +#define OMAP54XX_DSP_EDMA_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT 10 +#define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH 0x1 +#define OMAP54XX_DSP_EDMA_RETSTATE_MASK (1 << 10) + +/* Used by PM_DSP_PWRSTST */ +#define OMAP54XX_DSP_EDMA_STATEST_SHIFT 8 +#define OMAP54XX_DSP_EDMA_STATEST_WIDTH 0x2 +#define OMAP54XX_DSP_EDMA_STATEST_MASK (0x3 << 8) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_L1_ONSTATE_SHIFT 16 +#define OMAP54XX_DSP_L1_ONSTATE_WIDTH 0x2 +#define OMAP54XX_DSP_L1_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_L1_RETSTATE_SHIFT 8 +#define OMAP54XX_DSP_L1_RETSTATE_WIDTH 0x1 +#define OMAP54XX_DSP_L1_RETSTATE_MASK (1 << 8) + +/* Used by PM_DSP_PWRSTST */ +#define OMAP54XX_DSP_L1_STATEST_SHIFT 4 +#define OMAP54XX_DSP_L1_STATEST_WIDTH 0x2 +#define OMAP54XX_DSP_L1_STATEST_MASK (0x3 << 4) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_L2_ONSTATE_SHIFT 18 +#define OMAP54XX_DSP_L2_ONSTATE_WIDTH 0x2 +#define OMAP54XX_DSP_L2_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_L2_RETSTATE_SHIFT 9 +#define OMAP54XX_DSP_L2_RETSTATE_WIDTH 0x1 +#define OMAP54XX_DSP_L2_RETSTATE_MASK (1 << 9) + +/* Used by PM_DSP_PWRSTST */ +#define OMAP54XX_DSP_L2_STATEST_SHIFT 6 +#define OMAP54XX_DSP_L2_STATEST_WIDTH 0x2 +#define OMAP54XX_DSP_L2_STATEST_MASK (0x3 << 6) + +/* Used by PM_DSS_PWRSTCTRL */ +#define OMAP54XX_DSS_MEM_ONSTATE_SHIFT 16 +#define OMAP54XX_DSS_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_DSS_MEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_DSS_PWRSTCTRL */ +#define OMAP54XX_DSS_MEM_RETSTATE_SHIFT 8 +#define OMAP54XX_DSS_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_DSS_MEM_RETSTATE_MASK (1 << 8) + +/* Used by PM_DSS_PWRSTST */ +#define OMAP54XX_DSS_MEM_STATEST_SHIFT 4 +#define OMAP54XX_DSS_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_DSS_MEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_DEVICE_OFF_CTRL */ +#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT 8 +#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH 0x1 +#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8) + +/* Used by PRM_DEVICE_OFF_CTRL */ +#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT 9 +#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH 0x1 +#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9) + +/* Used by PM_EMU_PWRSTCTRL */ +#define OMAP54XX_EMU_BANK_ONSTATE_SHIFT 16 +#define OMAP54XX_EMU_BANK_ONSTATE_WIDTH 0x2 +#define OMAP54XX_EMU_BANK_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_EMU_PWRSTST */ +#define OMAP54XX_EMU_BANK_STATEST_SHIFT 4 +#define OMAP54XX_EMU_BANK_STATEST_WIDTH 0x2 +#define OMAP54XX_EMU_BANK_STATEST_MASK (0x3 << 4) + +/* +* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP, +* PRM_SRAM_WKUP_SETUP +*/ +#define OMAP54XX_ENABLE_RTA_SHIFT 0 +#define OMAP54XX_ENABLE_RTA_WIDTH 0x1 +#define OMAP54XX_ENABLE_RTA_MASK (1 << 0) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC1_SHIFT 3 +#define OMAP54XX_ENFUNC1_WIDTH 0x1 +#define OMAP54XX_ENFUNC1_MASK (1 << 3) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC2_SHIFT 4 +#define OMAP54XX_ENFUNC2_WIDTH 0x1 +#define OMAP54XX_ENFUNC2_MASK (1 << 4) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC3_SHIFT 5 +#define OMAP54XX_ENFUNC3_WIDTH 0x1 +#define OMAP54XX_ENFUNC3_MASK (1 << 5) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC4_SHIFT 6 +#define OMAP54XX_ENFUNC4_WIDTH 0x1 +#define OMAP54XX_ENFUNC4_MASK (1 << 6) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC5_SHIFT 7 +#define OMAP54XX_ENFUNC5_WIDTH 0x1 +#define OMAP54XX_ENFUNC5_MASK (1 << 7) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_ERRORGAIN_SHIFT 16 +#define OMAP54XX_ERRORGAIN_WIDTH 0x8 +#define OMAP54XX_ERRORGAIN_MASK (0xff << 16) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_ERROROFFSET_SHIFT 24 +#define OMAP54XX_ERROROFFSET_WIDTH 0x8 +#define OMAP54XX_ERROROFFSET_MASK (0xff << 24) + +/* Used by PRM_RSTST */ +#define OMAP54XX_EXTERNAL_WARM_RST_SHIFT 5 +#define OMAP54XX_EXTERNAL_WARM_RST_WIDTH 0x1 +#define OMAP54XX_EXTERNAL_WARM_RST_MASK (1 << 5) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_FORCEUPDATE_SHIFT 1 +#define OMAP54XX_FORCEUPDATE_WIDTH 0x1 +#define OMAP54XX_FORCEUPDATE_MASK (1 << 1) + +/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ +#define OMAP54XX_FORCEUPDATEWAIT_SHIFT 8 +#define OMAP54XX_FORCEUPDATEWAIT_WIDTH 0x18 +#define OMAP54XX_FORCEUPDATEWAIT_MASK (0xffffff << 8) + +/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */ +#define OMAP54XX_FORCEWKUP_EN_SHIFT 10 +#define OMAP54XX_FORCEWKUP_EN_WIDTH 0x1 +#define OMAP54XX_FORCEWKUP_EN_MASK (1 << 10) + +/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */ +#define OMAP54XX_FORCEWKUP_ST_SHIFT 10 +#define OMAP54XX_FORCEWKUP_ST_WIDTH 0x1 +#define OMAP54XX_FORCEWKUP_ST_MASK (1 << 10) + +/* Used by REVISION_PRM */ +#define OMAP54XX_FUNC_SHIFT 16 +#define OMAP54XX_FUNC_WIDTH 0xc +#define OMAP54XX_FUNC_MASK (0xfff << 16) + +/* Used by PRM_RSTST */ +#define OMAP54XX_GLOBAL_COLD_RST_SHIFT 0 +#define OMAP54XX_GLOBAL_COLD_RST_WIDTH 0x1 +#define OMAP54XX_GLOBAL_COLD_RST_MASK (1 << 0) + +/* Used by PRM_RSTST */ +#define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT 1 +#define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH 0x1 +#define OMAP54XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_GLOBAL_WUEN_SHIFT 16 +#define OMAP54XX_GLOBAL_WUEN_WIDTH 0x1 +#define OMAP54XX_GLOBAL_WUEN_MASK (1 << 16) + +/* Used by PM_GPU_PWRSTCTRL */ +#define OMAP54XX_GPU_MEM_ONSTATE_SHIFT 16 +#define OMAP54XX_GPU_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_GPU_MEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_GPU_PWRSTST */ +#define OMAP54XX_GPU_MEM_STATEST_SHIFT 4 +#define OMAP54XX_GPU_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_GPU_MEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_VC_CFG_I2C_MODE */ +#define OMAP54XX_HSMCODE_SHIFT 0 +#define OMAP54XX_HSMCODE_WIDTH 0x3 +#define OMAP54XX_HSMCODE_MASK (0x7 << 0) + +/* Used by PRM_VC_CFG_I2C_MODE */ +#define OMAP54XX_HSMODEEN_SHIFT 3 +#define OMAP54XX_HSMODEEN_WIDTH 0x1 +#define OMAP54XX_HSMODEEN_MASK (1 << 3) + +/* Used by PRM_VC_CFG_I2C_CLK */ +#define OMAP54XX_HSSCLH_SHIFT 16 +#define OMAP54XX_HSSCLH_WIDTH 0x8 +#define OMAP54XX_HSSCLH_MASK (0xff << 16) + +/* Used by PRM_VC_CFG_I2C_CLK */ +#define OMAP54XX_HSSCLL_SHIFT 24 +#define OMAP54XX_HSSCLL_WIDTH 0x8 +#define OMAP54XX_HSSCLL_MASK (0xff << 24) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_HWA_MEM_ONSTATE_SHIFT 16 +#define OMAP54XX_HWA_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_HWA_MEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_HWA_MEM_RETSTATE_SHIFT 8 +#define OMAP54XX_HWA_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_HWA_MEM_RETSTATE_MASK (1 << 8) + +/* Used by PM_IVA_PWRSTST */ +#define OMAP54XX_HWA_MEM_STATEST_SHIFT 4 +#define OMAP54XX_HWA_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_HWA_MEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_RSTST */ +#define OMAP54XX_ICEPICK_RST_SHIFT 9 +#define OMAP54XX_ICEPICK_RST_WIDTH 0x1 +#define OMAP54XX_ICEPICK_RST_MASK (1 << 9) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_INITVDD_SHIFT 2 +#define OMAP54XX_INITVDD_WIDTH 0x1 +#define OMAP54XX_INITVDD_MASK (1 << 2) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_INITVOLTAGE_SHIFT 8 +#define OMAP54XX_INITVOLTAGE_WIDTH 0x8 +#define OMAP54XX_INITVOLTAGE_MASK (0xff << 8) + +/* +* Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, +* PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, +* PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST, +* PRM_VOLTST_MM, PRM_VOLTST_MPU +*/ +#define OMAP54XX_INTRANSITION_SHIFT 20 +#define OMAP54XX_INTRANSITION_WIDTH 0x1 +#define OMAP54XX_INTRANSITION_MASK (1 << 20) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_IO_EN_SHIFT 9 +#define OMAP54XX_IO_EN_WIDTH 0x1 +#define OMAP54XX_IO_EN_MASK (1 << 9) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_IO_ON_STATUS_SHIFT 5 +#define OMAP54XX_IO_ON_STATUS_WIDTH 0x1 +#define OMAP54XX_IO_ON_STATUS_MASK (1 << 5) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_IO_ST_SHIFT 9 +#define OMAP54XX_IO_ST_WIDTH 0x1 +#define OMAP54XX_IO_ST_MASK (1 << 9) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT 20 +#define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_IPU_L2RAM_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT 10 +#define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_IPU_L2RAM_RETSTATE_MASK (1 << 10) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_IPU_L2RAM_STATEST_SHIFT 8 +#define OMAP54XX_IPU_L2RAM_STATEST_WIDTH 0x2 +#define OMAP54XX_IPU_L2RAM_STATEST_MASK (0x3 << 8) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT 22 +#define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH 0x2 +#define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK (0x3 << 22) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT 11 +#define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH 0x1 +#define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK (1 << 11) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT 10 +#define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH 0x2 +#define OMAP54XX_IPU_UNICACHE_STATEST_MASK (0x3 << 10) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_ISOCLK_OVERRIDE_SHIFT 0 +#define OMAP54XX_ISOCLK_OVERRIDE_WIDTH 0x1 +#define OMAP54XX_ISOCLK_OVERRIDE_MASK (1 << 0) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_ISOCLK_STATUS_SHIFT 1 +#define OMAP54XX_ISOCLK_STATUS_WIDTH 0x1 +#define OMAP54XX_ISOCLK_STATUS_MASK (1 << 1) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_ISOOVR_EXTEND_SHIFT 4 +#define OMAP54XX_ISOOVR_EXTEND_WIDTH 0x1 +#define OMAP54XX_ISOOVR_EXTEND_MASK (1 << 4) + +/* Used by PRM_IO_COUNT */ +#define OMAP54XX_ISO_2_ON_TIME_SHIFT 0 +#define OMAP54XX_ISO_2_ON_TIME_WIDTH 0x8 +#define OMAP54XX_ISO_2_ON_TIME_MASK (0xff << 0) + +/* Used by PM_L3INIT_PWRSTCTRL */ +#define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT 16 +#define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH 0x2 +#define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_L3INIT_PWRSTCTRL */ +#define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT 8 +#define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH 0x1 +#define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK (1 << 8) + +/* Used by PM_L3INIT_PWRSTST */ +#define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT 4 +#define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH 0x2 +#define OMAP54XX_L3INIT_BANK1_STATEST_MASK (0x3 << 4) + +/* Used by PM_L3INIT_PWRSTCTRL */ +#define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT 18 +#define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH 0x2 +#define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_L3INIT_PWRSTCTRL */ +#define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT 9 +#define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH 0x1 +#define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK (1 << 9) + +/* Used by PM_L3INIT_PWRSTST */ +#define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT 6 +#define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH 0x2 +#define OMAP54XX_L3INIT_BANK2_STATEST_MASK (0x3 << 6) + +/* +* Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, +* PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, +* PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST +*/ +#define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT 24 +#define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH 0x2 +#define OMAP54XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) + +/* Used by PRM_RSTST */ +#define OMAP54XX_LLI_RST_SHIFT 14 +#define OMAP54XX_LLI_RST_WIDTH 0x1 +#define OMAP54XX_LLI_RST_MASK (1 << 14) + +/* +* Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL, +* PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL +*/ +#define OMAP54XX_LOGICRETSTATE_SHIFT 2 +#define OMAP54XX_LOGICRETSTATE_WIDTH 0x1 +#define OMAP54XX_LOGICRETSTATE_MASK (1 << 2) + +/* +* Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, +* PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, +* PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST +*/ +#define OMAP54XX_LOGICSTATEST_SHIFT 2 +#define OMAP54XX_LOGICSTATEST_WIDTH 0x1 +#define OMAP54XX_LOGICSTATEST_MASK (1 << 2) + +/* +* Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, +* RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, +* RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT, +* RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, +* RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, +* RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, +* RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT, +* RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT, +* RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT, +* RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT, +* RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, +* RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT, +* RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT, +* RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT, +* RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, +* RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, +* RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, +* RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT, +* RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT, +* RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, +* RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, +* RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, +* RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, +* RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, +* RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT, +* RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT, +* RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, +* RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT, +* RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT, +* RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT, +* RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT, +* RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT, +* RM_WKUPAON_WD_TIMER2_CONTEXT +*/ +#define OMAP54XX_LOSTCONTEXT_DFF_SHIFT 0 +#define OMAP54XX_LOSTCONTEXT_DFF_WIDTH 0x1 +#define OMAP54XX_LOSTCONTEXT_DFF_MASK (1 << 0) + +/* +* Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, +* RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT, +* RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, +* RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT, +* RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, +* RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT, +* RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, +* RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, +* RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT, +* RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT, +* RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, +* RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, +* RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT, +* RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, +* RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, +* RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, +* RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT, +* RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, +* RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT +*/ +#define OMAP54XX_LOSTCONTEXT_RFF_SHIFT 1 +#define OMAP54XX_LOSTCONTEXT_RFF_WIDTH 0x1 +#define OMAP54XX_LOSTCONTEXT_RFF_MASK (1 << 1) + +/* Used by RM_ABE_AESS_CONTEXT */ +#define OMAP54XX_LOSTMEM_AESSMEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_AESSMEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_AESSMEM_MASK (1 << 8) + +/* Used by RM_CAM_CAL_CONTEXT */ +#define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CAL_MEM_MASK (1 << 8) + +/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ +#define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CAM_MEM_MASK (1 << 8) + +/* Used by RM_EMIF_DMM_CONTEXT */ +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT 9 +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK (1 << 9) + +/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */ +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT 8 +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK (1 << 8) + +/* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */ +#define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT 8 +#define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) + +/* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */ +#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) + +/* Used by RM_DSP_DSP_CONTEXT */ +#define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT 10 +#define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_DSP_EDMA_MASK (1 << 10) + +/* Used by RM_DSP_DSP_CONTEXT */ +#define OMAP54XX_LOSTMEM_DSP_L1_SHIFT 8 +#define OMAP54XX_LOSTMEM_DSP_L1_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_DSP_L1_MASK (1 << 8) + +/* Used by RM_DSP_DSP_CONTEXT */ +#define OMAP54XX_LOSTMEM_DSP_L2_SHIFT 9 +#define OMAP54XX_LOSTMEM_DSP_L2_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_DSP_L2_MASK (1 << 9) + +/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */ +#define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_DSS_MEM_MASK (1 << 8) + +/* Used by RM_EMU_DEBUGSS_CONTEXT */ +#define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_EMU_BANK_MASK (1 << 8) + +/* Used by RM_GPU_GPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_GPU_MEM_MASK (1 << 8) + +/* Used by RM_IVA_IVA_CONTEXT */ +#define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT 10 +#define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_HWA_MEM_MASK (1 << 10) + +/* Used by RM_IPU_IPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT 9 +#define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK (1 << 9) + +/* Used by RM_IPU_IPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT 8 +#define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK (1 << 8) + +/* +* Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, +* RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, +* RM_L3INIT_USB_OTG_SS_CONTEXT +*/ +#define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT 8 +#define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) + +/* Used by RM_MPU_MPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_MPU_L2_SHIFT 9 +#define OMAP54XX_LOSTMEM_MPU_L2_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_MPU_L2_MASK (1 << 9) + +/* Used by RM_MPU_MPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT 10 +#define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_MPU_RAM_MASK (1 << 10) + +/* +* Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, +* RM_L4SEC_FPKA_CONTEXT +*/ +#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) + +/* +* Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, +* RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT +*/ +#define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_PERIHPMEM_MASK (1 << 8) + +/* +* Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, +* RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, +* RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT +*/ +#define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK (1 << 8) + +/* Used by RM_IVA_SL2_CONTEXT */ +#define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_SL2_MEM_MASK (1 << 8) + +/* Used by RM_IVA_IVA_CONTEXT */ +#define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_TCM1_MEM_MASK (1 << 8) + +/* Used by RM_IVA_IVA_CONTEXT */ +#define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT 9 +#define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_TCM2_MEM_MASK (1 << 9) + +/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */ +#define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_WKUP_BANK_MASK (1 << 8) + +/* +* Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, +* PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, +* PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL +*/ +#define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT 4 +#define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH 0x1 +#define OMAP54XX_LOWPOWERSTATECHANGE_MASK (1 << 4) + +/* Used by PRM_DEBUG_TRANS_CFG */ +#define OMAP54XX_MODE_SHIFT 0 +#define OMAP54XX_MODE_WIDTH 0x2 +#define OMAP54XX_MODE_MASK (0x3 << 0) + +/* Used by PRM_MODEM_IF_CTRL */ +#define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT 9 +#define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH 0x1 +#define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) + +/* Used by PRM_MODEM_IF_CTRL */ +#define OMAP54XX_MODEM_WAKE_IRQ_SHIFT 8 +#define OMAP54XX_MODEM_WAKE_IRQ_WIDTH 0x1 +#define OMAP54XX_MODEM_WAKE_IRQ_MASK (1 << 8) + +/* Used by PM_MPU_PWRSTCTRL */ +#define OMAP54XX_MPU_L2_ONSTATE_SHIFT 18 +#define OMAP54XX_MPU_L2_ONSTATE_WIDTH 0x2 +#define OMAP54XX_MPU_L2_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_MPU_PWRSTCTRL */ +#define OMAP54XX_MPU_L2_RETSTATE_SHIFT 9 +#define OMAP54XX_MPU_L2_RETSTATE_WIDTH 0x1 +#define OMAP54XX_MPU_L2_RETSTATE_MASK (1 << 9) + +/* Used by PM_MPU_PWRSTST */ +#define OMAP54XX_MPU_L2_STATEST_SHIFT 6 +#define OMAP54XX_MPU_L2_STATEST_WIDTH 0x2 +#define OMAP54XX_MPU_L2_STATEST_MASK (0x3 << 6) + +/* Used by PM_MPU_PWRSTCTRL */ +#define OMAP54XX_MPU_RAM_ONSTATE_SHIFT 20 +#define OMAP54XX_MPU_RAM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_MPU_RAM_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_MPU_PWRSTCTRL */ +#define OMAP54XX_MPU_RAM_RETSTATE_SHIFT 10 +#define OMAP54XX_MPU_RAM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_MPU_RAM_RETSTATE_MASK (1 << 10) + +/* Used by PM_MPU_PWRSTST */ +#define OMAP54XX_MPU_RAM_STATEST_SHIFT 8 +#define OMAP54XX_MPU_RAM_STATEST_WIDTH 0x2 +#define OMAP54XX_MPU_RAM_STATEST_MASK (0x3 << 8) + +/* Used by PRM_RSTST */ +#define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT 2 +#define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH 0x1 +#define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) + +/* Used by PRM_RSTST */ +#define OMAP54XX_MPU_WDT_RST_SHIFT 3 +#define OMAP54XX_MPU_WDT_RST_WIDTH 0x1 +#define OMAP54XX_MPU_WDT_RST_MASK (1 << 3) + +/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ +#define OMAP54XX_NOCAP_SHIFT 4 +#define OMAP54XX_NOCAP_WIDTH 0x1 +#define OMAP54XX_NOCAP_MASK (1 << 4) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT 24 +#define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH 0x2 +#define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT 12 +#define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH 0x1 +#define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT 12 +#define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH 0x2 +#define OMAP54XX_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) + +/* +* Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, +* PRM_VC_VAL_CMD_VDD_MPU_L +*/ +#define OMAP54XX_OFF_SHIFT 0 +#define OMAP54XX_OFF_WIDTH 0x8 +#define OMAP54XX_OFF_MASK (0xff << 0) + +/* +* Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, +* PRM_VC_VAL_CMD_VDD_MPU_L +*/ +#define OMAP54XX_ON_SHIFT 24 +#define OMAP54XX_ON_WIDTH 0x8 +#define OMAP54XX_ON_MASK (0xff << 24) + +/* +* Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, +* PRM_VC_VAL_CMD_VDD_MPU_L +*/ +#define OMAP54XX_ONLP_SHIFT 16 +#define OMAP54XX_ONLP_WIDTH 0x8 +#define OMAP54XX_ONLP_MASK (0xff << 16) + +/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ +#define OMAP54XX_OPP_CHANGE_SHIFT 2 +#define OMAP54XX_OPP_CHANGE_WIDTH 0x1 +#define OMAP54XX_OPP_CHANGE_MASK (1 << 2) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT 25 +#define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH 0x1 +#define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK (1 << 25) + +/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ +#define OMAP54XX_OPP_SEL_SHIFT 0 +#define OMAP54XX_OPP_SEL_WIDTH 0x2 +#define OMAP54XX_OPP_SEL_MASK (0x3 << 0) + +/* Used by PRM_DEBUG_OUT */ +#define OMAP54XX_OUTPUT_SHIFT 0 +#define OMAP54XX_OUTPUT_WIDTH 0x20 +#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) + +/* Used by PRM_SRAM_COUNT */ +#define OMAP54XX_PCHARGECNT_VALUE_SHIFT 0 +#define OMAP54XX_PCHARGECNT_VALUE_WIDTH 0x6 +#define OMAP54XX_PCHARGECNT_VALUE_MASK (0x3f << 0) + +/* Used by PRM_PSCON_COUNT */ +#define OMAP54XX_PCHARGE_TIME_SHIFT 0 +#define OMAP54XX_PCHARGE_TIME_WIDTH 0x8 +#define OMAP54XX_PCHARGE_TIME_MASK (0xff << 0) + +/* Used by PM_ABE_PWRSTCTRL */ +#define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT 20 +#define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_PERIPHMEM_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_ABE_PWRSTCTRL */ +#define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT 10 +#define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_PERIPHMEM_RETSTATE_MASK (1 << 10) + +/* Used by PM_ABE_PWRSTST */ +#define OMAP54XX_PERIPHMEM_STATEST_SHIFT 8 +#define OMAP54XX_PERIPHMEM_STATEST_WIDTH 0x2 +#define OMAP54XX_PERIPHMEM_STATEST_MASK (0x3 << 8) + +/* Used by PRM_PHASE1_CNDP */ +#define OMAP54XX_PHASE1_CNDP_SHIFT 0 +#define OMAP54XX_PHASE1_CNDP_WIDTH 0x20 +#define OMAP54XX_PHASE1_CNDP_MASK (0xffffffff << 0) + +/* Used by PRM_PHASE2A_CNDP */ +#define OMAP54XX_PHASE2A_CNDP_SHIFT 0 +#define OMAP54XX_PHASE2A_CNDP_WIDTH 0x20 +#define OMAP54XX_PHASE2A_CNDP_MASK (0xffffffff << 0) + +/* Used by PRM_PHASE2B_CNDP */ +#define OMAP54XX_PHASE2B_CNDP_SHIFT 0 +#define OMAP54XX_PHASE2B_CNDP_WIDTH 0x20 +#define OMAP54XX_PHASE2B_CNDP_MASK (0xffffffff << 0) + +/* Used by PRM_PSCON_COUNT */ +#define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT 8 +#define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH 0x8 +#define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) + +/* +* Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, +* PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, +* PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, +* PM_MPU_PWRSTCTRL +*/ +#define OMAP54XX_POWERSTATE_SHIFT 0 +#define OMAP54XX_POWERSTATE_WIDTH 0x2 +#define OMAP54XX_POWERSTATE_MASK (0x3 << 0) + +/* +* Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, +* PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, +* PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST +*/ +#define OMAP54XX_POWERSTATEST_SHIFT 0 +#define OMAP54XX_POWERSTATEST_WIDTH 0x2 +#define OMAP54XX_POWERSTATEST_MASK (0x3 << 0) + +/* Used by PRM_PWRREQCTRL */ +#define OMAP54XX_PWRREQ_COND_SHIFT 0 +#define OMAP54XX_PWRREQ_COND_WIDTH 0x2 +#define OMAP54XX_PWRREQ_COND_MASK (0x3 << 0) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_RACEN_VDD_CORE_L_SHIFT 27 +#define OMAP54XX_RACEN_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_RACEN_VDD_CORE_L_MASK (1 << 27) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_RACEN_VDD_MM_L_SHIFT 27 +#define OMAP54XX_RACEN_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_RACEN_VDD_MM_L_MASK (1 << 27) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_RACEN_VDD_MPU_L_SHIFT 27 +#define OMAP54XX_RACEN_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_RACEN_VDD_MPU_L_MASK (1 << 27) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_RAC_VDD_CORE_L_SHIFT 26 +#define OMAP54XX_RAC_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_RAC_VDD_CORE_L_MASK (1 << 26) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_RAC_VDD_MM_L_SHIFT 26 +#define OMAP54XX_RAC_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_RAC_VDD_MM_L_MASK (1 << 26) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_RAC_VDD_MPU_L_SHIFT 26 +#define OMAP54XX_RAC_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_RAC_VDD_MPU_L_MASK (1 << 26) + +/* +* Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, +* PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, +* PRM_VOLTSETUP_MPU_RET_SLEEP +*/ +#define OMAP54XX_RAMP_DOWN_COUNT_SHIFT 16 +#define OMAP54XX_RAMP_DOWN_COUNT_WIDTH 0x6 +#define OMAP54XX_RAMP_DOWN_COUNT_MASK (0x3f << 16) + +/* +* Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, +* PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, +* PRM_VOLTSETUP_MPU_RET_SLEEP +*/ +#define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT 24 +#define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH 0x2 +#define OMAP54XX_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) + +/* +* Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, +* PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, +* PRM_VOLTSETUP_MPU_RET_SLEEP +*/ +#define OMAP54XX_RAMP_UP_COUNT_SHIFT 0 +#define OMAP54XX_RAMP_UP_COUNT_WIDTH 0x6 +#define OMAP54XX_RAMP_UP_COUNT_MASK (0x3f << 0) + +/* +* Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, +* PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, +* PRM_VOLTSETUP_MPU_RET_SLEEP +*/ +#define OMAP54XX_RAMP_UP_PRESCAL_SHIFT 8 +#define OMAP54XX_RAMP_UP_PRESCAL_WIDTH 0x2 +#define OMAP54XX_RAMP_UP_PRESCAL_MASK (0x3 << 8) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_RAV_VDD_CORE_L_SHIFT 25 +#define OMAP54XX_RAV_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_RAV_VDD_CORE_L_MASK (1 << 25) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_RAV_VDD_MM_L_SHIFT 25 +#define OMAP54XX_RAV_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_RAV_VDD_MM_L_MASK (1 << 25) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_RAV_VDD_MPU_L_SHIFT 25 +#define OMAP54XX_RAV_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_RAV_VDD_MPU_L_MASK (1 << 25) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_REGADDR_SHIFT 8 +#define OMAP54XX_REGADDR_WIDTH 0x8 +#define OMAP54XX_REGADDR_MASK (0xff << 8) + +/* +* Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, +* PRM_VC_VAL_CMD_VDD_MPU_L +*/ +#define OMAP54XX_RET_SHIFT 8 +#define OMAP54XX_RET_WIDTH 0x8 +#define OMAP54XX_RET_MASK (0xff << 8) + +/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ +#define OMAP54XX_RETMODE_ENABLE_SHIFT 0 +#define OMAP54XX_RETMODE_ENABLE_WIDTH 0x1 +#define OMAP54XX_RETMODE_ENABLE_MASK (1 << 0) + +/* Used by PRM_RSTTIME */ +#define OMAP54XX_RSTTIME1_SHIFT 0 +#define OMAP54XX_RSTTIME1_WIDTH 0xa +#define OMAP54XX_RSTTIME1_MASK (0x3ff << 0) + +/* Used by PRM_RSTTIME */ +#define OMAP54XX_RSTTIME2_SHIFT 10 +#define OMAP54XX_RSTTIME2_WIDTH 0x5 +#define OMAP54XX_RSTTIME2_MASK (0x1f << 10) + +/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ +#define OMAP54XX_RST_CPU0_SHIFT 0 +#define OMAP54XX_RST_CPU0_WIDTH 0x1 +#define OMAP54XX_RST_CPU0_MASK (1 << 0) + +/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ +#define OMAP54XX_RST_CPU1_SHIFT 1 +#define OMAP54XX_RST_CPU1_WIDTH 0x1 +#define OMAP54XX_RST_CPU1_MASK (1 << 1) + +/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ +#define OMAP54XX_RST_DSP_SHIFT 0 +#define OMAP54XX_RST_DSP_WIDTH 0x1 +#define OMAP54XX_RST_DSP_MASK (1 << 0) + +/* Used by RM_DSP_RSTST */ +#define OMAP54XX_RST_DSP_EMU_SHIFT 2 +#define OMAP54XX_RST_DSP_EMU_WIDTH 0x1 +#define OMAP54XX_RST_DSP_EMU_MASK (1 << 2) + +/* Used by RM_DSP_RSTST */ +#define OMAP54XX_RST_DSP_EMU_REQ_SHIFT 3 +#define OMAP54XX_RST_DSP_EMU_REQ_WIDTH 0x1 +#define OMAP54XX_RST_DSP_EMU_REQ_MASK (1 << 3) + +/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ +#define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT 1 +#define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH 0x1 +#define OMAP54XX_RST_DSP_MMU_CACHE_MASK (1 << 1) + +/* Used by RM_IPU_RSTST */ +#define OMAP54XX_RST_EMULATION_CPU0_SHIFT 3 +#define OMAP54XX_RST_EMULATION_CPU0_WIDTH 0x1 +#define OMAP54XX_RST_EMULATION_CPU0_MASK (1 << 3) + +/* Used by RM_IPU_RSTST */ +#define OMAP54XX_RST_EMULATION_CPU1_SHIFT 4 +#define OMAP54XX_RST_EMULATION_CPU1_WIDTH 0x1 +#define OMAP54XX_RST_EMULATION_CPU1_MASK (1 << 4) + +/* Used by RM_IVA_RSTST */ +#define OMAP54XX_RST_EMULATION_SEQ1_SHIFT 3 +#define OMAP54XX_RST_EMULATION_SEQ1_WIDTH 0x1 +#define OMAP54XX_RST_EMULATION_SEQ1_MASK (1 << 3) + +/* Used by RM_IVA_RSTST */ +#define OMAP54XX_RST_EMULATION_SEQ2_SHIFT 4 +#define OMAP54XX_RST_EMULATION_SEQ2_WIDTH 0x1 +#define OMAP54XX_RST_EMULATION_SEQ2_MASK (1 << 4) + +/* Used by PRM_RSTCTRL */ +#define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT 1 +#define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH 0x1 +#define OMAP54XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) + +/* Used by PRM_RSTCTRL */ +#define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT 0 +#define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH 0x1 +#define OMAP54XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) + +/* Used by RM_IPU_RSTST */ +#define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT 5 +#define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH 0x1 +#define OMAP54XX_RST_ICECRUSHER_CPU0_MASK (1 << 5) + +/* Used by RM_IPU_RSTST */ +#define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT 6 +#define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH 0x1 +#define OMAP54XX_RST_ICECRUSHER_CPU1_MASK (1 << 6) + +/* Used by RM_IVA_RSTST */ +#define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT 5 +#define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH 0x1 +#define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK (1 << 5) + +/* Used by RM_IVA_RSTST */ +#define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT 6 +#define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH 0x1 +#define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK (1 << 6) + +/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ +#define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT 2 +#define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH 0x1 +#define OMAP54XX_RST_IPU_MMU_CACHE_MASK (1 << 2) + +/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ +#define OMAP54XX_RST_LOGIC_SHIFT 2 +#define OMAP54XX_RST_LOGIC_WIDTH 0x1 +#define OMAP54XX_RST_LOGIC_MASK (1 << 2) + +/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ +#define OMAP54XX_RST_SEQ1_SHIFT 0 +#define OMAP54XX_RST_SEQ1_WIDTH 0x1 +#define OMAP54XX_RST_SEQ1_MASK (1 << 0) + +/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ +#define OMAP54XX_RST_SEQ2_SHIFT 1 +#define OMAP54XX_RST_SEQ2_WIDTH 0x1 +#define OMAP54XX_RST_SEQ2_MASK (1 << 1) + +/* Used by REVISION_PRM */ +#define OMAP54XX_R_RTL_SHIFT 11 +#define OMAP54XX_R_RTL_WIDTH 0x5 +#define OMAP54XX_R_RTL_MASK (0x1f << 11) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_SA_VDD_CORE_L_SHIFT 0 +#define OMAP54XX_SA_VDD_CORE_L_WIDTH 0x7 +#define OMAP54XX_SA_VDD_CORE_L_MASK (0x7f << 0) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_SA_VDD_MM_L_SHIFT 0 +#define OMAP54XX_SA_VDD_MM_L_WIDTH 0x7 +#define OMAP54XX_SA_VDD_MM_L_MASK (0x7f << 0) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_SA_VDD_MPU_L_SHIFT 0 +#define OMAP54XX_SA_VDD_MPU_L_WIDTH 0x7 +#define OMAP54XX_SA_VDD_MPU_L_MASK (0x7f << 0) + +/* Used by REVISION_PRM */ +#define OMAP54XX_SCHEME_SHIFT 30 +#define OMAP54XX_SCHEME_WIDTH 0x2 +#define OMAP54XX_SCHEME_MASK (0x3 << 30) + +/* Used by PRM_VC_CFG_I2C_CLK */ +#define OMAP54XX_SCLH_SHIFT 0 +#define OMAP54XX_SCLH_WIDTH 0x8 +#define OMAP54XX_SCLH_MASK (0xff << 0) + +/* Used by PRM_VC_CFG_I2C_CLK */ +#define OMAP54XX_SCLL_SHIFT 8 +#define OMAP54XX_SCLL_WIDTH 0x8 +#define OMAP54XX_SCLL_MASK (0xff << 8) + +/* Used by PRM_RSTST */ +#define OMAP54XX_SECURE_WDT_RST_SHIFT 4 +#define OMAP54XX_SECURE_WDT_RST_WIDTH 0x1 +#define OMAP54XX_SECURE_WDT_RST_MASK (1 << 4) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT 24 +#define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_SEL_SA_VDD_CORE_L_MASK (1 << 24) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT 24 +#define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_SEL_SA_VDD_MM_L_MASK (1 << 24) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT 24 +#define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_SEL_SA_VDD_MPU_L_MASK (1 << 24) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_SL2_MEM_ONSTATE_SHIFT 18 +#define OMAP54XX_SL2_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_SL2_MEM_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_SL2_MEM_RETSTATE_SHIFT 9 +#define OMAP54XX_SL2_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_SL2_MEM_RETSTATE_MASK (1 << 9) + +/* Used by PM_IVA_PWRSTST */ +#define OMAP54XX_SL2_MEM_STATEST_SHIFT 6 +#define OMAP54XX_SL2_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_SL2_MEM_STATEST_MASK (0x3 << 6) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_SLAVEADDR_SHIFT 0 +#define OMAP54XX_SLAVEADDR_WIDTH 0x7 +#define OMAP54XX_SLAVEADDR_MASK (0x7f << 0) + +/* Used by PRM_SRAM_COUNT */ +#define OMAP54XX_SLPCNT_VALUE_SHIFT 16 +#define OMAP54XX_SLPCNT_VALUE_WIDTH 0x8 +#define OMAP54XX_SLPCNT_VALUE_MASK (0xff << 16) + +/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ +#define OMAP54XX_SMPSWAITTIMEMAX_SHIFT 8 +#define OMAP54XX_SMPSWAITTIMEMAX_WIDTH 0x10 +#define OMAP54XX_SMPSWAITTIMEMAX_MASK (0xffff << 8) + +/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ +#define OMAP54XX_SMPSWAITTIMEMIN_SHIFT 8 +#define OMAP54XX_SMPSWAITTIMEMIN_WIDTH 0x10 +#define OMAP54XX_SMPSWAITTIMEMIN_MASK (0xffff << 8) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT 1 +#define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_SMPS_RA_ERR_CORE_MASK (1 << 1) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_SMPS_RA_ERR_MM_SHIFT 1 +#define OMAP54XX_SMPS_RA_ERR_MM_WIDTH 0x1 +#define OMAP54XX_SMPS_RA_ERR_MM_MASK (1 << 1) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT 1 +#define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_SMPS_RA_ERR_MPU_MASK (1 << 1) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT 0 +#define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_SMPS_SA_ERR_CORE_MASK (1 << 0) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_SMPS_SA_ERR_MM_SHIFT 0 +#define OMAP54XX_SMPS_SA_ERR_MM_WIDTH 0x1 +#define OMAP54XX_SMPS_SA_ERR_MM_MASK (1 << 0) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT 0 +#define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_SMPS_SA_ERR_MPU_MASK (1 << 0) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 +#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT 2 +#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH 0x1 +#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK (1 << 2) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT 2 +#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 2) + +/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ +#define OMAP54XX_SR2EN_SHIFT 0 +#define OMAP54XX_SR2EN_WIDTH 0x1 +#define OMAP54XX_SR2EN_MASK (1 << 0) + +/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ +#define OMAP54XX_SR2_IN_TRANSITION_SHIFT 6 +#define OMAP54XX_SR2_IN_TRANSITION_WIDTH 0x1 +#define OMAP54XX_SR2_IN_TRANSITION_MASK (1 << 6) + +/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ +#define OMAP54XX_SR2_STATUS_SHIFT 3 +#define OMAP54XX_SR2_STATUS_WIDTH 0x2 +#define OMAP54XX_SR2_STATUS_MASK (0x3 << 3) + +/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ +#define OMAP54XX_SR2_WTCNT_VALUE_SHIFT 8 +#define OMAP54XX_SR2_WTCNT_VALUE_WIDTH 0x8 +#define OMAP54XX_SR2_WTCNT_VALUE_MASK (0xff << 8) + +/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ +#define OMAP54XX_SRAMLDO_STATUS_SHIFT 8 +#define OMAP54XX_SRAMLDO_STATUS_WIDTH 0x1 +#define OMAP54XX_SRAMLDO_STATUS_MASK (1 << 8) + +/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ +#define OMAP54XX_SRAM_IN_TRANSITION_SHIFT 9 +#define OMAP54XX_SRAM_IN_TRANSITION_WIDTH 0x1 +#define OMAP54XX_SRAM_IN_TRANSITION_MASK (1 << 9) + +/* Used by PRM_VC_CFG_I2C_MODE */ +#define OMAP54XX_SRMODEEN_SHIFT 4 +#define OMAP54XX_SRMODEEN_WIDTH 0x1 +#define OMAP54XX_SRMODEEN_MASK (1 << 4) + +/* Used by PRM_VOLTSETUP_WARMRESET */ +#define OMAP54XX_STABLE_COUNT_SHIFT 0 +#define OMAP54XX_STABLE_COUNT_WIDTH 0x6 +#define OMAP54XX_STABLE_COUNT_MASK (0x3f << 0) + +/* Used by PRM_VOLTSETUP_WARMRESET */ +#define OMAP54XX_STABLE_PRESCAL_SHIFT 8 +#define OMAP54XX_STABLE_PRESCAL_WIDTH 0x2 +#define OMAP54XX_STABLE_PRESCAL_MASK (0x3 << 8) + +/* Used by PRM_BANDGAP_SETUP */ +#define OMAP54XX_STARTUP_COUNT_SHIFT 0 +#define OMAP54XX_STARTUP_COUNT_WIDTH 0x8 +#define OMAP54XX_STARTUP_COUNT_MASK (0xff << 0) + +/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ +#define OMAP54XX_STARTUP_COUNT_24_31_SHIFT 24 +#define OMAP54XX_STARTUP_COUNT_24_31_WIDTH 0x8 +#define OMAP54XX_STARTUP_COUNT_24_31_MASK (0xff << 24) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT 20 +#define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_TCM1_MEM_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT 10 +#define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_TCM1_MEM_RETSTATE_MASK (1 << 10) + +/* Used by PM_IVA_PWRSTST */ +#define OMAP54XX_TCM1_MEM_STATEST_SHIFT 8 +#define OMAP54XX_TCM1_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_TCM1_MEM_STATEST_MASK (0x3 << 8) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT 22 +#define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_TCM2_MEM_ONSTATE_MASK (0x3 << 22) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT 11 +#define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_TCM2_MEM_RETSTATE_MASK (1 << 11) + +/* Used by PM_IVA_PWRSTST */ +#define OMAP54XX_TCM2_MEM_STATEST_SHIFT 10 +#define OMAP54XX_TCM2_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_TCM2_MEM_STATEST_MASK (0x3 << 10) + +/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ +#define OMAP54XX_TIMEOUT_SHIFT 0 +#define OMAP54XX_TIMEOUT_WIDTH 0x10 +#define OMAP54XX_TIMEOUT_MASK (0xffff << 0) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_TIMEOUTEN_SHIFT 3 +#define OMAP54XX_TIMEOUTEN_WIDTH 0x1 +#define OMAP54XX_TIMEOUTEN_MASK (1 << 3) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_TRANSITION_EN_SHIFT 8 +#define OMAP54XX_TRANSITION_EN_WIDTH 0x1 +#define OMAP54XX_TRANSITION_EN_MASK (1 << 8) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_TRANSITION_ST_SHIFT 8 +#define OMAP54XX_TRANSITION_ST_WIDTH 0x1 +#define OMAP54XX_TRANSITION_ST_MASK (1 << 8) + +/* Used by PRM_DEBUG_TRANS_CFG */ +#define OMAP54XX_TRIGGER_CLEAR_SHIFT 2 +#define OMAP54XX_TRIGGER_CLEAR_WIDTH 0x1 +#define OMAP54XX_TRIGGER_CLEAR_MASK (1 << 2) + +/* Used by PRM_RSTST */ +#define OMAP54XX_TSHUT_CORE_RST_SHIFT 13 +#define OMAP54XX_TSHUT_CORE_RST_WIDTH 0x1 +#define OMAP54XX_TSHUT_CORE_RST_MASK (1 << 13) + +/* Used by PRM_RSTST */ +#define OMAP54XX_TSHUT_MM_RST_SHIFT 12 +#define OMAP54XX_TSHUT_MM_RST_WIDTH 0x1 +#define OMAP54XX_TSHUT_MM_RST_MASK (1 << 12) + +/* Used by PRM_RSTST */ +#define OMAP54XX_TSHUT_MPU_RST_SHIFT 11 +#define OMAP54XX_TSHUT_MPU_RST_WIDTH 0x1 +#define OMAP54XX_TSHUT_MPU_RST_MASK (1 << 11) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_VALID_SHIFT 24 +#define OMAP54XX_VALID_WIDTH 0x1 +#define OMAP54XX_VALID_MASK (1 << 24) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_BYPASSACK_EN_SHIFT 14 +#define OMAP54XX_VC_BYPASSACK_EN_WIDTH 0x1 +#define OMAP54XX_VC_BYPASSACK_EN_MASK (1 << 14) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_BYPASSACK_ST_SHIFT 14 +#define OMAP54XX_VC_BYPASSACK_ST_WIDTH 0x1 +#define OMAP54XX_VC_BYPASSACK_ST_MASK (1 << 14) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_CORE_VPACK_EN_SHIFT 22 +#define OMAP54XX_VC_CORE_VPACK_EN_WIDTH 0x1 +#define OMAP54XX_VC_CORE_VPACK_EN_MASK (1 << 22) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_CORE_VPACK_ST_SHIFT 22 +#define OMAP54XX_VC_CORE_VPACK_ST_WIDTH 0x1 +#define OMAP54XX_VC_CORE_VPACK_ST_MASK (1 << 22) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_MM_VPACK_EN_SHIFT 30 +#define OMAP54XX_VC_MM_VPACK_EN_WIDTH 0x1 +#define OMAP54XX_VC_MM_VPACK_EN_MASK (1 << 30) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_MM_VPACK_ST_SHIFT 30 +#define OMAP54XX_VC_MM_VPACK_ST_WIDTH 0x1 +#define OMAP54XX_VC_MM_VPACK_ST_MASK (1 << 30) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VC_MPU_VPACK_EN_SHIFT 6 +#define OMAP54XX_VC_MPU_VPACK_EN_WIDTH 0x1 +#define OMAP54XX_VC_MPU_VPACK_EN_MASK (1 << 6) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VC_MPU_VPACK_ST_SHIFT 6 +#define OMAP54XX_VC_MPU_VPACK_ST_WIDTH 0x1 +#define OMAP54XX_VC_MPU_VPACK_ST_MASK (1 << 6) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_RAERR_EN_SHIFT 12 +#define OMAP54XX_VC_RAERR_EN_WIDTH 0x1 +#define OMAP54XX_VC_RAERR_EN_MASK (1 << 12) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_RAERR_ST_SHIFT 12 +#define OMAP54XX_VC_RAERR_ST_WIDTH 0x1 +#define OMAP54XX_VC_RAERR_ST_MASK (1 << 12) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_SAERR_EN_SHIFT 11 +#define OMAP54XX_VC_SAERR_EN_WIDTH 0x1 +#define OMAP54XX_VC_SAERR_EN_MASK (1 << 11) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_SAERR_ST_SHIFT 11 +#define OMAP54XX_VC_SAERR_ST_WIDTH 0x1 +#define OMAP54XX_VC_SAERR_ST_MASK (1 << 11) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_TOERR_EN_SHIFT 13 +#define OMAP54XX_VC_TOERR_EN_WIDTH 0x1 +#define OMAP54XX_VC_TOERR_EN_MASK (1 << 13) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_TOERR_ST_SHIFT 13 +#define OMAP54XX_VC_TOERR_ST_WIDTH 0x1 +#define OMAP54XX_VC_TOERR_ST_MASK (1 << 13) + +/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ +#define OMAP54XX_VDDMAX_SHIFT 24 +#define OMAP54XX_VDDMAX_WIDTH 0x8 +#define OMAP54XX_VDDMAX_MASK (0xff << 24) + +/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ +#define OMAP54XX_VDDMIN_SHIFT 16 +#define OMAP54XX_VDDMIN_WIDTH 0x8 +#define OMAP54XX_VDDMIN_MASK (0xff << 16) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT 12 +#define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH 0x1 +#define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK (1 << 12) + +/* Used by PRM_RSTST */ +#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT 8 +#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH 0x1 +#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT 14 +#define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH 0x1 +#define OMAP54XX_VDD_MM_I2C_DISABLE_MASK (1 << 14) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_MM_PRESENCE_SHIFT 9 +#define OMAP54XX_VDD_MM_PRESENCE_WIDTH 0x1 +#define OMAP54XX_VDD_MM_PRESENCE_MASK (1 << 9) + +/* Used by PRM_RSTST */ +#define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT 7 +#define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH 0x1 +#define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK (1 << 7) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT 13 +#define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH 0x1 +#define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK (1 << 13) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_MPU_PRESENCE_SHIFT 8 +#define OMAP54XX_VDD_MPU_PRESENCE_WIDTH 0x1 +#define OMAP54XX_VDD_MPU_PRESENCE_MASK (1 << 8) + +/* Used by PRM_RSTST */ +#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT 6 +#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH 0x1 +#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT 4 +#define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_VFSM_RA_ERR_CORE_MASK (1 << 4) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_VFSM_RA_ERR_MM_SHIFT 4 +#define OMAP54XX_VFSM_RA_ERR_MM_WIDTH 0x1 +#define OMAP54XX_VFSM_RA_ERR_MM_MASK (1 << 4) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT 4 +#define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_VFSM_RA_ERR_MPU_MASK (1 << 4) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT 3 +#define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_VFSM_SA_ERR_CORE_MASK (1 << 3) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_VFSM_SA_ERR_MM_SHIFT 3 +#define OMAP54XX_VFSM_SA_ERR_MM_WIDTH 0x1 +#define OMAP54XX_VFSM_SA_ERR_MM_MASK (1 << 3) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT 3 +#define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_VFSM_SA_ERR_MPU_MASK (1 << 3) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 +#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT 5 +#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH 0x1 +#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK (1 << 5) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT 5 +#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 5) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT 8 +#define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH 0x8 +#define OMAP54XX_VOLRA_VDD_CORE_L_MASK (0xff << 8) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_VOLRA_VDD_MM_L_SHIFT 8 +#define OMAP54XX_VOLRA_VDD_MM_L_WIDTH 0x8 +#define OMAP54XX_VOLRA_VDD_MM_L_MASK (0xff << 8) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT 8 +#define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH 0x8 +#define OMAP54XX_VOLRA_VDD_MPU_L_MASK (0xff << 8) + +/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */ +#define OMAP54XX_VOLTSTATEST_SHIFT 0 +#define OMAP54XX_VOLTSTATEST_WIDTH 0x2 +#define OMAP54XX_VOLTSTATEST_MASK (0x3 << 0) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_VPENABLE_SHIFT 0 +#define OMAP54XX_VPENABLE_WIDTH 0x1 +#define OMAP54XX_VPENABLE_MASK (1 << 0) + +/* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */ +#define OMAP54XX_VPINIDLE_SHIFT 0 +#define OMAP54XX_VPINIDLE_WIDTH 0x1 +#define OMAP54XX_VPINIDLE_MASK (1 << 0) + +/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ +#define OMAP54XX_VPVOLTAGE_SHIFT 0 +#define OMAP54XX_VPVOLTAGE_WIDTH 0x8 +#define OMAP54XX_VPVOLTAGE_MASK (0xff << 0) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT 20 +#define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_EQVALUE_EN_MASK (1 << 20) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT 20 +#define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_EQVALUE_ST_MASK (1 << 20) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT 18 +#define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_MAXVDD_EN_MASK (1 << 18) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT 18 +#define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_MAXVDD_ST_MASK (1 << 18) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT 17 +#define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_MINVDD_EN_MASK (1 << 17) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT 17 +#define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_MINVDD_ST_MASK (1 << 17) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT 19 +#define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT 19 +#define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT 21 +#define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK (1 << 21) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT 21 +#define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK (1 << 21) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT 28 +#define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_EQVALUE_EN_MASK (1 << 28) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT 28 +#define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_EQVALUE_ST_MASK (1 << 28) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT 26 +#define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_MAXVDD_EN_MASK (1 << 26) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT 26 +#define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_MAXVDD_ST_MASK (1 << 26) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_MINVDD_EN_SHIFT 25 +#define OMAP54XX_VP_MM_MINVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_MINVDD_EN_MASK (1 << 25) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_MINVDD_ST_SHIFT 25 +#define OMAP54XX_VP_MM_MINVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_MINVDD_ST_MASK (1 << 25) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT 27 +#define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK (1 << 27) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT 27 +#define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK (1 << 27) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT 24 +#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK (1 << 24) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT 24 +#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK (1 << 24) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT 29 +#define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_TRANXDONE_EN_MASK (1 << 29) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT 29 +#define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_TRANXDONE_ST_MASK (1 << 29) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT 4 +#define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_EQVALUE_EN_MASK (1 << 4) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT 4 +#define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_EQVALUE_ST_MASK (1 << 4) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT 2 +#define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_MAXVDD_EN_MASK (1 << 2) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT 2 +#define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_MAXVDD_ST_MASK (1 << 2) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT 1 +#define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_MINVDD_EN_MASK (1 << 1) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT 1 +#define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_MINVDD_ST_MASK (1 << 1) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT 3 +#define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT 3 +#define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT 5 +#define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK (1 << 5) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT 5 +#define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK (1 << 5) + +/* Used by PRM_SRAM_COUNT */ +#define OMAP54XX_VSETUPCNT_VALUE_SHIFT 8 +#define OMAP54XX_VSETUPCNT_VALUE_WIDTH 0x8 +#define OMAP54XX_VSETUPCNT_VALUE_MASK (0xff << 8) + +/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ +#define OMAP54XX_VSTEPMAX_SHIFT 0 +#define OMAP54XX_VSTEPMAX_WIDTH 0x8 +#define OMAP54XX_VSTEPMAX_MASK (0xff << 0) + +/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ +#define OMAP54XX_VSTEPMIN_SHIFT 0 +#define OMAP54XX_VSTEPMIN_WIDTH 0x8 +#define OMAP54XX_VSTEPMIN_MASK (0xff << 0) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DISPC_DSP_MASK (1 << 2) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DISPC_IPU_MASK (1 << 1) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DISPC_MPU_MASK (1 << 0) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK (1 << 3) + +/* Used by PM_ABE_DMIC_WKDEP */ +#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK (1 << 6) + +/* Used by PM_ABE_DMIC_WKDEP */ +#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_ABE_DMIC_WKDEP */ +#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK (1 << 2) + +/* Used by PM_ABE_DMIC_WKDEP */ +#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK (1 << 6) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT 5 +#define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK (1 << 5) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT 4 +#define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK (1 << 4) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK (1 << 7) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT 10 +#define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK (1 << 10) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT 9 +#define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK (1 << 9) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT 8 +#define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK (1 << 8) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT 11 +#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK (1 << 11) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT 17 +#define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK (1 << 17) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT 16 +#define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK (1 << 16) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT 15 +#define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK (1 << 15) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT 18 +#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK (1 << 18) + +/* Used by PM_WKUPAON_GPIO1_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK (1 << 1) + +/* Used by PM_WKUPAON_GPIO1_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_GPIO1_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO2_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_GPIO2_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO2_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO3_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO3_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO4_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO4_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO5_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO5_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO6_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO6_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO7_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO8_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 +#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT 14 +#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK (1 << 14) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT 13 +#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK (1 << 13) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 +#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) + +/* Used by PM_L3INIT_HSI_WKDEP */ +#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK (1 << 6) + +/* Used by PM_L3INIT_HSI_WKDEP */ +#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_HSI_WKDEP */ +#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C1_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_L4PER_I2C1_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_I2C1_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C2_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_L4PER_I2C2_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_I2C2_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C3_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_L4PER_I2C3_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_I2C3_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C4_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_L4PER_I2C4_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_I2C4_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C5_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_KBD_WKDEP */ +#define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_KBD_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCASP_WKDEP */ +#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK (1 << 6) + +/* Used by PM_ABE_MCASP_WKDEP */ +#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_ABE_MCASP_WKDEP */ +#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCASP_WKDEP */ +#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCBSP1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCBSP1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCBSP1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) + +/* Used by PM_ABE_MCBSP2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCBSP2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCBSP2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) + +/* Used by PM_ABE_MCBSP3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCBSP3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCBSP3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) + +/* Used by PM_ABE_MCPDM_WKDEP */ +#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK (1 << 6) + +/* Used by PM_ABE_MCPDM_WKDEP */ +#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_ABE_MCPDM_WKDEP */ +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCPDM_WKDEP */ +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK (1 << 2) + +/* Used by PM_L4PER_MCSPI1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_MCSPI1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MCSPI2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_MCSPI2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MCSPI3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MCSPI4_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI4_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) + +/* Used by PM_L3INIT_MMC1_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC1_DSP_MASK (1 << 2) + +/* Used by PM_L3INIT_MMC1_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC1_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_MMC1_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC1_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_MMC1_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK (1 << 3) + +/* Used by PM_L3INIT_MMC2_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC2_DSP_MASK (1 << 2) + +/* Used by PM_L3INIT_MMC2_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC2_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_MMC2_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC2_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_MMC2_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MMC3_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC3_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_MMC3_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC3_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MMC3_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MMC4_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC4_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MMC4_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MMC5_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC5_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MMC5_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK (1 << 3) + +/* Used by PM_L3INIT_SATA_WKDEP */ +#define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SATA_MPU_MASK (1 << 0) + +/* Used by PM_ABE_SLIMBUS1_WKDEP */ +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK (1 << 6) + +/* Used by PM_ABE_SLIMBUS1_WKDEP */ +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_ABE_SLIMBUS1_WKDEP */ +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK (1 << 2) + +/* Used by PM_ABE_SLIMBUS1_WKDEP */ +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK (1 << 1) + +/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK (1 << 0) + +/* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */ +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK (1 << 0) + +/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */ +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER10_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER11_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_TIMER11_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_TIMER12_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_TIMER1_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER2_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER3_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_TIMER3_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER4_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_TIMER4_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK (1 << 0) + +/* Used by PM_ABE_TIMER5_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK (1 << 2) + +/* Used by PM_ABE_TIMER5_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK (1 << 0) + +/* Used by PM_ABE_TIMER6_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK (1 << 2) + +/* Used by PM_ABE_TIMER6_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK (1 << 0) + +/* Used by PM_ABE_TIMER7_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK (1 << 2) + +/* Used by PM_ABE_TIMER7_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK (1 << 0) + +/* Used by PM_ABE_TIMER8_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK (1 << 2) + +/* Used by PM_ABE_TIMER8_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER9_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_TIMER9_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART1_WKDEP */ +#define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART1_WKDEP */ +#define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART1_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART2_WKDEP */ +#define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART2_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART2_WKDEP */ +#define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART2_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART3_WKDEP */ +#define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART3_DSP_MASK (1 << 2) + +/* Used by PM_L4PER_UART3_WKDEP */ +#define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART3_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_UART3_WKDEP */ +#define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART3_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART3_WKDEP */ +#define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART3_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART4_WKDEP */ +#define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART4_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART4_WKDEP */ +#define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART4_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART5_WKDEP */ +#define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART5_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART5_WKDEP */ +#define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART5_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART6_WKDEP */ +#define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART6_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART6_WKDEP */ +#define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART6_SDMA_MASK (1 << 3) + +/* Used by PM_L3INIT_UNIPRO2_WKDEP */ +#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */ +#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK (1 << 0) + +/* Used by PM_ABE_WD_TIMER3_WKDEP */ +#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK (1 << 0) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_WUCLK_CTRL_SHIFT 8 +#define OMAP54XX_WUCLK_CTRL_WIDTH 0x1 +#define OMAP54XX_WUCLK_CTRL_MASK (1 << 8) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_WUCLK_STATUS_SHIFT 9 +#define OMAP54XX_WUCLK_STATUS_WIDTH 0x1 +#define OMAP54XX_WUCLK_STATUS_MASK (1 << 9) + +/* Used by REVISION_PRM */ +#define OMAP54XX_X_MAJOR_SHIFT 8 +#define OMAP54XX_X_MAJOR_WIDTH 0x3 +#define OMAP54XX_X_MAJOR_MASK (0x7 << 8) + +/* Used by REVISION_PRM */ +#define OMAP54XX_Y_MINOR_SHIFT 0 +#define OMAP54XX_Y_MINOR_WIDTH 0x6 +#define OMAP54XX_Y_MINOR_MASK (0x3f << 0) +#endif
arch/arm/mach-omap2/prm54xx.h new file +447 -0
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1.7.9.5
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PATCH 2/10 ARM: OMAP5: CM: Add OMAP54XX register and bitfield files
In reply to Santosh ShilimkarFrom: Benoit Cousson <[email protected]>
Add the new defines for OMAP54XX cm registers.
Cc Paul Walmsley <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
Signed-off-by Benoit Cousson <[email protected]>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by Santosh Shilimkar <[email protected]>
--- arch/arm/mach-omap2/cm-regbits-54xx.h | 1737 +++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/cm1_54xx.h | 216 ++++ arch/arm/mach-omap2/cm2_54xx.h | 392 ++++++++ 3 files changed, 2345 insertions(+) create mode 100644 arch/arm/mach-omap2/cm-regbits-54xx.h create mode 100644 arch/arm/mach-omap2/cm1_54xx.h create mode 100644 arch/arm/mach-omap2/cm2_54xx.h
arch/arm/mach-omap2/cm-regbits-54xx.h new file +1737 -0
@@ -0,0 +1,1737 @@ +/* +* OMAP54xx Clock Management register bits +* +* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com +* +* Paul Walmsley (paul at pwsan.com) +* Rajendra Nayak (rnayak at ti.com) +* Benoit Cousson (b-cousson at ti.com) +* +* This file is automatically generated from the OMAP hardware databases. +* We respectfully ask that any modifications to this file be coordinated +* with the public linux-omap at vger.kernel.org mailing list and the +* authors above to ensure that the autogeneration scripts are kept +* up-to-date with the file contents. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H +#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H + +/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */ +#define OMAP54XX_ABE_DYNDEP_SHIFT 3 +#define OMAP54XX_ABE_DYNDEP_WIDTH 0x1 +#define OMAP54XX_ABE_DYNDEP_MASK (1 << 3) + +/* +* Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, +* CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP +*/ +#define OMAP54XX_ABE_STATDEP_SHIFT 3 +#define OMAP54XX_ABE_STATDEP_WIDTH 0x1 +#define OMAP54XX_ABE_STATDEP_MASK (1 << 3) + +/* +* Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA, +* CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1, +* CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB +*/ +#define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0 +#define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3 +#define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) + +/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_C2C_DYNDEP_SHIFT 18 +#define OMAP54XX_C2C_DYNDEP_WIDTH 0x1 +#define OMAP54XX_C2C_DYNDEP_MASK (1 << 18) + +/* Used by CM_MPU_STATICDEP */ +#define OMAP54XX_C2C_STATDEP_SHIFT 18 +#define OMAP54XX_C2C_STATDEP_WIDTH 0x1 +#define OMAP54XX_C2C_STATDEP_MASK (1 << 18) + +/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_CAM_DYNDEP_SHIFT 9 +#define OMAP54XX_CAM_DYNDEP_WIDTH 0x1 +#define OMAP54XX_CAM_DYNDEP_MASK (1 << 9) + +/* +* Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, +* CM_MPU_STATICDEP +*/ +#define OMAP54XX_CAM_STATDEP_SHIFT 9 +#define OMAP54XX_CAM_STATDEP_WIDTH 0x1 +#define OMAP54XX_CAM_STATDEP_MASK (1 << 9) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13) + +/* Used by CM_C2C_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9) + +/* Used by CM_C2C_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10) + +/* Used by CM_C2C_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9) + +/* Used by CM_CUSTEFUSE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8) + +/* Used by CM_CUSTEFUSE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9) + +/* Used by CM_EMIF_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9) + +/* Used by CM_DMA_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8) + +/* Used by CM_DSP_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10) + +/* Used by CM_EMIF_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8) + +/* Used by CM_EMIF_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11) + +/* Used by CM_EMIF_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10) + +/* Used by CM_EMU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) + +/* Used by CM_GPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9) + +/* Used by CM_GPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10) + +/* Used by CM_GPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 +#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 +#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 +#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 +#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6 +#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7 +#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16 +#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16) + +/* Used by CM_IPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8) + +/* Used by CM_IVA_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28 +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29 +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11) + +/* Used by CM_L3INSTR_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9) + +/* Used by CM_L3INSTR_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L3INSTR_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10) + +/* Used by CM_L3MAIN1_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L3MAIN2_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L4CFG_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8) + +/* Used by CM_L4SEC_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L4SEC_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2 +#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17 +#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18 +#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18) + +/* Used by CM_MPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15 +#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3 +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4 +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15 +#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 +#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 +#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 +#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19 +#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 +#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 +#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 +#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 +#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31 +#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 +#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 +#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13) + +/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */ +#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8 +#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1 +#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8) + +/* +* Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, +* CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, +* CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, +* CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL +*/ +#define OMAP54XX_CLKSEL_SHIFT 24 +#define OMAP54XX_CLKSEL_WIDTH 0x1 +#define OMAP54XX_CLKSEL_MASK (1 << 24) + +/* +* Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF, +* CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON +*/ +#define OMAP54XX_CLKSEL_0_0_SHIFT 0 +#define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 +#define OMAP54XX_CLKSEL_0_0_MASK (1 << 0) + +/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ +#define OMAP54XX_CLKSEL_0_1_SHIFT 0 +#define OMAP54XX_CLKSEL_0_1_WIDTH 0x2 +#define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0) + +/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */ +#define OMAP54XX_CLKSEL_24_25_SHIFT 24 +#define OMAP54XX_CLKSEL_24_25_WIDTH 0x2 +#define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24) + +/* Used by CM_MPU_MPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26 +#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 +#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) + +/* Used by CM_ABE_AESS_CLKCTRL */ +#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 +#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24) + +/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */ +#define OMAP54XX_CLKSEL_DIV_SHIFT 25 +#define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 +#define OMAP54XX_CLKSEL_DIV_MASK (1 << 25) + +/* Used by CM_MPU_MPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2 +#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24) + +/* Used by CM_CAM_FDIF_CLKCTRL */ +#define OMAP54XX_CLKSEL_FCLK_SHIFT 24 +#define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24) + +/* Used by CM_GPU_GPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 +#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) + +/* Used by CM_GPU_GPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 +#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) + +/* Used by CM_GPU_GPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26 +#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26) + +/* +* Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, +* CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL +*/ +#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 +#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 +#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26) + +/* Used by CM_CLKSEL_CORE */ +#define OMAP54XX_CLKSEL_L3_SHIFT 4 +#define OMAP54XX_CLKSEL_L3_WIDTH 0x1 +#define OMAP54XX_CLKSEL_L3_MASK (1 << 4) + +/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ +#define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1 +#define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1 +#define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1) + +/* Used by CM_CLKSEL_CORE */ +#define OMAP54XX_CLKSEL_L4_SHIFT 8 +#define OMAP54XX_CLKSEL_L4_WIDTH 0x1 +#define OMAP54XX_CLKSEL_L4_MASK (1 << 8) + +/* Used by CM_EMIF_EMIF1_CLKCTRL */ +#define OMAP54XX_CLKSEL_LL_SHIFT 24 +#define OMAP54XX_CLKSEL_LL_WIDTH 0x1 +#define OMAP54XX_CLKSEL_LL_MASK (1 << 24) + +/* Used by CM_CLKSEL_ABE */ +#define OMAP54XX_CLKSEL_OPP_SHIFT 0 +#define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 +#define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0) + +/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */ +#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24 +#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1 +#define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24) + +/* +* Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, +* CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL +*/ +#define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 +#define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 +#define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24) + +/* +* Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL, +* CM_L3INIT_MMC2_CLKCTRL +*/ +#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 +#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 +#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 +#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 +#define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 +#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 +#define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25) + +/* +* Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, +* CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, +* CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, +* CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, +* CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE, +* CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, +* CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB, +* CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER +*/ +#define OMAP54XX_CLKST_SHIFT 9 +#define OMAP54XX_CLKST_WIDTH 0x1 +#define OMAP54XX_CLKST_MASK (1 << 9) + +/* +* Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL, +* CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL, +* CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL, +* CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL, +* CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL, +* CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, +* CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL +*/ +#define OMAP54XX_CLKTRCTRL_SHIFT 0 +#define OMAP54XX_CLKTRCTRL_WIDTH 0x2 +#define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0) + +/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */ +#define OMAP54XX_CLKX2ST_SHIFT 11 +#define OMAP54XX_CLKX2ST_WIDTH 0x1 +#define OMAP54XX_CLKX2ST_MASK (1 << 11) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_COREAON_DYNDEP_SHIFT 16 +#define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1 +#define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16) + +/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_COREAON_STATDEP_SHIFT 16 +#define OMAP54XX_COREAON_STATDEP_WIDTH 0x1 +#define OMAP54XX_COREAON_STATDEP_MASK (1 << 16) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17 +#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1 +#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17) + +/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17 +#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1 +#define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_CUSTOM_SHIFT 6 +#define OMAP54XX_CUSTOM_WIDTH 0x2 +#define OMAP54XX_CUSTOM_MASK (0x3 << 6) + +/* +* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, +* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, +* CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB +*/ +#define OMAP54XX_DCC_EN_SHIFT 22 +#define OMAP54XX_DCC_EN_WIDTH 0x1 +#define OMAP54XX_DCC_EN_MASK (1 << 22) + +/* +* Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS, +* CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS, +* CM_CORE_AON_DEBUG_L4SEC_FD_TRANS +*/ +#define OMAP54XX_CM_DEBUG_OUT_SHIFT 0 +#define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd +#define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0) + +/* +* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS, +* CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS +*/ +#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 +#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) + +/* +* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS, +* CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS +*/ +#define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9 +#define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0) + +/* +* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS, +* CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS +*/ +#define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5 +#define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0) + +/* +* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS, +* CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS +*/ +#define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6 +#define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0) + +/* +* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS, +* CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS +*/ +#define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb +#define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0) + +/* +* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS, +* CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS +*/ +#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 +#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */ +#define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14 +#define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa +#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */ +#define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b +#define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe +#define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */ +#define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16 +#define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0) + +/* +* Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, +* CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, +* CM_SSC_DELTAMSTEP_DPLL_PER +*/ +#define OMAP54XX_DELTAMSTEP_SHIFT 0 +#define OMAP54XX_DELTAMSTEP_WIDTH 0x14 +#define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0) + +/* +* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1, +* CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB +*/ +#define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0 +#define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15 +#define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0) + +/* +* Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, +* CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, +* CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, +* CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, +* CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE +*/ +#define OMAP54XX_DIVHS_SHIFT 0 +#define OMAP54XX_DIVHS_WIDTH 0x6 +#define OMAP54XX_DIVHS_MASK (0x3f << 0) + +/* +* Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, +* CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE, +* CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER +*/ +#define OMAP54XX_DIVHS_0_4_SHIFT 0 +#define OMAP54XX_DIVHS_0_4_WIDTH 0x5 +#define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) + +/* +* Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, +* CM_DIV_M2_DPLL_USB +*/ +#define OMAP54XX_DIVHS_0_6_SHIFT 0 +#define OMAP54XX_DIVHS_0_6_WIDTH 0x7 +#define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) + +/* Used by CM_DLL_CTRL */ +#define OMAP54XX_DLL_OVERRIDE_SHIFT 0 +#define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1 +#define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0) + +/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2 +#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1 +#define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2) + +/* Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_DLL_RESET_SHIFT 3 +#define OMAP54XX_DLL_RESET_WIDTH 0x1 +#define OMAP54XX_DLL_RESET_MASK (1 << 3) + +/* +* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, +* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, +* CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB +*/ +#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23 +#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1 +#define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23) + +/* Used by CM_CLKSEL_DPLL_CORE */ +#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 +#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 +#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) + +/* Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8 +#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3 +#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) + +/* Used by CM_SHADOW_FREQ_CONFIG2 */ +#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2 +#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6 +#define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2) + +/* Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11 +#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5 +#define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11) + +/* +* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, +* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER +*/ +#define OMAP54XX_DPLL_DIV_SHIFT 0 +#define OMAP54XX_DPLL_DIV_WIDTH 0x7 +#define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) + +/* +* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1, +* CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB +*/ +#define OMAP54XX_DPLL_DIV_0_7_SHIFT 0 +#define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8 +#define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0) + +/* +* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, +* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER +*/ +#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) + +/* +* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, +* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, +* CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB +*/ +#define OMAP54XX_DPLL_EN_SHIFT 0 +#define OMAP54XX_DPLL_EN_WIDTH 0x3 +#define OMAP54XX_DPLL_EN_MASK (0x7 << 0) + +/* +* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, +* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER +*/ +#define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10 +#define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) + +/* +* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, +* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER +*/ +#define OMAP54XX_DPLL_MULT_SHIFT 8 +#define OMAP54XX_DPLL_MULT_WIDTH 0xb +#define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) + +/* +* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1, +* CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB +*/ +#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8 +#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc +#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8) + +/* +* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, +* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER +*/ +#define OMAP54XX_DPLL_REGM4XEN_SHIFT 11 +#define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1 +#define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) + +/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ +#define OMAP54XX_DPLL_SD_DIV_SHIFT 24 +#define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8 +#define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) + +/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ +#define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21 +#define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1 +#define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21) + +/* +* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, +* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, +* CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB +*/ +#define OMAP54XX_DPLL_SSC_ACK_SHIFT 13 +#define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1 +#define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13) + +/* +* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, +* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, +* CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB +*/ +#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 +#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 +#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) + +/* +* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, +* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, +* CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB +*/ +#define OMAP54XX_DPLL_SSC_EN_SHIFT 12 +#define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_DSP_DYNDEP_SHIFT 1 +#define OMAP54XX_DSP_DYNDEP_WIDTH 0x1 +#define OMAP54XX_DSP_DYNDEP_MASK (1 << 1) + +/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_DSP_STATDEP_SHIFT 1 +#define OMAP54XX_DSP_STATDEP_WIDTH 0x1 +#define OMAP54XX_DSP_STATDEP_MASK (1 << 1) + +/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +#define OMAP54XX_DSS_DYNDEP_SHIFT 8 +#define OMAP54XX_DSS_DYNDEP_WIDTH 0x1 +#define OMAP54XX_DSS_DYNDEP_MASK (1 << 8) + +/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_DSS_STATDEP_SHIFT 8 +#define OMAP54XX_DSS_STATDEP_WIDTH 0x1 +#define OMAP54XX_DSS_STATDEP_MASK (1 << 8) + +/* +* Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, +* CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP +*/ +#define OMAP54XX_EMIF_DYNDEP_SHIFT 4 +#define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1 +#define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4) + +/* +* Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, +* CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, +* CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, +* CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP +*/ +#define OMAP54XX_EMIF_STATDEP_SHIFT 4 +#define OMAP54XX_EMIF_STATDEP_WIDTH 0x1 +#define OMAP54XX_EMIF_STATDEP_MASK (1 << 4) + +/* Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_FREQ_UPDATE_SHIFT 0 +#define OMAP54XX_FREQ_UPDATE_WIDTH 0x1 +#define OMAP54XX_FREQ_UPDATE_MASK (1 << 0) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_FUNC_SHIFT 16 +#define OMAP54XX_FUNC_WIDTH 0xc +#define OMAP54XX_FUNC_MASK (0xfff << 16) + +/* Used by CM_SHADOW_FREQ_CONFIG2 */ +#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0 +#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1 +#define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0) + +/* Used by CM_L3MAIN2_DYNAMICDEP */ +#define OMAP54XX_GPU_DYNDEP_SHIFT 10 +#define OMAP54XX_GPU_DYNDEP_WIDTH 0x1 +#define OMAP54XX_GPU_DYNDEP_MASK (1 << 10) + +/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_GPU_STATDEP_SHIFT 10 +#define OMAP54XX_GPU_STATDEP_WIDTH 0x1 +#define OMAP54XX_GPU_STATDEP_MASK (1 << 10) + +/* +* Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, +* CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, +* CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, +* CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, +* CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, +* CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, +* CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, +* CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, +* CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, +* CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, +* CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, +* CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, +* CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, +* CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, +* CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, +* CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, +* CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, +* CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, +* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, +* CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, +* CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, +* CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, +* CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, +* CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, +* CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, +* CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, +* CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, +* CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, +* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, +* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, +* CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, +* CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, +* CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, +* CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, +* CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, +* CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, +* CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, +* CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, +* CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, +* CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, +* CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, +* CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, +* CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, +* CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, +* CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, +* CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, +* CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, +* CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL +*/ +#define OMAP54XX_IDLEST_SHIFT 16 +#define OMAP54XX_IDLEST_WIDTH 0x2 +#define OMAP54XX_IDLEST_MASK (0x3 << 16) + +/* Used by CM_L3MAIN2_DYNAMICDEP */ +#define OMAP54XX_IPU_DYNDEP_SHIFT 0 +#define OMAP54XX_IPU_DYNDEP_WIDTH 0x1 +#define OMAP54XX_IPU_DYNDEP_MASK (1 << 0) + +/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_IPU_STATDEP_SHIFT 0 +#define OMAP54XX_IPU_STATDEP_WIDTH 0x1 +#define OMAP54XX_IPU_STATDEP_MASK (1 << 0) + +/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */ +#define OMAP54XX_IVA_DYNDEP_SHIFT 2 +#define OMAP54XX_IVA_DYNDEP_WIDTH 0x1 +#define OMAP54XX_IVA_DYNDEP_MASK (1 << 2) + +/* +* Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, +* CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, +* CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP +*/ +#define OMAP54XX_IVA_STATDEP_SHIFT 2 +#define OMAP54XX_IVA_STATDEP_WIDTH 0x1 +#define OMAP54XX_IVA_STATDEP_MASK (1 << 2) + +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +#define OMAP54XX_L3INIT_DYNDEP_SHIFT 7 +#define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7) + +/* +* Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, +* CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP +*/ +#define OMAP54XX_L3INIT_STATDEP_SHIFT 7 +#define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1 +#define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7) + +/* +* Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, +* CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP +*/ +#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5 +#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5) + +/* +* Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, +* CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, +* CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, +* CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP +*/ +#define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 +#define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1 +#define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5) + +/* +* Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP, +* CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP, +* CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, +* CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP +*/ +#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6 +#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6) + +/* +* Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, +* CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, +* CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, +* CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP +*/ +#define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 +#define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1 +#define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6) + +/* Used by CM_L3MAIN1_DYNAMICDEP */ +#define OMAP54XX_L4CFG_DYNDEP_SHIFT 12 +#define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12) + +/* +* Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, +* CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP +*/ +#define OMAP54XX_L4CFG_STATDEP_SHIFT 12 +#define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1 +#define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12) + +/* Used by CM_L3MAIN2_DYNAMICDEP */ +#define OMAP54XX_L4PER_DYNDEP_SHIFT 13 +#define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13) + +/* +* Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, +* CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, +* CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP +*/ +#define OMAP54XX_L4PER_STATDEP_SHIFT 13 +#define OMAP54XX_L4PER_STATDEP_WIDTH 0x1 +#define OMAP54XX_L4PER_STATDEP_MASK (1 << 13) + +/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +#define OMAP54XX_L4SEC_DYNDEP_SHIFT 14 +#define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14) + +/* +* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, +* CM_MPU_STATICDEP +*/ +#define OMAP54XX_L4SEC_STATDEP_SHIFT 14 +#define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1 +#define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14) + +/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21 +#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1 +#define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21) + +/* Used by CM_MPU_STATICDEP */ +#define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21 +#define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1 +#define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21) + +/* +* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, +* CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, +* CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, +* CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB +*/ +#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8 +#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3 +#define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) + +/* +* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, +* CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, +* CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, +* CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB +*/ +#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0 +#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7 +#define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) + +/* +* Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, +* CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, +* CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, +* CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, +* CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, +* CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, +* CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, +* CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, +* CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, +* CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, +* CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, +* CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, +* CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, +* CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, +* CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, +* CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, +* CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, +* CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, +* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, +* CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, +* CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, +* CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, +* CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, +* CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, +* CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, +* CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, +* CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, +* CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, +* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, +* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, +* CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, +* CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, +* CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, +* CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, +* CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, +* CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, +* CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, +* CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, +* CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, +* CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, +* CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, +* CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, +* CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, +* CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, +* CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, +* CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, +* CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, +* CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL +*/ +#define OMAP54XX_MODULEMODE_SHIFT 0 +#define OMAP54XX_MODULEMODE_WIDTH 0x2 +#define OMAP54XX_MODULEMODE_MASK (0x3 << 0) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_MPU_DYNDEP_SHIFT 19 +#define OMAP54XX_MPU_DYNDEP_WIDTH 0x1 +#define OMAP54XX_MPU_DYNDEP_MASK (1 << 19) + +/* Used by CM_DSS_DSS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11) + +/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8) + +/* Used by CM_DSS_DSS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) + +/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8) + +/* Used by CM_CAM_ISS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8) + +/* +* Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, +* CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, +* CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL +*/ +#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8) + +/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8) + +/* Used by CM_DSS_DSS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8) + +/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8) + +/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9) + +/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10 +#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15 +#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6) + +/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8) + +/* Used by CM_L3INIT_SATA_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8) + +/* Used by CM_WKUPAON_SCRM_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8) + +/* Used by CM_WKUPAON_SCRM_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9) + +/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 +#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11) + +/* Used by CM_DSS_DSS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 +#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10) + +/* Used by CM_MIPIEXT_LLI_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8) + +/* Used by CM_MIPIEXT_LLI_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9) + +/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) + +/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) + +/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 +#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 +#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) + +/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */ +#define OMAP54XX_OUTPUT_SHIFT 0 +#define OMAP54XX_OUTPUT_WIDTH 0x20 +#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) + +/* Used by CM_CLKSEL_ABE */ +#define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 +#define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1 +#define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8) + +/* Used by CM_RESTORE_ST */ +#define OMAP54XX_PHASE1_COMPLETED_SHIFT 0 +#define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1 +#define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0) + +/* Used by CM_RESTORE_ST */ +#define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1 +#define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1 +#define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1) + +/* Used by CM_RESTORE_ST */ +#define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2 +#define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1 +#define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2) + +/* Used by CM_DYN_DEP_PRESCAL */ +#define OMAP54XX_PRESCAL_SHIFT 0 +#define OMAP54XX_PRESCAL_WIDTH 0x6 +#define OMAP54XX_PRESCAL_MASK (0x3f << 0) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_R_RTL_SHIFT 11 +#define OMAP54XX_R_RTL_WIDTH 0x5 +#define OMAP54XX_R_RTL_MASK (0x1f << 11) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OMAP54XX_SAR_MODE_SHIFT 4 +#define OMAP54XX_SAR_MODE_WIDTH 0x1 +#define OMAP54XX_SAR_MODE_MASK (1 << 4) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_SCHEME_SHIFT 30 +#define OMAP54XX_SCHEME_WIDTH 0x2 +#define OMAP54XX_SCHEME_MASK (0x3 << 30) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_SDMA_DYNDEP_SHIFT 11 +#define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1 +#define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11) + +/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_SDMA_STATDEP_SHIFT 11 +#define OMAP54XX_SDMA_STATDEP_WIDTH 0x1 +#define OMAP54XX_SDMA_STATDEP_MASK (1 << 11) + +/* Used by CM_CORE_AON_DEBUG_CFG */ +#define OMAP54XX_SEL0_SHIFT 0 +#define OMAP54XX_SEL0_WIDTH 0x7 +#define OMAP54XX_SEL0_MASK (0x7f << 0) + +/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */ +#define OMAP54XX_SEL0_0_7_SHIFT 0 +#define OMAP54XX_SEL0_0_7_WIDTH 0x8 +#define OMAP54XX_SEL0_0_7_MASK (0xff << 0) + +/* Used by CM_CORE_AON_DEBUG_CFG */ +#define OMAP54XX_SEL1_SHIFT 8 +#define OMAP54XX_SEL1_WIDTH 0x7 +#define OMAP54XX_SEL1_MASK (0x7f << 8) + +/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */ +#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8 +#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8 +#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8) + +/* Used by CM_CORE_AON_DEBUG_CFG */ +#define OMAP54XX_SEL2_SHIFT 16 +#define OMAP54XX_SEL2_WIDTH 0x7 +#define OMAP54XX_SEL2_MASK (0x7f << 16) + +/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */ +#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16 +#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8 +#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16) + +/* Used by CM_CORE_AON_DEBUG_CFG */ +#define OMAP54XX_SEL3_SHIFT 24 +#define OMAP54XX_SEL3_WIDTH 0x7 +#define OMAP54XX_SEL3_MASK (0x7f << 24) + +/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */ +#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24 +#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8 +#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24) + +/* Used by CM_CLKSEL_ABE */ +#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 +#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1 +#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10) + +/* +* Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL, +* CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL, +* CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, +* CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL, +* CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, +* CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL, +* CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL, +* CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL, +* CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL +*/ +#define OMAP54XX_STBYST_SHIFT 18 +#define OMAP54XX_STBYST_WIDTH 0x1 +#define OMAP54XX_STBYST_MASK (1 << 18) + +/* +* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, +* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, +* CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB +*/ +#define OMAP54XX_ST_DPLL_CLK_SHIFT 0 +#define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1 +#define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) + +/* +* Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2, +* CM_CLKDCOLDO_DPLL_USB +*/ +#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9 +#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1 +#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9) + +/* +* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, +* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, +* CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB +*/ +#define OMAP54XX_ST_DPLL_INIT_SHIFT 4 +#define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1 +#define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4) + +/* +* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, +* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, +* CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB +*/ +#define OMAP54XX_ST_DPLL_MODE_SHIFT 1 +#define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3 +#define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1) + +/* Used by CM_CLKSEL_SYS */ +#define OMAP54XX_SYS_CLKSEL_SHIFT 0 +#define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 +#define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0) + +/* +* Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP, +* CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, +* CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP, +* CM_MPU_DYNAMICDEP +*/ +#define OMAP54XX_WINDOWSIZE_SHIFT 24 +#define OMAP54XX_WINDOWSIZE_WIDTH 0x4 +#define OMAP54XX_WINDOWSIZE_MASK (0xf << 24) + +/* Used by CM_L3MAIN1_DYNAMICDEP */ +#define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15 +#define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1 +#define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15) + +/* +* Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, +* CM_L3INIT_STATICDEP, CM_MPU_STATICDEP +*/ +#define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 +#define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1 +#define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_X_MAJOR_SHIFT 8 +#define OMAP54XX_X_MAJOR_WIDTH 0x3 +#define OMAP54XX_X_MAJOR_MASK (0x7 << 8) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_Y_MINOR_SHIFT 0 +#define OMAP54XX_Y_MINOR_WIDTH 0x6 +#define OMAP54XX_Y_MINOR_MASK (0x3f << 0) +#endif
arch/arm/mach-omap2/cm1_54xx.h new file +216 -0
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arch/arm/mach-omap2/cm2_54xx.h new file +392 -0
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Signature · 1 line
1.7.9.5
PATCH 3/10 ARM: OMAP5: PRCM: Add OMAP54XX local MPU PRCM registers
In reply to Santosh ShilimkarFrom: Benoit Cousson <[email protected]>
Add the PRCM MPU registers for OMAP54XX platforms.
Cc Paul Walmsley <[email protected]>
Signed-off-by Benoit Cousson <[email protected]>
[[email protected]: Generated es2.0 data]
Signed-off-by Santosh Shilimkar <[email protected]>
--- arch/arm/mach-omap2/prcm44xx.h | 6 +++ arch/arm/mach-omap2/prcm_mpu54xx.h | 92 ++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 arch/arm/mach-omap2/prcm_mpu54xx.h
arch/arm/mach-omap2/prcm44xx.h +6 -0
@@ -32,6 +32,12 @@#define OMAP4430_SCRM_PARTITION 4#define OMAP4430_PRCM_MPU_PARTITION 5 +#define OMAP54XX_PRM_PARTITION 1 +#define OMAP54XX_CM_CORE_AON_PARTITION 2 +#define OMAP54XX_CM_CORE_PARTITION 3 +#define OMAP54XX_SCRM_PARTITION 4 +#define OMAP54XX_PRCM_MPU_PARTITION 5 +/* * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition * IDs, plus one
arch/arm/mach-omap2/prcm_mpu54xx.h new file +92 -0
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Signature · 1 line
1.7.9.5
PATCH 4/10 ARM: OMAP5: SCRM: Add OMAP54XX header file.
In reply to Santosh ShilimkarFrom: Benoit Cousson <[email protected]>
Adding the OMAP5 specific header for SCRM module.
Cc Paul Walmsley <[email protected]>
Signed-off-by Benoit Cousson <[email protected]>
[[email protected]: Generated es2.0 data]
Signed-off-by Santosh Shilimkar <[email protected]>
--- arch/arm/mach-omap2/scrm54xx.h | 231 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 231 insertions(+) create mode 100644 arch/arm/mach-omap2/scrm54xx.h
arch/arm/mach-omap2/scrm54xx.h new file +231 -0
@@ -0,0 +1,231 @@ +/* +* OMAP54XX SCRM registers and bitfields +* +* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com +* +* Benoit Cousson ([email protected]) +* +* This file is automatically generated from the OMAP hardware databases. +* We respectfully ask that any modifications to this file be coordinated +* with the public [email protected] mailing list and the +* authors above to ensure that the autogeneration scripts are kept +* up-to-date with the file contents. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H +#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H + +#define OMAP5_SCRM_BASE 0x4ae0a000 + +#define OMAP54XX_SCRM_REGADDR (reg) \ + OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg)) + +/* SCRM */ + +/* SCRM.SCRM register offsets */ +#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000 +#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000) +#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100 +#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100) +#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104 +#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104) +#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110 +#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110) +#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118 +#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118) +#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c +#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c) +#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200 +#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200) +#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204 +#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204) +#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208 +#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208) +#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210 +#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210) +#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214 +#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214) +#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218 +#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218) +#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c +#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c) +#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220 +#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220) +#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224 +#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224) +#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234 +#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234) +#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310 +#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310) +#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314 +#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314) +#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318 +#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318) +#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c +#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c) +#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320 +#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320) +#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324 +#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324) +#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400 +#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400) +#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418 +#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418) +#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c +#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c) +#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 +#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420) +#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510 +#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510) +#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514 +#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514) +#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518 +#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518) +#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c +#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c) + +/* +* Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, +* AUXCLKREQ5, D2DCLKREQ +*/ +#define OMAP5_ACCURACY_SHIFT 1 +#define OMAP5_ACCURACY_WIDTH 0x1 +#define OMAP5_ACCURACY_MASK (1 << 1) + +/* Used by APEWARMRSTST */ +#define OMAP5_APEWARMRSTST_SHIFT 1 +#define OMAP5_APEWARMRSTST_WIDTH 0x1 +#define OMAP5_APEWARMRSTST_MASK (1 << 1) + +/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ +#define OMAP5_CLKDIV_SHIFT 16 +#define OMAP5_CLKDIV_WIDTH 0x4 +#define OMAP5_CLKDIV_MASK (0xf << 16) + +/* Used by D2DCLKM, MODEMCLKM */ +#define OMAP5_CLK_32KHZ_SHIFT 0 +#define OMAP5_CLK_32KHZ_WIDTH 0x1 +#define OMAP5_CLK_32KHZ_MASK (1 << 0) + +/* Used by D2DRSTCTRL, MODEMRSTCTRL */ +#define OMAP5_COLDRST_SHIFT 0 +#define OMAP5_COLDRST_WIDTH 0x1 +#define OMAP5_COLDRST_MASK (1 << 0) + +/* Used by D2DWARMRSTST */ +#define OMAP5_D2DWARMRSTST_SHIFT 3 +#define OMAP5_D2DWARMRSTST_WIDTH 0x1 +#define OMAP5_D2DWARMRSTST_MASK (1 << 3) + +/* Used by AUXCLK0 */ +#define OMAP5_DISABLECLK_SHIFT 9 +#define OMAP5_DISABLECLK_WIDTH 0x1 +#define OMAP5_DISABLECLK_MASK (1 << 9) + +/* Used by CLKSETUPTIME */ +#define OMAP5_DOWNTIME_SHIFT 16 +#define OMAP5_DOWNTIME_WIDTH 0x6 +#define OMAP5_DOWNTIME_MASK (0x3f << 16) + +/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ +#define OMAP5_ENABLE_SHIFT 8 +#define OMAP5_ENABLE_WIDTH 0x1 +#define OMAP5_ENABLE_MASK (1 << 8) + +/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */ +#define OMAP5_ENABLE_0_0_SHIFT 0 +#define OMAP5_ENABLE_0_0_WIDTH 0x1 +#define OMAP5_ENABLE_0_0_MASK (1 << 0) + +/* Used by ALTCLKSRC */ +#define OMAP5_ENABLE_EXT_SHIFT 3 +#define OMAP5_ENABLE_EXT_WIDTH 0x1 +#define OMAP5_ENABLE_EXT_MASK (1 << 3) + +/* Used by ALTCLKSRC */ +#define OMAP5_ENABLE_INT_SHIFT 2 +#define OMAP5_ENABLE_INT_WIDTH 0x1 +#define OMAP5_ENABLE_INT_MASK (1 << 2) + +/* Used by EXTWARMRSTST */ +#define OMAP5_EXTWARMRSTST_SHIFT 0 +#define OMAP5_EXTWARMRSTST_WIDTH 0x1 +#define OMAP5_EXTWARMRSTST_MASK (1 << 0) + +/* +* Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, +* AUXCLKREQ5 +*/ +#define OMAP5_MAPPING_SHIFT 2 +#define OMAP5_MAPPING_WIDTH 0x3 +#define OMAP5_MAPPING_MASK (0x7 << 2) + +/* Used by ALTCLKSRC */ +#define OMAP5_MODE_SHIFT 0 +#define OMAP5_MODE_WIDTH 0x2 +#define OMAP5_MODE_MASK (0x3 << 0) + +/* Used by MODEMWARMRSTST */ +#define OMAP5_MODEMWARMRSTST_SHIFT 2 +#define OMAP5_MODEMWARMRSTST_WIDTH 0x1 +#define OMAP5_MODEMWARMRSTST_MASK (1 << 2) + +/* +* Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5, +* AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5, +* D2DCLKREQ, EXTCLKREQ, PWRREQ +*/ +#define OMAP5_POLARITY_SHIFT 0 +#define OMAP5_POLARITY_WIDTH 0x1 +#define OMAP5_POLARITY_MASK (1 << 0) + +/* Used by EXTPWRONRSTCTRL */ +#define OMAP5_PWRONRST_SHIFT 1 +#define OMAP5_PWRONRST_WIDTH 0x1 +#define OMAP5_PWRONRST_MASK (1 << 1) + +/* Used by REVISION_SCRM */ +#define OMAP5_REV_SHIFT 0 +#define OMAP5_REV_WIDTH 0x8 +#define OMAP5_REV_MASK (0xff << 0) + +/* Used by RSTTIME */ +#define OMAP5_RSTTIME_SHIFT 0 +#define OMAP5_RSTTIME_WIDTH 0x4 +#define OMAP5_RSTTIME_MASK (0xf << 0) + +/* Used by CLKSETUPTIME */ +#define OMAP5_SETUPTIME_SHIFT 0 +#define OMAP5_SETUPTIME_WIDTH 0xc +#define OMAP5_SETUPTIME_MASK (0xfff << 0) + +/* Used by PMICSETUPTIME */ +#define OMAP5_SLEEPTIME_SHIFT 0 +#define OMAP5_SLEEPTIME_WIDTH 0x6 +#define OMAP5_SLEEPTIME_MASK (0x3f << 0) + +/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ +#define OMAP5_SRCSELECT_SHIFT 1 +#define OMAP5_SRCSELECT_WIDTH 0x2 +#define OMAP5_SRCSELECT_MASK (0x3 << 1) + +/* Used by D2DCLKM */ +#define OMAP5_SYSCLK_SHIFT 1 +#define OMAP5_SYSCLK_WIDTH 0x1 +#define OMAP5_SYSCLK_MASK (1 << 1) + +/* Used by PMICSETUPTIME */ +#define OMAP5_WAKEUPTIME_SHIFT 16 +#define OMAP5_WAKEUPTIME_WIDTH 0x6 +#define OMAP5_WAKEUPTIME_MASK (0x3f << 16) + +/* Used by D2DRSTCTRL, MODEMRSTCTRL */ +#define OMAP5_WARMRST_SHIFT 1 +#define OMAP5_WARMRST_WIDTH 0x1 +#define OMAP5_WARMRST_MASK (1 << 1) + +#endif
Signature · 1 line
1.7.9.5
PATCH 5/10 ARM: OMAP2+: clockdomain data: Add OMAP54XX data and update the header
In reply to Santosh ShilimkarFrom: Benoit Cousson <[email protected]>
Add the data file to describe all clock domains inside the OMAP54XX soc.
Cc Paul Walmsley <[email protected]>
Signed-off-by Benoit Cousson <[email protected]>
[[email protected]: Generated es2.0 data]
Signed-off-by Santosh Shilimkar <[email protected]>
--- arch/arm/mach-omap2/clockdomain.h | 1 + arch/arm/mach-omap2/clockdomains54xx_data.c | 464 +++++++++++++++++++++++++++ 2 files changed, 465 insertions(+) create mode 100644 arch/arm/mach-omap2/clockdomains54xx_data.c
arch/arm/mach-omap2/clockdomain.h +1 -0
@@ -214,6 +214,7 @@ extern void __init omap243x_clockdomains_init(void);extern void __init omap3xxx_clockdomains_init (void );extern void __init am33xx_clockdomains_init (void );extern void __init omap44xx_clockdomains_init (void ); +extern void __init omap54xx_clockdomains_init (void );extern void _clkdm_add_autodeps (struct clockdomain *clkdm);extern void _clkdm_del_autodeps (struct clockdomain *clkdm);
arch/arm/mach-omap2/clockdomains54xx_data.c new file +464 -0
464 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH 6/10 ARM: OMAP5: powerdomain data: Add OMAP54XX data and update the header
In reply to Santosh ShilimkarFrom: Benoit Cousson <[email protected]>
Add the data file to describe all power domains inside the OMAP54XX soc.
Cc Paul Walmsley <[email protected]>
Signed-off-by Benoit Cousson <[email protected]>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by Santosh Shilimkar <[email protected]>
--- arch/arm/mach-omap2/powerdomain.h | 1 + arch/arm/mach-omap2/powerdomains54xx_data.c | 331 +++++++++++++++++++++++++++ 2 files changed, 332 insertions(+) create mode 100644 arch/arm/mach-omap2/powerdomains54xx_data.c
arch/arm/mach-omap2/powerdomain.h +1 -0
@@ -239,6 +239,7 @@ extern void omap243x_powerdomains_init(void);extern void omap3xxx_powerdomains_init (void );extern void am33xx_powerdomains_init (void );extern void omap44xx_powerdomains_init (void ); +extern void omap54xx_powerdomains_init (void );extern struct pwrdm_ops omap2_pwrdm_operations;extern struct pwrdm_ops omap3_pwrdm_operations;
arch/arm/mach-omap2/powerdomains54xx_data.c new file +331 -0
331 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH 7/10 ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
In reply to Santosh ShilimkarFrom: Rajendra Nayak <[email protected]>
Add the clock tree related data for OMAP54xx platforms.
Cc Paul Walmsley <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
Signed-off-by Benoit Cousson <[email protected]>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by Santosh Shilimkar <[email protected]>
---
As mentioned in the summary, this patch will be updated once the movement of clock data to drivers/clock is clear.
arch/arm/mach-omap2/cclock54xx_data.c | 1794 +++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock.h | 23 +- arch/arm/mach-omap2/clock54xx.h | 12 + arch/arm/mach-omap2/clock_common_data.c | 139 ++- 4 files changed, 1931 insertions(+), 37 deletions(-) create mode 100644 arch/arm/mach-omap2/cclock54xx_data.c create mode 100644 arch/arm/mach-omap2/clock54xx.h
arch/arm/mach-omap2/cclock54xx_data.c new file +1794 -0
@@ -0,0 +1,1794 @@ +/* +* OMAP54xx Clock data +* +* Copyright (C) 2013 Texas Instruments, Inc. +* +* Paul Walmsley (paul at pwsan.com) +* Rajendra Nayak (rnayak at ti.com) +* Benoit Cousson (b-cousson at ti.com) +* Mike Turquette (mturquette at ti.com) +* +* This file is automatically generated from the OMAP hardware databases. +* We respectfully ask that any modifications to this file be coordinated +* with the public linux-omap at vger.kernel.org mailing list and the +* authors above to ensure that the autogeneration scripts are kept +* up-to-date with the file contents. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* XXX Some of the ES1 clocks have been removed/changed; once support +* is added for discriminating clocks by ES level, these should be added back +* in. +*/ + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/clk-private.h> +#include <linux/clkdev.h> +#include <linux/io.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock54xx.h" +#include "cm1_54xx.h" +#include "cm2_54xx.h" +#include "cm-regbits-54xx.h" +#include "prm54xx.h" +#include "prm-regbits-54xx.h" +#include "control.h" +#include "scrm54xx.h" + +/* OMAP4 modulemode control */ +#define OMAP54XX_MODULEMODE_HWCTRL 0 +#define OMAP54XX_MODULEMODE_SWCTRL 1 + +/* Root clocks */ + +DEFINE_CLK_FIXED_RATE (pad_clks_src_ck,CLK_IS_ROOT ,12000000 ,0x0 ); + +DEFINE_CLK_GATE (pad_clks_ck,"pad_clks_src_ck" , &pad_clks_src_ck,0x0 , +OMAP54XX_CM_CLKSEL_ABE ,OMAP54XX_PAD_CLKS_GATE_SHIFT ,0x0 , +NULL ); + +DEFINE_CLK_FIXED_RATE (secure_32k_clk_src_ck,CLK_IS_ROOT ,32768 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (slimbus_src_clk,CLK_IS_ROOT ,12000000 ,0x0 ); + +DEFINE_CLK_GATE (slimbus_clk,"slimbus_src_clk" , &slimbus_src_clk,0x0 , +OMAP54XX_CM_CLKSEL_ABE ,OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT ,0x0 , +NULL ); + +DEFINE_CLK_FIXED_RATE (sys_32k_ck,CLK_IS_ROOT ,32768 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_12000000_ck,CLK_IS_ROOT ,12000000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_13000000_ck,CLK_IS_ROOT ,13000000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_16800000_ck,CLK_IS_ROOT ,16800000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_19200000_ck,CLK_IS_ROOT ,19200000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_26000000_ck,CLK_IS_ROOT ,26000000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_27000000_ck,CLK_IS_ROOT ,27000000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_38400000_ck,CLK_IS_ROOT ,38400000 ,0x0 ); + +static const struct clksel_rate div_1_5_rates[] = { + { .div =1 , .val =5 , .flags =RATE_IN_54XX }, + { .div =0 }, +}; + +static const struct clksel_rate div_1_6_rates[] = { + { .div =1 , .val =6 , .flags =RATE_IN_54XX }, + { .div =0 }, +}; + +static const struct clksel_rate div_1_7_rates[] = { + { .div =1 , .val =7 , .flags =RATE_IN_54XX }, + { .div =0 }, +}; + +static const struct clksel sys_clkin_sel[] = { + { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, + { .parent = &virt_13000000_ck, .rates = div_1_2_rates }, + { .parent = &virt_16800000_ck, .rates = div_1_3_rates }, + { .parent = &virt_19200000_ck, .rates = div_1_4_rates }, + { .parent = &virt_26000000_ck, .rates = div_1_5_rates }, + { .parent = &virt_27000000_ck, .rates = div_1_6_rates }, + { .parent = &virt_38400000_ck, .rates = div_1_7_rates }, + { .parent =NULL }, +}; + +static const char *sys_clkin_parents[] = { +"virt_12000000_ck" , +"virt_13000000_ck" , +"virt_16800000_ck" , +"virt_19200000_ck" , +"virt_26000000_ck" , +"virt_27000000_ck" , +"virt_38400000_ck" , + +}; + +DEFINE_CLK_MUX (sys_clkin, sys_clkin_parents,NULL ,0x0 ,OMAP54XX_CM_CLKSEL_SYS , +OMAP54XX_SYS_CLKSEL_SHIFT ,OMAP54XX_SYS_CLKSEL_WIDTH , +CLK_MUX_INDEX_ONE ,NULL ); + +DEFINE_CLK_FIXED_RATE (xclk60mhsp1_ck,CLK_IS_ROOT ,60000000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (xclk60mhsp2_ck,CLK_IS_ROOT ,60000000 ,0x0 ); + +/* Module clocks and DPLL outputs */ + +static const char *abe_dpll_bypass_clk_mux_parents[] = { +"sys_clkin" ,"sys_32k_ck" , +}; + +DEFINE_CLK_MUX (abe_dpll_bypass_clk_mux, abe_dpll_bypass_clk_mux_parents,NULL , +0x0 ,OMAP54XX_CM_CLKSEL_WKUPAON ,OMAP54XX_CLKSEL_0_0_SHIFT , +OMAP54XX_CLKSEL_0_0_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (abe_dpll_clk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_CLKSEL_ABE_PLL_REF ,OMAP54XX_CLKSEL_0_0_SHIFT , +OMAP54XX_CLKSEL_0_0_WIDTH ,0x0 ,NULL ); + +/* DPLL_ABE */ +static struct dpll_data dpll_abe_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_ABE , + .clk_bypass = &abe_dpll_bypass_clk_mux, + .clk_ref = &abe_dpll_clk_mux, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_ABE , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_ABE , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_ABE , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =2047 , + .max_divider =128 , + .min_divider =1 , +}; + + +static const char *dpll_abe_ck_parents[] = { +"abe_dpll_clk_mux" , +}; + +static struct clk dpll_abe_ck; + +static const struct clk_ops dpll_abe_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap4_dpll_regm4xen_recalc, + .round_rate = &omap4_dpll_regm4xen_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_abe_ck_hw = { + .hw = { + .clk = &dpll_abe_ck, + }, + .dpll_data = &dpll_abe_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_abe_x2_ck_parents[] = { +"dpll_abe_ck" , +}; + +static struct clk dpll_abe_x2_ck; + +static const struct clk_ops dpll_abe_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, +}; + +static struct clk_hw_omap dpll_abe_x2_ck_hw = { + .hw = { + .clk = &dpll_abe_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK (dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops); + +static const struct clk_ops omap_hsdivider_ops = { + .set_rate = &omap2_clksel_set_rate, + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_abe_m2x2_ck,"dpll_abe_x2_ck" , &dpll_abe_x2_ck, +0x0 ,OMAP54XX_CM_DIV_M2_DPLL_ABE , +OMAP54XX_DIVHS_0_4_MASK ); + +DEFINE_CLK_FIXED_FACTOR (abe_24m_fclk,"dpll_abe_m2x2_ck" , &dpll_abe_m2x2_ck, +0x0 ,1 ,8 ); + +DEFINE_CLK_DIVIDER (abe_clk,"dpll_abe_m2x2_ck" , &dpll_abe_m2x2_ck,0x0 , +OMAP54XX_CM_CLKSEL_ABE ,OMAP54XX_CLKSEL_OPP_SHIFT , +OMAP54XX_CLKSEL_OPP_WIDTH ,CLK_DIVIDER_POWER_OF_TWO , +NULL ); + +DEFINE_CLK_FIXED_FACTOR (abe_iclk,"abe_clk" , &abe_clk,0x0 ,1 ,2 ); + +DEFINE_CLK_FIXED_FACTOR (abe_lp_clk_div,"dpll_abe_m2x2_ck" , &dpll_abe_m2x2_ck, +0x0 ,1 ,16 ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_abe_m3x2_ck,"dpll_abe_x2_ck" , &dpll_abe_x2_ck, +0x0 ,OMAP54XX_CM_DIV_M3_DPLL_ABE , +OMAP54XX_DIVHS_0_4_MASK ); + +/* DPLL_CORE */ +static struct dpll_data dpll_core_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_CORE , + .clk_bypass = &dpll_abe_m3x2_ck, + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_CORE , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_CORE , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_CORE , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =2047 , + .max_divider =128 , + .min_divider =1 , +}; + + +static const char *dpll_core_ck_parents[] = { +"sys_clkin" , +}; + +static struct clk dpll_core_ck; + +static const struct clk_ops dpll_core_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_core_ck_hw = { + .hw = { + .clk = &dpll_core_ck, + }, + .dpll_data = &dpll_core_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); + +static const char *dpll_core_x2_ck_parents[] = { +"dpll_core_ck" , +}; + +static struct clk dpll_core_x2_ck; + +static struct clk_hw_omap dpll_core_x2_ck_hw = { + .hw = { + .clk = &dpll_core_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK (dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h21x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H21_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +static const char *c2c_fclk_parents[] = { +"dpll_core_h21x2_ck" , +}; + +static struct clk c2c_fclk; + +static const struct clk_ops c2c_fclk_ops = { +}; + +static struct clk_hw_omap c2c_fclk_hw = { + .hw = { + .clk = &c2c_fclk, + }, +}; + +DEFINE_STRUCT_CLK (c2c_fclk, c2c_fclk_parents, c2c_fclk_ops); + +DEFINE_CLK_FIXED_FACTOR (c2c_iclk,"c2c_fclk" , &c2c_fclk,0x0 ,1 ,2 ); + +DEFINE_CLK_FIXED_FACTOR (custefuse_sys_gfclk_div,"sys_clkin" , &sys_clkin,0x0 , +1 ,2 ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h11x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H11_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h12x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H12_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h13x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H13_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h14x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H14_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h22x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H22_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h23x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H23_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h24x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H24_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_m2_ck,"dpll_core_ck" , &dpll_core_ck,0x0 , +OMAP54XX_CM_DIV_M2_DPLL_CORE , +OMAP54XX_DIVHS_0_4_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_m3x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 ,OMAP54XX_CM_DIV_M3_DPLL_CORE , +OMAP54XX_DIVHS_0_4_MASK ); + +static const char *iva_dpll_hs_clk_div_parents[] = { +"dpll_core_h12x2_ck" , +}; + +static struct clk iva_dpll_hs_clk_div; + +static struct clk_hw_omap iva_dpll_hs_clk_div_hw = { + .hw = { + .clk = &iva_dpll_hs_clk_div, + }, +}; + +DEFINE_STRUCT_CLK (iva_dpll_hs_clk_div, iva_dpll_hs_clk_div_parents, + c2c_fclk_ops); + +/* DPLL_IVA */ +static struct dpll_data dpll_iva_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_IVA , + .clk_bypass = &iva_dpll_hs_clk_div, + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_IVA , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_IVA , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_IVA , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =2047 , + .max_divider =128 , + .min_divider =1 , +}; + + +static struct clk dpll_iva_ck; + +static const struct clk_ops dpll_iva_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_iva_ck_hw = { + .hw = { + .clk = &dpll_iva_ck, + }, + .dpll_data = &dpll_iva_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_iva_ck, dpll_core_ck_parents, dpll_iva_ck_ops); + +static const char *dpll_iva_x2_ck_parents[] = { +"dpll_iva_ck" , +}; + +static struct clk dpll_iva_x2_ck; + +static struct clk_hw_omap dpll_iva_x2_ck_hw = { + .hw = { + .clk = &dpll_iva_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK (dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_iva_h11x2_ck,"dpll_iva_x2_ck" , + &dpll_iva_x2_ck,0x0 ,OMAP54XX_CM_DIV_H11_DPLL_IVA , +OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_iva_h12x2_ck,"dpll_iva_x2_ck" , + &dpll_iva_x2_ck,0x0 ,OMAP54XX_CM_DIV_H12_DPLL_IVA , +OMAP54XX_DIVHS_MASK ); + +static struct clk mpu_dpll_hs_clk_div; + +static struct clk_hw_omap mpu_dpll_hs_clk_div_hw = { + .hw = { + .clk = &mpu_dpll_hs_clk_div, + }, +}; + +DEFINE_STRUCT_CLK (mpu_dpll_hs_clk_div, iva_dpll_hs_clk_div_parents, + c2c_fclk_ops); + +/* DPLL_MPU */ +static struct dpll_data dpll_mpu_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_MPU , + .clk_bypass = &mpu_dpll_hs_clk_div, + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_MPU , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_MPU , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_MPU , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =2047 , + .max_divider =128 , + .min_divider =1 , +}; + + +static struct clk dpll_mpu_ck; + +static struct clk_hw_omap dpll_mpu_ck_hw = { + .hw = { + .clk = &dpll_mpu_ck, + }, + .dpll_data = &dpll_mpu_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_mpu_ck, dpll_core_ck_parents, dpll_iva_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_mpu_m2_ck,"dpll_mpu_ck" , &dpll_mpu_ck,0x0 , +OMAP54XX_CM_DIV_M2_DPLL_MPU , +OMAP54XX_DIVHS_0_4_MASK ); + +DEFINE_CLK_FIXED_FACTOR (per_dpll_hs_clk_div,"dpll_abe_m3x2_ck" , + &dpll_abe_m3x2_ck,0x0 ,1 ,2 ); + +/* DPLL_PER */ +static struct dpll_data dpll_per_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_PER , + .clk_bypass = &per_dpll_hs_clk_div, + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_PER , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_PER , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_PER , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =2047 , + .max_divider =128 , + .min_divider =1 , +}; + + +static struct clk dpll_per_ck; + +static struct clk_hw_omap dpll_per_ck_hw = { + .hw = { + .clk = &dpll_per_ck, + }, + .dpll_data = &dpll_per_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_per_ck, dpll_core_ck_parents, dpll_iva_ck_ops); + +static const char *dpll_per_x2_ck_parents[] = { +"dpll_per_ck" , +}; + +static struct clk dpll_per_x2_ck; + +static struct clk_hw_omap dpll_per_x2_ck_hw = { + .hw = { + .clk = &dpll_per_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK (dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_per_h11x2_ck,"dpll_per_x2_ck" , + &dpll_per_x2_ck,0x0 ,OMAP54XX_CM_DIV_H11_DPLL_PER , +OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_per_h12x2_ck,"dpll_per_x2_ck" , + &dpll_per_x2_ck,0x0 ,OMAP54XX_CM_DIV_H12_DPLL_PER , +OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_per_h14x2_ck,"dpll_per_x2_ck" , + &dpll_per_x2_ck,0x0 ,OMAP54XX_CM_DIV_H14_DPLL_PER , +OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_per_m2_ck,"dpll_per_ck" , &dpll_per_ck,0x0 , +OMAP54XX_CM_DIV_M2_DPLL_PER , +OMAP54XX_DIVHS_0_4_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_per_m2x2_ck,"dpll_per_x2_ck" , &dpll_per_x2_ck, +0x0 ,OMAP54XX_CM_DIV_M2_DPLL_PER , +OMAP54XX_DIVHS_0_4_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_per_m3x2_ck,"dpll_per_x2_ck" , &dpll_per_x2_ck, +0x0 ,OMAP54XX_CM_DIV_M3_DPLL_PER , +OMAP54XX_DIVHS_0_4_MASK ); + +/* DPLL_UNIPRO1 */ +static struct dpll_data dpll_unipro1_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1 , + .clk_bypass = &sys_clkin, + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1 , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1 , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_UNIPRO1 , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =4095 , + .max_divider =256 , + .min_divider =1 , +}; + + +static struct clk dpll_unipro1_ck; + +static struct clk_hw_omap dpll_unipro1_ck_hw = { + .hw = { + .clk = &dpll_unipro1_ck, + }, + .dpll_data = &dpll_unipro1_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_unipro1_ck, dpll_core_ck_parents, dpll_iva_ck_ops); + +static const char *dpll_unipro1_clkdcoldo_parents[] = { +"dpll_unipro1_ck" , +}; + +static struct clk dpll_unipro1_clkdcoldo; + +static struct clk_hw_omap dpll_unipro1_clkdcoldo_hw = { + .hw = { + .clk = &dpll_unipro1_clkdcoldo, + }, + .clksel_reg =OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1 , +}; + +DEFINE_STRUCT_CLK (dpll_unipro1_clkdcoldo, dpll_unipro1_clkdcoldo_parents, + c2c_fclk_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_unipro1_m2_ck,"dpll_unipro1_ck" , + &dpll_unipro1_ck,0x0 , +OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1 , +OMAP54XX_DIVHS_0_6_MASK ); + +/* DPLL_UNIPRO2 */ +static struct dpll_data dpll_unipro2_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2 , + .clk_bypass = &sys_clkin, + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2 , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2 , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_UNIPRO2 , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =4095 , + .max_divider =256 , + .min_divider =1 , +}; + + +static struct clk dpll_unipro2_ck; + +static struct clk_hw_omap dpll_unipro2_ck_hw = { + .hw = { + .clk = &dpll_unipro2_ck, + }, + .dpll_data = &dpll_unipro2_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_unipro2_ck, dpll_core_ck_parents, dpll_iva_ck_ops); + +static const char *dpll_unipro2_clkdcoldo_parents[] = { +"dpll_unipro2_ck" , +}; + +static struct clk dpll_unipro2_clkdcoldo; + +static struct clk_hw_omap dpll_unipro2_clkdcoldo_hw = { + .hw = { + .clk = &dpll_unipro2_clkdcoldo, + }, + .clksel_reg =OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2 , +}; + +DEFINE_STRUCT_CLK (dpll_unipro2_clkdcoldo, dpll_unipro2_clkdcoldo_parents, + c2c_fclk_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_unipro2_m2_ck,"dpll_unipro2_ck" , + &dpll_unipro2_ck,0x0 , +OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2 , +OMAP54XX_DIVHS_0_6_MASK ); + +DEFINE_CLK_FIXED_FACTOR (usb_dpll_hs_clk_div,"dpll_abe_m3x2_ck" , + &dpll_abe_m3x2_ck,0x0 ,1 ,3 ); + +/* DPLL_USB */ +static struct dpll_data dpll_usb_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_USB , + .clk_bypass = &usb_dpll_hs_clk_div, + .flags =DPLL_J_TYPE , + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_USB , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_USB , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_USB , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .sddiv_mask =OMAP54XX_DPLL_SD_DIV_MASK , + .max_multiplier =4095 , + .max_divider =256 , + .min_divider =1 , +}; + + +static struct clk dpll_usb_ck; + +static const struct clk_ops dpll_usb_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap dpll_usb_ck_hw = { + .hw = { + .clk = &dpll_usb_ck, + }, + .dpll_data = &dpll_usb_dd, + .clkdm_name ="l3init_clkdm" , + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_usb_ck, dpll_core_ck_parents, dpll_usb_ck_ops); + +static const char *dpll_usb_clkdcoldo_parents[] = { +"dpll_usb_ck" , +}; + +static struct clk dpll_usb_clkdcoldo; + +static struct clk_hw_omap dpll_usb_clkdcoldo_hw = { + .hw = { + .clk = &dpll_usb_clkdcoldo, + }, + .clksel_reg =OMAP54XX_CM_CLKDCOLDO_DPLL_USB , +}; + +DEFINE_STRUCT_CLK (dpll_usb_clkdcoldo, dpll_usb_clkdcoldo_parents, c2c_fclk_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_usb_m2_ck,"dpll_usb_ck" , &dpll_usb_ck,0x0 , +OMAP54XX_CM_DIV_M2_DPLL_USB , +OMAP54XX_DIVHS_0_6_MASK ); + +static const char *dss_syc_gfclk_div_parents[] = { +"sys_clkin" , +}; + +static struct clk dss_syc_gfclk_div; + +static struct clk_hw_omap dss_syc_gfclk_div_hw = { + .hw = { + .clk = &dss_syc_gfclk_div, + }, +}; + +DEFINE_STRUCT_CLK (dss_syc_gfclk_div, dss_syc_gfclk_div_parents, c2c_fclk_ops); + +static struct clk l3_iclk_div; + +static struct clk_hw_omap l3_iclk_div_hw = { + .hw = { + .clk = &l3_iclk_div, + }, +}; + +DEFINE_STRUCT_CLK (l3_iclk_div, iva_dpll_hs_clk_div_parents, c2c_fclk_ops); + +DEFINE_CLK_FIXED_FACTOR (func_128m_clk,"dpll_per_h11x2_ck" , &dpll_per_h11x2_ck, +0x0 ,1 ,2 ); + +DEFINE_CLK_FIXED_FACTOR (func_12m_fclk,"dpll_per_m2x2_ck" , &dpll_per_m2x2_ck, +0x0 ,1 ,16 ); + +DEFINE_CLK_FIXED_FACTOR (func_24m_clk,"dpll_per_m2_ck" , &dpll_per_m2_ck,0x0 ,1 , +4 ); + +DEFINE_CLK_FIXED_FACTOR (func_48m_fclk,"dpll_per_m2x2_ck" , &dpll_per_m2x2_ck, +0x0 ,1 ,4 ); + +DEFINE_CLK_FIXED_FACTOR (func_96m_fclk,"dpll_per_m2x2_ck" , &dpll_per_m2x2_ck, +0x0 ,1 ,2 ); + +static const char *gpu_core_gclk_mux_parents[] = { +"dpll_core_h14x2_ck" ,"dpll_per_h14x2_ck" , +}; + +DEFINE_CLK_MUX (gpu_core_gclk_mux, gpu_core_gclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_GPU_GPU_CLKCTRL ,OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT , +OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_GPU_GPU_CLKCTRL ,OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT , +OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH ,0x0 ,NULL ); + +static const char *gpu_l3_iclk_parents[] = { +"l3_iclk_div" , +}; + +static struct clk gpu_l3_iclk; + +static struct clk_hw_omap gpu_l3_iclk_hw = { + .hw = { + .clk = &gpu_l3_iclk, + }, +}; + +DEFINE_STRUCT_CLK (gpu_l3_iclk, gpu_l3_iclk_parents, c2c_fclk_ops); + +static const struct clk_div_table l3init_60m_fclk_rates[] = { + { .div =1 , .val =0 }, + { .div =8 , .val =1 }, + { .div =0 }, +}; +DEFINE_CLK_DIVIDER_TABLE (l3init_60m_fclk,"dpll_usb_m2_ck" , &dpll_usb_m2_ck, +0x0 ,OMAP54XX_CM_CLKSEL_USB_60MHZ , +OMAP54XX_CLKSEL_0_0_SHIFT ,OMAP54XX_CLKSEL_0_0_WIDTH , +0x0 , l3init_60m_fclk_rates,NULL ); + +static const char *wkupaon_iclk_mux_parents[] = { +"sys_clkin" ,"abe_lp_clk_div" , +}; + +DEFINE_CLK_MUX (wkupaon_iclk_mux, wkupaon_iclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_CLKSEL_WKUPAON ,OMAP54XX_CLKSEL_0_0_SHIFT , +OMAP54XX_CLKSEL_0_0_WIDTH ,0x0 ,NULL ); + +static const char *l3instr_ts_gclk_div_parents[] = { +"wkupaon_iclk_mux" , +}; + +static struct clk l3instr_ts_gclk_div; + +static struct clk_hw_omap l3instr_ts_gclk_div_hw = { + .hw = { + .clk = &l3instr_ts_gclk_div, + }, +}; + +DEFINE_STRUCT_CLK (l3instr_ts_gclk_div, l3instr_ts_gclk_div_parents, + c2c_fclk_ops); + +static struct clk l4_root_clk_div; + +static struct clk_hw_omap l4_root_clk_div_hw = { + .hw = { + .clk = &l4_root_clk_div, + }, +}; + +DEFINE_STRUCT_CLK (l4_root_clk_div, gpu_l3_iclk_parents, c2c_fclk_ops); + +DEFINE_CLK_MUX (timer10_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L4PER_TIMER10_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer11_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L4PER_TIMER11_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer1_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer2_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L4PER_TIMER2_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer3_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L4PER_TIMER3_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer4_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L4PER_TIMER4_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +static const char *timer5_gfclk_mux_parents[] = { +"dss_syc_gfclk_div" ,"sys_32k_ck" , +}; + +DEFINE_CLK_MUX (timer5_gfclk_mux, timer5_gfclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_TIMER5_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer6_gfclk_mux, timer5_gfclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_TIMER6_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer7_gfclk_mux, timer5_gfclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_TIMER7_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer8_gfclk_mux, timer5_gfclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_TIMER8_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer9_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L4PER_TIMER9_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +/* Leaf clocks controlled by modules */ + +static const char *dss_32khz_clk_parents[] = { +"sys_32k_ck" , +}; + +static struct clk dss_32khz_clk; + +static const struct clk_ops dss_32khz_clk_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap dss_32khz_clk_hw = { + .hw = { + .clk = &dss_32khz_clk, + }, + .clkdm_name ="dss_clkdm" , + .enable_reg =OMAP54XX_CM_DSS_DSS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (dss_32khz_clk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static const char *dss_48mhz_clk_parents[] = { +"func_48m_fclk" , +}; + +static struct clk dss_48mhz_clk; + +static struct clk_hw_omap dss_48mhz_clk_hw = { + .hw = { + .clk = &dss_48mhz_clk, + }, + .clkdm_name ="dss_clkdm" , + .enable_reg =OMAP54XX_CM_DSS_DSS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (dss_48mhz_clk, dss_48mhz_clk_parents, dss_32khz_clk_ops); + +static const char *dss_dss_clk_parents[] = { +"dpll_per_h12x2_ck" , +}; + +static struct clk dss_dss_clk; + +static struct clk_hw_omap dss_dss_clk_hw = { + .hw = { + .clk = &dss_dss_clk, + }, + .clkdm_name ="dss_clkdm" , + .enable_reg =OMAP54XX_CM_DSS_DSS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (dss_dss_clk, dss_dss_clk_parents, dss_32khz_clk_ops); + +static const char *dss_sys_clk_parents[] = { +"dss_syc_gfclk_div" , +}; + +static struct clk dss_sys_clk; + +static struct clk_hw_omap dss_sys_clk_hw = { + .hw = { + .clk = &dss_sys_clk, + }, + .clkdm_name ="dss_clkdm" , + .enable_reg =OMAP54XX_CM_DSS_DSS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (dss_sys_clk, dss_sys_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio1_dbclk; + +static struct clk_hw_omap gpio1_dbclk_hw = { + .hw = { + .clk = &gpio1_dbclk, + }, + .clkdm_name ="wkupaon_clkdm" , + .enable_reg =OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio1_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio2_dbclk; + +static struct clk_hw_omap gpio2_dbclk_hw = { + .hw = { + .clk = &gpio2_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO2_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio2_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio3_dbclk; + +static struct clk_hw_omap gpio3_dbclk_hw = { + .hw = { + .clk = &gpio3_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO3_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio3_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio4_dbclk; + +static struct clk_hw_omap gpio4_dbclk_hw = { + .hw = { + .clk = &gpio4_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO4_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio4_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio5_dbclk; + +static struct clk_hw_omap gpio5_dbclk_hw = { + .hw = { + .clk = &gpio5_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO5_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio5_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio6_dbclk; + +static struct clk_hw_omap gpio6_dbclk_hw = { + .hw = { + .clk = &gpio6_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO6_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio6_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio7_dbclk; + +static struct clk_hw_omap gpio7_dbclk_hw = { + .hw = { + .clk = &gpio7_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO7_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio7_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio8_dbclk; + +static struct clk_hw_omap gpio8_dbclk_hw = { + .hw = { + .clk = &gpio8_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO8_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio8_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static const char *iss_ctrlclk_parents[] = { +"func_96m_fclk" , +}; + +static struct clk iss_ctrlclk; + +static struct clk_hw_omap iss_ctrlclk_hw = { + .hw = { + .clk = &iss_ctrlclk, + }, + .clkdm_name ="cam_clkdm" , + .enable_reg =OMAP54XX_CM_CAM_ISS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (iss_ctrlclk, iss_ctrlclk_parents, dss_32khz_clk_ops); + +static const char *lli_txphy_clk_parents[] = { +"dpll_unipro1_clkdcoldo" , +}; + +static struct clk lli_txphy_clk; + +static struct clk_hw_omap lli_txphy_clk_hw = { + .hw = { + .clk = &lli_txphy_clk, + }, + .clkdm_name ="mipiext_clkdm" , + .enable_reg =OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (lli_txphy_clk, lli_txphy_clk_parents, dss_32khz_clk_ops); + +static const char *lli_txphy_ls_clk_parents[] = { +"dpll_unipro1_m2_ck" , +}; + +static struct clk lli_txphy_ls_clk; + +static struct clk_hw_omap lli_txphy_ls_clk_hw = { + .hw = { + .clk = &lli_txphy_ls_clk, + }, + .clkdm_name ="mipiext_clkdm" , + .enable_reg =OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (lli_txphy_ls_clk, lli_txphy_ls_clk_parents, + dss_32khz_clk_ops); + +static struct clk mmc1_32khz_clk; + +static struct clk_hw_omap mmc1_32khz_clk_hw = { + .hw = { + .clk = &mmc1_32khz_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_MMC1_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT , +}; + +DEFINE_STRUCT_CLK (mmc1_32khz_clk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk sata_ref_clk; + +static struct clk_hw_omap sata_ref_clk_hw = { + .hw = { + .clk = &sata_ref_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_SATA_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (sata_ref_clk, dss_syc_gfclk_div_parents, dss_32khz_clk_ops); + +static const char *slimbus1_slimbus_clk_parents[] = { +"slimbus_clk" , +}; + +static struct clk slimbus1_slimbus_clk; + +static struct clk_hw_omap slimbus1_slimbus_clk_hw = { + .hw = { + .clk = &slimbus1_slimbus_clk, + }, + .clkdm_name ="abe_clkdm" , + .enable_reg =OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (slimbus1_slimbus_clk, slimbus1_slimbus_clk_parents, + dss_32khz_clk_ops); + +static const char *usb_host_hs_hsic480m_p1_clk_parents[] = { +"dpll_usb_m2_ck" , +}; + +static struct clk usb_host_hs_hsic480m_p1_clk; + +static struct clk_hw_omap usb_host_hs_hsic480m_p1_clk_hw = { + .hw = { + .clk = &usb_host_hs_hsic480m_p1_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_hsic480m_p1_clk, + usb_host_hs_hsic480m_p1_clk_parents, dss_32khz_clk_ops); + +static struct clk usb_host_hs_hsic480m_p2_clk; + +static struct clk_hw_omap usb_host_hs_hsic480m_p2_clk_hw = { + .hw = { + .clk = &usb_host_hs_hsic480m_p2_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_hsic480m_p2_clk, + usb_host_hs_hsic480m_p1_clk_parents, dss_32khz_clk_ops); + +static struct clk usb_host_hs_hsic480m_p3_clk; + +static struct clk_hw_omap usb_host_hs_hsic480m_p3_clk_hw = { + .hw = { + .clk = &usb_host_hs_hsic480m_p3_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_hsic480m_p3_clk, + usb_host_hs_hsic480m_p1_clk_parents, dss_32khz_clk_ops); + +static const char *usb_host_hs_hsic60m_p1_clk_parents[] = { +"l3init_60m_fclk" , +}; + +static struct clk usb_host_hs_hsic60m_p1_clk; + +static struct clk_hw_omap usb_host_hs_hsic60m_p1_clk_hw = { + .hw = { + .clk = &usb_host_hs_hsic60m_p1_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_hsic60m_p1_clk, + usb_host_hs_hsic60m_p1_clk_parents, dss_32khz_clk_ops); + +static struct clk usb_host_hs_hsic60m_p2_clk; + +static struct clk_hw_omap usb_host_hs_hsic60m_p2_clk_hw = { + .hw = { + .clk = &usb_host_hs_hsic60m_p2_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_hsic60m_p2_clk, + usb_host_hs_hsic60m_p1_clk_parents, dss_32khz_clk_ops); + +static struct clk usb_host_hs_hsic60m_p3_clk; + +static struct clk_hw_omap usb_host_hs_hsic60m_p3_clk_hw = { + .hw = { + .clk = &usb_host_hs_hsic60m_p3_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_hsic60m_p3_clk, + usb_host_hs_hsic60m_p1_clk_parents, dss_32khz_clk_ops); + +static const char *utmi_p1_gfclk_parents[] = { +"l3init_60m_fclk" ,"xclk60mhsp1" , +}; + +DEFINE_CLK_MUX (utmi_p1_gfclk, utmi_p1_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , +OMAP54XX_CLKSEL_UTMI_P1_SHIFT ,OMAP54XX_CLKSEL_UTMI_P1_WIDTH , +0x0 ,NULL ); + +static const char *usb_host_hs_utmi_p1_clk_parents[] = { +"utmi_p1_gfclk" , +}; + +static struct clk usb_host_hs_utmi_p1_clk; + +static struct clk_hw_omap usb_host_hs_utmi_p1_clk_hw = { + .hw = { + .clk = &usb_host_hs_utmi_p1_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_utmi_p1_clk, usb_host_hs_utmi_p1_clk_parents, + dss_32khz_clk_ops); + +static const char *utmi_p2_gfclk_parents[] = { +"l3init_60m_fclk" ,"xclk60mhsp2" , +}; + +DEFINE_CLK_MUX (utmi_p2_gfclk, utmi_p2_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , +OMAP54XX_CLKSEL_UTMI_P2_SHIFT ,OMAP54XX_CLKSEL_UTMI_P2_WIDTH , +0x0 ,NULL ); + +static const char *usb_host_hs_utmi_p2_clk_parents[] = { +"utmi_p2_gfclk" , +}; + +static struct clk usb_host_hs_utmi_p2_clk; + +static struct clk_hw_omap usb_host_hs_utmi_p2_clk_hw = { + .hw = { + .clk = &usb_host_hs_utmi_p2_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_utmi_p2_clk, usb_host_hs_utmi_p2_clk_parents, + dss_32khz_clk_ops); + +static struct clk usb_host_hs_utmi_p3_clk; + +static struct clk_hw_omap usb_host_hs_utmi_p3_clk_hw = { + .hw = { + .clk = &usb_host_hs_utmi_p3_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_utmi_p3_clk, usb_host_hs_hsic60m_p1_clk_parents, + dss_32khz_clk_ops); + +static const char *usb_otg_ss_refclk960m_parents[] = { +"dpll_usb_clkdcoldo" , +}; + +static struct clk usb_otg_ss_refclk960m; + +static struct clk_hw_omap usb_otg_ss_refclk960m_hw = { + .hw = { + .clk = &usb_otg_ss_refclk960m, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_otg_ss_refclk960m, usb_otg_ss_refclk960m_parents, + dss_32khz_clk_ops); + +static struct clk usb_tll_hs_usb_ch0_clk; + +static struct clk_hw_omap usb_tll_hs_usb_ch0_clk_hw = { + .hw = { + .clk = &usb_tll_hs_usb_ch0_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_tll_hs_usb_ch0_clk, usb_host_hs_hsic60m_p1_clk_parents, + dss_32khz_clk_ops); + +static struct clk usb_tll_hs_usb_ch1_clk; + +static struct clk_hw_omap usb_tll_hs_usb_ch1_clk_hw = { + .hw = { + .clk = &usb_tll_hs_usb_ch1_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_tll_hs_usb_ch1_clk, usb_host_hs_hsic60m_p1_clk_parents, + dss_32khz_clk_ops); + +static struct clk usb_tll_hs_usb_ch2_clk; + +static struct clk_hw_omap usb_tll_hs_usb_ch2_clk_hw = { + .hw = { + .clk = &usb_tll_hs_usb_ch2_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_tll_hs_usb_ch2_clk, usb_host_hs_hsic60m_p1_clk_parents, + dss_32khz_clk_ops); + +/* Remaining optional clocks */ +DEFINE_CLK_DIVIDER (aess_fclk,"abe_clk" , &abe_clk,0x0 , +OMAP54XX_CM_ABE_AESS_CLKCTRL , +OMAP54XX_CLKSEL_AESS_FCLK_SHIFT , +OMAP54XX_CLKSEL_AESS_FCLK_WIDTH ,0x0 ,NULL ); + +static const char *dmic_sync_mux_ck_parents[] = { +"abe_24m_fclk" ,"dss_syc_gfclk_div" ,"func_24m_clk" , +}; + +DEFINE_CLK_MUX (dmic_sync_mux_ck, dmic_sync_mux_ck_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_DMIC_CLKCTRL , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH ,0x0 ,NULL ); + +static const char *dmic_gfclk_parents[] = { +"dmic_sync_mux_ck" ,"pad_clks" ,"slimbus_clk" , +}; + +DEFINE_CLK_MUX (dmic_gfclk, dmic_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_DMIC_CLKCTRL ,OMAP54XX_CLKSEL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_SOURCE_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_DIVIDER (fdif_fclk,"dpll_per_h11x2_ck" , &dpll_per_h11x2_ck,0x0 , +OMAP54XX_CM_CAM_FDIF_CLKCTRL ,OMAP54XX_CLKSEL_FCLK_SHIFT , +OMAP54XX_CLKSEL_FCLK_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_DIVIDER (hsi_fclk,"dpll_per_m2x2_ck" , &dpll_per_m2x2_ck,0x0 , +OMAP54XX_CM_L3INIT_HSI_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (mcasp_sync_mux_ck, dmic_sync_mux_ck_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCASP_CLKCTRL , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH ,0x0 ,NULL ); + +static const char *mcasp_gfclk_parents[] = { +"mcasp_sync_mux_ck" ,"pad_clks" ,"slimbus_clk" , +}; + +DEFINE_CLK_MUX (mcasp_gfclk, mcasp_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCASP_CLKCTRL ,OMAP54XX_CLKSEL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_SOURCE_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCBSP1_CLKCTRL , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH ,0x0 ,NULL ); + +static const char *mcbsp1_gfclk_parents[] = { +"mcbsp1_sync_mux_ck" ,"pad_clks" ,"slimbus_clk" , +}; + +DEFINE_CLK_MUX (mcbsp1_gfclk, mcbsp1_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCBSP1_CLKCTRL ,OMAP54XX_CLKSEL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_SOURCE_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCBSP2_CLKCTRL , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH ,0x0 ,NULL ); + +static const char *mcbsp2_gfclk_parents[] = { +"mcbsp2_sync_mux_ck" ,"pad_clks" ,"slimbus_clk" , +}; + +DEFINE_CLK_MUX (mcbsp2_gfclk, mcbsp2_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCBSP2_CLKCTRL ,OMAP54XX_CLKSEL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_SOURCE_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCBSP3_CLKCTRL , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH ,0x0 ,NULL ); + +static const char *mcbsp3_gfclk_parents[] = { +"mcbsp3_sync_mux_ck" ,"pad_clks" ,"slimbus_clk" , +}; + +DEFINE_CLK_MUX (mcbsp3_gfclk, mcbsp3_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCBSP3_CLKCTRL ,OMAP54XX_CLKSEL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_SOURCE_WIDTH ,0x0 ,NULL ); + +static const char *mmc1_fclk_mux_parents[] = { +"func_128m_clk" ,"dpll_per_m2x2_ck" , +}; + +DEFINE_CLK_MUX (mmc1_fclk_mux, mmc1_fclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L3INIT_MMC1_CLKCTRL , +OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT , +OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_DIVIDER (mmc1_fclk,"mmc1_fclk_mux" , &mmc1_fclk_mux,0x0 , +OMAP54XX_CM_L3INIT_MMC1_CLKCTRL ,OMAP54XX_CLKSEL_DIV_SHIFT , +OMAP54XX_CLKSEL_DIV_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (mmc2_fclk_mux, mmc1_fclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L3INIT_MMC2_CLKCTRL , +OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT , +OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_DIVIDER (mmc2_fclk,"mmc2_fclk_mux" , &mmc2_fclk_mux,0x0 , +OMAP54XX_CM_L3INIT_MMC2_CLKCTRL ,OMAP54XX_CLKSEL_DIV_SHIFT , +OMAP54XX_CLKSEL_DIV_WIDTH ,0x0 ,NULL ); + +/* SCRM aux clk nodes */ + +static const struct clksel auxclk_src_sel[] = { + { .parent = &sys_clkin, .rates = div_1_0_rates }, + { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, + { .parent =NULL }, +}; + +static const char *auxclk_src_ck_parents[] = { +"sys_clkin" ,"dpll_core_m3x2_ck" ,"dpll_per_m3x2_ck" , +}; + +static const struct clk_ops auxclk_src_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, +}; + +DEFINE_CLK_OMAP_MUX_GATE (auxclk0_src_ck,NULL , auxclk_src_sel, +OMAP5_SCRM_AUXCLK0 ,OMAP5_SRCSELECT_MASK , +OMAP5_SCRM_AUXCLK0 ,OMAP5_ENABLE_SHIFT ,NULL , + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER (auxclk0_ck,"auxclk0_src_ck" , &auxclk0_src_ck,0x0 , +OMAP5_SCRM_AUXCLK0 ,OMAP5_CLKDIV_SHIFT ,OMAP5_CLKDIV_WIDTH , +0x0 ,NULL ); + +DEFINE_CLK_OMAP_MUX_GATE (auxclk1_src_ck,NULL , auxclk_src_sel, +OMAP5_SCRM_AUXCLK1 ,OMAP5_SRCSELECT_MASK , +OMAP5_SCRM_AUXCLK1 ,OMAP5_ENABLE_SHIFT ,NULL , + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER (auxclk1_ck,"auxclk1_src_ck" , &auxclk1_src_ck,0x0 , +OMAP5_SCRM_AUXCLK1 ,OMAP5_CLKDIV_SHIFT ,OMAP5_CLKDIV_WIDTH , +0x0 ,NULL ); + +DEFINE_CLK_OMAP_MUX_GATE (auxclk2_src_ck,NULL , auxclk_src_sel, +OMAP5_SCRM_AUXCLK2 ,OMAP5_SRCSELECT_MASK , +OMAP5_SCRM_AUXCLK2 ,OMAP5_ENABLE_SHIFT ,NULL , + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER (auxclk2_ck,"auxclk2_src_ck" , &auxclk2_src_ck,0x0 , +OMAP5_SCRM_AUXCLK2 ,OMAP5_CLKDIV_SHIFT ,OMAP5_CLKDIV_WIDTH , +0x0 ,NULL ); + +DEFINE_CLK_OMAP_MUX_GATE (auxclk3_src_ck,NULL , auxclk_src_sel, +OMAP5_SCRM_AUXCLK3 ,OMAP5_SRCSELECT_MASK , +OMAP5_SCRM_AUXCLK3 ,OMAP5_ENABLE_SHIFT ,NULL , + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER (auxclk3_ck,"auxclk3_src_ck" , &auxclk3_src_ck,0x0 , +OMAP5_SCRM_AUXCLK3 ,OMAP5_CLKDIV_SHIFT ,OMAP5_CLKDIV_WIDTH , +0x0 ,NULL ); + +static const char *auxclkreq_ck_parents[] = { +"auxclk0_ck" ,"auxclk1_ck" ,"auxclk2_ck" ,"auxclk3_ck" ,"auxclk4_ck" , +"auxclk5_ck" , +}; + +DEFINE_CLK_MUX (auxclkreq0_ck, auxclkreq_ck_parents,NULL ,0x0 , +OMAP5_SCRM_AUXCLKREQ0 ,OMAP5_MAPPING_SHIFT ,OMAP5_MAPPING_WIDTH , +0x0 ,NULL ); + +DEFINE_CLK_MUX (auxclkreq1_ck, auxclkreq_ck_parents,NULL ,0x0 , +OMAP5_SCRM_AUXCLKREQ1 ,OMAP5_MAPPING_SHIFT ,OMAP5_MAPPING_WIDTH , +0x0 ,NULL ); + +DEFINE_CLK_MUX (auxclkreq2_ck, auxclkreq_ck_parents,NULL ,0x0 , +OMAP5_SCRM_AUXCLKREQ2 ,OMAP5_MAPPING_SHIFT ,OMAP5_MAPPING_WIDTH , +0x0 ,NULL ); + +DEFINE_CLK_MUX (auxclkreq3_ck, auxclkreq_ck_parents,NULL ,0x0 , +OMAP5_SCRM_AUXCLKREQ3 ,OMAP5_MAPPING_SHIFT ,OMAP5_MAPPING_WIDTH , +0x0 ,NULL ); + +/* +* clkdev +*/ + +static struct omap_clk omap54xx_clks[] = { +CLK (NULL ,"pad_clks_src_ck" , &pad_clks_src_ck,CK_54XX ), +CLK (NULL ,"pad_clks_ck" , &pad_clks_ck,CK_54XX ), +CLK (NULL ,"secure_32k_clk_src_ck" , &secure_32k_clk_src_ck,CK_54XX ), +CLK (NULL ,"slimbus_src_clk" , &slimbus_src_clk,CK_54XX ), +CLK (NULL ,"slimbus_clk" , &slimbus_clk,CK_54XX ), +CLK (NULL ,"sys_32k_ck" , &sys_32k_ck,CK_54XX ), +CLK (NULL ,"virt_12000000_ck" , &virt_12000000_ck,CK_54XX ), +CLK (NULL ,"virt_13000000_ck" , &virt_13000000_ck,CK_54XX ), +CLK (NULL ,"virt_16800000_ck" , &virt_16800000_ck,CK_54XX ), +CLK (NULL ,"virt_19200000_ck" , &virt_19200000_ck,CK_54XX ), +CLK (NULL ,"virt_26000000_ck" , &virt_26000000_ck,CK_54XX ), +CLK (NULL ,"virt_27000000_ck" , &virt_27000000_ck,CK_54XX ), +CLK (NULL ,"virt_38400000_ck" , &virt_38400000_ck,CK_54XX ), +CLK (NULL ,"sys_clkin" , &sys_clkin,CK_54XX ), +CLK (NULL ,"xclk60mhsp1_ck" , &xclk60mhsp1_ck,CK_54XX ), +CLK (NULL ,"xclk60mhsp2_ck" , &xclk60mhsp2_ck,CK_54XX ), +CLK (NULL ,"abe_dpll_bypass_clk_mux" , &abe_dpll_bypass_clk_mux,CK_54XX ), +CLK (NULL ,"abe_dpll_clk_mux" , &abe_dpll_clk_mux,CK_54XX ), +CLK (NULL ,"dpll_abe_ck" , &dpll_abe_ck,CK_54XX ), +CLK (NULL ,"dpll_abe_x2_ck" , &dpll_abe_x2_ck,CK_54XX ), +CLK (NULL ,"dpll_abe_m2x2_ck" , &dpll_abe_m2x2_ck,CK_54XX ), +CLK (NULL ,"abe_24m_fclk" , &abe_24m_fclk,CK_54XX ), +CLK (NULL ,"abe_clk" , &abe_clk,CK_54XX ), +CLK (NULL ,"abe_iclk" , &abe_iclk,CK_54XX ), +CLK (NULL ,"abe_lp_clk_div" , &abe_lp_clk_div,CK_54XX ), +CLK (NULL ,"dpll_abe_m3x2_ck" , &dpll_abe_m3x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_ck" , &dpll_core_ck,CK_54XX ), +CLK (NULL ,"dpll_core_x2_ck" , &dpll_core_x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h21x2_ck" , &dpll_core_h21x2_ck,CK_54XX ), +CLK (NULL ,"c2c_fclk" , &c2c_fclk,CK_54XX ), +CLK (NULL ,"c2c_iclk" , &c2c_iclk,CK_54XX ), +CLK (NULL ,"custefuse_sys_gfclk_div" , &custefuse_sys_gfclk_div,CK_54XX ), +CLK (NULL ,"dpll_core_h11x2_ck" , &dpll_core_h11x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h12x2_ck" , &dpll_core_h12x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h13x2_ck" , &dpll_core_h13x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h14x2_ck" , &dpll_core_h14x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h22x2_ck" , &dpll_core_h22x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h23x2_ck" , &dpll_core_h23x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h24x2_ck" , &dpll_core_h24x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_m2_ck" , &dpll_core_m2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_m3x2_ck" , &dpll_core_m3x2_ck,CK_54XX ), +CLK (NULL ,"iva_dpll_hs_clk_div" , &iva_dpll_hs_clk_div,CK_54XX ), +CLK (NULL ,"dpll_iva_ck" , &dpll_iva_ck,CK_54XX ), +CLK (NULL ,"dpll_iva_x2_ck" , &dpll_iva_x2_ck,CK_54XX ), +CLK (NULL ,"dpll_iva_h11x2_ck" , &dpll_iva_h11x2_ck,CK_54XX ), +CLK (NULL ,"dpll_iva_h12x2_ck" , &dpll_iva_h12x2_ck,CK_54XX ), +CLK (NULL ,"mpu_dpll_hs_clk_div" , &mpu_dpll_hs_clk_div,CK_54XX ), +CLK (NULL ,"dpll_mpu_ck" , &dpll_mpu_ck,CK_54XX ), +CLK (NULL ,"dpll_mpu_m2_ck" , &dpll_mpu_m2_ck,CK_54XX ), +CLK (NULL ,"per_dpll_hs_clk_div" , &per_dpll_hs_clk_div,CK_54XX ), +CLK (NULL ,"dpll_per_ck" , &dpll_per_ck,CK_54XX ), +CLK (NULL ,"dpll_per_x2_ck" , &dpll_per_x2_ck,CK_54XX ), +CLK (NULL ,"dpll_per_h11x2_ck" , &dpll_per_h11x2_ck,CK_54XX ), +CLK (NULL ,"dpll_per_h12x2_ck" , &dpll_per_h12x2_ck,CK_54XX ), +CLK (NULL ,"dpll_per_h14x2_ck" , &dpll_per_h14x2_ck,CK_54XX ), +CLK (NULL ,"dpll_per_m2_ck" , &dpll_per_m2_ck,CK_54XX ), +CLK (NULL ,"dpll_per_m2x2_ck" , &dpll_per_m2x2_ck,CK_54XX ), +CLK (NULL ,"dpll_per_m3x2_ck" , &dpll_per_m3x2_ck,CK_54XX ), +CLK (NULL ,"dpll_unipro1_ck" , &dpll_unipro1_ck,CK_54XX ), +CLK (NULL ,"dpll_unipro1_clkdcoldo" , &dpll_unipro1_clkdcoldo,CK_54XX ), +CLK (NULL ,"dpll_unipro1_m2_ck" , &dpll_unipro1_m2_ck,CK_54XX ), +CLK (NULL ,"dpll_unipro2_ck" , &dpll_unipro2_ck,CK_54XX ), +CLK (NULL ,"dpll_unipro2_clkdcoldo" , &dpll_unipro2_clkdcoldo,CK_54XX ), +CLK (NULL ,"dpll_unipro2_m2_ck" , &dpll_unipro2_m2_ck,CK_54XX ), +CLK (NULL ,"usb_dpll_hs_clk_div" , &usb_dpll_hs_clk_div,CK_54XX ), +CLK (NULL ,"dpll_usb_ck" , &dpll_usb_ck,CK_54XX ), +CLK (NULL ,"dpll_usb_clkdcoldo" , &dpll_usb_clkdcoldo,CK_54XX ), +CLK (NULL ,"dpll_usb_m2_ck" , &dpll_usb_m2_ck,CK_54XX ), +CLK (NULL ,"dss_syc_gfclk_div" , &dss_syc_gfclk_div,CK_54XX ), +CLK (NULL ,"l3_iclk_div" , &l3_iclk_div,CK_54XX ), +CLK (NULL ,"func_128m_clk" , &func_128m_clk,CK_54XX ), +CLK (NULL ,"func_12m_fclk" , &func_12m_fclk,CK_54XX ), +CLK (NULL ,"func_24m_clk" , &func_24m_clk,CK_54XX ), +CLK (NULL ,"func_48m_fclk" , &func_48m_fclk,CK_54XX ), +CLK (NULL ,"func_96m_fclk" , &func_96m_fclk,CK_54XX ), +CLK (NULL ,"gpu_core_gclk_mux" , &gpu_core_gclk_mux,CK_54XX ), +CLK (NULL ,"gpu_hyd_gclk_mux" , &gpu_hyd_gclk_mux,CK_54XX ), +CLK (NULL ,"gpu_l3_iclk" , &gpu_l3_iclk,CK_54XX ), +CLK (NULL ,"l3init_60m_fclk" , &l3init_60m_fclk,CK_54XX ), +CLK (NULL ,"wkupaon_iclk_mux" , &wkupaon_iclk_mux,CK_54XX ), +CLK (NULL ,"l3instr_ts_gclk_div" , &l3instr_ts_gclk_div,CK_54XX ), +CLK (NULL ,"l4_root_clk_div" , &l4_root_clk_div,CK_54XX ), +CLK (NULL ,"timer10_gfclk_mux" , &timer10_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer11_gfclk_mux" , &timer11_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer1_gfclk_mux" , &timer1_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer2_gfclk_mux" , &timer2_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer3_gfclk_mux" , &timer3_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer4_gfclk_mux" , &timer4_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer5_gfclk_mux" , &timer5_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer6_gfclk_mux" , &timer6_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer7_gfclk_mux" , &timer7_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer8_gfclk_mux" , &timer8_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer9_gfclk_mux" , &timer9_gfclk_mux,CK_54XX ), +CLK (NULL ,"dss_32khz_clk" , &dss_32khz_clk,CK_54XX ), +CLK (NULL ,"dss_48mhz_clk" , &dss_48mhz_clk,CK_54XX ), +CLK (NULL ,"dss_dss_clk" , &dss_dss_clk,CK_54XX ), +CLK (NULL ,"dss_sys_clk" , &dss_sys_clk,CK_54XX ), +CLK (NULL ,"gpio1_dbclk" , &gpio1_dbclk,CK_54XX ), +CLK (NULL ,"gpio2_dbclk" , &gpio2_dbclk,CK_54XX ), +CLK (NULL ,"gpio3_dbclk" , &gpio3_dbclk,CK_54XX ), +CLK (NULL ,"gpio4_dbclk" , &gpio4_dbclk,CK_54XX ), +CLK (NULL ,"gpio5_dbclk" , &gpio5_dbclk,CK_54XX ), +CLK (NULL ,"gpio6_dbclk" , &gpio6_dbclk,CK_54XX ), +CLK (NULL ,"gpio7_dbclk" , &gpio7_dbclk,CK_54XX ), +CLK (NULL ,"gpio8_dbclk" , &gpio8_dbclk,CK_54XX ), +CLK (NULL ,"iss_ctrlclk" , &iss_ctrlclk,CK_54XX ), +CLK (NULL ,"lli_txphy_clk" , &lli_txphy_clk,CK_54XX ), +CLK (NULL ,"lli_txphy_ls_clk" , &lli_txphy_ls_clk,CK_54XX ), +CLK (NULL ,"mmc1_32khz_clk" , &mmc1_32khz_clk,CK_54XX ), +CLK (NULL ,"sata_ref_clk" , &sata_ref_clk,CK_54XX ), +CLK (NULL ,"slimbus1_slimbus_clk" , &slimbus1_slimbus_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_hsic480m_p1_clk" , &usb_host_hs_hsic480m_p1_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_hsic480m_p2_clk" , &usb_host_hs_hsic480m_p2_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_hsic480m_p3_clk" , &usb_host_hs_hsic480m_p3_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_hsic60m_p1_clk" , &usb_host_hs_hsic60m_p1_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_hsic60m_p2_clk" , &usb_host_hs_hsic60m_p2_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_hsic60m_p3_clk" , &usb_host_hs_hsic60m_p3_clk,CK_54XX ), +CLK (NULL ,"utmi_p1_gfclk" , &utmi_p1_gfclk,CK_54XX ), +CLK (NULL ,"usb_host_hs_utmi_p1_clk" , &usb_host_hs_utmi_p1_clk,CK_54XX ), +CLK (NULL ,"utmi_p2_gfclk" , &utmi_p2_gfclk,CK_54XX ), +CLK (NULL ,"usb_host_hs_utmi_p2_clk" , &usb_host_hs_utmi_p2_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_utmi_p3_clk" , &usb_host_hs_utmi_p3_clk,CK_54XX ), +CLK (NULL ,"usb_otg_ss_refclk960m" , &usb_otg_ss_refclk960m,CK_54XX ), +CLK (NULL ,"usb_tll_hs_usb_ch0_clk" , &usb_tll_hs_usb_ch0_clk,CK_54XX ), +CLK (NULL ,"usb_tll_hs_usb_ch1_clk" , &usb_tll_hs_usb_ch1_clk,CK_54XX ), +CLK (NULL ,"usb_tll_hs_usb_ch2_clk" , &usb_tll_hs_usb_ch2_clk,CK_54XX ), +CLK (NULL ,"aess_fclk" , &aess_fclk,CK_54XX ), +CLK (NULL ,"dmic_sync_mux_ck" , &dmic_sync_mux_ck,CK_54XX ), +CLK (NULL ,"dmic_gfclk" , &dmic_gfclk,CK_54XX ), +CLK (NULL ,"fdif_fclk" , &fdif_fclk,CK_54XX ), +CLK (NULL ,"hsi_fclk" , &hsi_fclk,CK_54XX ), +CLK (NULL ,"mcasp_sync_mux_ck" , &mcasp_sync_mux_ck,CK_54XX ), +CLK (NULL ,"mcasp_gfclk" , &mcasp_gfclk,CK_54XX ), +CLK (NULL ,"mcbsp1_sync_mux_ck" , &mcbsp1_sync_mux_ck,CK_54XX ), +CLK (NULL ,"mcbsp1_gfclk" , &mcbsp1_gfclk,CK_54XX ), +CLK (NULL ,"mcbsp2_sync_mux_ck" , &mcbsp2_sync_mux_ck,CK_54XX ), +CLK (NULL ,"mcbsp2_gfclk" , &mcbsp2_gfclk,CK_54XX ), +CLK (NULL ,"mcbsp3_sync_mux_ck" , &mcbsp3_sync_mux_ck,CK_54XX ), +CLK (NULL ,"mcbsp3_gfclk" , &mcbsp3_gfclk,CK_54XX ), +CLK (NULL ,"mmc1_fclk_mux" , &mmc1_fclk_mux,CK_54XX ), +CLK (NULL ,"mmc1_fclk" , &mmc1_fclk,CK_54XX ), +CLK (NULL ,"mmc2_fclk_mux" , &mmc2_fclk_mux,CK_54XX ), +CLK (NULL ,"mmc2_fclk" , &mmc2_fclk,CK_54XX ), +CLK (NULL ,"utmi_p1_gfclk" , &utmi_p1_gfclk,CK_54XX ), +CLK (NULL ,"utmi_p2_gfclk" , &utmi_p2_gfclk,CK_54XX ), +CLK (NULL ,"auxclk0_src_ck" , &auxclk0_src_ck,CK_54XX ), +CLK (NULL ,"auxclk0_ck" , &auxclk0_ck,CK_54XX ), +CLK (NULL ,"auxclkreq0_ck" , &auxclkreq0_ck,CK_54XX ), +CLK (NULL ,"auxclk1_src_ck" , &auxclk1_src_ck,CK_54XX ), +CLK (NULL ,"auxclk1_ck" , &auxclk1_ck,CK_54XX ), +CLK (NULL ,"auxclkreq1_ck" , &auxclkreq1_ck,CK_54XX ), +CLK (NULL ,"auxclk2_src_ck" , &auxclk2_src_ck,CK_54XX ), +CLK (NULL ,"auxclk2_ck" , &auxclk2_ck,CK_54XX ), +CLK (NULL ,"auxclkreq2_ck" , &auxclkreq2_ck,CK_54XX ), +CLK (NULL ,"auxclk3_src_ck" , &auxclk3_src_ck,CK_54XX ), +CLK (NULL ,"auxclk3_ck" , &auxclk3_ck,CK_54XX ), +CLK (NULL ,"auxclkreq3_ck" , &auxclkreq3_ck,CK_54XX ), +CLK (NULL ,"gpmc_ck" , &dummy_ck,CK_54XX ), +CLK ("omap_i2c.1" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_i2c.2" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_i2c.3" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_i2c.4" ,"ick" , &dummy_ck,CK_54XX ), +CLK (NULL ,"mailboxes_ick" , &dummy_ck,CK_54XX ), +CLK ("omap_hsmmc.0" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_hsmmc.1" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_hsmmc.2" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_hsmmc.3" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_hsmmc.4" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap-mcbsp.1" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap-mcbsp.2" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap-mcbsp.3" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap-mcbsp.4" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap2_mcspi.1" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap2_mcspi.2" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap2_mcspi.3" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap2_mcspi.4" ,"ick" , &dummy_ck,CK_54XX ), +CLK (NULL ,"uart1_ick" , &dummy_ck,CK_54XX ), +CLK (NULL ,"uart2_ick" , &dummy_ck,CK_54XX ), +CLK (NULL ,"uart3_ick" , &dummy_ck,CK_54XX ), +CLK (NULL ,"uart4_ick" , &dummy_ck,CK_54XX ), +CLK ("usbhs_omap" ,"usbhost_ick" , &dummy_ck,CK_54XX ), +CLK ("usbhs_omap" ,"usbtll_fck" , &dummy_ck,CK_54XX ), +CLK ("omap_wdt" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_timer.1" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.2" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.3" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.4" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.5" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.6" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.7" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.8" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.9" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.10" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.11" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.1" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.2" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.3" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.4" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.9" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.10" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.11" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.5" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), +CLK ("omap_timer.6" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), +CLK ("omap_timer.7" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), +CLK ("omap_timer.8" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), +}; + +int __init omap5xxx_clk_init (void ) +{ +u32 cpu_clkflg; +struct omap_clk *c; + +if (soc_is_omap54xx ()) { + cpu_mask =RATE_IN_54XX ; + cpu_clkflg =CK_54XX ; + } + +/* +* Must stay commented until all OMAP SoC drivers are +* converted to runtime PM, or drivers may start crashing +* +* omap2_clk_disable_clkdm_control(); +*/ + +for (c = omap54xx_clks; c < omap54xx_clks +ARRAY_SIZE (omap54xx_clks); + c++) { +if (c->cpu & cpu_clkflg) { +clkdev_add (&c->lk); +if (!__clk_init (NULL , c->lk.clk)) +omap2_init_clk_hw_omap_clocks (c->lk.clk); + } + } + +omap2_clk_disable_autoidle_all (); + +return 0 ; +}
arch/arm/mach-omap2/clock.h +22 -1
@@ -48,6 +48,7 @@ struct omap_clk {#define CK_TI816X (1 << 7)#define CK_446X (1 << 8)#define CK_AM33XX (1 << 9)/* AM33xx specific clocks */ +#define CK_54XX (1 << 10)/* OMAP54xx specific clocks */ #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
@@ -107,13 +108,31 @@ struct clockdomain; }; \DEFINE_STRUCT_CLK (_name, _parent_names, _ops); + +#define DEFINE_CLK_OMAP_HSDIVIDER63 (_name, _parent_name, \ + _parent_ptr, _flags, \ + _clksel_reg, _clksel_mask) \ + \ + _DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ + _parent_ptr, _flags, \ + _clksel_reg, _clksel_mask, 63) +#define DEFINE_CLK_OMAP_HSDIVIDER (_name, _parent_name, \ _parent_ptr, _flags, \ _clksel_reg, _clksel_mask) \ + \ + _DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ + _parent_ptr, _flags, \ + _clksel_reg, _clksel_mask, 31) + + +#define _DEFINE_CLK_OMAP_HSDIVIDER (_name, _parent_name, \ + _parent_ptr, _flags, \ + _clksel_reg, _clksel_mask, mdiv)\ static const struct clksel _name##_div[] = { \ { \ .parent = _parent_ptr, \ - .rates = div31_1to31_rates \ + .rates = div##mdiv##_1to##mdiv##_rates \ }, \ { .parent = NULL }, \ }; \
@@ -143,6 +162,7 @@ struct clockdomain;#define RATE_IN_4460 (1 << 7)#define RATE_IN_AM33XX (1 << 8)#define RATE_IN_TI814X (1 << 9) +#define RATE_IN_54XX (1 << 10)#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@@ -463,6 +483,7 @@ extern const struct clksel_rate div_1_2_rates[];extern const struct clksel_rate div_1_3_rates[];extern const struct clksel_rate div_1_4_rates[];extern const struct clksel_rate div31_1to31_rates[]; +extern const struct clksel_rate div63_1to63_rates[];extern int am33xx_clk_init (void );
arch/arm/mach-omap2/clock54xx.h new file +12 -0
@@ -0,0 +1,12 @@ +/* +* OMAP5 clock function prototypes and macros +* +* Copyright (C) 2013 Texas Instruments, Inc. +*/ + +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK54XX_H +#define __ARCH_ARM_MACH_OMAP2_CLOCK54XX_H + +int omap5xxx_clk_init (void ); + +#endif
arch/arm/mach-omap2/clock_common_data.c +103 -36
167 lines not on this page · raw message
Signature · 1 line
1.7.9.5
Tony Lindgren
maintainerPATCH 7/10 ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
Quoted 6 lines · Santosh Shilimkar
From: Rajendra Nayak <[email protected]>
Add the clock tree related data for OMAP54xx platforms.
Cc Paul Walmsley <[email protected]>
Quoted 7 lines
Signed-off-by Rajendra Nayak <[email protected]>Signed-off-by Benoit Cousson <[email protected]>[santosh.shilimkar at ti.com: Generated es2.0 data]Signed-off-by Santosh Shilimkar <[email protected]>---
As mentioned in the summary, this patch will be updated once the movement of clock data todrivers/clockis clear.
Yes let's first fix up the issues prevent us from moving all the cclock*_data.c files to live under drivers/clock/omap.
It seems that fixing this issue boils down to rearranging some clock related headers in arch/arm/mach-omap2, and then populating some of the clock data dynamically. Or am I missing something?
Regards,
Tony
PATCH 7/10 ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
Quoted 15 lines · Tony Lindgren
Quoted 6 lines · Santosh Shilimkar
From: Rajendra Nayak <[email protected]>
Add the clock tree related data for OMAP54xx platforms.
Cc Paul Walmsley <[email protected]>Quoted 7 lines
Signed-off-by Rajendra Nayak <[email protected]>Signed-off-by Benoit Cousson <[email protected]>[[email protected]: Generated es2.0 data]Signed-off-by Santosh Shilimkar <[email protected]>---
As mentioned in the summary, this patch will be updated once the movement of clock data todrivers/clockis clear.
Quoted 7 lines
Yes let's first fix up the issues prevent us from moving all the cclock*_data.c files to live under
drivers/clock/omap.It seems that fixing this issue boils down to rearranging some clock related headers in
arch/arm/mach-omap2, and then populating some of the clock data dynamically. Or am I missing something?
Am not sure of all the dependencies. Since clock data is using the low level prm/cm APIs, all those needs to be exported some how to move the data. Paul can comment better on it.
Regards,
Santosh
Tony Lindgren
maintainerPATCH 7/10 ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
Quoted 19 lines · Santosh Shilimkar
Quoted 18 lines · Tony Lindgren
Quoted 6 lines · Santosh Shilimkar
From: Rajendra Nayak <[email protected]>
Add the clock tree related data for OMAP54xx platforms.
Cc Paul Walmsley <[email protected]>Quoted 7 lines
Signed-off-by Rajendra Nayak <[email protected]>Signed-off-by Benoit Cousson <[email protected]>[santosh.shilimkar at ti.com: Generated es2.0 data]Signed-off-by Santosh Shilimkar <[email protected]>---
As mentioned in the summary, this patch will be updated once the movement of clock data todrivers/clockis clear.Yes let's first fix up the issues prevent us from moving all the cclock*_data.c files to live under
drivers/clock/omap.
Quoted 7 lines
Quoted 4 lines
It seems that fixing this issue boils down to rearranging some clock related headers in
arch/arm/mach-omap2, and then populating some of the clock data dynamically. Or am I missing something?Am not sure of all the dependencies. Since clock data is using the low level prm/cm APIs, all those needs to be exported some how to move the data. Paul can comment better on it.
It seems that we should be able to export some omap specific functions from drivers/clk/omap for that.
Regards,
Tony
PATCH 7/10 ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
In reply to Santosh ShilimkarHi Santosh,
I check the tree with Audio and it is working. Just a comment for the addition of ABE DPLL locking like for OMAP4.
Sebastien
Quoted 1,809 lines · Santosh Shilimkar
From: Rajendra Nayak <[email protected]>
Add the clock tree related data for OMAP54xx platforms.
Cc Paul Walmsley <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>Signed-off-by Benoit Cousson <[email protected]>[santosh.shilimkar at ti.com: Generated es2.0 data]Signed-off-by Santosh Shilimkar <[email protected]>---
As mentioned in the summary, this patch will be updated once the movement of clock data todrivers/clockis clear.arch/arm/mach-omap2/cclock54xx_data.c | 1794 +++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock.h | 23 +- arch/arm/mach-omap2/clock54xx.h | 12 + arch/arm/mach-omap2/clock_common_data.c | 139 ++- 4 files changed, 1931 insertions(+), 37 deletions(-)create mode 100644
arch/arm/mach-omap2/cclock54xx_data.ccreate mode 100644arch/arm/mach-omap2/clock54xx.harch/arm/mach-omap2/cclock54xx_data.c new file +1781
-0@@ -0,0 +1,1794 @@ +/* +* OMAP54xx Clock data +* +* Copyright (C) 2013 Texas Instruments, Inc. +* +* Paul Walmsley (paul at pwsan.com) +* Rajendra Nayak (rnayak at ti.com) +* Benoit Cousson (b-cousson at ti.com) +* Mike Turquette (mturquette at ti.com) +* +* This file is automatically generated from the OMAP hardware databases. +* We respectfully ask that any modifications to this file be coordinated +* with the public linux-omap at vger.kernel.org mailing list and the +* authors above to ensure that the autogeneration scripts are kept +* up-to-date with the file contents. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* XXX Some of the ES1 clocks have been removed/changed; once support +* is added for discriminating clocks by ES level, these should be added back +* in. +*/ + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/clk-private.h> +#include <linux/clkdev.h> +#include <linux/io.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock54xx.h" +#include "cm1_54xx.h" +#include "cm2_54xx.h" +#include "cm-regbits-54xx.h" +#include "prm54xx.h" +#include "prm-regbits-54xx.h" +#include "control.h" +#include "scrm54xx.h" + +/* OMAP4 modulemode control */ +#define OMAP54XX_MODULEMODE_HWCTRL 0 +#define OMAP54XX_MODULEMODE_SWCTRL 1 + +/* Root clocks */ + +DEFINE_CLK_FIXED_RATE (pad_clks_src_ck,CLK_IS_ROOT ,12000000 ,0x0 ); + +DEFINE_CLK_GATE (pad_clks_ck,"pad_clks_src_ck" , &pad_clks_src_ck,0x0 , +OMAP54XX_CM_CLKSEL_ABE ,OMAP54XX_PAD_CLKS_GATE_SHIFT ,0x0 , +NULL ); + +DEFINE_CLK_FIXED_RATE (secure_32k_clk_src_ck,CLK_IS_ROOT ,32768 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (slimbus_src_clk,CLK_IS_ROOT ,12000000 ,0x0 ); + +DEFINE_CLK_GATE (slimbus_clk,"slimbus_src_clk" , &slimbus_src_clk,0x0 , +OMAP54XX_CM_CLKSEL_ABE ,OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT ,0x0 , +NULL ); + +DEFINE_CLK_FIXED_RATE (sys_32k_ck,CLK_IS_ROOT ,32768 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_12000000_ck,CLK_IS_ROOT ,12000000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_13000000_ck,CLK_IS_ROOT ,13000000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_16800000_ck,CLK_IS_ROOT ,16800000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_19200000_ck,CLK_IS_ROOT ,19200000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_26000000_ck,CLK_IS_ROOT ,26000000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_27000000_ck,CLK_IS_ROOT ,27000000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (virt_38400000_ck,CLK_IS_ROOT ,38400000 ,0x0 ); + +static const struct clksel_rate div_1_5_rates[] = { + { .div =1 , .val =5 , .flags =RATE_IN_54XX }, + { .div =0 }, +}; + +static const struct clksel_rate div_1_6_rates[] = { + { .div =1 , .val =6 , .flags =RATE_IN_54XX }, + { .div =0 }, +}; + +static const struct clksel_rate div_1_7_rates[] = { + { .div =1 , .val =7 , .flags =RATE_IN_54XX }, + { .div =0 }, +}; + +static const struct clksel sys_clkin_sel[] = { + { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, + { .parent = &virt_13000000_ck, .rates = div_1_2_rates }, + { .parent = &virt_16800000_ck, .rates = div_1_3_rates }, + { .parent = &virt_19200000_ck, .rates = div_1_4_rates }, + { .parent = &virt_26000000_ck, .rates = div_1_5_rates }, + { .parent = &virt_27000000_ck, .rates = div_1_6_rates }, + { .parent = &virt_38400000_ck, .rates = div_1_7_rates }, + { .parent =NULL }, +}; + +static const char *sys_clkin_parents[] = { +"virt_12000000_ck" , +"virt_13000000_ck" , +"virt_16800000_ck" , +"virt_19200000_ck" , +"virt_26000000_ck" , +"virt_27000000_ck" , +"virt_38400000_ck" , + +}; + +DEFINE_CLK_MUX (sys_clkin, sys_clkin_parents,NULL ,0x0 ,OMAP54XX_CM_CLKSEL_SYS , +OMAP54XX_SYS_CLKSEL_SHIFT ,OMAP54XX_SYS_CLKSEL_WIDTH , +CLK_MUX_INDEX_ONE ,NULL ); + +DEFINE_CLK_FIXED_RATE (xclk60mhsp1_ck,CLK_IS_ROOT ,60000000 ,0x0 ); + +DEFINE_CLK_FIXED_RATE (xclk60mhsp2_ck,CLK_IS_ROOT ,60000000 ,0x0 ); + +/* Module clocks and DPLL outputs */ + +static const char *abe_dpll_bypass_clk_mux_parents[] = { +"sys_clkin" ,"sys_32k_ck" , +}; + +DEFINE_CLK_MUX (abe_dpll_bypass_clk_mux, abe_dpll_bypass_clk_mux_parents,NULL , +0x0 ,OMAP54XX_CM_CLKSEL_WKUPAON ,OMAP54XX_CLKSEL_0_0_SHIFT , +OMAP54XX_CLKSEL_0_0_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (abe_dpll_clk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_CLKSEL_ABE_PLL_REF ,OMAP54XX_CLKSEL_0_0_SHIFT , +OMAP54XX_CLKSEL_0_0_WIDTH ,0x0 ,NULL ); + +/* DPLL_ABE */ +static struct dpll_data dpll_abe_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_ABE , + .clk_bypass = &abe_dpll_bypass_clk_mux, + .clk_ref = &abe_dpll_clk_mux, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_ABE , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_ABE , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_ABE , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =2047 , + .max_divider =128 , + .min_divider =1 , +}; + + +static const char *dpll_abe_ck_parents[] = { +"abe_dpll_clk_mux" , +}; + +static struct clk dpll_abe_ck; + +static const struct clk_ops dpll_abe_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap4_dpll_regm4xen_recalc, + .round_rate = &omap4_dpll_regm4xen_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_abe_ck_hw = { + .hw = { + .clk = &dpll_abe_ck, + }, + .dpll_data = &dpll_abe_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_abe_x2_ck_parents[] = { +"dpll_abe_ck" , +}; + +static struct clk dpll_abe_x2_ck; + +static const struct clk_ops dpll_abe_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, +}; + +static struct clk_hw_omap dpll_abe_x2_ck_hw = { + .hw = { + .clk = &dpll_abe_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK (dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops); + +static const struct clk_ops omap_hsdivider_ops = { + .set_rate = &omap2_clksel_set_rate, + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_abe_m2x2_ck,"dpll_abe_x2_ck" , &dpll_abe_x2_ck, +0x0 ,OMAP54XX_CM_DIV_M2_DPLL_ABE , +OMAP54XX_DIVHS_0_4_MASK ); + +DEFINE_CLK_FIXED_FACTOR (abe_24m_fclk,"dpll_abe_m2x2_ck" , &dpll_abe_m2x2_ck, +0x0 ,1 ,8 ); + +DEFINE_CLK_DIVIDER (abe_clk,"dpll_abe_m2x2_ck" , &dpll_abe_m2x2_ck,0x0 , +OMAP54XX_CM_CLKSEL_ABE ,OMAP54XX_CLKSEL_OPP_SHIFT , +OMAP54XX_CLKSEL_OPP_WIDTH ,CLK_DIVIDER_POWER_OF_TWO , +NULL ); + +DEFINE_CLK_FIXED_FACTOR (abe_iclk,"abe_clk" , &abe_clk,0x0 ,1 ,2 ); + +DEFINE_CLK_FIXED_FACTOR (abe_lp_clk_div,"dpll_abe_m2x2_ck" , &dpll_abe_m2x2_ck, +0x0 ,1 ,16 ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_abe_m3x2_ck,"dpll_abe_x2_ck" , &dpll_abe_x2_ck, +0x0 ,OMAP54XX_CM_DIV_M3_DPLL_ABE , +OMAP54XX_DIVHS_0_4_MASK ); + +/* DPLL_CORE */ +static struct dpll_data dpll_core_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_CORE , + .clk_bypass = &dpll_abe_m3x2_ck, + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_CORE , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_CORE , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_CORE , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =2047 , + .max_divider =128 , + .min_divider =1 , +}; + + +static const char *dpll_core_ck_parents[] = { +"sys_clkin" , +}; + +static struct clk dpll_core_ck; + +static const struct clk_ops dpll_core_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_core_ck_hw = { + .hw = { + .clk = &dpll_core_ck, + }, + .dpll_data = &dpll_core_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); + +static const char *dpll_core_x2_ck_parents[] = { +"dpll_core_ck" , +}; + +static struct clk dpll_core_x2_ck; + +static struct clk_hw_omap dpll_core_x2_ck_hw = { + .hw = { + .clk = &dpll_core_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK (dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h21x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H21_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +static const char *c2c_fclk_parents[] = { +"dpll_core_h21x2_ck" , +}; + +static struct clk c2c_fclk; + +static const struct clk_ops c2c_fclk_ops = { +}; + +static struct clk_hw_omap c2c_fclk_hw = { + .hw = { + .clk = &c2c_fclk, + }, +}; + +DEFINE_STRUCT_CLK (c2c_fclk, c2c_fclk_parents, c2c_fclk_ops); + +DEFINE_CLK_FIXED_FACTOR (c2c_iclk,"c2c_fclk" , &c2c_fclk,0x0 ,1 ,2 ); + +DEFINE_CLK_FIXED_FACTOR (custefuse_sys_gfclk_div,"sys_clkin" , &sys_clkin,0x0 , +1 ,2 ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h11x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H11_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h12x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H12_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h13x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H13_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h14x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H14_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h22x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H22_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h23x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H23_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_h24x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 , +OMAP54XX_CM_DIV_H24_DPLL_CORE ,OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_m2_ck,"dpll_core_ck" , &dpll_core_ck,0x0 , +OMAP54XX_CM_DIV_M2_DPLL_CORE , +OMAP54XX_DIVHS_0_4_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_core_m3x2_ck,"dpll_core_x2_ck" , + &dpll_core_x2_ck,0x0 ,OMAP54XX_CM_DIV_M3_DPLL_CORE , +OMAP54XX_DIVHS_0_4_MASK ); + +static const char *iva_dpll_hs_clk_div_parents[] = { +"dpll_core_h12x2_ck" , +}; + +static struct clk iva_dpll_hs_clk_div; + +static struct clk_hw_omap iva_dpll_hs_clk_div_hw = { + .hw = { + .clk = &iva_dpll_hs_clk_div, + }, +}; + +DEFINE_STRUCT_CLK (iva_dpll_hs_clk_div, iva_dpll_hs_clk_div_parents, + c2c_fclk_ops); + +/* DPLL_IVA */ +static struct dpll_data dpll_iva_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_IVA , + .clk_bypass = &iva_dpll_hs_clk_div, + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_IVA , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_IVA , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_IVA , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =2047 , + .max_divider =128 , + .min_divider =1 , +}; + + +static struct clk dpll_iva_ck; + +static const struct clk_ops dpll_iva_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_iva_ck_hw = { + .hw = { + .clk = &dpll_iva_ck, + }, + .dpll_data = &dpll_iva_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_iva_ck, dpll_core_ck_parents, dpll_iva_ck_ops); + +static const char *dpll_iva_x2_ck_parents[] = { +"dpll_iva_ck" , +}; + +static struct clk dpll_iva_x2_ck; + +static struct clk_hw_omap dpll_iva_x2_ck_hw = { + .hw = { + .clk = &dpll_iva_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK (dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_iva_h11x2_ck,"dpll_iva_x2_ck" , + &dpll_iva_x2_ck,0x0 ,OMAP54XX_CM_DIV_H11_DPLL_IVA , +OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_iva_h12x2_ck,"dpll_iva_x2_ck" , + &dpll_iva_x2_ck,0x0 ,OMAP54XX_CM_DIV_H12_DPLL_IVA , +OMAP54XX_DIVHS_MASK ); + +static struct clk mpu_dpll_hs_clk_div; + +static struct clk_hw_omap mpu_dpll_hs_clk_div_hw = { + .hw = { + .clk = &mpu_dpll_hs_clk_div, + }, +}; + +DEFINE_STRUCT_CLK (mpu_dpll_hs_clk_div, iva_dpll_hs_clk_div_parents, + c2c_fclk_ops); + +/* DPLL_MPU */ +static struct dpll_data dpll_mpu_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_MPU , + .clk_bypass = &mpu_dpll_hs_clk_div, + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_MPU , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_MPU , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_MPU , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =2047 , + .max_divider =128 , + .min_divider =1 , +}; + + +static struct clk dpll_mpu_ck; + +static struct clk_hw_omap dpll_mpu_ck_hw = { + .hw = { + .clk = &dpll_mpu_ck, + }, + .dpll_data = &dpll_mpu_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_mpu_ck, dpll_core_ck_parents, dpll_iva_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_mpu_m2_ck,"dpll_mpu_ck" , &dpll_mpu_ck,0x0 , +OMAP54XX_CM_DIV_M2_DPLL_MPU , +OMAP54XX_DIVHS_0_4_MASK ); + +DEFINE_CLK_FIXED_FACTOR (per_dpll_hs_clk_div,"dpll_abe_m3x2_ck" , + &dpll_abe_m3x2_ck,0x0 ,1 ,2 ); + +/* DPLL_PER */ +static struct dpll_data dpll_per_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_PER , + .clk_bypass = &per_dpll_hs_clk_div, + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_PER , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_PER , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_PER , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =2047 , + .max_divider =128 , + .min_divider =1 , +}; + + +static struct clk dpll_per_ck; + +static struct clk_hw_omap dpll_per_ck_hw = { + .hw = { + .clk = &dpll_per_ck, + }, + .dpll_data = &dpll_per_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_per_ck, dpll_core_ck_parents, dpll_iva_ck_ops); + +static const char *dpll_per_x2_ck_parents[] = { +"dpll_per_ck" , +}; + +static struct clk dpll_per_x2_ck; + +static struct clk_hw_omap dpll_per_x2_ck_hw = { + .hw = { + .clk = &dpll_per_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK (dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_per_h11x2_ck,"dpll_per_x2_ck" , + &dpll_per_x2_ck,0x0 ,OMAP54XX_CM_DIV_H11_DPLL_PER , +OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_per_h12x2_ck,"dpll_per_x2_ck" , + &dpll_per_x2_ck,0x0 ,OMAP54XX_CM_DIV_H12_DPLL_PER , +OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_per_h14x2_ck,"dpll_per_x2_ck" , + &dpll_per_x2_ck,0x0 ,OMAP54XX_CM_DIV_H14_DPLL_PER , +OMAP54XX_DIVHS_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_per_m2_ck,"dpll_per_ck" , &dpll_per_ck,0x0 , +OMAP54XX_CM_DIV_M2_DPLL_PER , +OMAP54XX_DIVHS_0_4_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_per_m2x2_ck,"dpll_per_x2_ck" , &dpll_per_x2_ck, +0x0 ,OMAP54XX_CM_DIV_M2_DPLL_PER , +OMAP54XX_DIVHS_0_4_MASK ); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_per_m3x2_ck,"dpll_per_x2_ck" , &dpll_per_x2_ck, +0x0 ,OMAP54XX_CM_DIV_M3_DPLL_PER , +OMAP54XX_DIVHS_0_4_MASK ); + +/* DPLL_UNIPRO1 */ +static struct dpll_data dpll_unipro1_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1 , + .clk_bypass = &sys_clkin, + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1 , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1 , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_UNIPRO1 , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =4095 , + .max_divider =256 , + .min_divider =1 , +}; + + +static struct clk dpll_unipro1_ck; + +static struct clk_hw_omap dpll_unipro1_ck_hw = { + .hw = { + .clk = &dpll_unipro1_ck, + }, + .dpll_data = &dpll_unipro1_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_unipro1_ck, dpll_core_ck_parents, dpll_iva_ck_ops); + +static const char *dpll_unipro1_clkdcoldo_parents[] = { +"dpll_unipro1_ck" , +}; + +static struct clk dpll_unipro1_clkdcoldo; + +static struct clk_hw_omap dpll_unipro1_clkdcoldo_hw = { + .hw = { + .clk = &dpll_unipro1_clkdcoldo, + }, + .clksel_reg =OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1 , +}; + +DEFINE_STRUCT_CLK (dpll_unipro1_clkdcoldo, dpll_unipro1_clkdcoldo_parents, + c2c_fclk_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_unipro1_m2_ck,"dpll_unipro1_ck" , + &dpll_unipro1_ck,0x0 , +OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1 , +OMAP54XX_DIVHS_0_6_MASK ); + +/* DPLL_UNIPRO2 */ +static struct dpll_data dpll_unipro2_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2 , + .clk_bypass = &sys_clkin, + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2 , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2 , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_UNIPRO2 , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .max_multiplier =4095 , + .max_divider =256 , + .min_divider =1 , +}; + + +static struct clk dpll_unipro2_ck; + +static struct clk_hw_omap dpll_unipro2_ck_hw = { + .hw = { + .clk = &dpll_unipro2_ck, + }, + .dpll_data = &dpll_unipro2_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_unipro2_ck, dpll_core_ck_parents, dpll_iva_ck_ops); + +static const char *dpll_unipro2_clkdcoldo_parents[] = { +"dpll_unipro2_ck" , +}; + +static struct clk dpll_unipro2_clkdcoldo; + +static struct clk_hw_omap dpll_unipro2_clkdcoldo_hw = { + .hw = { + .clk = &dpll_unipro2_clkdcoldo, + }, + .clksel_reg =OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2 , +}; + +DEFINE_STRUCT_CLK (dpll_unipro2_clkdcoldo, dpll_unipro2_clkdcoldo_parents, + c2c_fclk_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_unipro2_m2_ck,"dpll_unipro2_ck" , + &dpll_unipro2_ck,0x0 , +OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2 , +OMAP54XX_DIVHS_0_6_MASK ); + +DEFINE_CLK_FIXED_FACTOR (usb_dpll_hs_clk_div,"dpll_abe_m3x2_ck" , + &dpll_abe_m3x2_ck,0x0 ,1 ,3 ); + +/* DPLL_USB */ +static struct dpll_data dpll_usb_dd = { + .mult_div1_reg =OMAP54XX_CM_CLKSEL_DPLL_USB , + .clk_bypass = &usb_dpll_hs_clk_div, + .flags =DPLL_J_TYPE , + .clk_ref = &sys_clkin, + .control_reg =OMAP54XX_CM_CLKMODE_DPLL_USB , + .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), + .autoidle_reg =OMAP54XX_CM_AUTOIDLE_DPLL_USB , + .idlest_reg =OMAP54XX_CM_IDLEST_DPLL_USB , + .mult_mask =OMAP54XX_DPLL_MULT_MASK , + .div1_mask =OMAP54XX_DPLL_DIV_MASK , + .enable_mask =OMAP54XX_DPLL_EN_MASK , + .autoidle_mask =OMAP54XX_AUTO_DPLL_MODE_MASK , + .idlest_mask =OMAP54XX_ST_DPLL_CLK_MASK , + .sddiv_mask =OMAP54XX_DPLL_SD_DIV_MASK , + .max_multiplier =4095 , + .max_divider =256 , + .min_divider =1 , +}; + + +static struct clk dpll_usb_ck; + +static const struct clk_ops dpll_usb_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap dpll_usb_ck_hw = { + .hw = { + .clk = &dpll_usb_ck, + }, + .dpll_data = &dpll_usb_dd, + .clkdm_name ="l3init_clkdm" , + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK (dpll_usb_ck, dpll_core_ck_parents, dpll_usb_ck_ops); + +static const char *dpll_usb_clkdcoldo_parents[] = { +"dpll_usb_ck" , +}; + +static struct clk dpll_usb_clkdcoldo; + +static struct clk_hw_omap dpll_usb_clkdcoldo_hw = { + .hw = { + .clk = &dpll_usb_clkdcoldo, + }, + .clksel_reg =OMAP54XX_CM_CLKDCOLDO_DPLL_USB , +}; + +DEFINE_STRUCT_CLK (dpll_usb_clkdcoldo, dpll_usb_clkdcoldo_parents, c2c_fclk_ops); + +DEFINE_CLK_OMAP_HSDIVIDER63 (dpll_usb_m2_ck,"dpll_usb_ck" , &dpll_usb_ck,0x0 , +OMAP54XX_CM_DIV_M2_DPLL_USB , +OMAP54XX_DIVHS_0_6_MASK ); + +static const char *dss_syc_gfclk_div_parents[] = { +"sys_clkin" , +}; + +static struct clk dss_syc_gfclk_div; + +static struct clk_hw_omap dss_syc_gfclk_div_hw = { + .hw = { + .clk = &dss_syc_gfclk_div, + }, +}; + +DEFINE_STRUCT_CLK (dss_syc_gfclk_div, dss_syc_gfclk_div_parents, c2c_fclk_ops); + +static struct clk l3_iclk_div; + +static struct clk_hw_omap l3_iclk_div_hw = { + .hw = { + .clk = &l3_iclk_div, + }, +}; + +DEFINE_STRUCT_CLK (l3_iclk_div, iva_dpll_hs_clk_div_parents, c2c_fclk_ops); + +DEFINE_CLK_FIXED_FACTOR (func_128m_clk,"dpll_per_h11x2_ck" , &dpll_per_h11x2_ck, +0x0 ,1 ,2 ); + +DEFINE_CLK_FIXED_FACTOR (func_12m_fclk,"dpll_per_m2x2_ck" , &dpll_per_m2x2_ck, +0x0 ,1 ,16 ); + +DEFINE_CLK_FIXED_FACTOR (func_24m_clk,"dpll_per_m2_ck" , &dpll_per_m2_ck,0x0 ,1 , +4 ); + +DEFINE_CLK_FIXED_FACTOR (func_48m_fclk,"dpll_per_m2x2_ck" , &dpll_per_m2x2_ck, +0x0 ,1 ,4 ); + +DEFINE_CLK_FIXED_FACTOR (func_96m_fclk,"dpll_per_m2x2_ck" , &dpll_per_m2x2_ck, +0x0 ,1 ,2 ); + +static const char *gpu_core_gclk_mux_parents[] = { +"dpll_core_h14x2_ck" ,"dpll_per_h14x2_ck" , +}; + +DEFINE_CLK_MUX (gpu_core_gclk_mux, gpu_core_gclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_GPU_GPU_CLKCTRL ,OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT , +OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_GPU_GPU_CLKCTRL ,OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT , +OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH ,0x0 ,NULL ); + +static const char *gpu_l3_iclk_parents[] = { +"l3_iclk_div" , +}; + +static struct clk gpu_l3_iclk; + +static struct clk_hw_omap gpu_l3_iclk_hw = { + .hw = { + .clk = &gpu_l3_iclk, + }, +}; + +DEFINE_STRUCT_CLK (gpu_l3_iclk, gpu_l3_iclk_parents, c2c_fclk_ops); + +static const struct clk_div_table l3init_60m_fclk_rates[] = { + { .div =1 , .val =0 }, + { .div =8 , .val =1 }, + { .div =0 }, +}; +DEFINE_CLK_DIVIDER_TABLE (l3init_60m_fclk,"dpll_usb_m2_ck" , &dpll_usb_m2_ck, +0x0 ,OMAP54XX_CM_CLKSEL_USB_60MHZ , +OMAP54XX_CLKSEL_0_0_SHIFT ,OMAP54XX_CLKSEL_0_0_WIDTH , +0x0 , l3init_60m_fclk_rates,NULL ); + +static const char *wkupaon_iclk_mux_parents[] = { +"sys_clkin" ,"abe_lp_clk_div" , +}; + +DEFINE_CLK_MUX (wkupaon_iclk_mux, wkupaon_iclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_CLKSEL_WKUPAON ,OMAP54XX_CLKSEL_0_0_SHIFT , +OMAP54XX_CLKSEL_0_0_WIDTH ,0x0 ,NULL ); + +static const char *l3instr_ts_gclk_div_parents[] = { +"wkupaon_iclk_mux" , +}; + +static struct clk l3instr_ts_gclk_div; + +static struct clk_hw_omap l3instr_ts_gclk_div_hw = { + .hw = { + .clk = &l3instr_ts_gclk_div, + }, +}; + +DEFINE_STRUCT_CLK (l3instr_ts_gclk_div, l3instr_ts_gclk_div_parents, + c2c_fclk_ops); + +static struct clk l4_root_clk_div; + +static struct clk_hw_omap l4_root_clk_div_hw = { + .hw = { + .clk = &l4_root_clk_div, + }, +}; + +DEFINE_STRUCT_CLK (l4_root_clk_div, gpu_l3_iclk_parents, c2c_fclk_ops); + +DEFINE_CLK_MUX (timer10_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L4PER_TIMER10_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer11_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L4PER_TIMER11_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer1_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer2_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L4PER_TIMER2_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer3_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L4PER_TIMER3_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer4_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L4PER_TIMER4_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +static const char *timer5_gfclk_mux_parents[] = { +"dss_syc_gfclk_div" ,"sys_32k_ck" , +}; + +DEFINE_CLK_MUX (timer5_gfclk_mux, timer5_gfclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_TIMER5_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer6_gfclk_mux, timer5_gfclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_TIMER6_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer7_gfclk_mux, timer5_gfclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_TIMER7_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer8_gfclk_mux, timer5_gfclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_TIMER8_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (timer9_gfclk_mux, abe_dpll_bypass_clk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L4PER_TIMER9_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +/* Leaf clocks controlled by modules */ + +static const char *dss_32khz_clk_parents[] = { +"sys_32k_ck" , +}; + +static struct clk dss_32khz_clk; + +static const struct clk_ops dss_32khz_clk_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap dss_32khz_clk_hw = { + .hw = { + .clk = &dss_32khz_clk, + }, + .clkdm_name ="dss_clkdm" , + .enable_reg =OMAP54XX_CM_DSS_DSS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (dss_32khz_clk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static const char *dss_48mhz_clk_parents[] = { +"func_48m_fclk" , +}; + +static struct clk dss_48mhz_clk; + +static struct clk_hw_omap dss_48mhz_clk_hw = { + .hw = { + .clk = &dss_48mhz_clk, + }, + .clkdm_name ="dss_clkdm" , + .enable_reg =OMAP54XX_CM_DSS_DSS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (dss_48mhz_clk, dss_48mhz_clk_parents, dss_32khz_clk_ops); + +static const char *dss_dss_clk_parents[] = { +"dpll_per_h12x2_ck" , +}; + +static struct clk dss_dss_clk; + +static struct clk_hw_omap dss_dss_clk_hw = { + .hw = { + .clk = &dss_dss_clk, + }, + .clkdm_name ="dss_clkdm" , + .enable_reg =OMAP54XX_CM_DSS_DSS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (dss_dss_clk, dss_dss_clk_parents, dss_32khz_clk_ops); + +static const char *dss_sys_clk_parents[] = { +"dss_syc_gfclk_div" , +}; + +static struct clk dss_sys_clk; + +static struct clk_hw_omap dss_sys_clk_hw = { + .hw = { + .clk = &dss_sys_clk, + }, + .clkdm_name ="dss_clkdm" , + .enable_reg =OMAP54XX_CM_DSS_DSS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (dss_sys_clk, dss_sys_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio1_dbclk; + +static struct clk_hw_omap gpio1_dbclk_hw = { + .hw = { + .clk = &gpio1_dbclk, + }, + .clkdm_name ="wkupaon_clkdm" , + .enable_reg =OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio1_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio2_dbclk; + +static struct clk_hw_omap gpio2_dbclk_hw = { + .hw = { + .clk = &gpio2_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO2_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio2_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio3_dbclk; + +static struct clk_hw_omap gpio3_dbclk_hw = { + .hw = { + .clk = &gpio3_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO3_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio3_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio4_dbclk; + +static struct clk_hw_omap gpio4_dbclk_hw = { + .hw = { + .clk = &gpio4_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO4_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio4_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio5_dbclk; + +static struct clk_hw_omap gpio5_dbclk_hw = { + .hw = { + .clk = &gpio5_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO5_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio5_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio6_dbclk; + +static struct clk_hw_omap gpio6_dbclk_hw = { + .hw = { + .clk = &gpio6_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO6_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio6_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio7_dbclk; + +static struct clk_hw_omap gpio7_dbclk_hw = { + .hw = { + .clk = &gpio7_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO7_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio7_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk gpio8_dbclk; + +static struct clk_hw_omap gpio8_dbclk_hw = { + .hw = { + .clk = &gpio8_dbclk, + }, + .clkdm_name ="l4per_clkdm" , + .enable_reg =OMAP54XX_CM_L4PER_GPIO8_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_DBCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (gpio8_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static const char *iss_ctrlclk_parents[] = { +"func_96m_fclk" , +}; + +static struct clk iss_ctrlclk; + +static struct clk_hw_omap iss_ctrlclk_hw = { + .hw = { + .clk = &iss_ctrlclk, + }, + .clkdm_name ="cam_clkdm" , + .enable_reg =OMAP54XX_CM_CAM_ISS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (iss_ctrlclk, iss_ctrlclk_parents, dss_32khz_clk_ops); + +static const char *lli_txphy_clk_parents[] = { +"dpll_unipro1_clkdcoldo" , +}; + +static struct clk lli_txphy_clk; + +static struct clk_hw_omap lli_txphy_clk_hw = { + .hw = { + .clk = &lli_txphy_clk, + }, + .clkdm_name ="mipiext_clkdm" , + .enable_reg =OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (lli_txphy_clk, lli_txphy_clk_parents, dss_32khz_clk_ops); + +static const char *lli_txphy_ls_clk_parents[] = { +"dpll_unipro1_m2_ck" , +}; + +static struct clk lli_txphy_ls_clk; + +static struct clk_hw_omap lli_txphy_ls_clk_hw = { + .hw = { + .clk = &lli_txphy_ls_clk, + }, + .clkdm_name ="mipiext_clkdm" , + .enable_reg =OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (lli_txphy_ls_clk, lli_txphy_ls_clk_parents, + dss_32khz_clk_ops); + +static struct clk mmc1_32khz_clk; + +static struct clk_hw_omap mmc1_32khz_clk_hw = { + .hw = { + .clk = &mmc1_32khz_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_MMC1_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT , +}; + +DEFINE_STRUCT_CLK (mmc1_32khz_clk, dss_32khz_clk_parents, dss_32khz_clk_ops); + +static struct clk sata_ref_clk; + +static struct clk_hw_omap sata_ref_clk_hw = { + .hw = { + .clk = &sata_ref_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_SATA_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (sata_ref_clk, dss_syc_gfclk_div_parents, dss_32khz_clk_ops); + +static const char *slimbus1_slimbus_clk_parents[] = { +"slimbus_clk" , +}; + +static struct clk slimbus1_slimbus_clk; + +static struct clk_hw_omap slimbus1_slimbus_clk_hw = { + .hw = { + .clk = &slimbus1_slimbus_clk, + }, + .clkdm_name ="abe_clkdm" , + .enable_reg =OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (slimbus1_slimbus_clk, slimbus1_slimbus_clk_parents, + dss_32khz_clk_ops); + +static const char *usb_host_hs_hsic480m_p1_clk_parents[] = { +"dpll_usb_m2_ck" , +}; + +static struct clk usb_host_hs_hsic480m_p1_clk; + +static struct clk_hw_omap usb_host_hs_hsic480m_p1_clk_hw = { + .hw = { + .clk = &usb_host_hs_hsic480m_p1_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_hsic480m_p1_clk, + usb_host_hs_hsic480m_p1_clk_parents, dss_32khz_clk_ops); + +static struct clk usb_host_hs_hsic480m_p2_clk; + +static struct clk_hw_omap usb_host_hs_hsic480m_p2_clk_hw = { + .hw = { + .clk = &usb_host_hs_hsic480m_p2_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_hsic480m_p2_clk, + usb_host_hs_hsic480m_p1_clk_parents, dss_32khz_clk_ops); + +static struct clk usb_host_hs_hsic480m_p3_clk; + +static struct clk_hw_omap usb_host_hs_hsic480m_p3_clk_hw = { + .hw = { + .clk = &usb_host_hs_hsic480m_p3_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_hsic480m_p3_clk, + usb_host_hs_hsic480m_p1_clk_parents, dss_32khz_clk_ops); + +static const char *usb_host_hs_hsic60m_p1_clk_parents[] = { +"l3init_60m_fclk" , +}; + +static struct clk usb_host_hs_hsic60m_p1_clk; + +static struct clk_hw_omap usb_host_hs_hsic60m_p1_clk_hw = { + .hw = { + .clk = &usb_host_hs_hsic60m_p1_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_hsic60m_p1_clk, + usb_host_hs_hsic60m_p1_clk_parents, dss_32khz_clk_ops); + +static struct clk usb_host_hs_hsic60m_p2_clk; + +static struct clk_hw_omap usb_host_hs_hsic60m_p2_clk_hw = { + .hw = { + .clk = &usb_host_hs_hsic60m_p2_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_hsic60m_p2_clk, + usb_host_hs_hsic60m_p1_clk_parents, dss_32khz_clk_ops); + +static struct clk usb_host_hs_hsic60m_p3_clk; + +static struct clk_hw_omap usb_host_hs_hsic60m_p3_clk_hw = { + .hw = { + .clk = &usb_host_hs_hsic60m_p3_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_hsic60m_p3_clk, + usb_host_hs_hsic60m_p1_clk_parents, dss_32khz_clk_ops); + +static const char *utmi_p1_gfclk_parents[] = { +"l3init_60m_fclk" ,"xclk60mhsp1" , +}; + +DEFINE_CLK_MUX (utmi_p1_gfclk, utmi_p1_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , +OMAP54XX_CLKSEL_UTMI_P1_SHIFT ,OMAP54XX_CLKSEL_UTMI_P1_WIDTH , +0x0 ,NULL ); + +static const char *usb_host_hs_utmi_p1_clk_parents[] = { +"utmi_p1_gfclk" , +}; + +static struct clk usb_host_hs_utmi_p1_clk; + +static struct clk_hw_omap usb_host_hs_utmi_p1_clk_hw = { + .hw = { + .clk = &usb_host_hs_utmi_p1_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_utmi_p1_clk, usb_host_hs_utmi_p1_clk_parents, + dss_32khz_clk_ops); + +static const char *utmi_p2_gfclk_parents[] = { +"l3init_60m_fclk" ,"xclk60mhsp2" , +}; + +DEFINE_CLK_MUX (utmi_p2_gfclk, utmi_p2_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , +OMAP54XX_CLKSEL_UTMI_P2_SHIFT ,OMAP54XX_CLKSEL_UTMI_P2_WIDTH , +0x0 ,NULL ); + +static const char *usb_host_hs_utmi_p2_clk_parents[] = { +"utmi_p2_gfclk" , +}; + +static struct clk usb_host_hs_utmi_p2_clk; + +static struct clk_hw_omap usb_host_hs_utmi_p2_clk_hw = { + .hw = { + .clk = &usb_host_hs_utmi_p2_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_utmi_p2_clk, usb_host_hs_utmi_p2_clk_parents, + dss_32khz_clk_ops); + +static struct clk usb_host_hs_utmi_p3_clk; + +static struct clk_hw_omap usb_host_hs_utmi_p3_clk_hw = { + .hw = { + .clk = &usb_host_hs_utmi_p3_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_host_hs_utmi_p3_clk, usb_host_hs_hsic60m_p1_clk_parents, + dss_32khz_clk_ops); + +static const char *usb_otg_ss_refclk960m_parents[] = { +"dpll_usb_clkdcoldo" , +}; + +static struct clk usb_otg_ss_refclk960m; + +static struct clk_hw_omap usb_otg_ss_refclk960m_hw = { + .hw = { + .clk = &usb_otg_ss_refclk960m, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_otg_ss_refclk960m, usb_otg_ss_refclk960m_parents, + dss_32khz_clk_ops); + +static struct clk usb_tll_hs_usb_ch0_clk; + +static struct clk_hw_omap usb_tll_hs_usb_ch0_clk_hw = { + .hw = { + .clk = &usb_tll_hs_usb_ch0_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_tll_hs_usb_ch0_clk, usb_host_hs_hsic60m_p1_clk_parents, + dss_32khz_clk_ops); + +static struct clk usb_tll_hs_usb_ch1_clk; + +static struct clk_hw_omap usb_tll_hs_usb_ch1_clk_hw = { + .hw = { + .clk = &usb_tll_hs_usb_ch1_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_tll_hs_usb_ch1_clk, usb_host_hs_hsic60m_p1_clk_parents, + dss_32khz_clk_ops); + +static struct clk usb_tll_hs_usb_ch2_clk; + +static struct clk_hw_omap usb_tll_hs_usb_ch2_clk_hw = { + .hw = { + .clk = &usb_tll_hs_usb_ch2_clk, + }, + .clkdm_name ="l3init_clkdm" , + .enable_reg =OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL , + .enable_bit =OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT , +}; + +DEFINE_STRUCT_CLK (usb_tll_hs_usb_ch2_clk, usb_host_hs_hsic60m_p1_clk_parents, + dss_32khz_clk_ops); + +/* Remaining optional clocks */ +DEFINE_CLK_DIVIDER (aess_fclk,"abe_clk" , &abe_clk,0x0 , +OMAP54XX_CM_ABE_AESS_CLKCTRL , +OMAP54XX_CLKSEL_AESS_FCLK_SHIFT , +OMAP54XX_CLKSEL_AESS_FCLK_WIDTH ,0x0 ,NULL ); + +static const char *dmic_sync_mux_ck_parents[] = { +"abe_24m_fclk" ,"dss_syc_gfclk_div" ,"func_24m_clk" , +}; + +DEFINE_CLK_MUX (dmic_sync_mux_ck, dmic_sync_mux_ck_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_DMIC_CLKCTRL , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH ,0x0 ,NULL ); + +static const char *dmic_gfclk_parents[] = { +"dmic_sync_mux_ck" ,"pad_clks" ,"slimbus_clk" , +}; + +DEFINE_CLK_MUX (dmic_gfclk, dmic_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_DMIC_CLKCTRL ,OMAP54XX_CLKSEL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_SOURCE_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_DIVIDER (fdif_fclk,"dpll_per_h11x2_ck" , &dpll_per_h11x2_ck,0x0 , +OMAP54XX_CM_CAM_FDIF_CLKCTRL ,OMAP54XX_CLKSEL_FCLK_SHIFT , +OMAP54XX_CLKSEL_FCLK_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_DIVIDER (hsi_fclk,"dpll_per_m2x2_ck" , &dpll_per_m2x2_ck,0x0 , +OMAP54XX_CM_L3INIT_HSI_CLKCTRL ,OMAP54XX_CLKSEL_SHIFT , +OMAP54XX_CLKSEL_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (mcasp_sync_mux_ck, dmic_sync_mux_ck_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCASP_CLKCTRL , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH ,0x0 ,NULL ); + +static const char *mcasp_gfclk_parents[] = { +"mcasp_sync_mux_ck" ,"pad_clks" ,"slimbus_clk" , +}; + +DEFINE_CLK_MUX (mcasp_gfclk, mcasp_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCASP_CLKCTRL ,OMAP54XX_CLKSEL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_SOURCE_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCBSP1_CLKCTRL , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH ,0x0 ,NULL ); + +static const char *mcbsp1_gfclk_parents[] = { +"mcbsp1_sync_mux_ck" ,"pad_clks" ,"slimbus_clk" , +}; + +DEFINE_CLK_MUX (mcbsp1_gfclk, mcbsp1_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCBSP1_CLKCTRL ,OMAP54XX_CLKSEL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_SOURCE_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCBSP2_CLKCTRL , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH ,0x0 ,NULL ); + +static const char *mcbsp2_gfclk_parents[] = { +"mcbsp2_sync_mux_ck" ,"pad_clks" ,"slimbus_clk" , +}; + +DEFINE_CLK_MUX (mcbsp2_gfclk, mcbsp2_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCBSP2_CLKCTRL ,OMAP54XX_CLKSEL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_SOURCE_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCBSP3_CLKCTRL , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH ,0x0 ,NULL ); + +static const char *mcbsp3_gfclk_parents[] = { +"mcbsp3_sync_mux_ck" ,"pad_clks" ,"slimbus_clk" , +}; + +DEFINE_CLK_MUX (mcbsp3_gfclk, mcbsp3_gfclk_parents,NULL ,0x0 , +OMAP54XX_CM_ABE_MCBSP3_CLKCTRL ,OMAP54XX_CLKSEL_SOURCE_SHIFT , +OMAP54XX_CLKSEL_SOURCE_WIDTH ,0x0 ,NULL ); + +static const char *mmc1_fclk_mux_parents[] = { +"func_128m_clk" ,"dpll_per_m2x2_ck" , +}; + +DEFINE_CLK_MUX (mmc1_fclk_mux, mmc1_fclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L3INIT_MMC1_CLKCTRL , +OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT , +OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_DIVIDER (mmc1_fclk,"mmc1_fclk_mux" , &mmc1_fclk_mux,0x0 , +OMAP54XX_CM_L3INIT_MMC1_CLKCTRL ,OMAP54XX_CLKSEL_DIV_SHIFT , +OMAP54XX_CLKSEL_DIV_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_MUX (mmc2_fclk_mux, mmc1_fclk_mux_parents,NULL ,0x0 , +OMAP54XX_CM_L3INIT_MMC2_CLKCTRL , +OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT , +OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH ,0x0 ,NULL ); + +DEFINE_CLK_DIVIDER (mmc2_fclk,"mmc2_fclk_mux" , &mmc2_fclk_mux,0x0 , +OMAP54XX_CM_L3INIT_MMC2_CLKCTRL ,OMAP54XX_CLKSEL_DIV_SHIFT , +OMAP54XX_CLKSEL_DIV_WIDTH ,0x0 ,NULL ); + +/* SCRM aux clk nodes */ + +static const struct clksel auxclk_src_sel[] = { + { .parent = &sys_clkin, .rates = div_1_0_rates }, + { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, + { .parent =NULL }, +}; + +static const char *auxclk_src_ck_parents[] = { +"sys_clkin" ,"dpll_core_m3x2_ck" ,"dpll_per_m3x2_ck" , +}; + +static const struct clk_ops auxclk_src_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, +}; + +DEFINE_CLK_OMAP_MUX_GATE (auxclk0_src_ck,NULL , auxclk_src_sel, +OMAP5_SCRM_AUXCLK0 ,OMAP5_SRCSELECT_MASK , +OMAP5_SCRM_AUXCLK0 ,OMAP5_ENABLE_SHIFT ,NULL , + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER (auxclk0_ck,"auxclk0_src_ck" , &auxclk0_src_ck,0x0 , +OMAP5_SCRM_AUXCLK0 ,OMAP5_CLKDIV_SHIFT ,OMAP5_CLKDIV_WIDTH , +0x0 ,NULL ); + +DEFINE_CLK_OMAP_MUX_GATE (auxclk1_src_ck,NULL , auxclk_src_sel, +OMAP5_SCRM_AUXCLK1 ,OMAP5_SRCSELECT_MASK , +OMAP5_SCRM_AUXCLK1 ,OMAP5_ENABLE_SHIFT ,NULL , + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER (auxclk1_ck,"auxclk1_src_ck" , &auxclk1_src_ck,0x0 , +OMAP5_SCRM_AUXCLK1 ,OMAP5_CLKDIV_SHIFT ,OMAP5_CLKDIV_WIDTH , +0x0 ,NULL ); + +DEFINE_CLK_OMAP_MUX_GATE (auxclk2_src_ck,NULL , auxclk_src_sel, +OMAP5_SCRM_AUXCLK2 ,OMAP5_SRCSELECT_MASK , +OMAP5_SCRM_AUXCLK2 ,OMAP5_ENABLE_SHIFT ,NULL , + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER (auxclk2_ck,"auxclk2_src_ck" , &auxclk2_src_ck,0x0 , +OMAP5_SCRM_AUXCLK2 ,OMAP5_CLKDIV_SHIFT ,OMAP5_CLKDIV_WIDTH , +0x0 ,NULL ); + +DEFINE_CLK_OMAP_MUX_GATE (auxclk3_src_ck,NULL , auxclk_src_sel, +OMAP5_SCRM_AUXCLK3 ,OMAP5_SRCSELECT_MASK , +OMAP5_SCRM_AUXCLK3 ,OMAP5_ENABLE_SHIFT ,NULL , + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER (auxclk3_ck,"auxclk3_src_ck" , &auxclk3_src_ck,0x0 , +OMAP5_SCRM_AUXCLK3 ,OMAP5_CLKDIV_SHIFT ,OMAP5_CLKDIV_WIDTH , +0x0 ,NULL ); + +static const char *auxclkreq_ck_parents[] = { +"auxclk0_ck" ,"auxclk1_ck" ,"auxclk2_ck" ,"auxclk3_ck" ,"auxclk4_ck" , +"auxclk5_ck" , +}; + +DEFINE_CLK_MUX (auxclkreq0_ck, auxclkreq_ck_parents,NULL ,0x0 , +OMAP5_SCRM_AUXCLKREQ0 ,OMAP5_MAPPING_SHIFT ,OMAP5_MAPPING_WIDTH , +0x0 ,NULL ); + +DEFINE_CLK_MUX (auxclkreq1_ck, auxclkreq_ck_parents,NULL ,0x0 , +OMAP5_SCRM_AUXCLKREQ1 ,OMAP5_MAPPING_SHIFT ,OMAP5_MAPPING_WIDTH , +0x0 ,NULL ); + +DEFINE_CLK_MUX (auxclkreq2_ck, auxclkreq_ck_parents,NULL ,0x0 , +OMAP5_SCRM_AUXCLKREQ2 ,OMAP5_MAPPING_SHIFT ,OMAP5_MAPPING_WIDTH , +0x0 ,NULL ); + +DEFINE_CLK_MUX (auxclkreq3_ck, auxclkreq_ck_parents,NULL ,0x0 , +OMAP5_SCRM_AUXCLKREQ3 ,OMAP5_MAPPING_SHIFT ,OMAP5_MAPPING_WIDTH , +0x0 ,NULL ); + +/* +* clkdev +*/ + +static struct omap_clk omap54xx_clks[] = { +CLK (NULL ,"pad_clks_src_ck" , &pad_clks_src_ck,CK_54XX ), +CLK (NULL ,"pad_clks_ck" , &pad_clks_ck,CK_54XX ), +CLK (NULL ,"secure_32k_clk_src_ck" , &secure_32k_clk_src_ck,CK_54XX ), +CLK (NULL ,"slimbus_src_clk" , &slimbus_src_clk,CK_54XX ), +CLK (NULL ,"slimbus_clk" , &slimbus_clk,CK_54XX ), +CLK (NULL ,"sys_32k_ck" , &sys_32k_ck,CK_54XX ), +CLK (NULL ,"virt_12000000_ck" , &virt_12000000_ck,CK_54XX ), +CLK (NULL ,"virt_13000000_ck" , &virt_13000000_ck,CK_54XX ), +CLK (NULL ,"virt_16800000_ck" , &virt_16800000_ck,CK_54XX ), +CLK (NULL ,"virt_19200000_ck" , &virt_19200000_ck,CK_54XX ), +CLK (NULL ,"virt_26000000_ck" , &virt_26000000_ck,CK_54XX ), +CLK (NULL ,"virt_27000000_ck" , &virt_27000000_ck,CK_54XX ), +CLK (NULL ,"virt_38400000_ck" , &virt_38400000_ck,CK_54XX ), +CLK (NULL ,"sys_clkin" , &sys_clkin,CK_54XX ), +CLK (NULL ,"xclk60mhsp1_ck" , &xclk60mhsp1_ck,CK_54XX ), +CLK (NULL ,"xclk60mhsp2_ck" , &xclk60mhsp2_ck,CK_54XX ), +CLK (NULL ,"abe_dpll_bypass_clk_mux" , &abe_dpll_bypass_clk_mux,CK_54XX ), +CLK (NULL ,"abe_dpll_clk_mux" , &abe_dpll_clk_mux,CK_54XX ), +CLK (NULL ,"dpll_abe_ck" , &dpll_abe_ck,CK_54XX ), +CLK (NULL ,"dpll_abe_x2_ck" , &dpll_abe_x2_ck,CK_54XX ), +CLK (NULL ,"dpll_abe_m2x2_ck" , &dpll_abe_m2x2_ck,CK_54XX ), +CLK (NULL ,"abe_24m_fclk" , &abe_24m_fclk,CK_54XX ), +CLK (NULL ,"abe_clk" , &abe_clk,CK_54XX ), +CLK (NULL ,"abe_iclk" , &abe_iclk,CK_54XX ), +CLK (NULL ,"abe_lp_clk_div" , &abe_lp_clk_div,CK_54XX ), +CLK (NULL ,"dpll_abe_m3x2_ck" , &dpll_abe_m3x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_ck" , &dpll_core_ck,CK_54XX ), +CLK (NULL ,"dpll_core_x2_ck" , &dpll_core_x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h21x2_ck" , &dpll_core_h21x2_ck,CK_54XX ), +CLK (NULL ,"c2c_fclk" , &c2c_fclk,CK_54XX ), +CLK (NULL ,"c2c_iclk" , &c2c_iclk,CK_54XX ), +CLK (NULL ,"custefuse_sys_gfclk_div" , &custefuse_sys_gfclk_div,CK_54XX ), +CLK (NULL ,"dpll_core_h11x2_ck" , &dpll_core_h11x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h12x2_ck" , &dpll_core_h12x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h13x2_ck" , &dpll_core_h13x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h14x2_ck" , &dpll_core_h14x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h22x2_ck" , &dpll_core_h22x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h23x2_ck" , &dpll_core_h23x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_h24x2_ck" , &dpll_core_h24x2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_m2_ck" , &dpll_core_m2_ck,CK_54XX ), +CLK (NULL ,"dpll_core_m3x2_ck" , &dpll_core_m3x2_ck,CK_54XX ), +CLK (NULL ,"iva_dpll_hs_clk_div" , &iva_dpll_hs_clk_div,CK_54XX ), +CLK (NULL ,"dpll_iva_ck" , &dpll_iva_ck,CK_54XX ), +CLK (NULL ,"dpll_iva_x2_ck" , &dpll_iva_x2_ck,CK_54XX ), +CLK (NULL ,"dpll_iva_h11x2_ck" , &dpll_iva_h11x2_ck,CK_54XX ), +CLK (NULL ,"dpll_iva_h12x2_ck" , &dpll_iva_h12x2_ck,CK_54XX ), +CLK (NULL ,"mpu_dpll_hs_clk_div" , &mpu_dpll_hs_clk_div,CK_54XX ), +CLK (NULL ,"dpll_mpu_ck" , &dpll_mpu_ck,CK_54XX ), +CLK (NULL ,"dpll_mpu_m2_ck" , &dpll_mpu_m2_ck,CK_54XX ), +CLK (NULL ,"per_dpll_hs_clk_div" , &per_dpll_hs_clk_div,CK_54XX ), +CLK (NULL ,"dpll_per_ck" , &dpll_per_ck,CK_54XX ), +CLK (NULL ,"dpll_per_x2_ck" , &dpll_per_x2_ck,CK_54XX ), +CLK (NULL ,"dpll_per_h11x2_ck" , &dpll_per_h11x2_ck,CK_54XX ), +CLK (NULL ,"dpll_per_h12x2_ck" , &dpll_per_h12x2_ck,CK_54XX ), +CLK (NULL ,"dpll_per_h14x2_ck" , &dpll_per_h14x2_ck,CK_54XX ), +CLK (NULL ,"dpll_per_m2_ck" , &dpll_per_m2_ck,CK_54XX ), +CLK (NULL ,"dpll_per_m2x2_ck" , &dpll_per_m2x2_ck,CK_54XX ), +CLK (NULL ,"dpll_per_m3x2_ck" , &dpll_per_m3x2_ck,CK_54XX ), +CLK (NULL ,"dpll_unipro1_ck" , &dpll_unipro1_ck,CK_54XX ), +CLK (NULL ,"dpll_unipro1_clkdcoldo" , &dpll_unipro1_clkdcoldo,CK_54XX ), +CLK (NULL ,"dpll_unipro1_m2_ck" , &dpll_unipro1_m2_ck,CK_54XX ), +CLK (NULL ,"dpll_unipro2_ck" , &dpll_unipro2_ck,CK_54XX ), +CLK (NULL ,"dpll_unipro2_clkdcoldo" , &dpll_unipro2_clkdcoldo,CK_54XX ), +CLK (NULL ,"dpll_unipro2_m2_ck" , &dpll_unipro2_m2_ck,CK_54XX ), +CLK (NULL ,"usb_dpll_hs_clk_div" , &usb_dpll_hs_clk_div,CK_54XX ), +CLK (NULL ,"dpll_usb_ck" , &dpll_usb_ck,CK_54XX ), +CLK (NULL ,"dpll_usb_clkdcoldo" , &dpll_usb_clkdcoldo,CK_54XX ), +CLK (NULL ,"dpll_usb_m2_ck" , &dpll_usb_m2_ck,CK_54XX ), +CLK (NULL ,"dss_syc_gfclk_div" , &dss_syc_gfclk_div,CK_54XX ), +CLK (NULL ,"l3_iclk_div" , &l3_iclk_div,CK_54XX ), +CLK (NULL ,"func_128m_clk" , &func_128m_clk,CK_54XX ), +CLK (NULL ,"func_12m_fclk" , &func_12m_fclk,CK_54XX ), +CLK (NULL ,"func_24m_clk" , &func_24m_clk,CK_54XX ), +CLK (NULL ,"func_48m_fclk" , &func_48m_fclk,CK_54XX ), +CLK (NULL ,"func_96m_fclk" , &func_96m_fclk,CK_54XX ), +CLK (NULL ,"gpu_core_gclk_mux" , &gpu_core_gclk_mux,CK_54XX ), +CLK (NULL ,"gpu_hyd_gclk_mux" , &gpu_hyd_gclk_mux,CK_54XX ), +CLK (NULL ,"gpu_l3_iclk" , &gpu_l3_iclk,CK_54XX ), +CLK (NULL ,"l3init_60m_fclk" , &l3init_60m_fclk,CK_54XX ), +CLK (NULL ,"wkupaon_iclk_mux" , &wkupaon_iclk_mux,CK_54XX ), +CLK (NULL ,"l3instr_ts_gclk_div" , &l3instr_ts_gclk_div,CK_54XX ), +CLK (NULL ,"l4_root_clk_div" , &l4_root_clk_div,CK_54XX ), +CLK (NULL ,"timer10_gfclk_mux" , &timer10_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer11_gfclk_mux" , &timer11_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer1_gfclk_mux" , &timer1_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer2_gfclk_mux" , &timer2_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer3_gfclk_mux" , &timer3_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer4_gfclk_mux" , &timer4_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer5_gfclk_mux" , &timer5_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer6_gfclk_mux" , &timer6_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer7_gfclk_mux" , &timer7_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer8_gfclk_mux" , &timer8_gfclk_mux,CK_54XX ), +CLK (NULL ,"timer9_gfclk_mux" , &timer9_gfclk_mux,CK_54XX ), +CLK (NULL ,"dss_32khz_clk" , &dss_32khz_clk,CK_54XX ), +CLK (NULL ,"dss_48mhz_clk" , &dss_48mhz_clk,CK_54XX ), +CLK (NULL ,"dss_dss_clk" , &dss_dss_clk,CK_54XX ), +CLK (NULL ,"dss_sys_clk" , &dss_sys_clk,CK_54XX ), +CLK (NULL ,"gpio1_dbclk" , &gpio1_dbclk,CK_54XX ), +CLK (NULL ,"gpio2_dbclk" , &gpio2_dbclk,CK_54XX ), +CLK (NULL ,"gpio3_dbclk" , &gpio3_dbclk,CK_54XX ), +CLK (NULL ,"gpio4_dbclk" , &gpio4_dbclk,CK_54XX ), +CLK (NULL ,"gpio5_dbclk" , &gpio5_dbclk,CK_54XX ), +CLK (NULL ,"gpio6_dbclk" , &gpio6_dbclk,CK_54XX ), +CLK (NULL ,"gpio7_dbclk" , &gpio7_dbclk,CK_54XX ), +CLK (NULL ,"gpio8_dbclk" , &gpio8_dbclk,CK_54XX ), +CLK (NULL ,"iss_ctrlclk" , &iss_ctrlclk,CK_54XX ), +CLK (NULL ,"lli_txphy_clk" , &lli_txphy_clk,CK_54XX ), +CLK (NULL ,"lli_txphy_ls_clk" , &lli_txphy_ls_clk,CK_54XX ), +CLK (NULL ,"mmc1_32khz_clk" , &mmc1_32khz_clk,CK_54XX ), +CLK (NULL ,"sata_ref_clk" , &sata_ref_clk,CK_54XX ), +CLK (NULL ,"slimbus1_slimbus_clk" , &slimbus1_slimbus_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_hsic480m_p1_clk" , &usb_host_hs_hsic480m_p1_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_hsic480m_p2_clk" , &usb_host_hs_hsic480m_p2_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_hsic480m_p3_clk" , &usb_host_hs_hsic480m_p3_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_hsic60m_p1_clk" , &usb_host_hs_hsic60m_p1_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_hsic60m_p2_clk" , &usb_host_hs_hsic60m_p2_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_hsic60m_p3_clk" , &usb_host_hs_hsic60m_p3_clk,CK_54XX ), +CLK (NULL ,"utmi_p1_gfclk" , &utmi_p1_gfclk,CK_54XX ), +CLK (NULL ,"usb_host_hs_utmi_p1_clk" , &usb_host_hs_utmi_p1_clk,CK_54XX ), +CLK (NULL ,"utmi_p2_gfclk" , &utmi_p2_gfclk,CK_54XX ), +CLK (NULL ,"usb_host_hs_utmi_p2_clk" , &usb_host_hs_utmi_p2_clk,CK_54XX ), +CLK (NULL ,"usb_host_hs_utmi_p3_clk" , &usb_host_hs_utmi_p3_clk,CK_54XX ), +CLK (NULL ,"usb_otg_ss_refclk960m" , &usb_otg_ss_refclk960m,CK_54XX ), +CLK (NULL ,"usb_tll_hs_usb_ch0_clk" , &usb_tll_hs_usb_ch0_clk,CK_54XX ), +CLK (NULL ,"usb_tll_hs_usb_ch1_clk" , &usb_tll_hs_usb_ch1_clk,CK_54XX ), +CLK (NULL ,"usb_tll_hs_usb_ch2_clk" , &usb_tll_hs_usb_ch2_clk,CK_54XX ), +CLK (NULL ,"aess_fclk" , &aess_fclk,CK_54XX ), +CLK (NULL ,"dmic_sync_mux_ck" , &dmic_sync_mux_ck,CK_54XX ), +CLK (NULL ,"dmic_gfclk" , &dmic_gfclk,CK_54XX ), +CLK (NULL ,"fdif_fclk" , &fdif_fclk,CK_54XX ), +CLK (NULL ,"hsi_fclk" , &hsi_fclk,CK_54XX ), +CLK (NULL ,"mcasp_sync_mux_ck" , &mcasp_sync_mux_ck,CK_54XX ), +CLK (NULL ,"mcasp_gfclk" , &mcasp_gfclk,CK_54XX ), +CLK (NULL ,"mcbsp1_sync_mux_ck" , &mcbsp1_sync_mux_ck,CK_54XX ), +CLK (NULL ,"mcbsp1_gfclk" , &mcbsp1_gfclk,CK_54XX ), +CLK (NULL ,"mcbsp2_sync_mux_ck" , &mcbsp2_sync_mux_ck,CK_54XX ), +CLK (NULL ,"mcbsp2_gfclk" , &mcbsp2_gfclk,CK_54XX ), +CLK (NULL ,"mcbsp3_sync_mux_ck" , &mcbsp3_sync_mux_ck,CK_54XX ), +CLK (NULL ,"mcbsp3_gfclk" , &mcbsp3_gfclk,CK_54XX ), +CLK (NULL ,"mmc1_fclk_mux" , &mmc1_fclk_mux,CK_54XX ), +CLK (NULL ,"mmc1_fclk" , &mmc1_fclk,CK_54XX ), +CLK (NULL ,"mmc2_fclk_mux" , &mmc2_fclk_mux,CK_54XX ), +CLK (NULL ,"mmc2_fclk" , &mmc2_fclk,CK_54XX ), +CLK (NULL ,"utmi_p1_gfclk" , &utmi_p1_gfclk,CK_54XX ), +CLK (NULL ,"utmi_p2_gfclk" , &utmi_p2_gfclk,CK_54XX ), +CLK (NULL ,"auxclk0_src_ck" , &auxclk0_src_ck,CK_54XX ), +CLK (NULL ,"auxclk0_ck" , &auxclk0_ck,CK_54XX ), +CLK (NULL ,"auxclkreq0_ck" , &auxclkreq0_ck,CK_54XX ), +CLK (NULL ,"auxclk1_src_ck" , &auxclk1_src_ck,CK_54XX ), +CLK (NULL ,"auxclk1_ck" , &auxclk1_ck,CK_54XX ), +CLK (NULL ,"auxclkreq1_ck" , &auxclkreq1_ck,CK_54XX ), +CLK (NULL ,"auxclk2_src_ck" , &auxclk2_src_ck,CK_54XX ), +CLK (NULL ,"auxclk2_ck" , &auxclk2_ck,CK_54XX ), +CLK (NULL ,"auxclkreq2_ck" , &auxclkreq2_ck,CK_54XX ), +CLK (NULL ,"auxclk3_src_ck" , &auxclk3_src_ck,CK_54XX ), +CLK (NULL ,"auxclk3_ck" , &auxclk3_ck,CK_54XX ), +CLK (NULL ,"auxclkreq3_ck" , &auxclkreq3_ck,CK_54XX ), +CLK (NULL ,"gpmc_ck" , &dummy_ck,CK_54XX ), +CLK ("omap_i2c.1" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_i2c.2" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_i2c.3" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_i2c.4" ,"ick" , &dummy_ck,CK_54XX ), +CLK (NULL ,"mailboxes_ick" , &dummy_ck,CK_54XX ), +CLK ("omap_hsmmc.0" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_hsmmc.1" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_hsmmc.2" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_hsmmc.3" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_hsmmc.4" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap-mcbsp.1" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap-mcbsp.2" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap-mcbsp.3" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap-mcbsp.4" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap2_mcspi.1" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap2_mcspi.2" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap2_mcspi.3" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap2_mcspi.4" ,"ick" , &dummy_ck,CK_54XX ), +CLK (NULL ,"uart1_ick" , &dummy_ck,CK_54XX ), +CLK (NULL ,"uart2_ick" , &dummy_ck,CK_54XX ), +CLK (NULL ,"uart3_ick" , &dummy_ck,CK_54XX ), +CLK (NULL ,"uart4_ick" , &dummy_ck,CK_54XX ), +CLK ("usbhs_omap" ,"usbhost_ick" , &dummy_ck,CK_54XX ), +CLK ("usbhs_omap" ,"usbtll_fck" , &dummy_ck,CK_54XX ), +CLK ("omap_wdt" ,"ick" , &dummy_ck,CK_54XX ), +CLK ("omap_timer.1" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.2" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.3" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.4" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.5" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.6" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.7" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.8" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.9" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.10" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.11" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.1" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.2" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.3" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.4" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.9" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.10" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.11" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.5" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), +CLK ("omap_timer.6" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), +CLK ("omap_timer.7" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), +CLK ("omap_timer.8" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), +}; + +int __init omap5xxx_clk_init (void ) +{ +u32 cpu_clkflg; +struct omap_clk *c; + +if (soc_is_omap54xx ()) { + cpu_mask =RATE_IN_54XX ; + cpu_clkflg =CK_54XX ; + } + +/* +* Must stay commented until all OMAP SoC drivers are +* converted to runtime PM, or drivers may start crashing +* +* omap2_clk_disable_clkdm_control(); +*/ +
arch/arm/mach-omap2/cclock54xx_data.c line 1791
Quoted 10 lines
arch/arm/mach-omap2/cclock54xx_data.c new file +10
-0+for (c = omap54xx_clks; c < omap54xx_clks +ARRAY_SIZE (omap54xx_clks); + c++) { +if (c->cpu & cpu_clkflg) { +clkdev_add (&c->lk); +if (!__clk_init (NULL , c->lk.clk)) +omap2_init_clk_hw_omap_clocks (c->lk.clk); + } + } + +omap2_clk_disable_autoidle_all ();
Can we add the ABE DPLL locking on 32kHz here like for OMAP4. Otherwise we will get the same problem
/*
* Lock the ABE DPLL in any case to avoid issues with audio.
*/
rc = clk_set_parent(&abe_dpll_clk_mux, &sys_32k_ck);
if (!rc)
rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);Quoted 256 lines
arch/arm/mach-omap2/cclock54xx_data.c new file +3
-0+ +return 0 ; +}arch/arm/mach-omap2/clock.h +22
-1@@ -48,6 +48,7 @@ struct omap_clk {#define CK_TI816X (1 << 7)#define CK_446X (1 << 8)#define CK_AM33XX (1 << 9)/* AM33xx specific clocks */ +#define CK_54XX (1 << 10)/* OMAP54xx specific clocks */ #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)@@ -107,13 +108,31 @@ struct clockdomain; }; \DEFINE_STRUCT_CLK (_name, _parent_names, _ops); + +#define DEFINE_CLK_OMAP_HSDIVIDER63 (_name, _parent_name, \ + _parent_ptr, _flags, \ + _clksel_reg, _clksel_mask) \ + \ + _DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ + _parent_ptr, _flags, \ + _clksel_reg, _clksel_mask, 63) +#define DEFINE_CLK_OMAP_HSDIVIDER (_name, _parent_name, \ _parent_ptr, _flags, \ _clksel_reg, _clksel_mask) \ + \ + _DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ + _parent_ptr, _flags, \ + _clksel_reg, _clksel_mask, 31) + + +#define _DEFINE_CLK_OMAP_HSDIVIDER (_name, _parent_name, \ + _parent_ptr, _flags, \ + _clksel_reg, _clksel_mask, mdiv)\ static const struct clksel _name##_div[] = { \ { \ .parent = _parent_ptr, \ - .rates = div31_1to31_rates \ + .rates = div##mdiv##_1to##mdiv##_rates \ }, \ { .parent = NULL }, \ }; \@@ -143,6 +162,7 @@ struct clockdomain;#define RATE_IN_4460 (1 << 7)#define RATE_IN_AM33XX (1 << 8)#define RATE_IN_TI814X (1 << 9) +#define RATE_IN_54XX (1 << 10)#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)@@ -463,6 +483,7 @@ extern const struct clksel_rate div_1_2_rates[];extern const struct clksel_rate div_1_3_rates[];extern const struct clksel_rate div_1_4_rates[];extern const struct clksel_rate div31_1to31_rates[]; +extern const struct clksel_rate div63_1to63_rates[];extern int am33xx_clk_init (void );arch/arm/mach-omap2/clock54xx.h new file +12
-0@@ -0,0 +1,12 @@ +/* +* OMAP5 clock function prototypes and macros +* +* Copyright (C) 2013 Texas Instruments, Inc. +*/ + +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK54XX_H +#define __ARCH_ARM_MACH_OMAP2_CLOCK54XX_H + +int omap5xxx_clk_init (void ); + +#endif arch/arm/mach-omap2/clock_common_data.c +103
-36@@ -49,7 +49,7 @@ const struct clksel_rate dsp_ick_rates[] = {/* clksel_rate blocks shared between OMAP44xx and AM33xx */ const struct clksel_rate div_1_0_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, + { .div =1 , .val =0 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, { .div =0 }, };@@ -61,57 +61,124 @@ const struct clksel_rate div3_1to4_rates[] = { };const struct clksel_rate div_1_1_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, + { .div =1 , .val =1 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, { .div =0 }, };const struct clksel_rate div_1_2_rates[] = { - { .div =1 , .val =2 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, + { .div =1 , .val =2 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, { .div =0 }, };const struct clksel_rate div_1_3_rates[] = { - { .div =1 , .val =3 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, + { .div =1 , .val =3 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, { .div =0 }, };const struct clksel_rate div_1_4_rates[] = { - { .div =1 , .val =4 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, + { .div =1 , .val =4 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, { .div =0 }, };const struct clksel_rate div31_1to31_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =2 , .val =2 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =3 , .val =3 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =4 , .val =4 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =5 , .val =5 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =6 , .val =6 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =7 , .val =7 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =8 , .val =8 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =9 , .val =9 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =10 , .val =10 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =11 , .val =11 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =12 , .val =12 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =13 , .val =13 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =14 , .val =14 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =15 , .val =15 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =16 , .val =16 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =17 , .val =17 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =18 , .val =18 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =19 , .val =19 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =20 , .val =20 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =21 , .val =21 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =22 , .val =22 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =23 , .val =23 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =24 , .val =24 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =25 , .val =25 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =26 , .val =26 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =27 , .val =27 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =28 , .val =28 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =29 , .val =29 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =30 , .val =30 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, - { .div =31 , .val =31 , .flags =RATE_IN_4430 |RATE_IN_AM33XX }, + { .div =1 , .val =1 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =2 , .val =2 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =3 , .val =3 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =4 , .val =4 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =5 , .val =5 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =6 , .val =6 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =7 , .val =7 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =8 , .val =8 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =9 , .val =9 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =10 , .val =10 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =11 , .val =11 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =12 , .val =12 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =13 , .val =13 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =14 , .val =14 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =15 , .val =15 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =16 , .val =16 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =17 , .val =17 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =18 , .val =18 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =19 , .val =19 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =20 , .val =20 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =21 , .val =21 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =22 , .val =22 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =23 , .val =23 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =24 , .val =24 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =25 , .val =25 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =26 , .val =26 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =27 , .val =27 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =28 , .val =28 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =29 , .val =29 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =30 , .val =30 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =31 , .val =31 , .flags =RATE_IN_4430 |RATE_IN_AM33XX |RATE_IN_54XX }, + { .div =0 }, +}; + +const struct clksel_rate div63_1to63_rates[] = { + { .div =1 , .val =1 , .flags =RATE_IN_54XX }, + { .div =2 , .val =2 , .flags =RATE_IN_54XX }, + { .div =3 , .val =3 , .flags =RATE_IN_54XX }, + { .div =4 , .val =4 , .flags =RATE_IN_54XX }, + { .div =5 , .val =5 , .flags =RATE_IN_54XX }, + { .div =6 , .val =6 , .flags =RATE_IN_54XX }, + { .div =7 , .val =7 , .flags =RATE_IN_54XX }, + { .div =8 , .val =8 , .flags =RATE_IN_54XX }, + { .div =9 , .val =9 , .flags =RATE_IN_54XX }, + { .div =10 , .val =10 , .flags =RATE_IN_54XX }, + { .div =11 , .val =11 , .flags =RATE_IN_54XX }, + { .div =12 , .val =12 , .flags =RATE_IN_54XX }, + { .div =13 , .val =13 , .flags =RATE_IN_54XX }, + { .div =14 , .val =14 , .flags =RATE_IN_54XX }, + { .div =15 , .val =15 , .flags =RATE_IN_54XX }, + { .div =16 , .val =16 , .flags =RATE_IN_54XX }, + { .div =17 , .val =17 , .flags =RATE_IN_54XX }, + { .div =18 , .val =18 , .flags =RATE_IN_54XX }, + { .div =19 , .val =19 , .flags =RATE_IN_54XX }, + { .div =20 , .val =20 , .flags =RATE_IN_54XX }, + { .div =21 , .val =21 , .flags =RATE_IN_54XX }, + { .div =22 , .val =22 , .flags =RATE_IN_54XX }, + { .div =23 , .val =23 , .flags =RATE_IN_54XX }, + { .div =24 , .val =24 , .flags =RATE_IN_54XX }, + { .div =25 , .val =25 , .flags =RATE_IN_54XX }, + { .div =26 , .val =26 , .flags =RATE_IN_54XX }, + { .div =27 , .val =27 , .flags =RATE_IN_54XX }, + { .div =28 , .val =28 , .flags =RATE_IN_54XX }, + { .div =29 , .val =29 , .flags =RATE_IN_54XX }, + { .div =30 , .val =30 , .flags =RATE_IN_54XX }, + { .div =31 , .val =31 , .flags =RATE_IN_54XX }, + { .div =32 , .val =32 , .flags =RATE_IN_54XX }, + { .div =33 , .val =33 , .flags =RATE_IN_54XX }, + { .div =34 , .val =34 , .flags =RATE_IN_54XX }, + { .div =35 , .val =35 , .flags =RATE_IN_54XX }, + { .div =36 , .val =36 , .flags =RATE_IN_54XX }, + { .div =37 , .val =37 , .flags =RATE_IN_54XX }, + { .div =38 , .val =38 , .flags =RATE_IN_54XX }, + { .div =39 , .val =39 , .flags =RATE_IN_54XX }, + { .div =40 , .val =40 , .flags =RATE_IN_54XX }, + { .div =41 , .val =41 , .flags =RATE_IN_54XX }, + { .div =42 , .val =42 , .flags =RATE_IN_54XX }, + { .div =43 , .val =43 , .flags =RATE_IN_54XX }, + { .div =44 , .val =44 , .flags =RATE_IN_54XX }, + { .div =45 , .val =45 , .flags =RATE_IN_54XX }, + { .div =46 , .val =46 , .flags =RATE_IN_54XX }, + { .div =47 , .val =47 , .flags =RATE_IN_54XX }, + { .div =48 , .val =48 , .flags =RATE_IN_54XX }, + { .div =49 , .val =49 , .flags =RATE_IN_54XX }, + { .div =50 , .val =50 , .flags =RATE_IN_54XX }, + { .div =51 , .val =51 , .flags =RATE_IN_54XX }, + { .div =52 , .val =52 , .flags =RATE_IN_54XX }, + { .div =53 , .val =53 , .flags =RATE_IN_54XX }, + { .div =54 , .val =54 , .flags =RATE_IN_54XX }, + { .div =55 , .val =55 , .flags =RATE_IN_54XX }, + { .div =56 , .val =56 , .flags =RATE_IN_54XX }, + { .div =57 , .val =57 , .flags =RATE_IN_54XX }, + { .div =58 , .val =58 , .flags =RATE_IN_54XX }, + { .div =59 , .val =59 , .flags =RATE_IN_54XX }, + { .div =60 , .val =60 , .flags =RATE_IN_54XX }, + { .div =61 , .val =61 , .flags =RATE_IN_54XX }, + { .div =62 , .val =62 , .flags =RATE_IN_54XX }, + { .div =63 , .val =63 , .flags =RATE_IN_54XX }, { .div =0 }, };
PATCH 7/10 ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
Quoted 5 lines · Sebastien Guiriec
Hi Santosh,
I check the tree with Audio and it is working. Just a comment for the addition of ABE DPLL locking like for OMAP4.
Excellent. Can you send the update please?
I will fold that in.
Regards
santosh
PATCH 7/10 ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
Hi Santosh,
I have push under the omap-audio gitorious two patches on top of your series. One for adding the ABE DPLL and a second for the remove of Audio DMA addresses.
https://gitorious.org/omap-audio/linux-audio/commits/base/omap5_es2_data
I will try to check Display tomorrow.
Sebastien
Quoted 12 lines · Santosh Shilimkar
Quoted 5 lines · Sebastien Guiriec
Hi Santosh,
I check the tree with Audio and it is working. Just a comment for the addition of ABE DPLL locking like for OMAP4.
Excellent. Can you send the update please?
I will fold that in.Regards
santosh
PATCH 7/10 ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
In reply to Santosh ShilimkarQuoted 3 lines · Santosh Shilimkar
From: Rajendra Nayak <[email protected]>
Add the clock tree related data for OMAP54xx platforms.
[snip]
arch/arm/mach-omap2/cclock54xx_data.c line 1751
Quoted 11 lines
arch/arm/mach-omap2/cclock54xx_data.c new file +11
-0+CLK ("omap_timer.1" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.2" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.3" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.4" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.5" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.6" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.7" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.8" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.9" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.10" ,"32k_ck" , &sys_32k_ck,CK_54XX ), + CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_54XX),
I have been trying to get away from having so many aliases for the same clock for timers. Here we should replace all of the above and just have ...
+ CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_54XX),
For more details see [1].
arch/arm/mach-omap2/cclock54xx_data.c line 1763
Quoted 12 lines
arch/arm/mach-omap2/cclock54xx_data.c new file +12
-0+CLK ("omap_timer.1" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.2" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.3" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.4" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.9" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.10" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.11" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.5" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), +CLK ("omap_timer.6" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), +CLK ("omap_timer.7" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), + CLK("omap_timer.8", "sys_ck", &dss_syc_gfclk_div, CK_54XX), +};
These aliases will not work with device-tree because the device-name is formatted <addr>.<device>. Hence, when configuring a the timer parent clock via the dmtimer driver it will fail. So it should be more like ...
+ CLK("4ae18000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
+ CLK("48032000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
+ CLK("48034000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
+ CLK("48036000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
+ CLK("40138000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
+ CLK("4013a000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
+ CLK("4013c000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
+ CLK("4013e000.timer", "timer_sys_ck", &dss_syc_gfclk_div,CK_54XX),
+ CLK("4803e000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX),
+ CLK("48086000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX),
+ CLK("48088000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX),
For more details see [2].
If you would like to test the dmtimer driver on omap5, then you can grab my omap-test module [3], build it (see README), load it and then ...
# echo 1 > /sys/kernel/debug/omap-test/timer/all
This will perform some basic tests on all the dmtimers. I would do it myself, but there appears to be several issues getting this to boot on an ES1.0 (which is probably expected).
Cheers
Jon
[1] http://www.spinics.net/lists/linux-omap/msg71272.html
[2] https://patchwork.kernel.org/patch/1204351/
[3] https://github.com/jonhunter/omap-test
PATCH 7/10 ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
Quoted 57 lines · Jon Hunter
Quoted 3 lines · Santosh Shilimkar
From: Rajendra Nayak <[email protected]>
Add the clock tree related data for OMAP54xx platforms.
[snip]
arch/arm/mach-omap2/cclock54xx_data.c line 1751
Quoted 11 lines
arch/arm/mach-omap2/cclock54xx_data.c new file +11
-0+CLK ("omap_timer.1" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.2" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.3" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.4" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.5" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.6" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.7" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.8" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.9" ,"32k_ck" , &sys_32k_ck,CK_54XX ), +CLK ("omap_timer.10" ,"32k_ck" , &sys_32k_ck,CK_54XX ), + CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_54XX),I have been trying to get away from having so many aliases for the same clock for timers. Here we should replace all of the above and just have ...
(quoted diff) +1
-0+ CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_54XX),For more details see [1].
arch/arm/mach-omap2/cclock54xx_data.c line 1763
Quoted 12 lines
arch/arm/mach-omap2/cclock54xx_data.c new file +12
-0+CLK ("omap_timer.1" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.2" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.3" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.4" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.9" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.10" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.11" ,"sys_ck" , &sys_clkin,CK_54XX ), +CLK ("omap_timer.5" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), +CLK ("omap_timer.6" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), +CLK ("omap_timer.7" ,"sys_ck" , &dss_syc_gfclk_div,CK_54XX ), + CLK("omap_timer.8", "sys_ck", &dss_syc_gfclk_div, CK_54XX), +};These aliases will not work with device-tree because the device-name is formatted <addr>.<device>. Hence, when configuring a the timer parent clock via the dmtimer driver it will fail. So it should be more like ...
(quoted diff) +8
-0+ CLK("4ae18000.timer", "timer_sys_ck", &sys_clkin, CK_54XX), + CLK("48032000.timer", "timer_sys_ck", &sys_clkin, CK_54XX), + CLK("48034000.timer", "timer_sys_ck", &sys_clkin, CK_54XX), + CLK("48036000.timer", "timer_sys_ck", &sys_clkin, CK_54XX), + CLK("40138000.timer", "timer_sys_ck", &sys_clkin, CK_54XX), + CLK("4013a000.timer", "timer_sys_ck", &sys_clkin, CK_54XX), + CLK("4013c000.timer", "timer_sys_ck", &sys_clkin, CK_54XX), + CLK("4013e000.timer", "timer_sys_ck", &dss_syc_gfclk_div,
CK_54XX),(quoted diff) +3
-0+ CLK("4803e000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX), + CLK("48086000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX), + CLK("48088000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX),
Quoted 1 line
For more details see [2].
Thanks Jon. I will update the autogen scripts to generate these accordingly.
Quoted 9 lines
If you would like to test the dmtimer driver on omap5, then you can grab my omap-test module [3], build it (see README), load it and then ...
# echo 1 > /sys/kernel/debug/omap-test/timer/allThis will perform some basic tests on all the dmtimers. I would do it myself, but there appears to be several issues getting this to boot on an ES1.0 (which is probably expected).
Right. This is ES2.0 data, so won't boot on an ES1.0 device.
regards,
Rajendra
Quoted 8 lines
Cheers
Jon[1] http://www.spinics.net/lists/linux-omap/msg71272.html
[2] https://patchwork.kernel.org/patch/1204351/
[3] https://github.com/jonhunter/omap-test
PATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
In reply to Santosh ShilimkarFrom: Benoit Cousson <[email protected]>
Adding the hwmod data for OMAP54xx platforms.
Cc Paul Walmsley <[email protected]>
Signed-off-by Benoit Cousson <[email protected]>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by Santosh Shilimkar <[email protected]>
--- arch/arm/mach-omap2/omap_hwmod.h | 1 + arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 5988 ++++++++++++++++++++++++++++ 2 files changed, 5989 insertions(+) create mode 100644 arch/arm/mach-omap2/omap_hwmod_54xx_data.c
arch/arm/mach-omap2/omap_hwmod.h +1 -0
@@ -678,6 +678,7 @@ extern int omap2420_hwmod_init(void);extern int omap2430_hwmod_init (void );extern int omap3xxx_hwmod_init (void );extern int omap44xx_hwmod_init (void ); +extern int omap54xx_hwmod_init (void );extern int am33xx_hwmod_init (void );extern int __init omap_hwmod_register_links (struct omap_hwmod_ocp_if **ois);
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +5988 -0
2,993 lines not on this page · raw message
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Signature · 1 line
1.7.9.5
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Tony Lindgren
maintainerPATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Hi,
Quoted 10 lines · Santosh Shilimkar
From: Benoit Cousson <[email protected]>
Adding the hwmod data for OMAP54xx platforms.
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +5
-0+/* bb2d */ +static struct omap_hwmod_irq_info omap54xx_bb2d_irqs[] = { + { .irq =125 +OMAP54XX_IRQ_GIC_START }, + { .irq =-1 } +};
...
Quoted 5 lines
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +5
-0+/* c2c */ +static struct omap_hwmod_irq_info omap54xx_c2c_irqs[] = { + { .irq =88 +OMAP54XX_IRQ_GIC_START }, + { .irq =-1 } +};
...
Quoted 15 lines
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +12
-0+static struct omap_hwmod_dma_info omap54xx_c2c_sdma_reqs[] = { + { .dma_req =68 +OMAP54XX_DMA_REQ_START }, + { .dma_req =-1 } +}; +static struct omap_hwmod_addr_space omap54xx_elm_addrs[] = { + { + .pa_start =0x48078000 , + .pa_end =0x48078fff , + .flags =ADDR_TYPE_RT + }, + { } +};
...
arch/arm/mach-omap2/omap_hwmod_54xx_data.c line 4266
Quoted 8 lines
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +8
-0+static struct omap_hwmod_addr_space omap54xx_emif1_addrs[] = { + { + .pa_start =0x4c000000 , + .pa_end =0x4c0003ff , + .flags =ADDR_TYPE_RT + }, + { } +};
As discussed earlier on this list, let's not duplicate the standard resources here as they already are supposed to come from device tree.
Whatever issues prevent us from dropping the duplicate data here need to be fixed. I believe Benoit already had some scripts/patches for that and was just waiting for the DMA binding to get merged?
Regards,
Tony
PATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Quoted 52 lines · Tony Lindgren
Hi,
Quoted 10 lines · Santosh Shilimkar
From: Benoit Cousson <[email protected]>
Adding the hwmod data for OMAP54xx platforms.
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +5
-0+/* bb2d */ +static struct omap_hwmod_irq_info omap54xx_bb2d_irqs[] = { + { .irq =125 +OMAP54XX_IRQ_GIC_START }, + { .irq =-1 } +};...
Quoted 5 lines
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +5
-0+/* c2c */ +static struct omap_hwmod_irq_info omap54xx_c2c_irqs[] = { + { .irq =88 +OMAP54XX_IRQ_GIC_START }, + { .irq =-1 } +};...
Quoted 15 lines
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +12
-0+static struct omap_hwmod_dma_info omap54xx_c2c_sdma_reqs[] = { + { .dma_req =68 +OMAP54XX_DMA_REQ_START }, + { .dma_req =-1 } +}; +static struct omap_hwmod_addr_space omap54xx_elm_addrs[] = { + { + .pa_start =0x48078000 , + .pa_end =0x48078fff , + .flags =ADDR_TYPE_RT + }, + { } +};...
arch/arm/mach-omap2/omap_hwmod_54xx_data.c line 4266
Quoted 8 lines
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +8
-0+static struct omap_hwmod_addr_space omap54xx_emif1_addrs[] = { + { + .pa_start =0x4c000000 , + .pa_end =0x4c0003ff , + .flags =ADDR_TYPE_RT + }, + { } +};As discussed earlier on this list, let's not duplicate the standard resources here as they already are supposed to come from device tree.
Quoted 4 lines
Whatever issues prevent us from dropping the duplicate data here need to be fixed. I believe Benoit already had some
scripts/patchesfor that and was just waiting for the DMA binding to get merged?
Will have a loot at it. DMA binding pull request narrowly missed 3.8 but should get into 3.9.
Regards
santosh
PATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Hi Santosh
We can also remove all the next data:
omap54xx_l4_abe__aess_dma, omap54xx_l4_abe__dmic_dma, omap54xx_l4_abe__mcasp_dma, omap54xx_l4_abe__mcbsp1_dma, omap54xx_l4_abe__mcbsp2_dma, omap54xx_l4_abe__mcbsp3_dma, omap54xx_l4_abe__mcpdm_dma, omap54xx_l4_abe__slimbus1_dma, omap54xx_l4_abe__timer5_dma, omap54xx_l4_abe__timer6_dma, omap54xx_l4_abe__timer7_dma, omap54xx_l4_abe__timer8_dma, omap54xx_l4_abe__wd_timer3_dma,
It was needed in the past due to the way the lockup between DT data and hwmod was done but Peter clean it up in 3.8.
For AESS we just need the last memory bank due to hwmod code for SYS_CONFIG access.
Best regards,
Sebastien
Quoted 68 lines · Santosh Shilimkar
Quoted 52 lines · Tony Lindgren
Hi,
Quoted 10 lines · Santosh Shilimkar
From: Benoit Cousson <[email protected]>
Adding the hwmod data for OMAP54xx platforms.
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +5
-0+/* bb2d */ +static struct omap_hwmod_irq_info omap54xx_bb2d_irqs[] = { + { .irq =125 +OMAP54XX_IRQ_GIC_START }, + { .irq =-1 } +};...
Quoted 5 lines
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +5
-0+/* c2c */ +static struct omap_hwmod_irq_info omap54xx_c2c_irqs[] = { + { .irq =88 +OMAP54XX_IRQ_GIC_START }, + { .irq =-1 } +};...
Quoted 15 lines
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +12
-0+static struct omap_hwmod_dma_info omap54xx_c2c_sdma_reqs[] = { + { .dma_req =68 +OMAP54XX_DMA_REQ_START }, + { .dma_req =-1 } +}; +static struct omap_hwmod_addr_space omap54xx_elm_addrs[] = { + { + .pa_start =0x48078000 , + .pa_end =0x48078fff , + .flags =ADDR_TYPE_RT + }, + { } +};...
arch/arm/mach-omap2/omap_hwmod_54xx_data.c line 4266
Quoted 8 lines
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +8
-0+static struct omap_hwmod_addr_space omap54xx_emif1_addrs[] = { + { + .pa_start =0x4c000000 , + .pa_end =0x4c0003ff , + .flags =ADDR_TYPE_RT + }, + { } +};As discussed earlier on this list, let's not duplicate the standard resources here as they already are supposed to come from device tree.
Quoted 4 lines
Whatever issues prevent us from dropping the duplicate data here need to be fixed. I believe Benoit already had some
scripts/patchesfor that and was just waiting for the DMA binding to get merged?Will have a loot at it. DMA binding pull request narrowly missed 3.8 but should get into 3.9.
Regards
santosh--
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PATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
In reply to Santosh ShilimkarQuoted 53 lines · Santosh Shilimkar
Quoted 52 lines · Tony Lindgren
Hi,
Quoted 10 lines · Santosh Shilimkar
From: Benoit Cousson <[email protected]>
Adding the hwmod data for OMAP54xx platforms.
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +5
-0+/* bb2d */ +static struct omap_hwmod_irq_info omap54xx_bb2d_irqs[] = { + { .irq =125 +OMAP54XX_IRQ_GIC_START }, + { .irq =-1 } +};...
Quoted 5 lines
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +5
-0+/* c2c */ +static struct omap_hwmod_irq_info omap54xx_c2c_irqs[] = { + { .irq =88 +OMAP54XX_IRQ_GIC_START }, + { .irq =-1 } +};...
Quoted 15 lines
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +12
-0+static struct omap_hwmod_dma_info omap54xx_c2c_sdma_reqs[] = { + { .dma_req =68 +OMAP54XX_DMA_REQ_START }, + { .dma_req =-1 } +}; +static struct omap_hwmod_addr_space omap54xx_elm_addrs[] = { + { + .pa_start =0x48078000 , + .pa_end =0x48078fff , + .flags =ADDR_TYPE_RT + }, + { } +};...
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
Quoted 8 lines
arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file +8
-0+static struct omap_hwmod_addr_space omap54xx_emif1_addrs[] = { + { + .pa_start =0x4c000000 , + .pa_end =0x4c0003ff , + .flags =ADDR_TYPE_RT + }, + { } +};As discussed earlier on this list, let's not duplicate the standard resources here as they already are supposed to come from device tree.
Quoted 7 lines
Quoted 4 lines
Whatever issues prevent us from dropping the duplicate data here need to be fixed. I believe Benoit already had some
scripts/patchesfor that and was just waiting for the DMA binding to get merged?Will have a loot at it. DMA binding pull request narrowly missed 3.8 but should get into 3.9.
So I looked at this one with help of Rajendra. We can get rid of the IRQ and DMA data(needs DMA biding updates) easily. The address space though is needed since hwmod code uses it to setup the sysconfig registers.
Extracting that from DT code seems to be really expensive and ugly [1]. I am yet to try out DMA lines removal but that seems to be doable by pulling Vinod'd DMA engine branch and updating DT file.
Whats your suggestion on address space part ?
Regards,
Santosh
[1] HACK address extraction with DT.
--- arch/arm/mach-omap2/omap_hwmod.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-)
arch/arm/mach-omap2/omap_hwmod.c +27 -4
@@ -138,6 +138,7 @@#include <linux/spinlock.h> #include <linux/slab.h> #include <linux/bootmem.h> +#include <linux/of.h> #include "clock.h" #include "omap_hwmod.h"
@@ -2335,7 +2336,12 @@ static int _shutdown(struct omap_hwmod *oh)static void __init _init_mpu_rt_base (struct omap_hwmod *oh,void *data) {struct omap_hwmod_addr_space *mem; -void __iomem *va_start; +void __iomem *va_start =NULL ; +struct device_node *np; +unsigned long start =0 , size =0 ; +const void *reg_prop; +const char *p; +if (!oh)return ;
@@ -2349,15 +2355,32 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)if (!mem) {pr_debug ("omap_hwmod: %s: no MPU register target found\n" , oh->name); -return ; +/*Check in Device Tree blob*/ +for_each_child_of_node (of_find_node_by_name (NULL ,"ocp" ), np) { +printk ("np-name=%s\n" , np->name); +if (of_find_property (np,"ti,hwmods" ,NULL )) { + p =of_get_property (np,"ti,hwmods" ,NULL ); +if (!strcmp (p, oh->name)) { + reg_prop =of_get_property (np,"reg" ,NULL ); + start =of_read_number (reg_prop,1 ); + size =of_read_number (reg_prop +4 ,1 ); + } + } + } + }else { + start = mem->pa_start; + size = mem->pa_end - mem->pa_start; } - va_start =ioremap (mem->pa_start, mem->pa_end - mem->pa_start); +if (!start) +return ; + + va_start =ioremap (start, size);if (!va_start) {pr_err ("omap_hwmod: %s: Could not ioremap\n" , oh->name);return ; } - +pr_debug ("omap_hwmod: %s: MPU register target at va %p\n" , oh->name, va_start);
Signature · 1 line
1.7.9.5
Tony Lindgren
maintainerPATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Quoted 5 lines · Santosh Shilimkar
Quoted 1 line
So I looked at this one with help of Rajendra. We can get rid of the IRQ and DMA data(needs DMA biding updates) easily. The address space though is needed since hwmod code uses it to setup the sysconfig registers.
OK great. The address space tinkering in hwmod code should be moved to be done in the drivers.
As discussed earlier, there should be a driver specific reset function driver_xyz_reset() in the driver header file so the hwmod code can call it too in a late_initcall if no driver is loaded.
Quoted 4 lines
Extracting that from DT code seems to be really expensive and ugly [1]. I am yet to try out DMA lines removal but that seems to be doable by pulling Vinod'd DMA engine branch and updating DT file.
The overhead here does not matter as it should only happen in a late_initcall and only for some of the drivers. For that to happen we just need to go through the list of modules not yet probed. We also need to have some locking in the driver specific reset function to avoid races with the loadable modules.
Quoted 1 line
Whats your suggestion on address space part ?
Let's add the code to hwmod to extract it from DT so hwmod code can call the driver specific reset function defined in the driver header. That way we can start moving the driver code out of hwmod one driver at a time.
Note that the ioremapping should be done in the driver specific reset function, not in hwmod code. We just need to pass the iorange in a struct resource to the driver specific reset function.
Regards,
Tony
PATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Hi Tony,
Quoted 20 lines · Tony Lindgren
Quoted 5 lines · Santosh Shilimkar
Quoted 1 line
So I looked at this one with help of Rajendra. We can get rid of the IRQ and DMA data(needs DMA biding updates) easily. The address space though is needed since hwmod code uses it to setup the sysconfig registers.
OK great. The address space tinkering in hwmod code should be moved to be done in the drivers.
As discussed earlier, there should be a driver specific reset function
driver_xyz_reset()in the driver header file so the hwmod code can call it too in alate_initcallif no driver is loaded.Quoted 4 lines
Extracting that from DT code seems to be really expensive and ugly [1]. I am yet to try out DMA lines removal but that seems to be doable by pulling Vinod'd DMA engine branch and updating DT file.
Quoted 5 lines
The overhead here does not matter as it should only happen in a
late_initcalland only for some of the drivers. For that to happen we just need to go through the list of modules not yet probed. We also need to have some locking in the driver specific reset function to avoid races with the loadable modules.
Mmm, not really, that address is used by *every* hwmod for sysconfig access. So iterating over every DT nodes for every hwmods seems pretty ugly and un-optimized.
That being said, it might worth checking the overhead. That will not make the fix nicer anyway, but at least it will allow a smooth transition toward a real clean solution. Assuming someone will work on that later, which might never happen.
Regards,
Benoit
Tony Lindgren
maintainerPATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Quoted 29 lines · Benoit Cousson
Hi Tony,
Quoted 20 lines · Tony Lindgren
Quoted 5 lines · Santosh Shilimkar
Quoted 1 line
So I looked at this one with help of Rajendra. We can get rid of the IRQ and DMA data(needs DMA biding updates) easily. The address space though is needed since hwmod code uses it to setup the sysconfig registers.
OK great. The address space tinkering in hwmod code should be moved to be done in the drivers.
As discussed earlier, there should be a driver specific reset function
driver_xyz_reset()in the driver header file so the hwmod code can call it too in alate_initcallif no driver is loaded.Quoted 4 lines
Extracting that from DT code seems to be really expensive and ugly [1]. I am yet to try out DMA lines removal but that seems to be doable by pulling Vinod'd DMA engine branch and updating DT file.
Quoted 5 lines
The overhead here does not matter as it should only happen in a
late_initcalland only for some of the drivers. For that to happen we just need to go through the list of modules not yet probed. We also need to have some locking in the driver specific reset function to avoid races with the loadable modules.
Quoted 3 lines
Mmm, not really, that address is used by *every* hwmod for sysconfig access. So iterating over every DT nodes for every hwmods seems pretty ugly and un-optimized.
I think you missed one point. Iterating over all the modules should only happen for the unused modules. With sysconfig access moved to the drivers getting the ioaddress is done in the standard way in the driver probe instead of iterating over all of them.
Quoted 4 lines
That being said, it might worth checking the overhead. That will not make the fix nicer anyway, but at least it will allow a smooth transition toward a real clean solution. Assuming someone will work on that later, which might never happen.
Right, so who is going to do all the work needed?
Regards,
Tony
PATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Quoted 39 lines · Tony Lindgren
Quoted 29 lines · Benoit Cousson
Hi Tony,
Quoted 20 lines · Tony Lindgren
Quoted 5 lines · Santosh Shilimkar
Quoted 1 line
So I looked at this one with help of Rajendra. We can get rid of the IRQ and DMA data(needs DMA biding updates) easily. The address space though is needed since hwmod code uses it to setup the sysconfig registers.
OK great. The address space tinkering in hwmod code should be moved to be done in the drivers.
As discussed earlier, there should be a driver specific reset function
driver_xyz_reset()in the driver header file so the hwmod code can call it too in alate_initcallif no driver is loaded.Quoted 4 lines
Extracting that from DT code seems to be really expensive and ugly [1]. I am yet to try out DMA lines removal but that seems to be doable by pulling Vinod'd DMA engine branch and updating DT file.
Quoted 5 lines
The overhead here does not matter as it should only happen in a
late_initcalland only for some of the drivers. For that to happen we just need to go through the list of modules not yet probed. We also need to have some locking in the driver specific reset function to avoid races with the loadable modules.Quoted 3 lines
Mmm, not really, that address is used by *every* hwmod for sysconfig access. So iterating over every DT nodes for every hwmods seems pretty ugly and un-optimized.
I think you missed one point. Iterating over all the modules should only happen for the unused modules. With sysconfig access moved to the drivers getting the ioaddress is done in the standard way in the driver probe instead of iterating over all of them.
Quoted 7 lines
Quoted 4 lines
That being said, it might worth checking the overhead. That will not make the fix nicer anyway, but at least it will allow a smooth transition toward a real clean solution. Assuming someone will work on that later, which might never happen.
Right, so who is going to do all the work needed?
OK so we do managed to clean up the address space, IRQ lines and DMA request lines data from hwmod completely.
-OMAP5 hwmod data file, 2076 lines we could remove which significant reduction. I ran the same scripts on OMAP4 and there too about 2200 lines getting deleted.
- I have to udapte DT file to add the all supported hwmods with reg property so that OMAP5 continue to boot. Similar work is needed for OMAP4 too once OMAP4 is made DT only support.
- To my suprise, the DT lookup isn't that bad. It is adding just 24 milliseconds to the boot time which is more or less noise.
Have pushed a branch with above update for OMAP5 here [1]
So we are left with two other topics which you mentioned in the comments.
1. Movement of clock data to drivers/clk. Till we get direction here I would like to hear the alternative to get OMAP5 booting from mainline. If there is no alternative, we can keep OMAP5 clock data alone out of tree and get rest of the data files merged.
2. The iormap() done by hwmod for sysconfig handling which you are discussing with Rajendra. So far we don't have a viable way to get the iormapped address from device drivers back to platform code. Lets continue on this thread but this can evolve in parallel.
Let me know your thoughts.
Regards,
Santosh
[1] git://github.com/SantoshShilimkar/linux.git
3.9/omap5-testing-hwmod-cleanup
Tony Lindgren
maintainerPATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Quoted 6 lines · Santosh Shilimkar
OK so we do managed to clean up the address space, IRQ lines and DMA request lines data from hwmod completely.
-OMAP5 hwmod data file, 2076 lines we could remove which significant reduction. I ran the same scripts on OMAP4 and there too about 2200 lines getting deleted.
Great, thanks for looking into it. I guess we cannot do that quite yet for omap4 as we have not made it DT only. But we should be able to do that for am33xx as that's DT only already.
Quoted 3 lines
- I have to udapte DT file to add the all supported hwmods with reg property so that OMAP5 continue to boot. Similar work is needed for OMAP4 too once OMAP4 is made DT only support.
OK
Quoted 2 lines
- To my suprise, the DT lookup isn't that bad. It is adding just 24 milliseconds to the boot time which is more or less noise.
That's good to hear.
Quoted 9 lines
Have pushed a branch with above update for OMAP5 here [1]
So we are left with two other topics which you mentioned in the comments.
1. Movement of clock data to
drivers/clk. Till we get direction here I would like to hear the alternative to get OMAP5 booting from mainline. If there is no alternative, we can keep OMAP5 clock data alone out of tree and get rest of the data files merged.
I agree, no reason to hold back the other patches. But we should resolve the common clock move to drivers/clk properly now, otherwise it will just get postponed again and we have even bigger problem to deal with.
Quoted 5 lines
2. The
iormap()done by hwmod for sysconfig handling which you are discussing with Rajendra. So far we don't have a viable way to get the iormapped address from device drivers back to platform code. Lets continue on this thread but this can evolve in parallel.
Yes that can be fixed separately.
Regards,
Tony
Quoted 2 lines
[1]
git://github.com/SantoshShilimkar/linux.git
3.9/omap5-testing-hwmod-cleanup
PATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Quoted 33 lines · Tony Lindgren
Quoted 6 lines · Santosh Shilimkar
OK so we do managed to clean up the address space, IRQ lines and DMA request lines data from hwmod completely.
-OMAP5 hwmod data file, 2076 lines we could remove which significant reduction. I ran the same scripts on OMAP4 and there too about 2200 lines getting deleted.
Great, thanks for looking into it. I guess we cannot do that quite yet for omap4 as we have not made it DT only. But we should be able to do that for am33xx as that's DT only already.
Quoted 3 lines
- I have to udapte DT file to add the all supported hwmods with reg property so that OMAP5 continue to boot. Similar work is needed for OMAP4 too once OMAP4 is made DT only support.
OK
Quoted 2 lines
- To my suprise, the DT lookup isn't that bad. It is adding just 24 milliseconds to the boot time which is more or less noise.
That's good to hear.
Quoted 9 lines
Have pushed a branch with above update for OMAP5 here [1]
So we are left with two other topics which you mentioned in the comments.
1. Movement of clock data to
drivers/clk. Till we get direction here I would like to hear the alternative to get OMAP5 booting from mainline. If there is no alternative, we can keep OMAP5 clock data alone out of tree and get rest of the data files merged.
Quoted 5 lines
I agree, no reason to hold back the other patches. But we should resolve the common clock move to
drivers/clkproperly now, otherwise it will just get postponed again and we have even bigger problem to deal with.
I will go ahead and separate the clock data from rest of the data files so that we can get rest of the data patches in.
Quoted 8 lines
Quoted 5 lines
2. The
iormap()done by hwmod for sysconfig handling which you are discussing with Rajendra. So far we don't have a viable way to get the iormapped address from device drivers back to platform code. Lets continue on this thread but this can evolve in parallel.Yes that can be fixed separately.
Yep. Thanks for the comments.
Regards
Santosh
PATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
In reply to Tony LindgrenHi Tony,
Quoted 5 lines
Quoted 4 lines
So I looked at this one with help of Rajendra. We can get rid of the IRQ and DMA data(needs DMA biding updates) easily. The address space though is needed since hwmod code uses it to setup the sysconfig registers.
Quoted 7 lines
OK great. The address space tinkering in hwmod code should be moved to be done in the drivers.
As discussed earlier, there should be a driver specific reset function
driver_xyz_reset()in the driver header file so the hwmod code can call it too in alate_initcallif no driver is loaded.
I am a little confused with what you are saying. The hwmod doing reset of modules (and not relying on drivers doing it) was mainly for modules which do not have drivers built in (and hence run a risk of gating system sleep in case the bootloaders left them in a bad state).
But if the drivers aren't built in (or are built as modules) *then* hwmod still needs to be able to do reset (maybe in a late_initcall) of these modules on its own (because there is no driver code to do it).
The other big reason why hwmod would need the address space tinkering is because it also controls the various OCP master/slave modes of these modules. Quite often these modes are broken and need tinkering every time the module is enable/idled and also need to be restored back to sane values (smart_idle/smart_standby) post reset. All of this is today handled as part of hwmod and would defeat the whole purpose of the framework if all this is moved into drivers.
So completely getting rid of all address space tinkering in hwmod looks really difficult.
regards,
Rajendra
Quoted 27 lines
Quoted 5 lines
Extracting that from DT code seems to be really expensive and ugly [1]. I am yet to try out DMA lines removal but that seems to be doable by pulling Vinod'd DMA engine branch and updating DT file.
The overhead here does not matter as it should only happen in a
late_initcalland only for some of the drivers. For that to happen we just need to go through the list of modules not yet probed. We also need to have some locking in the driver specific reset function to avoid races with the loadable modules.Quoted 1 line
Whats your suggestion on address space part ?
Let's add the code to hwmod to extract it from DT so hwmod code can call the driver specific reset function defined in the driver header. That way we can start moving the driver code out of hwmod one driver at a time.
Note that the ioremapping should be done in the driver specific reset function, not in hwmod code. We just need to pass the iorange in a struct resource to the driver specific reset function.
Regards,
Tony
Tony Lindgren
maintainerPATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Quoted 15 lines · Rajendra Nayak
Hi Tony,
Quoted 5 lines
Quoted 4 lines
So I looked at this one with help of Rajendra. We can get rid of the IRQ and DMA data(needs DMA biding updates) easily. The address space though is needed since hwmod code uses it to setup the sysconfig registers.
Quoted 7 lines
OK great. The address space tinkering in hwmod code should be moved to be done in the drivers.
As discussed earlier, there should be a driver specific reset function
driver_xyz_reset()in the driver header file so the hwmod code can call it too in alate_initcallif no driver is loaded.
Quoted 5 lines
I am a little confused with what you are saying. The hwmod doing reset of modules (and not relying on drivers doing it) was mainly for modules which do not have drivers built in (and hence run a risk of gating system sleep in case the bootloaders left them in a bad state).
Right, but we should not duplicate driver code in the hwmod in those cases. And that's why those reset functions need to be in the driver specific headers so they work both for the driver probe, and hwmod late_initcall.
Quoted 3 lines
But if the drivers aren't built in (or are built as modules) *then* hwmod still needs to be able to do reset (maybe in a
late_initcall) of these modules on its own (because there is no driver code to do it).
Yes that's the idea.
Quoted 8 lines
The other big reason why hwmod would need the address space tinkering is because it also controls the various OCP master/slave modes of these modules. Quite often these modes are broken and need tinkering every time the module is enable/idled and also need to be restored back to sane values (smart_idle/smart_standby) post reset. All of this is today handled as part of hwmod and would defeat the whole purpose of the framework if all this is moved into drivers.
It seems that we should have the iospace available in the driver at that point. And it should be also available to the runtime PM code in hwmod in the device somewhere?
Quoted 2 lines
So completely getting rid of all address space tinkering in hwmod looks really difficult.
We can certainly use common hwmod functions via runtime PM for doing that. There should not be any need to ioremap things both in hwmod and in the driver. And there certainly should not be need to provide duplicate iospace from both DT and hwmod. As the DT is what we're standardizing on, we really must move over to use that data.
Regards,
Tony
PATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Quoted 3 lines · Tony Lindgren
It seems that we should have the iospace available in the driver at that point. And it should be also available to the runtime PM code in hwmod in the device somewhere?
I couldn't find anything as part of the device. Definitely not the ioremaped address. There's a device_private->driver_data which the drivers can use to populate the ioremaped address but I am sure thats not whats its meant for.
Tony Lindgren
maintainerPATCH 8/10 ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Quoted 9 lines · Rajendra Nayak
Quoted 3 lines · Tony Lindgren
It seems that we should have the iospace available in the driver at that point. And it should be also available to the runtime PM code in hwmod in the device somewhere?
I couldn't find anything as part of the device. Definitely not the ioremaped address. There's a
device_private->driver_datawhich the drivers can use to populate the ioremaped address but I am sure thats not whats its meant for.
I guess we could have runtime PM init function to pass the driver region to the low level bus code if needed. Anybody got better ideas?
Regards,
Tony
PATCH 9/10 ARM: OMAP5: voltagedomain data: Add OMAP5 voltage domain data
In reply to Santosh ShilimkarAdd voltagedomain related data for OMAP54XX SOCs.
Cc Paul Walmsley <[email protected]>
Signed-off-by Benoit Cousson <[email protected]>
Signed-off-by Santosh Shilimkar <[email protected]>
--- arch/arm/mach-omap2/voltage.h | 1 + arch/arm/mach-omap2/voltagedomains54xx_data.c | 102 +++++++++++++++++++++++++ 2 files changed, 103 insertions(+) create mode 100644 arch/arm/mach-omap2/voltagedomains54xx_data.c
arch/arm/mach-omap2/voltage.h +1 -0
@@ -171,6 +171,7 @@ extern void omap2xxx_voltagedomains_init(void);extern void omap3xxx_voltagedomains_init (void );extern void am33xx_voltagedomains_init (void );extern void omap44xx_voltagedomains_init (void ); +extern void omap54xx_voltagedomains_init (void );struct voltagedomain *voltdm_lookup (const char *name);void voltdm_init (struct voltagedomain **voltdm_list);
arch/arm/mach-omap2/voltagedomains54xx_data.c new file +102 -0
102 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH 10/10 ARM: OMAP5: Enable build and frameowrk initialisations
In reply to Santosh ShilimkarInclude the OMAP5 data files in build. Initialise the voltage, power, clock domains and the clock tree.
Cc Paul Walmsley <[email protected]>
Signed-off-by Santosh Shilimkar <[email protected]>
--- arch/arm/mach-omap2/Makefile | 6 +++++- arch/arm/mach-omap2/io.c | 9 +++++++++ 2 files changed, 14 insertions(+), 1 deletion(-)
arch/arm/mach-omap2/Makefile +5 -1
@@ -123,6 +123,7 @@ obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) +obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o
@@ -137,6 +138,7 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) +obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o # PRCM clockdomain control clockdomain-common += clockdomain.o
@@ -152,6 +154,7 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) +obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@@ -171,7 +174,7 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(clock-common) +obj-$(CONFIG_SOC_OMAP5) += $(clock-common) cclock54xx_data.o obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o # OMAP2 clock rate set data (old "OPP" data)
@@ -194,6 +197,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o +obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o
arch/arm/mach-omap2/io.c +9 -0
@@ -38,6 +38,7 @@#include "clock2xxx.h" #include "clock3xxx.h" #include "clock44xx.h" +#include "clock54xx.h" #include "omap-pm.h" #include "sdrc.h" #include "control.h"
@@ -618,7 +619,15 @@ void __init omap5_init_early(void)omap2_set_globals_prcm_mpu (OMAP2_L4_IO_ADDRESS (OMAP54XX_PRCM_MPU_BASE ));omap_prm_base_init ();omap_cm_base_init (); +omap44xx_prm_init ();omap5xxx_check_revision (); +omap54xx_voltagedomains_init (); +omap54xx_powerdomains_init (); +omap54xx_clockdomains_init (); +omap54xx_hwmod_init (); +omap_hwmod_init_postsetup (); + omap5xxx_clk_init(); + }#endif
Signature · 1 line
1.7.9.5
cover ARM: OMAP5: hwmod, clock and prm data files
In reply to Santosh ShilimkarTony,
Quoted 38 lines · Santosh Shilimkar
Series contains the hwmod, clock and prm data files for OMAP54xx SOCs. This data was kept out of tree to be validated on es2.0 silicon version and also to avoid the es1.0/es2.0 differences which are many.
Benoit Cousson, Rajendra Nayak, Paul Walmesly and Mike have all contributed to get the autogen scripts in shape for OMAP5.
From various discussion on the list, the clock data files are suppose
to be moved todrivers/clk/. Once the direction is clear, patch 8 can be updated accordingly.Patches are tested on OMAP5 sEVM and uEVM. For testing few additional patches are needed. Same tree can be fetched from here [1]
The following changes since commit
7d1f9aeff1ee4a20b1aeb377dd0f579fe9647619:Linux 3.8-rc4 (2013-01-17 19:25:45 -0800)are available in the git repository at:
git://github.com/SantoshShilimkar/linux.gitfor_3.9/omap5_data_filesfor you to fetch changes up to
7f534e1ebeb2bc64250b56fe00eb7d4dfa585e8e:ARM: OMAP5: Enable build and frameowrk initialisations (2013-01-18 19:45:48 +0530)
----------------------------------------------------------------
Benoit Cousson (7):
ARM: OMAP5: PRM: Add OMAP54XX register and bitfield files
ARM: OMAP5: CM: Add OMAP54XX register and bitfield files
ARM: OMAP5: PRCM: Add OMAP54XX local MPU PRCM registers
ARM: OMAP5: SCRM: Add OMAP54XX header file.
ARM: OMAP2+: clockdomain data: Add OMAP54XX data and update the
header
ARM: OMAP5: powerdomain data: Add OMAP54XX data and update the header
ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Quoted 7 lines
Rajendra Nayak (1):
ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headersSantosh Shilimkar (2):
ARM: OMAP5: voltagedomain data: Add OMAP5 voltage domain data
ARM: OMAP5: Enable build and frameowrk initialisations
As discussed on the list, I am going to drop the clock-data[7/10] and build patch[10/10] and prepare a pull request. Let me know if thats fine with you.
Regards,
Santosh
Paul Walmsley
maintainercover ARM: OMAP5: hwmod, clock and prm data files
In reply to Santosh ShilimkarHi,
Quoted 18 lines · Santosh Shilimkar
Series contains the hwmod, clock and prm data files for OMAP54xx SOCs. This data was kept out of tree to be validated on es2.0 silicon version and also to avoid the es1.0/es2.0 differences which are many.
Benoit Cousson, Rajendra Nayak, Paul Walmesly and Mike have all contributed to get the autogen scripts in shape for OMAP5.
Quoted 1 line
From various discussion on the list, the clock data files are suppose
to be moved to
drivers/clk/. Once the direction is clear, patch 8 can be updated accordingly.Patches are tested on OMAP5 sEVM and uEVM. For testing few additional patches are needed. Same tree can be fetched from here [1]
The following changes since commit
7d1f9aeff1ee4a20b1aeb377dd0f579fe9647619:Linux 3.8-rc4 (2013-01-17 19:25:45 -0800)
Quoted 7 lines
are available in the git repository at:
git://github.com/SantoshShilimkar/linux.gitfor_3.9/omap5_data_filesfor you to fetch changes up to
7f534e1ebeb2bc64250b56fe00eb7d4dfa585e8e:ARM: OMAP5: Enable build and frameowrk initialisations (2013-01-18 19:45:48 +0530)
I've posted several comments on the patch contents themselves, all of which are relatively minor, and should be easy to fix:
http://marc.info/?l=linux-omap&m=136501977311223&w=2
- Paul
cover ARM: OMAP5: hwmod, clock and prm data files
Quoted 24 lines · Paul Walmsley
Hi,
Quoted 20 lines · Santosh Shilimkar
Series contains the hwmod, clock and prm data files for OMAP54xx SOCs. This data was kept out of tree to be validated on es2.0 silicon version and also to avoid the es1.0/es2.0 differences which are many.
Benoit Cousson, Rajendra Nayak, Paul Walmesly and Mike have all contributed to get the autogen scripts in shape for OMAP5.
Quoted 1 line
From various discussion on the list, the clock data files are suppose
to be moved to
drivers/clk/. Once the direction is clear, patch 8 can be updated accordingly.Patches are tested on OMAP5 sEVM and uEVM. For testing few additional patches are needed. Same tree can be fetched from here [1]
The following changes since commit
7d1f9aeff1ee4a20b1aeb377dd0f579fe9647619:Linux 3.8-rc4 (2013-01-17 19:25:45 -0800)
are available in the git repository at:
Quoted 9 lines
Quoted 5 lines
git://github.com/SantoshShilimkar/linux.gitfor_3.9/omap5_data_filesfor you to fetch changes up to
7f534e1ebeb2bc64250b56fe00eb7d4dfa585e8e:ARM: OMAP5: Enable build and frameowrk initialisations (2013-01-18 19:45:48 +0530)
I've posted several comments on the patch contents themselves, all of which are relatively minor, and should be easy to fix:
Indeed the fixes were easy. Have posted v2 [1] with the updates.
Regards,
Santosh