Add pinctrl driver for Allwinner A1X SoCs
Subsystems (6)
v3 cover Add pinctrl driver for Allwinner A1X SoCs
Hi everyone,
This patch set adds a pinctrl driver for the IP found in the Allwinner A10 and A13, and the SoC-specific bits for the A13. It also adds the documentation for the device tree bindings.
This patch set has been tested on a Olimex A13-Olinuxino.
Thanks,
Maxime
Changes from v2:
- Rebased on top of 3.8-rc2
- Changed the name of the pinconf argument, split the change to pinconf-generic.h to a separate patch, and documented the argument
Changes from v1:
- Uses the pinconf-generic mechanism
- Changed the dt interface to remove the direct bitstuffing to a more readable format
- Replaced the register accessor macros by inline functions and documented them
Maxime Ripard (7):
pinctrl: pinconf-generic: add drive strength parameter
ARM: sunxi: Add pinctrl driver for Allwinner SoCs
ARM: pinctrl: sunxi: Add the pinctrl pin set for sun5i
ARM: sunxi: Add pinctrl node to the device tree
ARM: sunxi: Add uart1 pinctrl groups
tty: of_serial: Add pinctrl support
ARM: sunxi: olinuxino: Add muxing for the uart
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 60 ++ arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 2 + arch/arm/boot/dts/sun5i-a13.dtsi | 23 + arch/arm/mach-sunxi/Kconfig | 1 + drivers/pinctrl/Kconfig | 5 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-sunxi.c | 802 ++++++++++++++++++++ drivers/pinctrl/pinctrl-sunxi.h | 384 ++++++++++ drivers/tty/serial/of_serial.c | 7 + include/linux/pinctrl/pinconf-generic.h | 3 + 10 files changed, 1288 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt create mode 100644 drivers/pinctrl/pinctrl-sunxi.c create mode 100644 drivers/pinctrl/pinctrl-sunxi.h
Signature · 1 line
1.7.10.4
PATCH v3 1/7 pinctrl: pinconf-generic: add drive strength parameter
Some pin configurations IP allows to set the current output to the pin. This patch adds such a parameter to the pinconf-generic mechanism.
This parameter takes as argument the drive strength in mA.
--- include/linux/pinctrl/pinconf-generic.h | 3 +++ 1 file changed, 3 insertions(+)
include/linux/pinctrl/pinconf-generic.h +3 -0
@@ -46,6 +46,8 @@* @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source * (open emitter). Sending this config will enabale open drain mode, the * argument is ignored. +* @PIN_CONFIG_DRIVE_STRENGTH: the pin will output the current passed as +* argument. The argument is in mA. * @PIN_CONFIG_INPUT_SCHMITT_DISABLE: disable schmitt-trigger mode on the pin. * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in * schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis,
@@ -74,6 +76,7 @@ enum pin_config_param {PIN_CONFIG_DRIVE_PUSH_PULL ,PIN_CONFIG_DRIVE_OPEN_DRAIN ,PIN_CONFIG_DRIVE_OPEN_SOURCE , +PIN_CONFIG_DRIVE_STRENGTH ,PIN_CONFIG_INPUT_SCHMITT_DISABLE ,PIN_CONFIG_INPUT_SCHMITT , PIN_CONFIG_INPUT_DEBOUNCE,
Signature · 1 line
1.7.10.4
Re: [PATCH 1/7] pinctrl: pinconf-generic: add drive strength parameter
Quoted 6 lines · Maxime Ripard
Some pin configurations IP allows to set the current output to the pin. This patch adds such a parameter to the pinconf-generic mechanism.
This parameter takes as argument the drive strength in mA.
Signed-off-by Maxime Ripard <[email protected]>
Patch applied!
Thanks,
Linus Walleij
PATCH v3 2/7 ARM: sunxi: Add pinctrl driver for Allwinner SoCs
In reply to Maxime RipardThe Allwinner SoCs have an IP module that handle both the muxing and the GPIOs.
This IP has 8 banks of 32 bits, with a number of pins actually useful for each of these banks varying from one to another, and depending on the SoC used on the board.
This driver only implements the pinctrl part, the gpio part will come eventually.
--- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 60 +++ arch/arm/mach-sunxi/Kconfig | 1 + drivers/pinctrl/Kconfig | 5 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-sunxi.c | 549 ++++++++++++++++++++ drivers/pinctrl/pinctrl-sunxi.h | 384 ++++++++++++++ 6 files changed, 1000 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt create mode 100644 drivers/pinctrl/pinctrl-sunxi.c create mode 100644 drivers/pinctrl/pinctrl-sunxi.h
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt new file +60 -0
@@ -0,0 +1,60 @@ +* Allwinner A1X Pin Controller + +The pins controlled by sunXi pin controller are organized in banks, +each bank has 32 pins. Each pin has 7 multiplexing functions, with +the first two functions being GPIO in and out. The configuration on +the pins includes drive strength and pull-up. + +Required properties: +- compatible: "allwinner,<soc>-pinctrl". Supported SoCs for now are: + sun5i-a13. +- reg: Should contain the register physical address and length for the + pin controller. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices. + +A pinctrl node should contain at least one subnodes representing the +pinctrl groups available on the machine. Each subnode will list the +pins it needs, and how they should be configured, with regard to muxer +configuration, drive strength and pullups. If one of these options is +not set, its actual value will be unspecified. + +Required subnode-properties: + +- allwinner,pins: List of strings containing the pin name. +- allwinner,function: Function to mux the pins listed above to. + +Optional subnode-properties: +- allwinner,drive: Integer. Represents the current sent to the pin + 0: 10 mA + 1: 20 mA + 2: 30 mA + 3: 40 mA +- allwinner,pull: Integer. + 0: No resistor + 1: Pull-up resistor + 2: Pull-down resistor + +Examples: + +pinctrl at 01c20800 { + compatible = "allwinner,sun5i-a13-pinctrl"; + reg = <0x01c20800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + uart1_pins_a: uart1 at 0 { + allwinner,pins = "PE10", "PE11"; + allwinner,function = "uart1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart1_pins_b: uart1 at 1 { + allwinner,pins = "PG3", "PG4"; + allwinner,function = "uart1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; +};
arch/arm/mach-sunxi/Kconfig +1 -0
@@ -7,3 +7,4 @@ config ARCH_SUNXI select PINCTRL select SPARSE_IRQ select SUNXI_TIMER + select PINCTRL_SUNXI
drivers/pinctrl/Kconfig +5 -0
@@ -151,6 +151,11 @@ config PINCTRL_SIRF depends on ARCH_SIRF select PINMUX +config PINCTRL_SUNXI + bool + select PINMUX + select GENERIC_PINCONF + config PINCTRL_TEGRA bool select PINMUX
drivers/pinctrl/Makefile +1 -0
@@ -30,6 +30,7 @@ obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o +obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
drivers/pinctrl/pinctrl-sunxi.c new file +549 -0
549 lines not on this page · raw message
drivers/pinctrl/pinctrl-sunxi.h new file +384 -0
384 lines not on this page · raw message
Signature · 1 line
1.7.10.4
Re: [PATCH 2/7] ARM: sunxi: Add pinctrl driver for Allwinner SoCs
drivers/pinctrl/Kconfig config PINCTRL_SIRF · line 157
Quoted 4 lines · Maxime Ripard
drivers/pinctrl/Kconfig +4
-0+config PINCTRL_SUNXI + bool + select PINMUX + select GENERIC_PINCONF
Very nice that you use generic pinconf!
Quoted 1 line
+++
b/drivers/pinctrl/pinctrl-sunxi.c
(...)
drivers/pinctrl/pinctrl-sunxi.c line 264
Quoted 10 lines
drivers/pinctrl/pinctrl-sunxi.c new file +10
-0+switch (pinconf_to_config_param (config)) { +case PIN_CONFIG_DRIVE_STRENGTH : + strength =pinconf_to_config_argument (config); +/* +* We convert from mA to what the register expects: +* - 0: 10mA +* - 1: 20mA +* - 2: 30mA +* - 3: 40mA +*/
Nitpick: remove the "-" (dash), some newcomer will invariably interpret the numbers as negative :-/
Don't you want some bounds checking here?
if (strength > 40) { bail out }
drivers/pinctrl/pinctrl-sunxi.c line 267
Quoted 3 lines
drivers/pinctrl/pinctrl-sunxi.c new file +3
-0+ dlevel = strength /10 -1 ; + val =readl (pctl->membase +sunxi_dlevel_reg (g->pin)); + mask = ((1 <<DLEVEL_PINS_BITS ) -1 ) <<sunxi_dlevel_offset (g->pin);
Uhhh ... ((1 << DLEVEL_PINS_BITS) - 1) ...
Which in this case is ((1 << 4) - 1). So ...
10000 - 1 = 01111
So this is a way to say "mask four lowest bits".
What about just adding this instead then:
#define DLEVEL_PINS_MASK 0x0f
drivers/pinctrl/pinctrl-sunxi.c line 274
Quoted 7 lines
drivers/pinctrl/pinctrl-sunxi.c new file +7
-0+ val &= ~mask; + val |= dlevel <<sunxi_dlevel_offset (g->pin); +writel (val, pctl->membase +sunxi_dlevel_reg (g->pin)); +break ; +case PIN_CONFIG_BIAS_PULL_UP : + val =readl (pctl->membase +sunxi_pull_reg (g->pin)); + mask = ((1 <<PULL_PINS_BITS ) -1 ) <<sunxi_pull_offset (g->pin);
Same. #define a MASK.
drivers/pinctrl/pinctrl-sunxi.c line 281
Quoted 7 lines
drivers/pinctrl/pinctrl-sunxi.c new file +7
-0+ val &= ~mask; + val |=1 <<sunxi_pull_offset (g->pin); +writel (val, pctl->membase +sunxi_pull_reg (g->pin)); +break ; +case PIN_CONFIG_BIAS_PULL_DOWN : + val =readl (pctl->membase +sunxi_pull_reg (g->pin)); + mask = ((1 <<PULL_PINS_BITS ) -1 ) <<sunxi_pull_offset (g->pin);
Dito.
Quoted 13 lines
drivers/pinctrl/pinctrl-sunxi.c new file +13
-0+ val &= ~mask; + val |=2 <<sunxi_pull_offset (g->pin); +writel (val, pctl->membase +sunxi_pull_reg (g->pin)); +break ; +default : +break ; + } + +/* cache the config value */ + g->config = config; + +return 0 ; +}
(...)
drivers/pinctrl/pinctrl-sunxi.c line 336
Quoted 8 lines
drivers/pinctrl/pinctrl-sunxi.c new file +8
-0+static void sunxi_pmx_set (struct pinctrl_dev *pctldev, +unsigned pin, +u8 config) +{ +struct sunxi_pinctrl *pctl =pinctrl_dev_get_drvdata (pctldev); + +u32 val =readl (pctl->membase +sunxi_mux_reg (pin)); +u32 mask = ((1 <<MUX_PINS_BITS ) -1 ) <<sunxi_mux_offset (pin);
Dito.
Quoted 3 lines
drivers/pinctrl/pinctrl-sunxi.c new file +3
-0+writel ((val & ~mask) | config <<sunxi_mux_offset (pin), + pctl->membase +sunxi_mux_reg (pin)); +}
(...)
drivers/pinctrl/pinctrl-sunxi.c line 376
Quoted 3 lines
drivers/pinctrl/pinctrl-sunxi.c new file +3
-0+static struct of_device_id sunxi_pinctrl_match[]__devinitconst = { + {} +};
What is this supposed to match?
Maybe I don't understand DT boilerplate at all times, bear with me.
Quoted 1 line
+MODULE_DEVICE_TABLE(of,
sunxi_pinctrl_match);
(...)
drivers/pinctrl/pinctrl-sunxi.c line 380
Quoted 2 lines
drivers/pinctrl/pinctrl-sunxi.c new file +2
-0+static int __devinit sunxi_pinctrl_add_function (struct sunxi_pinctrl *pctl, +const char *name)
__devinit is deleted in the kernel so I would get a regression if I tried to apply this patch. Just remove __devinit.
(...)
Quoted 1 line
+static int
__devinitsunxi_pinctrl_build_state(struct platform_device *pdev)
Dito.
(...)
Quoted 1 line
+static int
__devinitsunxi_pinctrl_probe(struct platform_device *pdev)
Dito.
(...)
Quoted 1 line
+++
b/drivers/pinctrl/pinctrl-sunxi.h
(...)
Quoted 9 lines
+/*
+ * The sunXi PIO registers are organized as is:
+ *0x00-0x0cMuxing values.
+ * 8 pins per register, each pin having a 4bits value
+ *0x10Pin values
+ * 32 bits per register, each pin corresponding to one bit
+ *0x14-0x18Drive level
+ * 16 pins per register, each pin having a 2bits value
+ *0x1c-0x20Pull-Up values
Quoted 8 lines
+ * 16 pins per register, each pin having a 2bits value
+ *
+ * This is for the first bank. Each bank will have the same layout,
+ * with an offset being a multiple of0x24.
+ *
+ * The following functions calculate from the pin number the register
+ * and the bit offset that we should access.
+ */
Very nice with this documentation!
Yours,
Linus Walleij
PATCH v3 3/7 ARM: pinctrl: sunxi: Add the pinctrl pin set for sun5i
In reply to Maxime RipardSince the Allwinner SoCs variants don't have the same set of pins to handle, we need to declare the pin ranges available.
--- drivers/pinctrl/pinctrl-sunxi.c | 253 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 253 insertions(+)
drivers/pinctrl/pinctrl-sunxi.c +253 -0
@@ -26,6 +26,258 @@#include "core.h" #include "pinctrl-sunxi.h" +static const struct sunxi_desc_pin sun5i_a13_pins[] = { +/* Hole */ +SUNXI_PIN (SUNXI_PINCTRL_PIN_PB0 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PB1 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PB2 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PB3 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PB4 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +/* Hole */ +SUNXI_PIN (SUNXI_PINCTRL_PIN_PB10 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +/* Hole */ +SUNXI_PIN (SUNXI_PINCTRL_PIN_PB15 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PB16 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PB17 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PB18 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +/* Hole */ +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC0 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC1 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC2 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC3 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC4 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC5 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC6 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC7 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC8 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC9 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC10 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC11 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC12 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC13 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC14 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC15 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +/* Hole */ +SUNXI_PIN (SUNXI_PINCTRL_PIN_PC19 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +/* Hole */ +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD2 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD3 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD4 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD5 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD6 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD7 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +/* Hole */ +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD10 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD11 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD12 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD13 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD14 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD15 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +/* Hole */ +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD18 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD19 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD20 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD21 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD22 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD23 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD24 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD25 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD26 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PD27 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +/* Hole */ +SUNXI_PIN (SUNXI_PINCTRL_PIN_PE0 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PE1 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PE2 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PE3 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PE4 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PE5 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PE6 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PE7 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PE8 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PE9 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PE10 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" ), +SUNXI_FUNCTION (0x4 ,"uart1" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PE11 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" ), +SUNXI_FUNCTION (0x4 ,"uart1" )), +/* Hole */ +SUNXI_PIN (SUNXI_PINCTRL_PIN_PF0 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PF1 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PF2 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PF3 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PF4 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PF5 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +/* Hole */ +SUNXI_PIN (SUNXI_PINCTRL_PIN_PG0 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PG1 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PG2 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PG3 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" ), +SUNXI_FUNCTION (0x4 ,"uart1" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PG4 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" ), +SUNXI_FUNCTION (0x4 ,"uart1" )), +/* Hole */ +SUNXI_PIN (SUNXI_PINCTRL_PIN_PG9 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PG10 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PG11 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +SUNXI_PIN (SUNXI_PINCTRL_PIN_PG12 , +SUNXI_FUNCTION (0x0 ,"gpio_in" ), +SUNXI_FUNCTION (0x1 ,"gpio_out" )), +}; + +static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { + .pins = sun5i_a13_pins, + .npins =ARRAY_SIZE (sun5i_a13_pins), +}; +static struct sunxi_pinctrl_group *sunxi_pinctrl_find_group_by_name (struct sunxi_pinctrl *pctl,const char *group) {
@@ -372,6 +624,7 @@ static struct pinctrl_desc sunxi_pctrl_desc = { };static struct of_device_id sunxi_pinctrl_match[]__devinitconst = { + { .compatible ="allwinner,sun5i-a13-pinctrl" , .data = (void *)&sun5i_a13_pinctrl_data }, {} };MODULE_DEVICE_TABLE (of, sunxi_pinctrl_match);
Signature · 1 line
1.7.10.4
Re: [PATCH 3/7] ARM: pinctrl: sunxi: Add the pinctrl pin set for sun5i
Quoted 4 lines · Maxime Ripard
Since the Allwinner SoCs variants don't have the same set of pins to handle, we need to declare the pin ranges available.
Signed-off-by Maxime Ripard <[email protected]>
(...)
Quoted 1 line
static struct
of_device_idsunxi_pinctrl_match[]__devinitconst= {
I think __devinitconst is also deprecated.
Quoted 4 lines
+ { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
{}};
MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
Aha so the match table is in the subdrivers, hm.... OK.
Yours,
Linus Walleij
PATCH v3 4/7 ARM: sunxi: Add pinctrl node to the device tree
In reply to Maxime Ripard--- arch/arm/boot/dts/sun5i-a13.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm/boot/dts/sun5i-a13.dtsi +9 -0
@@ -17,4 +17,13 @@ memory { reg = <0x40000000 0x20000000>; }; + + soc { + pinctrl at 01c20800 { + compatible = "allwinner,sun5i-a13-pinctrl"; + reg = <0x01c20800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; };
Signature · 1 line
1.7.10.4
PATCH v3 5/7 ARM: sunxi: Add uart1 pinctrl groups
In reply to Maxime Ripard--- arch/arm/boot/dts/sun5i-a13.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/sun5i-a13.dtsi +14 -0
@@ -24,6 +24,20 @@ reg = <0x01c20800 0x400>; #address-cells = <1>; #size-cells = <0>; + + uart1_pins_a: uart1 at 0 { + allwinner,pins = "PE10", "PE11"; + allwinner,function = "uart1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart1_pins_b: uart1 at 1 { + allwinner,pins = "PG3", "PG4"; + allwinner,function = "uart1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; }; };
Signature · 1 line
1.7.10.4
PATCH v3 6/7 tty: of_serial: Add pinctrl support
In reply to Maxime RipardUse pinctrl to configure the SoCs pins directly from the driver.
--- drivers/tty/serial/of_serial.c | 7 +++++++ 1 file changed, 7 insertions(+)
drivers/tty/serial/of_serial.c +7 -0
@@ -13,6 +13,7 @@#include <linux/module.h> #include <linux/slab.h> #include <linux/delay.h> +#include <linux/pinctrl/consumer.h> #include <linux/serial_core.h> #include <linux/serial_8250.h> #include <linux/serial_reg.h>
@@ -57,6 +58,7 @@ static int of_platform_serial_setup(struct platform_device *ofdev, struct of_serial_info *info) {struct resource resource; +struct pinctrl *pinctrl;struct device_node *np = ofdev->dev.of_node;u32 clk, spd, prop;int ret;
@@ -85,6 +87,11 @@ static int of_platform_serial_setup(struct platform_device *ofdev, goto out; } + pinctrl =devm_pinctrl_get_select_default (&ofdev->dev); +if (IS_ERR (pinctrl)) +dev_warn (&ofdev->dev, +"pins are not configured from the driver\n" ); +spin_lock_init (&port->lock); port->mapbase = resource.start;
Signature · 1 line
1.7.10.4
PATCH v3 7/7 ARM: sunxi: olinuxino: Add muxing for the uart
In reply to Maxime Ripard--- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/boot/dts/sun5i-a13-olinuxino.dts +2 -0
@@ -24,6 +24,8 @@ soc { uart1: uart at 01c28400 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; status = "okay"; }; };
Signature · 1 line
1.7.10.4
v3 cover Add pinctrl driver for Allwinner A1X SoCs
In reply to Maxime RipardHi Linus,
Quoted 10 lines · Maxime Ripard
Hi everyone,
This patch set adds a pinctrl driver for the IP found in the Allwinner A10 and A13, and the SoC-specific bits for the A13. It also adds the documentation for the device tree bindings.
This patch set has been tested on a Olimex A13-Olinuxino.
Thanks,
Maxime
Are you ok with this version or do you have additionnal comments ?
Thanks,
Maxime
Signature · 4 lines
Maxime Ripard, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
v3 cover Add pinctrl driver for Allwinner A1X SoCs
Quoted 7 lines · Maxime Ripard
Quoted 6 lines · Maxime Ripard
Hi everyone,
This patch set adds a pinctrl driver for the IP found in the Allwinner A10 and A13, and the SoC-specific bits for the A13. It also adds the documentation for the device tree bindings.
Quoted 6 lines
Quoted 4 lines
This patch set has been tested on a Olimex A13-Olinuxino.
Thanks,
MaximeAre you ok with this version or do you have additionnal comments ?
I'm probably OK with it, I've only just now reached this point in my mail backlog.
Yours,
Linus Walleij
v3 cover Add pinctrl driver for Allwinner A1X SoCs
Quoted 6 lines · Linus Walleij
On Tue, Jan 15, 2013 at 11:19 AM, Maxime Ripard
Quoted 1 line
Are you ok with this version or do you have additionnal comments ?
I'm probably OK with it, I've only just now reached this point in my mail backlog.
As noted I had more comments, they should be quick to address.
When finished, shall this be applied to the pinctrl tree or some other subtree, like ARM SoC?
In that case I should probably remove the patch adding the drive strength parameter from my tree so tell me how to proceed...
Yours,
Linus Walleij
v3 cover Add pinctrl driver for Allwinner A1X SoCs
Hi Linus,
Thanks for your review.
Quoted 5 lines · Linus Walleij
Quoted 4 lines · Linus Walleij
On Tue, Jan 15, 2013 at 11:19 AM, Maxime Ripard
Quoted 1 line
Are you ok with this version or do you have additionnal comments ?
Quoted 7 lines
Quoted 2 lines
I'm probably OK with it, I've only just now reached this point in my mail backlog.
As noted I had more comments, they should be quick to address.
When finished, shall this be applied to the pinctrl tree or some other subtree, like ARM SoC?
Maybe the easiest thing to do would be to push the pinctrl driver in itself through your tree, and the dt additions through the arm-soc one?
Signature · 4 lines
Maxime Ripard, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
v3 cover Add pinctrl driver for Allwinner A1X SoCs
Quoted 13 lines · Maxime Ripard
Hi Linus,
Thanks for your review.
Quoted 8 lines · Linus Walleij
Quoted 6 lines · Linus Walleij
On Tue, Jan 15, 2013 at 11:19 AM, Maxime Ripard
Quoted 1 line
Are you ok with this version or do you have additionnal comments ?
I'm probably OK with it, I've only just now reached this point in my mail backlog.
Quoted 7 lines
Quoted 4 lines
As noted I had more comments, they should be quick to address.
When finished, shall this be applied to the pinctrl tree or some other subtree, like ARM SoC?
Maybe the easiest thing to do would be to push the pinctrl driver in itself through your tree, and the dt additions through the arm-soc one?
As long as things work without the DT pieces, that's a good way to do it for new code (conversion of existing platforms gets more complicated most of the time).
-Olof