Renesas ARM-based SoC for v3.9

---
 arch/arm/mach-shmobile/setup-r8a7740.c |    1 -
 1 file changed, 1 deletion(-)

arch/arm/mach-shmobile/setup-r8a7740.c +0 -1

index 03c69f9..9ef397d 100644
@@ -27,7 +27,6 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
-#include <linux/dma-mapping.h>
 #include <mach/dma-register.h>
 #include <mach/r8a7740.h>
 #include <mach/pm-rmobile.h>

Signature · 1 line

1.7.10.4

Sachin Kamat

2013-01-25 02:55 UTC #2 lore raw

PATCH 1/15 ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in setup-r8a7740.c

Hi Simon,

You seem to have changed the authorship of this patch.

Original one at:
https://patchwork.kernel.org/patch/1771091/

Regards
Sachin

Quoted 23 lines · Simon Horman

linux/dma-mapping.h was included twice.
Signed-off-by Sachin Kamat <[email protected]>
Signed-off-by Simon Horman <[email protected]>
---
 arch/arm/mach-shmobile/setup-r8a7740.c |    1 -
 1 file changed, 1 deletion(-)
arch/arm/mach-shmobile/setup-r8a7740.c +0 -2
index 03c69f9..9ef397d 100644
@@ -27,7 +27,6 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
-#include <linux/dma-mapping.h>
 #include <mach/dma-register.h>
 #include <mach/r8a7740.h>
 #include <mach/pm-rmobile.h>
--
1.7.10.4

Simon Horman

2013-01-25 03:38 UTC #3 lore raw

PATCH 1/15 ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in setup-r8a7740.c

Quoted 3 lines · Sachin Kamat

Hi Simon,
You seem to have changed the authorship of this patch.

Sorry about that, I'll fix that up.

Quoted 35 lines

Original one at:
https://patchwork.kernel.org/patch/1771091/
Regards
Sachin
Quoted 21 lines · Simon Horman
linux/dma-mapping.h was included twice.
Signed-off-by Sachin Kamat <[email protected]>
Signed-off-by Simon Horman <[email protected]>
---
 arch/arm/mach-shmobile/setup-r8a7740.c |    1 -
 1 file changed, 1 deletion(-)
arch/arm/mach-shmobile/setup-r8a7740.c +0 -2
index 03c69f9..9ef397d 100644
@@ -27,7 +27,6 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
-#include <linux/dma-mapping.h>
 #include <mach/dma-register.h>
 #include <mach/r8a7740.h>
 #include <mach/pm-rmobile.h>
--
Quoted 2 lines
1.7.10.4
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Sachin Kamat

2013-01-25 03:44 UTC #4 lore raw

PATCH 1/15 ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in setup-r8a7740.c

Quoted 6 lines · Simon Horman

Quoted 3 lines · Sachin Kamat
Hi Simon,
You seem to have changed the authorship of this patch.
Sorry about that, I'll fix that up.

Thanks Simon :)

Quoted 15 lines

Quoted 15 lines
Original one at:
https://patchwork.kernel.org/patch/1771091/
Regards
Sachin
Quoted 7 lines · Simon Horman
linux/dma-mapping.h was included twice.
Signed-off-by Sachin Kamat <[email protected]>
Signed-off-by Simon Horman <[email protected]>
---
 arch/arm/mach-shmobile/setup-r8a7740.c |    1 -
 1 file changed, 1 deletion(-)

Signature · 2 lines

With warm regards,
Sachin

Simon Horman

author

2013-01-25 02:13 UTC #5 lore raw

PATCH 2/15 ARM: shmobile: r8a7740: add TMU timer support

From: Kuninori Morimoto <[email protected]>

This patch enabled TMU0 timer on r8a7740.
But TMU1 timer is not supported yet

Signed-off-by Kuninori Morimoto <[email protected]>

---
 arch/arm/mach-shmobile/clock-r8a7740.c |    6 +-
 arch/arm/mach-shmobile/setup-r8a7740.c |   94 ++++++++++++++++++++++++++++++++
 2 files changed, 99 insertions(+), 1 deletion(-)

arch/arm/mach-shmobile/clock-r8a7740.c +5 -1

index eac49d5..19ce885 100644
@@ -581,10 +581,14 @@ static struct clk_lookup lookups[] = {
 
 	/* MSTP32 clocks */
 	CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0",	&mstp_clks[MSTP100]),
-	CLKDEV_DEV_ID("sh_tmu.1",		&mstp_clks[MSTP111]),
+	CLKDEV_DEV_ID("sh_tmu.3",		&mstp_clks[MSTP111]),
+	CLKDEV_DEV_ID("sh_tmu.4",		&mstp_clks[MSTP111]),
+	CLKDEV_DEV_ID("sh_tmu.5",		&mstp_clks[MSTP111]),
 	CLKDEV_DEV_ID("i2c-sh_mobile.0",	&mstp_clks[MSTP116]),
 	CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",	&mstp_clks[MSTP117]),
 	CLKDEV_DEV_ID("sh_tmu.0",		&mstp_clks[MSTP125]),
+	CLKDEV_DEV_ID("sh_tmu.1",		&mstp_clks[MSTP125]),
+	CLKDEV_DEV_ID("sh_tmu.2",		&mstp_clks[MSTP125]),
 	CLKDEV_DEV_ID("sh_mobile_ceu.0",	&mstp_clks[MSTP127]),
 	CLKDEV_DEV_ID("sh_mobile_ceu.1",	&mstp_clks[MSTP128]),

arch/arm/mach-shmobile/setup-r8a7740.c +94 -0

106 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Simon Horman

author

2013-01-25 02:13 UTC #6 lore raw

PATCH 3/15 ARM: shmobile: sh73a0: fixup div4_clks bitmap

From: Kuninori Morimoto <[email protected]>

div4_clks's bitmap of sh73a0 was wrong.
This patch is based on v2.0 datasheet.

Signed-off-by Kuninori Morimoto <[email protected]>

---
 arch/arm/mach-shmobile/clock-sh73a0.c |   22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

arch/arm/mach-shmobile/clock-sh73a0.c +11 ~~-11~~

index 516ff7f..5f57701 100644
@@ -264,17 +264,17 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 	SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
 
 static struct clk div4_clks[DIV4_NR] = {
-	[DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
-	[DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
-	[DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
-	[DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
-	[DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
-	[DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
-	[DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
-	[DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
-	[DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
-	[DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
-	[DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
+	[DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
+	[DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
+	[DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
+	[DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
+	[DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
+	[DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
+	[DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
+	[DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
+	[DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
+	[DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
+	[DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
 };
 
 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,

Signature · 1 line

1.7.10.4

Simon Horman

author

2013-01-25 02:13 UTC #7 lore raw

PATCH 4/15 ARM: mach-shmobile: sh73a0 external IRQ wake update

From: Magnus Damm <[email protected]>

Use sh73a0_set_wake() for external IRQ signals on sh73a0.

The sh73a0 IRQ hardware for external IRQ pins consists of the INTCA interrupt controller and the GIC together doing their best to limp along. These external IRQ pins are treated as a special case where interrupts need to be managed in both interrupt controllers in parallel.

The ->irq_set_wake() callback for the external IRQ pins can be dealt with in the same way as INTCA-only without involving the GIC. So this patch updates the external IRQ pin code for sh73a0 to no longer involve the GIC.

Signed-off-by Magnus Damm <[email protected]>

---
 arch/arm/mach-shmobile/intc-sh73a0.c |    7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

arch/arm/mach-shmobile/intc-sh73a0.c +1 -6

index 9783699..45973b5 100644
@@ -315,11 +315,6 @@ static int intca_gic_set_type(struct irq_data *data, unsigned int type)
 	return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
 }
 
-static int intca_gic_set_wake(struct irq_data *data, unsigned int on)
-{
-	return irq_cbp(irq_set_wake, to_intca_reloc_irq(data), on);
-}
-
 #ifdef CONFIG_SMP
 static int intca_gic_set_affinity(struct irq_data *data,
 				  const struct cpumask *cpumask,

@@ -339,7 +334,7 @@ struct irq_chip intca_gic_irq_chip = {
 	.irq_disable		= intca_gic_disable,
 	.irq_shutdown		= intca_gic_disable,
 	.irq_set_type		= intca_gic_set_type,
-	.irq_set_wake		= intca_gic_set_wake,
+	.irq_set_wake		= sh73a0_set_wake,
 #ifdef CONFIG_SMP
 	.irq_set_affinity	= intca_gic_set_affinity,
 #endif

Signature · 1 line

1.7.10.4

Simon Horman

author

2013-01-25 02:13 UTC #8 lore raw

PATCH 5/15 ARM: sh7372: add clock lookup entries for DT-based devices

From: Guennadi Liakhovetski <[email protected]>

When booting with DT, devices are named differently. To get their clocks additional entries have to be added to the lookup table.

Signed-off-by Guennadi Liakhovetski <[email protected]>

---
 arch/arm/mach-shmobile/clock-sh7372.c |    9 +++++++++
 1 file changed, 9 insertions(+)

arch/arm/mach-shmobile/clock-sh7372.c +9 -0

index 3ca6757b..45d21fe 100644
@@ -544,6 +544,7 @@ static struct clk_lookup lookups[] = {
 
 	/* MSTP32 clocks */
 	CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
+	CLKDEV_DEV_ID("fff30000.i2c", &mstp_clks[MSTP001]), /* IIC2 */
 	CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
 	CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
 	CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */

@@ -556,6 +557,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
 	CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
 	CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
+	CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), /* IIC0 */
 	CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */
 	CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
 	CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */

@@ -577,18 +579,25 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
 	CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
 	CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
+	CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), /* IIC1 */
 	CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
 	CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
 	CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
 	CLKDEV_DEV_ID("sh_flctl.0", &mstp_clks[MSTP315]), /* FLCTL */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+	CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+	CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
 	CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
+	CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMC */
 	CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
+	CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), /* SDHI2 */
 	CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
 	CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
+	CLKDEV_DEV_ID("e6d20000.i2c", &mstp_clks[MSTP411]), /* IIC3 */
 	CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
+	CLKDEV_DEV_ID("e6d30000.i2c", &mstp_clks[MSTP410]), /* IIC4 */
 	CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */
 	CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
 	CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */

Signature · 1 line

1.7.10.4

Simon Horman

author

2013-01-25 02:13 UTC #9 lore raw

PATCH 6/15 ARM: sh7372: fix cache clean / invalidate order

From: Guennadi Liakhovetski <[email protected]>

According to the Cortex A8 TRM the L2 cache should be first cleaned and then disabled. Fix the swapped order on sh7372.

Signed-off-by Guennadi Liakhovetski <[email protected]>

Reviewed-by Santosh Shilimkar <[email protected]>

---
 arch/arm/mach-shmobile/sleep-sh7372.S |   12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

arch/arm/mach-shmobile/sleep-sh7372.S +7 -5

index 1d56467..a9df53b 100644
@@ -59,17 +59,19 @@ sh7372_do_idle_sysc:
 	mcr	p15, 0, r0, c1, c0, 0
 	isb
 
+	/*
+	 * Clean and invalidate data cache again.
+	 */
+	ldr	r1, kernel_flush
+	blx	r1
+
 	/* disable L2 cache in the aux control register */
 	mrc     p15, 0, r10, c1, c0, 1
 	bic     r10, r10, #2
 	mcr     p15, 0, r10, c1, c0, 1
+	isb
 
 	/*
-	 * Invalidate data cache again.
-	 */
-	ldr	r1, kernel_flush
-	blx	r1
-	/*
 	 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
 	 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
 	 * This sequence switches back to ARM.  Note that .align may insert a

Signature · 1 line

1.7.10.4

Simon Horman

author

2013-01-25 02:13 UTC #10 lore raw

PATCH 7/15 ARM: shmobile: add function declarations for sh7372 DT helper functions

From: Guennadi Liakhovetski <[email protected]>

sh7372_add_early_devices_dt() and sh7372_add_standard_devices_dt() are defined as global functions in arch/arm/mach-shmobile/setup-sh7372.c, but their declarations are missing. Add them to common.h, where similar functions for this and other SoC types are already declared.

Signed-off-by Guennadi Liakhovetski <[email protected]>

---
 arch/arm/mach-shmobile/include/mach/common.h |    2 ++
 1 file changed, 2 insertions(+)

arch/arm/mach-shmobile/include/mach/common.h +2 -0

index a57439e..2d1686b 100644
@@ -23,6 +23,8 @@ extern void sh7372_map_io(void);
 extern void sh7372_earlytimer_init(void);
 extern void sh7372_add_early_devices(void);
 extern void sh7372_add_standard_devices(void);
+extern void sh7372_add_early_devices_dt(void);
+extern void sh7372_add_standard_devices_dt(void);
 extern void sh7372_clock_init(void);
 extern void sh7372_pinmux_init(void);
 extern void sh7372_pm_init(void);

Signature · 1 line

1.7.10.4

Simon Horman

author

2013-01-25 02:13 UTC #11 lore raw

PATCH 8/15 ARM: shmobile: sh73a0: Add CPU sleep suspend

From: Bastian Hecht <[email protected]>

Add the lighest possible sleep mode on Cortex-A9 cores: CPU sleep. It is entered by a simple dsb and wfi instruction via cpu_do_idle(). As just clocks are stopped there is no need to save or restore any state of the system.

Acked-by Magnus Damm <[email protected]>

---
 arch/arm/mach-shmobile/Makefile              |    1 +
 arch/arm/mach-shmobile/board-kzm9g.c         |    2 ++
 arch/arm/mach-shmobile/include/mach/common.h |    1 +
 arch/arm/mach-shmobile/pm-sh73a0.c           |   32 ++++++++++++++++++++++++++
 4 files changed, 36 insertions(+)
 create mode 100644 arch/arm/mach-shmobile/pm-sh73a0.c

arch/arm/mach-shmobile/Makefile +1 -0

index 0b71479..f6aba6d 100644
@@ -37,6 +37,7 @@ obj-$(CONFIG_ARCH_SHMOBILE)	+= pm-rmobile.o
 obj-$(CONFIG_ARCH_SH7372)	+= pm-sh7372.o sleep-sh7372.o
 obj-$(CONFIG_ARCH_R8A7740)	+= pm-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7779)	+= pm-r8a7779.o
+obj-$(CONFIG_ARCH_SH73A0)	+= pm-sh73a0.o
 
 # Board objects
 obj-$(CONFIG_MACH_AP4EVB)	+= board-ap4evb.o

arch/arm/mach-shmobile/board-kzm9g.c +2 -0

index ac94285..363c6ed 100644
@@ -772,6 +772,8 @@ static void __init kzm_init(void)
 
 	sh73a0_add_standard_devices();
 	platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices));
+
+	sh73a0_pm_init();
 }
 
 static void kzm9g_restart(char mode, const char *cmd)

arch/arm/mach-shmobile/include/mach/common.h +1 -0

index 2d1686b..f221c11 100644
@@ -40,6 +40,7 @@ extern void sh73a0_add_early_devices(void);
 extern void sh73a0_add_standard_devices(void);
 extern void sh73a0_clock_init(void);
 extern void sh73a0_pinmux_init(void);
+extern void sh73a0_pm_init(void);
 extern struct clk sh73a0_extal1_clk;
 extern struct clk sh73a0_extal2_clk;
 extern struct clk sh73a0_extcki_clk;

arch/arm/mach-shmobile/pm-sh73a0.c new file +32 -0

new file mode 100644
index 0000000..99086e9
@@ -0,0 +1,32 @@
+/*
+ * sh73a0 Power management support
+ *
+ *  Copyright (C) 2012 Bastian Hecht <[email protected]>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/suspend.h>
+#include <mach/common.h>
+
+#ifdef CONFIG_SUSPEND
+static int sh73a0_enter_suspend(suspend_state_t suspend_state)
+{
+	cpu_do_idle();
+	return 0;
+}
+
+static void sh73a0_suspend_init(void)
+{
+	shmobile_suspend_ops.enter = sh73a0_enter_suspend;
+}
+#else
+static void sh73a0_suspend_init(void) {}
+#endif
+
+void __init sh73a0_pm_init(void)
+{
+	sh73a0_suspend_init();
+}

Signature · 1 line

1.7.10.4

Simon Horman

author

2013-01-25 02:13 UTC #12 lore raw

PATCH 9/15 ARM: shmobile: r8a7740: Add CPU sleep suspend

From: Bastian Hecht <[email protected]>

Acked-by Magnus Damm <[email protected]>

[ horms at verge.net.au: Added missing includes ]

---
 arch/arm/mach-shmobile/board-armadillo800eva.c |    2 ++
 arch/arm/mach-shmobile/include/mach/common.h   |    1 +
 arch/arm/mach-shmobile/pm-r8a7740.c            |   22 ++++++++++++++++++++++
 3 files changed, 25 insertions(+)

arch/arm/mach-shmobile/board-armadillo800eva.c +2 -0

index e791244..6573137 100644
@@ -1181,6 +1181,8 @@ static void __init eva_init(void)
 	rmobile_add_device_to_domain("A4LC", &hdmi_lcdc_device);
 	if (usb)
 		rmobile_add_device_to_domain("A3SP", usb);
+
+	r8a7740_pm_init();
 }
 
 static void __init eva_earlytimer_init(void)

arch/arm/mach-shmobile/include/mach/common.h +1 -0

index f221c11..c0ab595 100644
@@ -52,6 +52,7 @@ extern void r8a7740_add_early_devices(void);
 extern void r8a7740_add_standard_devices(void);
 extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
+extern void r8a7740_pm_init(void);
 
 extern void r8a7779_init_irq(void);
 extern void r8a7779_map_io(void);

arch/arm/mach-shmobile/pm-r8a7740.c +22 -0

index 21e5316d..40b87aa 100644
@@ -9,7 +9,9 @@
  * for more details.
  */
 #include <linux/console.h>
+#include <linux/suspend.h>
 #include <mach/pm-rmobile.h>
+#include <mach/common.h>
 
 #ifdef CONFIG_PM
 static int r8a7740_pd_a4s_suspend(void)

@@ -58,3 +60,23 @@ void __init r8a7740_init_pm_domains(void)
 }
 
 #endif /* CONFIG_PM */
+
+#ifdef CONFIG_SUSPEND
+static int r8a7740_enter_suspend(suspend_state_t suspend_state)
+{
+	cpu_do_idle();
+	return 0;
+}
+
+static void r8a7740_suspend_init(void)
+{
+	shmobile_suspend_ops.enter = r8a7740_enter_suspend;
+}
+#else
+static void r8a7740_suspend_init(void) {}
+#endif
+
+void __init r8a7740_pm_init(void)
+{
+	r8a7740_suspend_init();
+}

Signature · 1 line

1.7.10.4

Simon Horman

author

2013-01-25 02:13 UTC #13 lore raw

PATCH 10/15 ARM: SH-Mobile: sh73a0: Secondary CPUs handle own SCU flags

From: Bastian Hecht <[email protected]>

When booting secondary CPUs we have used the main CPU to set up the Snoop Control Unit flags of these CPUs. It is a cleaner approach if every CPU takes care of its own flags. We avoid the need for locking and the program logic is more concise. With this patch the file headsmp-sh73a0.S is added that contains a startup vector for secondary CPUs that sets up its own SCU flags.
Further in sh73a0_smp_prepare_cpus() we can rely on the generic ARM helper scu_power_mode(). This is possible as we don't cross borders anymore (every CPU handles its own flags) and need no locking. So we can throw out the needless function modify_scu_cpu_psr().

---
 arch/arm/mach-shmobile/Makefile              |    2 +-
 arch/arm/mach-shmobile/headsmp-sh73a0.S      |   50 ++++++++++++++++++++++++++
 arch/arm/mach-shmobile/include/mach/common.h |    1 +
 arch/arm/mach-shmobile/smp-sh73a0.c          |   30 +++-------------
 4 files changed, 56 insertions(+), 27 deletions(-)
 create mode 100644 arch/arm/mach-shmobile/headsmp-sh73a0.S

arch/arm/mach-shmobile/Makefile +1 -1

index f6aba6d..700e662 100644
@@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.o clock-emev2.o
 # SMP objects
 smp-y				:= platsmp.o headsmp.o
 smp-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
-smp-$(CONFIG_ARCH_SH73A0)	+= smp-sh73a0.o
+smp-$(CONFIG_ARCH_SH73A0)	+= smp-sh73a0.o headsmp-sh73a0.o
 smp-$(CONFIG_ARCH_R8A7779)	+= smp-r8a7779.o
 smp-$(CONFIG_ARCH_EMEV2)	+= smp-emev2.o

arch/arm/mach-shmobile/headsmp-sh73a0.S new file +50 -0

50 lines not on this page · raw message

arch/arm/mach-shmobile/include/mach/common.h +1 -0

index c0ab595..4b1af93 100644
@@ -41,6 +41,7 @@ extern void sh73a0_add_standard_devices(void);
 extern void sh73a0_clock_init(void);
 extern void sh73a0_pinmux_init(void);
 extern void sh73a0_pm_init(void);
+extern void sh73a0_secondary_vector(void);
 extern struct clk sh73a0_extal1_clk;
 extern struct clk sh73a0_extal2_clk;
 extern struct clk sh73a0_extcki_clk;

arch/arm/mach-shmobile/smp-sh73a0.c +4 ~~-26~~

index 5c5bcb5..430b44e 100644
@@ -41,9 +41,6 @@ static void __iomem *scu_base_addr(void)
 	return (void __iomem *)0xf0000000;
 }
 
-static DEFINE_SPINLOCK(scu_lock);
-static unsigned long tmp;
-
 #ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
 void __init sh73a0_register_twd(void)

@@ -52,20 +49,6 @@ void __init sh73a0_register_twd(void)
 }
 #endif
 
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-	void __iomem *scu_base = scu_base_addr();
-
-	spin_lock(&scu_lock);
-	tmp = __raw_readl(scu_base + 8);
-	tmp &= ~clr;
-	tmp |= set;
-	spin_unlock(&scu_lock);
-
-	/* disable cache coherency after releasing the lock */
-	__raw_writel(tmp, scu_base + 8);
-}
-
 static unsigned int __init sh73a0_get_core_count(void)
 {
 	void __iomem *scu_base = scu_base_addr();

@@ -82,9 +65,6 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
 {
 	cpu = cpu_logical_map(cpu);
 
-	/* enable cache coherency */
-	modify_scu_cpu_psr(0, 3 << (cpu * 8));
-
 	if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
 		__raw_writel(1 << cpu, WUPCR);	/* wake up */
 	else

@@ -95,16 +75,14 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
 
 static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
 {
-	int cpu = cpu_logical_map(0);
-
 	scu_enable(scu_base_addr());
 
-	/* Map the reset vector (in headsmp.S) */
+	/* Map the reset vector (in headsmp-sh73a0.S) */
 	__raw_writel(0, APARMBAREA);      /* 4k */
-	__raw_writel(__pa(shmobile_secondary_vector), SBAR);
+	__raw_writel(__pa(sh73a0_secondary_vector), SBAR);
 
-	/* enable cache coherency on CPU0 */
-	modify_scu_cpu_psr(0, 3 << (cpu * 8));
+	/* enable cache coherency on booting CPU */
+	scu_power_mode(scu_base_addr(), SCU_PM_NORMAL);
 }
 
 static void __init sh73a0_smp_init_cpus(void)

Signature · 1 line

1.7.10.4

Simon Horman

author

2013-01-25 02:13 UTC #14 lore raw

PATCH 11/15 ARM: SH-Mobile: sh73a0: Add CPU Hotplug

From: Bastian Hecht <[email protected]>

Add the capability to add and remove CPUs on the fly.
The Cortex-A9 offers the possibility to take single cores out of the MP Core. We add this capabilty taking care that caches are kept coherent. For verifying the shutdown we rely on the internal SH73A0 Power Status Register PSTR.

---
 arch/arm/mach-shmobile/smp-sh73a0.c |   36 +++++++++++++++++++++++++++++------
 1 file changed, 30 insertions(+), 6 deletions(-)

arch/arm/mach-shmobile/smp-sh73a0.c +30 -6

index 430b44e..9812ea3 100644
@@ -25,6 +25,7 @@
 #include <linux/delay.h>
 #include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
+#include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <mach/sh73a0.h>
 #include <asm/smp_scu.h>

@@ -36,6 +37,8 @@
 #define SBAR		IOMEM(0xe6180020)
 #define APARMBAREA	IOMEM(0xe6f10020)
 
+#define PSTR_SHUTDOWN_MODE	3
+
 static void __iomem *scu_base_addr(void)
 {
 	return (void __iomem *)0xf0000000;

@@ -92,16 +95,20 @@ static void __init sh73a0_smp_init_cpus(void)
 	shmobile_smp_init_cpus(ncores);
 }
 
-static int __maybe_unused sh73a0_cpu_kill(unsigned int cpu)
+#ifdef CONFIG_HOTPLUG_CPU
+static int sh73a0_cpu_kill(unsigned int cpu)
 {
+
 	int k;
+	u32 pstr;
 
-	/* this function is running on another CPU than the offline target,
-	 * here we need wait for shutdown code in platform_cpu_die() to
-	 * finish before asking SoC-specific code to power off the CPU core.
+	/*
+	 * wait until the power status register confirms the shutdown of the
+	 * offline target
 	 */
 	for (k = 0; k < 1000; k++) {
-		if (shmobile_cpu_is_dead(cpu))
+		pstr = (__raw_readl(PSTR) >> (4 * cpu)) & 3;
+		if (pstr == PSTR_SHUTDOWN_MODE)
 			return 1;
 
 		mdelay(1);

@@ -110,6 +117,23 @@ static int __maybe_unused sh73a0_cpu_kill(unsigned int cpu)
 	return 0;
 }
 
+static void sh73a0_cpu_die(unsigned int cpu)
+{
+	/*
+	 * The ARM MPcore does not issue a cache coherency request for the L1
+	 * cache when powering off single CPUs. We must take care of this and
+	 * further caches.
+	 */
+	dsb();
+	flush_cache_all();
+
+	/* Set power off mode. This takes the CPU out of the MP cluster */
+	scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF);
+
+	/* Enter shutdown mode */
+	cpu_do_idle();
+}
+#endif /* CONFIG_HOTPLUG_CPU */
 
 struct smp_operations sh73a0_smp_ops __initdata = {
 	.smp_init_cpus		= sh73a0_smp_init_cpus,

@@ -118,7 +142,7 @@ struct smp_operations sh73a0_smp_ops __initdata = {
 	.smp_boot_secondary	= sh73a0_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_kill		= sh73a0_cpu_kill,
-	.cpu_die		= shmobile_cpu_die,
+	.cpu_die		= sh73a0_cpu_die,
 	.cpu_disable		= shmobile_cpu_disable,
 #endif
 };

Signature · 1 line

1.7.10.4

Simon Horman

author

2013-01-25 02:13 UTC #15 lore raw

PATCH 12/15 ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT

This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob.

It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers.

This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers.

Includes update to use irqchip_init() by Thierry Reding

Cc Thierry Reding <[email protected]>

---
 arch/arm/boot/dts/sh73a0.dtsi                |   33 ++++++++++++++++++++++++++
 arch/arm/mach-shmobile/include/mach/common.h |    1 +
 arch/arm/mach-shmobile/intc-sh73a0.c         |    9 +++++++
 3 files changed, 43 insertions(+)
 create mode 100644 arch/arm/boot/dts/sh73a0.dtsi

arch/arm/boot/dts/sh73a0.dtsi new file +33 -0

new file mode 100644
index 0000000..7dae1f4
@@ -0,0 +1,33 @@
+/*
+ * Device Tree Source for the SH73A0 SoC
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "renesas,sh73a0";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,cortex-a9";
+		};
+		cpu at 1 {
+			compatible = "arm,cortex-a9";
+		};
+	};
+
+	gic: interrupt-controller at f0001000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+		interrupt-controller;
+		reg = <0xf0001000 0x1000>,
+		      <0xf0000100 0x100>;
+	};
+};

arch/arm/mach-shmobile/include/mach/common.h +1 -0

index 4b1af93..e2ba16b 100644
@@ -34,6 +34,7 @@ extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
 
 extern void sh73a0_init_irq(void);
+extern void sh73a0_init_irq_dt(void);
 extern void sh73a0_map_io(void);
 extern void sh73a0_earlytimer_init(void);
 extern void sh73a0_add_early_devices(void);

arch/arm/mach-shmobile/intc-sh73a0.c +9 -0

index 45973b5..91faba6 100644
@@ -23,6 +23,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/sh_intc.h>
+#include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
 #include <mach/intc.h>
 #include <mach/irqs.h>

@@ -459,3 +460,11 @@ void __init sh73a0_init_irq(void)
 	sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
 	setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
 }
+
+#ifdef CONFIG_OF
+void __init sh73a0_init_irq_dt(void)
+{
+	irqchip_init();
+	gic_arch_extn.irq_set_wake = sh73a0_set_wake;
+}
+#endif

Signature · 1 line

1.7.10.4

Mark Rutland

2013-01-25 10:08 UTC #16 lore raw

PATCH 12/15 ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT

Quoted 42 lines · Simon Horman

This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob.
It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers.
This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers.
Includes update to use irqchip_init() by Thierry Reding
Cc Thierry Reding <[email protected]>
Signed-off-by Simon Horman <[email protected]>
---
 arch/arm/boot/dts/sh73a0.dtsi                |   33 ++++++++++++++++++++++++++
 arch/arm/mach-shmobile/include/mach/common.h |    1 +
 arch/arm/mach-shmobile/intc-sh73a0.c         |    9 +++++++
 3 files changed, 43 insertions(+)
 create mode 100644 arch/arm/boot/dts/sh73a0.dtsi
arch/arm/boot/dts/sh73a0.dtsi new file +13 -0
new file mode 100644
index 0000000..7dae1f4
@@ -0,0 +1,33 @@
+/*
+ * Device Tree Source for the SH73A0 SoC
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {

arch/arm/boot/dts/sh73a0.dtsi line 23

Quoted 10 lines

arch/arm/boot/dts/sh73a0.dtsi new file +10 -0

+	compatible = "renesas,sh73a0";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,cortex-a9";
+		};
+		cpu at 1 {
+			compatible = "arm,cortex-a9";
+		};
+	};

It would be good the have reg and device_type properties set for the cpu nodes, so they're guaranteed to work with the logical map.

[...]

Thanks,
Mark.

Simon Horman

author

2013-01-25 02:13 UTC #17 lore raw

PATCH 13/15 ARM: mach-shmobile: sh73a0: Minimal setup using DT

Allow a minimal setup of the sh73a0 SoC using a flattened device tree. In particular, Configure the i2c controllers using a flattened device tree.

SCI serial controller and CMT clock source, whose drivers do not yet support configuration using a flattened device tree, are still configured using C code in order to allow booting of a board with this SoC.

*** Please note that the clock initialisation scheme used in
this patch does not currently work with SMP as there is a yet to be resolved lock-up in workqueue initialisation.

CONFIG_SMP must be disabled when using this code. ***

Includes update from Thierry Reding to no longer use gic_handle_irq()

Cc Thierry Reding <[email protected]>

fix

---
 arch/arm/boot/dts/sh73a0.dtsi                |   60 +++++++++++++++++++++++++
 arch/arm/mach-shmobile/clock-sh73a0.c        |   12 +++++
 arch/arm/mach-shmobile/include/mach/common.h |    2 +
 arch/arm/mach-shmobile/setup-sh73a0.c        |   62 +++++++++++++++++++++++++-
 4 files changed, 135 insertions(+), 1 deletion(-)

arch/arm/boot/dts/sh73a0.dtsi +60 -0

index 7dae1f4..721f486 100644
@@ -30,4 +30,64 @@
 		reg = <0xf0001000 0x1000>,
 		      <0xf0000100 0x100>;
 	};
+
+	i2c0: i2c at 0xe6820000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0xe6820000 0x425>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 167 0x4
+			      0 168 0x4
+			      0 169 0x4
+			      0 170 0x4>;
+	};
+
+	i2c1: i2c at 0xe6822000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0xe6822000 0x425>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 51 0x4
+			      0 52 0x4
+			      0 53 0x4
+			      0 54 0x4>;
+	};
+
+	i2c2: i2c at 0xe6824000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0xe6824000 0x425>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 171 0x4
+			      0 172 0x4
+			      0 173 0x4
+			      0 174 0x4>;
+	};
+
+	i2c3: i2c at 0xe6826000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0xe6826000 0x425>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 183 0x4
+			      0 184 0x4
+			      0 185 0x4
+			      0 186 0x4>;
+	};
+
+	i2c4: i2c at 0xe6828000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0xe6828000 0x425>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 187 0x4
+			      0 188 0x4
+			      0 189 0x4
+			      0 190 0x4>;
+	};
 };

arch/arm/mach-shmobile/clock-sh73a0.c +12 -0

index 5f57701..eab2667 100644
@@ -525,6 +525,13 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
 };
 
+/* The lookups structure below includes duplicate entries for some clocks
+ * with alternate names.
+ * - The traditional name used when a device is initialised with platform data
+ * - The name used when a device is initialised using device tree
+ * The longer-term aim is to remove these duplicates, and indeed the
+ * lookups table entirely, by describing clocks using device tree.
+ */
 static struct clk_lookup lookups[] = {
 	/* main clocks */
 	CLKDEV_CON_ID("r_clk", &r_clk),

@@ -545,6 +552,7 @@ static struct clk_lookup lookups[] = {
 
 	/* MSTP32 clocks */
 	CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
+	CLKDEV_DEV_ID("e6824000.i2c", &mstp_clks[MSTP001]), /* I2C2 */
 	CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
 	CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
 	CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */

@@ -553,6 +561,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
 	CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
 	CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
+	CLKDEV_DEV_ID("e6820000.i2c", &mstp_clks[MSTP116]), /* I2C0 */
 	CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
 	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
 	CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */

@@ -569,6 +578,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
 	CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
 	CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
+	CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
 	CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */

@@ -579,7 +589,9 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
 	CLKDEV_DEV_ID("leds-renesas-tpu.41", &mstp_clks[MSTP300]), /* TPU4 */
 	CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
+	CLKDEV_DEV_ID("e6826000.i2c", &mstp_clks[MSTP411]), /* I2C3 */
 	CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
+	CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */
 	CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
 };

arch/arm/mach-shmobile/include/mach/common.h +2 -0

index e2ba16b..64c0622 100644
@@ -38,7 +38,9 @@ extern void sh73a0_init_irq_dt(void);
 extern void sh73a0_map_io(void);
 extern void sh73a0_earlytimer_init(void);
 extern void sh73a0_add_early_devices(void);
+extern void sh73a0_add_early_devices_dt(void);
 extern void sh73a0_add_standard_devices(void);
+extern void sh73a0_add_standard_devices_dt(void);
 extern void sh73a0_clock_init(void);
 extern void sh73a0_pinmux_init(void);
 extern void sh73a0_pm_init(void);

arch/arm/mach-shmobile/setup-sh73a0.c +61 -1

95 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Simon Horman

author

2013-01-25 02:13 UTC #18 lore raw

PATCH 14/15 ARM: mach-shmobile: sh73a0: Initialise MMCIF using DT

This device also requires a voltage regulator which should be defined in a board-specific maner. An example dts snipped follows.

/ {
	fixedregulator1v8: fixedregulator at 0 {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};
};

&mmcif {
	vmmc-supply = <&fixedregulator1v8>;
	vqmmc-supply = <&fixedregulator1v8>;
};

---
 arch/arm/boot/dts/sh73a0-reference.dtsi |   24 ++++++++++++++++++++++++
 arch/arm/mach-shmobile/clock-sh73a0.c   |    1 +
 2 files changed, 25 insertions(+)
 create mode 100644 arch/arm/boot/dts/sh73a0-reference.dtsi

arch/arm/boot/dts/sh73a0-reference.dtsi new file +24 -0

new file mode 100644
index 0000000..d4bb012
@@ -0,0 +1,24 @@
+/*
+ * Device Tree Source for the SH73A0 SoC
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "sh73a0.dtsi"
+
+/ {
+	compatible = "renesas,sh73a0";
+
+	mmcif: mmcif at 0x10010000 {
+		compatible = "renesas,sh-mmcif";
+		reg = <0xe6bd0000 0x100>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 140 0x4
+			      0 141 0x4>;
+		reg-io-width = <4>;
+	};
+};

arch/arm/mach-shmobile/clock-sh73a0.c +1 -0

index eab2667..afa5423 100644
@@ -583,6 +583,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
 	CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
+	CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
 	CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
 	CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */

Signature · 1 line

1.7.10.4

Simon Horman

author

2013-01-25 02:13 UTC #19 lore raw

PATCH 15/15 ARM: shmobile: r8a7779: scif .irqs used SCIx_IRQ_MUXED()

From: Kuninori Morimoto <[email protected]>

This patch tidyup scif .irqs settings by using
SCIx_IRQ_MUXED() macro.

Signed-off-by Kuninori Morimoto <[email protected]>

---
 arch/arm/mach-shmobile/setup-r8a7779.c |   18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

arch/arm/mach-shmobile/setup-r8a7779.c +6 ~~-12~~

index a181ced..7e87ab3 100644
@@ -66,8 +66,7 @@ static struct plat_sci_port scif0_platform_data = {
 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 	.scbrr_algo_id	= SCBRR_ALGO_2,
 	.type		= PORT_SCIF,
-	.irqs		= { gic_spi(88), gic_spi(88),
-			    gic_spi(88), gic_spi(88) },
+	.irqs		= SCIx_IRQ_MUXED(gic_spi(88)),
 };
 
 static struct platform_device scif0_device = {

@@ -84,8 +83,7 @@ static struct plat_sci_port scif1_platform_data = {
 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 	.scbrr_algo_id	= SCBRR_ALGO_2,
 	.type		= PORT_SCIF,
-	.irqs		= { gic_spi(89), gic_spi(89),
-			    gic_spi(89), gic_spi(89) },
+	.irqs		= SCIx_IRQ_MUXED(gic_spi(89)),
 };
 
 static struct platform_device scif1_device = {

@@ -102,8 +100,7 @@ static struct plat_sci_port scif2_platform_data = {
 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 	.scbrr_algo_id	= SCBRR_ALGO_2,
 	.type		= PORT_SCIF,
-	.irqs		= { gic_spi(90), gic_spi(90),
-			    gic_spi(90), gic_spi(90) },
+	.irqs		= SCIx_IRQ_MUXED(gic_spi(90)),
 };
 
 static struct platform_device scif2_device = {

@@ -120,8 +117,7 @@ static struct plat_sci_port scif3_platform_data = {
 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 	.scbrr_algo_id	= SCBRR_ALGO_2,
 	.type		= PORT_SCIF,
-	.irqs		= { gic_spi(91), gic_spi(91),
-			    gic_spi(91), gic_spi(91) },
+	.irqs		= SCIx_IRQ_MUXED(gic_spi(91)),
 };
 
 static struct platform_device scif3_device = {

@@ -138,8 +134,7 @@ static struct plat_sci_port scif4_platform_data = {
 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 	.scbrr_algo_id	= SCBRR_ALGO_2,
 	.type		= PORT_SCIF,
-	.irqs		= { gic_spi(92), gic_spi(92),
-			    gic_spi(92), gic_spi(92) },
+	.irqs		= SCIx_IRQ_MUXED(gic_spi(92)),
 };
 
 static struct platform_device scif4_device = {

@@ -156,8 +151,7 @@ static struct plat_sci_port scif5_platform_data = {
 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 	.scbrr_algo_id	= SCBRR_ALGO_2,
 	.type		= PORT_SCIF,
-	.irqs		= { gic_spi(93), gic_spi(93),
-			    gic_spi(93), gic_spi(93) },
+	.irqs		= SCIx_IRQ_MUXED(gic_spi(93)),
 };
 
 static struct platform_device scif5_device = {

Signature · 1 line

1.7.10.4

Simon Horman

2013-01-25 03:43 UTC #20 lore raw