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Enabling socfpga on hardware

PATCH Superseded dinguyen at altera.com 8 participants 33 messages Jan 25, 2013 – Jan 29, 2013

Subsystems (8)
Device tree bindings Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape +4 more subsystems

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dinguyen at altera.com

author
#0 lore raw

cover Enabling socfpga on hardware

From: Dinh Nguyen <[email protected]>

Hi,

Up until this point, support for socfpga has only been for a virtual target environment. Here are a set of patches that enables socfpga on actual hardware.

patch: arm: Add v7_invalidate_l1 to cache-v7.S should be of some interest. When enabling SMP on ARMv7 hardware on socfpga, the call to v7_flush_dcache_all was making the main CPU lost. On socfpga, as well as IMX, SHMOBILE, and TEGRA the call to v7_invalidate_l1 was required.

Thanks,
Dinh

Dinh Nguyen (5):
arm: socfpga: Add new device tree source for actual socfpga HW
arm: socfpga: Add clock entries to socfpga.dtsi
arm: socfpga: Add entries to enable make dtbs socfpga
arm: Add v7_invalidate_l1 to cache-v7.S
arm: socfpga: Add SMP support for actual socfpga harware

 arch/arm/boot/dts/Makefile             |    2 ++
 arch/arm/boot/dts/socfpga.dtsi         |   59 ++++++++++++++++++++++++-------
 arch/arm/boot/dts/socfpga_cyclone5.dts |   28 ++++++++++++++-
 arch/arm/boot/dts/socfpga_vt.dts       |   60 ++++++++++++++++++++++++++++++++
 arch/arm/configs/socfpga_defconfig     |    1 +
 arch/arm/mach-imx/headsmp.S            |   47 -------------------------
 arch/arm/mach-shmobile/headsmp.S       |   48 -------------------------
 arch/arm/mach-socfpga/core.h           |    4 ++-
 arch/arm/mach-socfpga/headsmp.S        |   14 +++++---
 arch/arm/mach-socfpga/platsmp.c        |    3 +-
 arch/arm/mach-socfpga/socfpga.c        |   17 +++++++++
 arch/arm/mach-tegra/headsmp.S          |   43 -----------------------
 arch/arm/mm/cache-v7.S                 |   47 +++++++++++++++++++++++++
 13 files changed, 216 insertions(+), 157 deletions(-)
 create mode 100644 arch/arm/boot/dts/socfpga_vt.dts
Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH 1/5 arm: socfpga: Add new device tree source for actual socfpga HW

From: Dinh Nguyen <[email protected]>

Up to this point, support for socfpga has only been on a virtual platform. Now that actual hardware is available, we add the appropriate device tree source files.

Signed-off-by Dinh Nguyen <[email protected]>
Cc Russell King <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Pavel Machek <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi         |   22 ++++++------
 arch/arm/boot/dts/socfpga_cyclone5.dts |   28 ++++++++++++++-
 arch/arm/boot/dts/socfpga_vt.dts       |   60 ++++++++++++++++++++++++++++++++
 arch/arm/mach-socfpga/socfpga.c        |    1 +
 4 files changed, 98 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/boot/dts/socfpga_vt.dts
arch/arm/boot/dts/socfpga.dtsi +10 -12
index 19aec42..936d230 100644
@@ -25,6 +25,10 @@
 		ethernet0 = &gmac0;
 		serial0 = &uart0;
 		serial1 = &uart1;
+		timer0 = &timer0;
+		timer1 = &timer1;
+		timer2 = &timer2;
+		timer3 = &timer3;
 	};
 
 	cpus {

@@ -98,47 +102,41 @@
 			interrupts = <1 13 0xf04>;
 		};
 
-		timer0: timer at ffc08000 {
+		timer0: timer0 at ffc08000 {
 			compatible = "snps,dw-apb-timer-sp";
 			interrupts = <0 167 4>;
-			clock-frequency = <200000000>;
 			reg = <0xffc08000 0x1000>;
 		};
 
-		timer1: timer at ffc09000 {
+		timer1: timer1 at ffc09000 {
 			compatible = "snps,dw-apb-timer-sp";
 			interrupts = <0 168 4>;
-			clock-frequency = <200000000>;
 			reg = <0xffc09000 0x1000>;
 		};
 
-		timer2: timer at ffd00000 {
+		timer2: timer2 at ffd00000 {
 			compatible = "snps,dw-apb-timer-osc";
 			interrupts = <0 169 4>;
-			clock-frequency = <200000000>;
 			reg = <0xffd00000 0x1000>;
 		};
 
-		timer3: timer at ffd01000 {
+		timer3: timer3 at ffd01000 {
 			compatible = "snps,dw-apb-timer-osc";
 			interrupts = <0 170 4>;
-			clock-frequency = <200000000>;
 			reg = <0xffd01000 0x1000>;
 		};
 
-		uart0: uart at ffc02000 {
+		uart0: serial0 at ffc02000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0xffc02000 0x1000>;
-			clock-frequency = <7372800>;
 			interrupts = <0 162 4>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 		};
 
-		uart1: uart at ffc03000 {
+		uart1: serial1 at ffc03000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0xffc03000 0x1000>;
-			clock-frequency = <7372800>;
 			interrupts = <0 163 4>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
arch/arm/boot/dts/socfpga_cyclone5.dts +27 -1
index ab7e4a9..1a6d088 100644
@@ -29,6 +29,32 @@
 	memory {
 		name = "memory";
 		device_type = "memory";
-		reg = <0x0 0x10000000>; /* 256MB */
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	soc {
+		timer0 at ffc08000 {
+			clock-frequency = <100000000>;
+		};
+
+		timer1 at ffc09000 {
+			clock-frequency = <100000000>;
+		};
+
+		timer2 at ffd00000 {
+			clock-frequency = <25000000>;
+		};
+
+		timer3 at ffd01000 {
+			clock-frequency = <25000000>;
+		};
+
+		serial0 at ffc02000 {
+			clock-frequency = <100000000>;
+		};
+
+		serial1 at ffc03000 {
+			clock-frequency = <100000000>;
+		};
 	};
 };
arch/arm/boot/dts/socfpga_vt.dts new file +60 -0

60 lines not on this page · raw message

arch/arm/mach-socfpga/socfpga.c +1 -0
index 6732924..198f491 100644
@@ -99,6 +99,7 @@ static void __init socfpga_cyclone5_init(void)
 static const char *altera_dt_match[] = {
 	"altr,socfpga",
 	"altr,socfpga-cyclone5",
+	"altr,socfpga-vt",
 	NULL
 };
Signature · 1 line
1.7.9.5
#2 lore raw

PATCH 1/5 arm: socfpga: Add new device tree source for actual socfpga HW

Hi!

Quoted 5 lines

From: Dinh Nguyen <[email protected]>

Up to this point, support for socfpga has only been on a virtual platform. Now that actual hardware is available, we add the appropriate device tree source files.

Wow, actual hardware :-). Can I get one?

Quoted 5 lines
Signed-off-by Dinh Nguyen <[email protected]>
Cc Russell King <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Pavel Machek <[email protected]>

I tested it on 3.7-rc2-based tree, as it is newest I have around. It seems to work ok. [Do you have newer git tree somewhere?]

Tested-by Pavel Machek <[email protected]>
Reviewed-by Pavel Machek <[email protected]>

Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#3 lore raw

PATCH 1/5 arm: socfpga: Add new device tree source for actual socfpga HW

Hi Pavel,

Quoted 9 lines · Pavel Machek

Hi!

Quoted 5 lines

From: Dinh Nguyen <[email protected]>

Up to this point, support for socfpga has only been on a virtual platform. Now that actual hardware is available, we add the appropriate device tree source files.

Wow, actual hardware :-). Can I get one?

Ramping up production now...

Quoted 7 lines
Quoted 6 lines
Signed-off-by Dinh Nguyen <[email protected]>
Cc Russell King <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Pavel Machek <[email protected]>
Quoted 5 lines

I tested it on 3.7-rc2-based tree, as it is newest I have around. It seems to work ok. [Do you have newer git tree somewhere?]

Tested-by Pavel Machek <[email protected]>
Reviewed-by Pavel Machek <[email protected]>

Thanks,
Dinh

Quoted 3 lines

Pavel

#4 lore raw

PATCH 1/5 arm: socfpga: Add new device tree source for actual socfpga HW

In reply to dinguyen at altera.com

Hi,

Nit below.

Quoted 30 lines · dinguyen at altera.com
arch/arm/boot/dts/socfpga_vt.dts new file +24 -0
new file mode 100644
index 0000000..df3551f
@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/include/ "socfpga.dtsi"
+
+/ {
+	model = "Altera SOCFPGA VT";
+	compatible = "altr,socfpga-vt";
+

[...]

arch/arm/mach-socfpga/socfpga.c static void __init socfpga_cyclone5_init(void) · line 104

Quoted 11 lines
arch/arm/mach-socfpga/socfpga.c +1 -0
index 6732924..198f491 100644
@@ -99,6 +99,7 @@ static void __init socfpga_cyclone5_init(void)
 static const char *altera_dt_match[] = {
 	"altr,socfpga",
 	"altr,socfpga-cyclone5",
+	"altr,socfpga-vt",
 	NULL
 };

If you add "altr,socfpga" as a second compatible field in the dts for the board, then you won't have to update the board C file every time you add a new board dts (as long as you don't need to do something special with that board).

-Olof

author
#5 lore raw

PATCH 2/5 arm: socfpga: Add clock entries to socfpga.dtsi

In reply to dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

Signed-off-by Dinh Nguyen <[email protected]>
Cc Russell King <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Pavel Machek <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi |   37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
arch/arm/boot/dts/socfpga.dtsi +37 -0
index 936d230..688729f 100644
@@ -78,6 +78,43 @@
 			};
 		};
 
+		clkmgr at ffd04000 {
+			compatible = "altr, clk-mgr";
+			reg = <0xffd04000 0x1000>;
+
+			clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				osc1: oscillator {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+					clock-frequency = <50000000>;
+				};
+
+				mainpll: mainpll {
+					#clock-cells = <0>;
+					compatible = "altr,main-pll-clock";
+					clocks = <&osc1>;
+					reg = <0x40>;
+				};
+
+				perpll: perpll {
+					#clock-cells = <0>;
+					compatible = "altr,per-pll-clock";
+					clocks = <&osc1>;
+					reg = <0x80>;
+				};
+
+				sdrampll: sdrampll {
+					#clock-cells = <0>;
+					compatible = "altr,sdram-pll-clock";
+					clocks = <&osc1>;
+					reg = <0xC0>;
+				};
+			};
+		};
+
 		gmac0: stmmac at ff700000 {
 			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 			reg = <0xff700000 0x2000>;
Signature · 1 line
1.7.9.5
#6 lore raw

PATCH 2/5 arm: socfpga: Add clock entries to socfpga.dtsi

Hi,

Quoted 16 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

Signed-off-by Dinh Nguyen <[email protected]>
Cc Russell King <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Pavel Machek <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi |   37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
arch/arm/boot/dts/socfpga.dtsi +0 -0
index 936d230..688729f 100644

arch/arm/boot/dts/socfpga.dtsi line 82

Quoted 5 lines
arch/arm/boot/dts/socfpga.dtsi +2 -0
@@ -78,6 +78,43 @@
 			};
 		};
 
+		clkmgr at ffd04000 {
+			compatible = "altr, clk-mgr";

No space after "altr,". Also, this should have documented bindings under Documentation/device-tree/bindings (and those should be cc:d to the appropriate maintainers).

-Olof

#7 lore raw

PATCH 2/5 arm: socfpga: Add clock entries to socfpga.dtsi

Hi!

Quoted 20 lines · dinguyen at altera.com
Quoted 19 lines

From: Dinh Nguyen <[email protected]>

Signed-off-by Dinh Nguyen <[email protected]>
Cc Russell King <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Pavel Machek <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi |   37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
arch/arm/boot/dts/socfpga.dtsi +0 -0
index 936d230..688729f 100644
@@ -78,6 +78,43 @@
 			};
 		};
Quoted 7 lines

arch/arm/boot/dts/socfpga.dtsi line 82

Quoted 2 lines
arch/arm/boot/dts/socfpga.dtsi +2 -0
+		clkmgr at ffd04000 {
+			compatible = "altr, clk-mgr";

No space after "altr,". Also, this should have documented bindings under Documentation/device-tree/bindings (and those should be cc:d to the appropriate maintainers).

Are the clk-mgr entries used in this series? I see only definition in device tree, but no usage... Thanks,
Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#8 lore raw

PATCH 3/5 arm: socfpga: Add entries to enable make dtbs socfpga

In reply to dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

Signed-off-by Dinh Nguyen <[email protected]>
Cc Russell King <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Pavel Machek <[email protected]>
---
 arch/arm/boot/dts/Makefile |    2 ++
 1 file changed, 2 insertions(+)
arch/arm/boot/dts/Makefile +2 -0
index 5ebb44f..1b8276c 100644
@@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
 	r8a7740-armadillo800eva.dtb \
 	sh73a0-kzm9g.dtb \
 	sh7372-mackerel.dtb
+dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
+	socfpga_vt.dtb
 dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
 	spear1340-evb.dtb
 dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
Signature · 1 line
1.7.9.5
#9 lore raw

PATCH 3/5 arm: socfpga: Add entries to enable make dtbs socfpga

arch/arm/boot/dts/Makefile dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ · line 131

Quoted 12 lines
arch/arm/boot/dts/Makefile +2 -0
@@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
 	r8a7740-armadillo800eva.dtb \
 	sh73a0-kzm9g.dtb \
 	sh7372-mackerel.dtb
+dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
+	socfpga_vt.dtb
 dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
 	spear1340-evb.dtb
 dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \

This allows me to remove manual dtb invocation from the build scripts. Good.

For 2,3/5:

Tested-by Pavel Machek <[email protected]>
Reviewed-by Pavel Machek <[email protected]>

Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#10 lore raw

PATCH 3/5 arm: socfpga: Add entries to enable make dtbs socfpga

Hi Pavel,

Quoted 15 lines · Pavel Machek

arch/arm/boot/dts/Makefile dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ · line 131

Quoted 11 lines
arch/arm/boot/dts/Makefile +2 -0
@@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
 	r8a7740-armadillo800eva.dtb \
 	sh73a0-kzm9g.dtb \
 	sh7372-mackerel.dtb
+dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
+	socfpga_vt.dtb
 dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
 	spear1340-evb.dtb
 dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \

This allows me to remove manual dtb invocation from the build scripts. Good.

Quoted 4 lines

For 2,3/5:

Tested-by Pavel Machek <[email protected]>
Reviewed-by Pavel Machek <[email protected]>

Thanks,
Dinh

Quoted 2 lines

Pavel

author
#11 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

In reply to dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

Signed-off-by Dinh Nguyen <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Russell King <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
Cc Sascha Hauer <[email protected]>
Cc Simon Horman <[email protected]>
Cc Magnus Damm <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Pavel Machek <[email protected]>
---
 arch/arm/mach-imx/headsmp.S      |   47 -------------------------------------
 arch/arm/mach-shmobile/headsmp.S |   48 --------------------------------------
 arch/arm/mach-tegra/headsmp.S    |   43 ----------------------------------
 arch/arm/mm/cache-v7.S           |   47 +++++++++++++++++++++++++++++++++++++
 4 files changed, 47 insertions(+), 138 deletions(-)
arch/arm/mach-imx/headsmp.S +0 -47
index 7e49deb..921fc15 100644
@@ -17,53 +17,6 @@
 
 	.section ".text.head", "ax"
 
-/*
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor.  We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- *
- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
- * to be called for both secondary cores startup and primary core resume
- * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
- */
-ENTRY(v7_invalidate_l1)
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache
-	mcr	p15, 2, r0, c0, c0, 0
-	mrc	p15, 1, r0, c0, c0, 0
-
-	ldr	r1, =0x7fff
-	and	r2, r1, r0, lsr #13
-
-	ldr	r1, =0x3ff
-
-	and	r3, r1, r0, lsr #3	@ NumWays - 1
-	add	r2, r2, #1		@ NumSets
-
-	and	r0, r0, #0x7
-	add	r0, r0, #4	@ SetShift
-
-	clz	r1, r3		@ WayShift
-	add	r4, r3, #1	@ NumWays
-1:	sub	r2, r2, #1	@ NumSets--
-	mov	r3, r4		@ Temp = NumWays
-2:	subs	r3, r3, #1	@ Temp--
-	mov	r5, r3, lsl r1
-	mov	r6, r2, lsl r0
-	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-	mcr	p15, 0, r5, c7, c6, 2
-	bgt	2b
-	cmp	r2, #0
-	bgt	1b
-	dsb
-	isb
-	mov	pc, lr
-ENDPROC(v7_invalidate_l1)
-
 #ifdef CONFIG_SMP
 ENTRY(v7_secondary_startup)
 	bl	v7_invalidate_l1
arch/arm/mach-shmobile/headsmp.S +0 -48

54 lines not on this page · raw message

arch/arm/mach-tegra/headsmp.S +0 -43

49 lines not on this page · raw message

arch/arm/mm/cache-v7.S +47 -0

53 lines not on this page · raw message

Signature · 1 line
1.7.9.5
#12 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

Quoted 6 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

Quoted 11 lines
Signed-off-by Dinh Nguyen <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Russell King <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
Cc Sascha Hauer <[email protected]>
Cc Simon Horman <[email protected]>
Cc Magnus Damm <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Pavel Machek <[email protected]>

mach-shmobile portion:

Acked-by Simon Horman <[email protected]>
#13 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

Quoted 19 lines · Simon Horman
Quoted 6 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

Quoted 11 lines
Signed-off-by Dinh Nguyen <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Russell King <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
Cc Sascha Hauer <[email protected]>
Cc Simon Horman <[email protected]>
Cc Magnus Damm <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Pavel Machek <[email protected]>
Quoted 3 lines

mach-shmobile portion:

Acked-by Simon Horman <[email protected]>

For the record, I tested this on the kzm9g, kzm9d and marzen boards.

author
#14 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

Hi Simon,

Quoted 20 lines · Simon Horman
Quoted 19 lines · Simon Horman
Quoted 17 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

Signed-off-by Dinh Nguyen <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Russell King <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
Cc Sascha Hauer <[email protected]>
Cc Simon Horman <[email protected]>
Cc Magnus Damm <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Pavel Machek <[email protected]>
Quoted 5 lines
Quoted 3 lines

mach-shmobile portion:

Acked-by Simon Horman <[email protected]>

For the record, I tested this on the kzm9g, kzm9d and marzen boards.

Thanks,
Dinh

Quoted 1 line
#15 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

In reply to dinguyen at altera.com

arch/arm/mach-tegra/headsmp.S

Quoted 10 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

arch/arm/mach-tegra/headsmp.S +0 -2
 
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0

Unfortunately, there's a patch in the Tegra tree for 3.9 that moves that function from headsmp.S to reset-handler.S, so this patch will conflict. How do you want to handle that?

#16 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

Quoted 7 lines · Stephen Warren
Quoted 5 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

Quoted 8 lines

arch/arm/mach-tegra/headsmp.S

Quoted 4 lines
arch/arm/mach-tegra/headsmp.S +0 -2
 
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0

Unfortunately, there's a patch in the Tegra tree for 3.9 that moves that function from headsmp.S to reset-handler.S, so this patch will conflict. How do you want to handle that?

Drop the patch from Tegra tree and merge this one there? Having three copies of code is not nice to start with, no matter where it is...
Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#17 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

Quoted 13 lines · Pavel Machek
Quoted 12 lines · Stephen Warren
Quoted 10 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

arch/arm/mach-tegra/headsmp.S +0 -2
 
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
Quoted 6 lines
Quoted 3 lines

Unfortunately, there's a patch in the Tegra tree for 3.9 that moves that function from headsmp.S to reset-handler.S, so this patch will conflict. How do you want to handle that?

Drop the patch from Tegra tree and merge this one there? Having three copies of code is not nice to start with, no matter where it is...

Well, I guess for other reasons rebasing the Tegra tree is useful for a few dependencies, so I'll drop that part of the patch which moves v7_invalidate_l1() from one file to another, so there shouldn't be any conflicts, and you can feel free to take this series through whatever tree you want.

I haven't tested this patch yet though, to see whether the slight differences in the code in your patch mentioned in the other sub-thread affect Tegra at all. Hopefully I can test this later today.

author
#18 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

Hi Stephen,

Quoted 27 lines · Stephen Warren
Quoted 13 lines · Pavel Machek
Quoted 12 lines · Stephen Warren
Quoted 10 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

arch/arm/mach-tegra/headsmp.S +0 -2
 
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
Quoted 6 lines
Quoted 3 lines

Unfortunately, there's a patch in the Tegra tree for 3.9 that moves that function from headsmp.S to reset-handler.S, so this patch will conflict. How do you want to handle that?

Drop the patch from Tegra tree and merge this one there? Having three copies of code is not nice to start with, no matter where it is...

Well, I guess for other reasons rebasing the Tegra tree is useful for a few dependencies, so I'll drop that part of the patch which moves v7_invalidate_l1() from one file to another, so there shouldn't be any conflicts, and you can feel free to take this series through whatever tree you want.

Quoted 3 lines

I haven't tested this patch yet though, to see whether the slight differences in the code in your patch mentioned in the other sub-thread affect Tegra at all. Hopefully I can test this later today.

Shawn Guo mentioned that the instruction to invalidate I-Cache is unnecessary becauce of this commit: 612539e (ARM: 7296/1: proc-v7.S:
remove HARVARD_CACHE preprocessor guards)

So I'll send v2 without the extra instruction.

Thanks,
Dinh

Quoted 1 line
#19 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

In reply to dinguyen at altera.com
Quoted 17 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

Signed-off-by Dinh Nguyen <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Russell King <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
Cc Sascha Hauer <[email protected]>
Cc Simon Horman <[email protected]>
Cc Magnus Damm <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Pavel Machek <[email protected]>
Quoted 7 lines
---
  arch/arm/mach-imx/headsmp.S      |   47 -------------------------------------
  arch/arm/mach-shmobile/headsmp.S |   48 --------------------------------------
  arch/arm/mach-tegra/headsmp.S    |   43 ----------------------------------
  arch/arm/mm/cache-v7.S           |   47 +++++++++++++++++++++++++++++++++++++
  4 files changed, 47 insertions(+), 138 deletions(-)

Does yor kernel skips the decompresser. Am just curious about what you describe above since you should see the issue already at decompresser. Your boot loader is expected to clean and invalidating the caches before jumping into the kernel.

Regards,
Santosh

author
#20 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

Hi Santosh,

Quoted 25 lines · Santosh Shilimkar
Quoted 17 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

Signed-off-by Dinh Nguyen <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Russell King <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
Cc Sascha Hauer <[email protected]>
Cc Simon Horman <[email protected]>
Cc Magnus Damm <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Pavel Machek <[email protected]>
Quoted 7 lines
---
  arch/arm/mach-imx/headsmp.S      |   47 -------------------------------------
  arch/arm/mach-shmobile/headsmp.S |   48 --------------------------------------
  arch/arm/mach-tegra/headsmp.S    |   43 ----------------------------------
  arch/arm/mm/cache-v7.S           |   47 +++++++++++++++++++++++++++++++++++++
  4 files changed, 47 insertions(+), 138 deletions(-)
Quoted 4 lines

Does yor kernel skips the decompresser. Am just curious about what you describe above since you should see the issue already at decompresser. Your boot loader is expected to clean and invalidating the caches before jumping into the kernel.

This is for bringing up the 2nd core after the main CPU is already alive. Indeed, I did see this issue when the main CPU was coming up and have changed the bootloader to clean and invalidate the caches.

Dinh

Quoted 5 lines

Regards,
Santosh

#21 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

Quoted 28 lines · Dinh Nguyen

Hi Santosh,

Quoted 25 lines · Santosh Shilimkar
Quoted 24 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

Signed-off-by Dinh Nguyen <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Russell King <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Rob Herring <[email protected]>
Cc Sascha Hauer <[email protected]>
Cc Simon Horman <[email protected]>
Cc Magnus Damm <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Pavel Machek <[email protected]>
---
   arch/arm/mach-imx/headsmp.S      |   47 -------------------------------------
   arch/arm/mach-shmobile/headsmp.S |   48 --------------------------------------
   arch/arm/mach-tegra/headsmp.S    |   43 ----------------------------------
   arch/arm/mm/cache-v7.S           |   47 +++++++++++++++++++++++++++++++++++++
   4 files changed, 47 insertions(+), 138 deletions(-)
Quoted 9 lines
Quoted 4 lines

Does yor kernel skips the decompresser. Am just curious about what you describe above since you should see the issue already at decompresser. Your boot loader is expected to clean and invalidating the caches before jumping into the kernel.

This is for bringing up the 2nd core after the main CPU is already alive. Indeed, I did see this issue when the main CPU was coming up and have changed the bootloader to clean and invalidate the caches.

Ahh. I understand it now.

Regards
Santosh

#22 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

In reply to dinguyen at altera.com

Hi!

Quoted 3 lines

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

If there are three copies of code, with fourth one needed for next platform, moving it into common code makes sense.

But... The code was not identical before the merge. Are you sure that the differences do not hurt? At the very least, it should be mentioned in the changelog.

Thanks,
Pavel

Quoted 10 lines
arch/arm/mach-imx/headsmp.S +0 -5
index 7e49deb..921fc15 100644
@@ -17,53 +17,6 @@
-ENTRY(v7_invalidate_l1)
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache
-	mcr	p15, 2, r0, c0, c0, 0
-	mrc	p15, 1, r0, c0, c0, 0

...

arch/arm/mach-tegra/headsmp.S line 21

Quoted 9 lines
arch/arm/mach-tegra/headsmp.S +0 -4
index 4a317fa..fb082c4 100644
@@ -18,49 +18,6 @@
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
-        mcr     p15, 2, r0, c0, c0, 0
-        mrc     p15, 1, r0, c0, c0, 0

[Note missing mcr p15, 0, .. line.]

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#23 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

Hi Pavel,

Quoted 6 lines · Pavel Machek

Hi!

Quoted 3 lines

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

Quoted 6 lines

If there are three copies of code, with fourth one needed for next platform, moving it into common code makes sense.

But... The code was not identical before the merge. Are you sure that the differences do not hurt? At the very least, it should be mentioned in the changelog.

Indeed, the addition of

mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache

was done by commit # 5b2acf384c8a8707d32a98106192ee7187e4446d

This adds invalidate I-Cache as well as D-Cache, which I think should be ok for most platforms.

Hopefully, Stephen can test and verify.

Dinh

Quoted 28 lines

Thanks,
Pavel

Quoted 10 lines
arch/arm/mach-imx/headsmp.S +0 -5
index 7e49deb..921fc15 100644
@@ -17,53 +17,6 @@
-ENTRY(v7_invalidate_l1)
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache
-	mcr	p15, 2, r0, c0, c0, 0
-	mrc	p15, 1, r0, c0, c0, 0

...

arch/arm/mach-tegra/headsmp.S line 21

Quoted 9 lines
arch/arm/mach-tegra/headsmp.S +0 -4
index 4a317fa..fb082c4 100644
@@ -18,49 +18,6 @@
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
-        mcr     p15, 2, r0, c0, c0, 0
-        mrc     p15, 1, r0, c0, c0, 0

[Note missing mcr p15, 0, .. line.]

#24 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

Quoted 17 lines · Dinh Nguyen

Hi Pavel,

Quoted 6 lines · Pavel Machek

Hi!

Quoted 3 lines

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

Quoted 6 lines

If there are three copies of code, with fourth one needed for next platform, moving it into common code makes sense.

But... The code was not identical before the merge. Are you sure that the differences do not hurt? At the very least, it should be mentioned in the changelog.

Indeed, the addition of

Quoted 8 lines

mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache

was done by commit # 5b2acf384c8a8707d32a98106192ee7187e4446d

This adds invalidate I-Cache as well as D-Cache, which I think should be ok for most platforms.

Hopefully, Stephen can test and verify.

Otherwise it works for me... and looks like a good idea.

Tested-by Pavel Machek <[email protected]>
Reviewed-by Pavel Machek <[email protected]>

Thanks,
Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#25 lore raw

PATCH 4/5 arm: Add v7_invalidate_l1 to cache-v7.S

In reply to Dinh Nguyen
Quoted 11 lines · Dinh Nguyen

Hi Pavel,

Quoted 9 lines · Pavel Machek

Hi!

Quoted 3 lines

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

If there are three copies of code, with fourth one needed for next platform, moving it into common code makes sense.

Quoted 8 lines
Quoted 3 lines

But... The code was not identical before the merge. Are you sure that the differences do not hurt? At the very least, it should be mentioned in the changelog.

Indeed, the addition of

mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache

This becomes unnecessary since commit 612539e (ARM: 7296/1: proc-v7.S:
remove HARVARD_CACHE preprocessor guards) gets in.

Shawn

Quoted 5 lines

was done by commit # 5b2acf384c8a8707d32a98106192ee7187e4446d

This adds invalidate I-Cache as well as D-Cache, which I think should be ok for most platforms.

author
#26 lore raw

PATCH 5/5 arm: socfpga: Add SMP support for actual socfpga harware

In reply to dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

Because the CPU1 start address is different for socfpga-vt and socfpga-cyclone5, we add code to use the correct CPU1 start addr.

Signed-off-by Dinh Nguyen <[email protected]>
Cc Russell King <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Pavel Machek <[email protected]>
---
 arch/arm/configs/socfpga_defconfig |    1 +
 arch/arm/mach-socfpga/core.h       |    4 +++-
 arch/arm/mach-socfpga/headsmp.S    |   14 ++++++++++----
 arch/arm/mach-socfpga/platsmp.c    |    3 ++-
 arch/arm/mach-socfpga/socfpga.c    |   16 ++++++++++++++++
 5 files changed, 32 insertions(+), 6 deletions(-)
arch/arm/configs/socfpga_defconfig +1 -0
index 4e1ce21..480ab64 100644
@@ -21,6 +21,7 @@ CONFIG_ARM_THUMBEE=y
 # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_VMSPLIT_2G=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_AEABI=y
arch/arm/mach-socfpga/core.h +3 -1
index 9941caa..5b76dd4 100644
@@ -20,7 +20,7 @@
 #ifndef __MACH_CORE_H
 #define __MACH_CORE_H
 
-extern void secondary_startup(void);
+extern void v7_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 
 extern void socfpga_init_clocks(void);

@@ -29,6 +29,8 @@ extern void socfpga_sysmgr_init(void);
 extern struct smp_operations socfpga_smp_ops;
 extern char secondary_trampoline, secondary_trampoline_end;
 
+extern unsigned long cpu1start_addr;
+
 #define SOCFPGA_SCU_VIRT_BASE   0xfffec000
 
 #endif
arch/arm/mach-socfpga/headsmp.S +10 -4
index f09b128..01911e8 100644
@@ -13,13 +13,19 @@
 	__CPUINIT
 	.arch	armv7-a
 
-#define CPU1_START_ADDR 	        0xffd08010
-
 ENTRY(secondary_trampoline)
-	movw	r0, #:lower16:CPU1_START_ADDR
-	movt  r0, #:upper16:CPU1_START_ADDR
+	movw	r2, #:lower16:cpu1start_addr
+	movt  r2, #:upper16:cpu1start_addr
 
+	ldr	r0, [r2]
 	ldr	r1, [r0]
 	bx	r1
 
 ENTRY(secondary_trampoline_end)
+
+#ifdef CONFIG_SMP
+ENTRY(v7_secondary_startup)
+       bl      v7_invalidate_l1
+       b       secondary_startup
+ENDPROC(v7_secondary_startup)
+#endif
arch/arm/mach-socfpga/platsmp.c +2 -1
index 68dd1b6..c428519 100644
@@ -49,7 +49,8 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct
 
 	memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
 
-	__raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
+	__raw_writel(virt_to_phys(v7_secondary_startup),
+		(sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
 
 	flush_cache_all();
 	smp_wmb();
arch/arm/mach-socfpga/socfpga.c +16 -0
index 198f491..317f4c3 100644
@@ -29,6 +29,7 @@
 void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
 void __iomem *sys_manager_base_addr;
 void __iomem *rst_manager_base_addr;
+unsigned long cpu1start_addr;
 
 static struct map_desc scu_io_desc __initdata = {
 	.virtual	= SOCFPGA_SCU_VIRT_BASE,

@@ -55,6 +56,16 @@ static void __init socfpga_scu_map_io(void)
 	iotable_init(&scu_io_desc, 1);
 }
 
+static void __init init_socfpga_vt(void)
+{
+	cpu1start_addr = 0xffd08010;
+}
+
+static void __init init_socfpga(void)
+{
+	cpu1start_addr = 0xffd080c4;
+}
+
 static void __init socfpga_map_io(void)
 {
 	socfpga_scu_map_io();

@@ -82,6 +93,11 @@ static void __init gic_init_irq(void)
 {
 	of_irq_init(irq_match);
 	socfpga_sysmgr_init();
+
+	if (of_machine_is_compatible("altr,socfpga-vt"))
+		init_socfpga_vt();
+	else
+		init_socfpga();
 }
 
 static void socfpga_cyclone5_restart(char mode, const char *cmd)
Signature · 1 line
1.7.9.5
#27 lore raw

PATCH 5/5 arm: socfpga: Add SMP support for actual socfpga harware

Hi!

Quoted 7 lines

From: Dinh Nguyen <[email protected]>

Because the CPU1 start address is different for socfpga-vt and socfpga-cyclone5, we add code to use the correct CPU1 start addr.

+++ b/arch/arm/configs/socfpga_defconfig

arch/arm/configs/socfpga_defconfig CONFIG_ARM_THUMBEE=y · line 27

Quoted 7 lines
arch/arm/configs/socfpga_defconfig +1 -0
@@ -21,6 +21,7 @@ CONFIG_ARM_THUMBEE=y
 # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_VMSPLIT_2G=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_AEABI=y

Is this related to CPU1 start address?

Quoted 15 lines

+++ b/arch/arm/mach-socfpga/headsmp.S

arch/arm/mach-socfpga/headsmp.S +3 -4
@@ -13,13 +13,19 @@
 	__CPUINIT
 	.arch	armv7-a
 
-#define CPU1_START_ADDR 	        0xffd08010
-
 ENTRY(secondary_trampoline)
-	movw	r0, #:lower16:CPU1_START_ADDR
-	movt  r0, #:upper16:CPU1_START_ADDR
+	movw	r2, #:lower16:cpu1start_addr
+	movt  r2, #:upper16:cpu1start_addr
 
+	ldr	r0, [r2]
 	ldr	r1, [r0]

arch/arm/mach-socfpga/headsmp.S line 31

Quoted 10 lines
arch/arm/mach-socfpga/headsmp.S +7 -0
 	bx	r1
 
 ENTRY(secondary_trampoline_end)
+
+#ifdef CONFIG_SMP
+ENTRY(v7_secondary_startup)
+       bl      v7_invalidate_l1
+       b       secondary_startup
+ENDPROC(v7_secondary_startup)
+#endif

#ifdef should not be neccessary, as headsmp.S is only compiled when CONFIG_SMP.

arch/arm/mach-socfpga/platsmp.c static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct · line 54

Quoted 9 lines

+++ b/arch/arm/mach-socfpga/platsmp.c

arch/arm/mach-socfpga/platsmp.c +2 -1
@@ -49,7 +49,8 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct
 
 	memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
 
-	__raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
+	__raw_writel(virt_to_phys(v7_secondary_startup),
+		(sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));

The math is rather interesting here; is (sys_manager_base_addr + (cpu1start_addr & 0x000000ff)) == cpu1start_addr ?

arch/arm/mach-socfpga/socfpga.c static void __init socfpga_scu_map_io(void) · line 67

Quoted 13 lines
arch/arm/mach-socfpga/socfpga.c +9 -0
@@ -55,6 +56,16 @@ static void __init socfpga_scu_map_io(void)
 	iotable_init(&scu_io_desc, 1);
 }
 
+static void __init init_socfpga_vt(void)
+{
+	cpu1start_addr = 0xffd08010;
+}
+
+static void __init init_socfpga(void)
+{
+	cpu1start_addr = 0xffd080c4;
+}

Should this be put into device tree somewhere?

In addition, this patch seems to break operation in the emulator for me. In fact, it looks pretty much like emulator crash, with continuous scroll of

B_TRANSPORT::(R(Addr=0x23092FD0, Count=08 ...

[sorry, it is hard to copy moving messages].

I'm using kernel based on 3.7-rc2. Should I attempt updating?

Thanks,
Pavel

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author
#28 lore raw

PATCH 5/5 arm: socfpga: Add SMP support for actual socfpga harware

Hi Pavel,

Quoted 8 lines · Pavel Machek

Hi!

Quoted 5 lines

From: Dinh Nguyen <[email protected]>

Because the CPU1 start address is different for socfpga-vt and socfpga-cyclone5, we add code to use the correct CPU1 start addr.

Quoted 11 lines

arch/arm/configs/socfpga_defconfig CONFIG_ARM_THUMBEE=y · line 27

Quoted 9 lines

+++ b/arch/arm/configs/socfpga_defconfig

arch/arm/configs/socfpga_defconfig +1 -0
@@ -21,6 +21,7 @@ CONFIG_ARM_THUMBEE=y
 # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_VMSPLIT_2G=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_AEABI=y

Is this related to CPU1 start address?

Yes, it's really only necessary when running the virtual simulator.

Quoted 58 lines
Quoted 16 lines

+++ b/arch/arm/mach-socfpga/headsmp.S

arch/arm/mach-socfpga/headsmp.S +3 -4
@@ -13,13 +13,19 @@
 	__CPUINIT
 	.arch	armv7-a
 
-#define CPU1_START_ADDR 	        0xffd08010
-
 ENTRY(secondary_trampoline)
-	movw	r0, #:lower16:CPU1_START_ADDR
-	movt  r0, #:upper16:CPU1_START_ADDR
+	movw	r2, #:lower16:cpu1start_addr
+	movt  r2, #:upper16:cpu1start_addr
 
+	ldr	r0, [r2]
 	ldr	r1, [r0]

arch/arm/mach-socfpga/headsmp.S line 31

Quoted 10 lines
arch/arm/mach-socfpga/headsmp.S +7 -0
 	bx	r1
 
 ENTRY(secondary_trampoline_end)
+
+#ifdef CONFIG_SMP
+ENTRY(v7_secondary_startup)
+       bl      v7_invalidate_l1
+       b       secondary_startup
+ENDPROC(v7_secondary_startup)
+#endif

#ifdef should not be neccessary, as headsmp.S is only compiled when CONFIG_SMP.

arch/arm/mach-socfpga/platsmp.c static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct · line 54

Quoted 9 lines

+++ b/arch/arm/mach-socfpga/platsmp.c

arch/arm/mach-socfpga/platsmp.c +2 -1
@@ -49,7 +49,8 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct
 
 	memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
 
-	__raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
+	__raw_writel(virt_to_phys(v7_secondary_startup),
+		(sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));

The math is rather interesting here; is (sys_manager_base_addr + (cpu1start_addr & 0x000000ff)) == cpu1start_addr ?

arch/arm/mach-socfpga/socfpga.c static void __init socfpga_scu_map_io(void) · line 67

Quoted 13 lines
arch/arm/mach-socfpga/socfpga.c +9 -0
@@ -55,6 +56,16 @@ static void __init socfpga_scu_map_io(void)
 	iotable_init(&scu_io_desc, 1);
 }
 
+static void __init init_socfpga_vt(void)
+{
+	cpu1start_addr = 0xffd08010;
+}
+
+static void __init init_socfpga(void)
+{
+	cpu1start_addr = 0xffd080c4;
+}

Should this be put into device tree somewhere?

Quoted 5 lines

In addition, this patch seems to break operation in the emulator for me. In fact, it looks pretty much like emulator crash, with continuous scroll of

B_TRANSPORT::(R(Addr=0x23092FD0, Count=08 ...

Definitely make sure CONFIG_VMSPLIT_2G=y is set for the Virtual Target.

Dinh

Quoted 7 lines

[sorry, it is hard to copy moving messages].

I'm using kernel based on 3.7-rc2. Should I attempt updating?

Thanks,
Pavel

#29 lore raw

PATCH 5/5 arm: socfpga: Add SMP support for actual socfpga harware

Hi!

Quoted 15 lines
Quoted 14 lines

Review CONFIG_ARM_THUMBEE=y · line 27

Quoted 12 lines

Because the CPU1 start address is different for socfpga-vt and socfpga-cyclone5, we add code to use the correct CPU1 start addr.

+++ b/arch/arm/configs/socfpga_defconfig

(quoted diff) +1 -0
@@ -21,6 +21,7 @@ CONFIG_ARM_THUMBEE=y
 # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_VMSPLIT_2G=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_AEABI=y

Is this related to CPU1 start address?

Quoted 1 line

Yes, it's really only necessary when running the virtual simulator.

Aha, but defconfig does not mean that people will not try that config (and it may be useful for multiarch kernels etc). If we don't know what the cause is, what about this?

Remove unneccessary #ifdef.

socfpga will not boot in VMSPLIT_3G mode on emulator for some reason. Warn when such configuration is detected, and fall back to UP mode (so that user has chance to read the message).

Thanks,
Pavel

Signed-off-by Pavel Machek <[email protected]>
arch/arm/mach-socfpga/headsmp.S +0 -2
index 44cd055..dabf325 100644
@@ -23,9 +23,7 @@ ENTRY(secondary_trampoline)
 
 ENTRY(secondary_trampoline_end)
 
-#ifdef CONFIG_SMP
 ENTRY(v7_secondary_startup)
        bl      v7_invalidate_l1
        b       secondary_startup
 ENDPROC(v7_secondary_startup)
-#endif
arch/arm/mach-socfpga/platsmp.c +7 -0
index d54647e..81e0da0 100644
@@ -75,6 +75,13 @@ static void __init socfpga_smp_init_cpus(void)
 
 	ncores = scu_get_core_count(socfpga_scu_base_addr);
 
+#ifndef CONFIG_VMSPLIT_2G
+	if (of_machine_is_compatible("altr,socfpga-vt")) {
+		printk("Emulator needs VMSPLIT_2G to work in SMP mode.\n");
+		early_printk("Emulator needs VMSPLIT_2G to work in SMP mode.\n");
+		ncores = 1;
+	}
+#endif
 	for (i = 0; i < ncores; i++)
 		set_cpu_possible(i, true);
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#30 lore raw

PATCH 5/5 arm: socfpga: Add SMP support for actual socfpga harware

In reply to dinguyen at altera.com

Hi!

I believe cpu1start_addr should go to the device tree, so that this code is not neccessary. Proposed patch is below...

Thanks,
Pavel

Quoted 10 lines
(quoted diff) +10 -0
+static void __init init_socfpga_vt(void)
+{
+	cpu1start_addr = 0xffd08010;
+}
+
+static void __init init_socfpga(void)
+{
+	cpu1start_addr = 0xffd080c4;
+}
+

...

Review

Quoted 5 lines
(quoted diff) +5 -0
+
+	if (of_machine_is_compatible("altr,socfpga-vt"))
+		init_socfpga_vt();
+	else
+		init_socfpga();

commit b0d651bb4deeb0d8d08969a47b77d3317cbbc0a2

Author: Pavel <[email protected]>
Date:   Mon Jan 28 20:28:06 2013 +0100

Fix whitespace in socfpga.dtsi.

Move cpu1-start-addr variable to device tree, so that config code is not neccessary in kernel.

Signed-off-by Pavel Machek <[email protected]>
arch/arm/boot/dts/socfpga.dtsi +6 -6
index 688729f..35d4bdc 100644
@@ -180,13 +180,13 @@
 		};
 
 		rstmgr at ffd05000 {
-				compatible = "altr,rst-mgr";
-				reg = <0xffd05000 0x1000>;
-			};
+			compatible = "altr,rst-mgr";
+			reg = <0xffd05000 0x1000>;
+		};
 
 		sysmgr at ffd08000 {
-				compatible = "altr,sys-mgr";
-				reg = <0xffd08000 0x4000>;
-			};
+			compatible = "altr,sys-mgr";
+			reg = <0xffd08000 0x4000>;
+		};
 	};
 };
arch/arm/boot/dts/socfpga_cyclone5.dts +4 -0
index 1a6d088..e922475 100644
@@ -56,5 +56,9 @@
 		serial1 at ffc03000 {
 			clock-frequency = <100000000>;
 		};
+
+		sysmgr at ffd08000 {
+			cpu1-start-addr = <0xffd08010>;
+		};
 	};
 };
arch/arm/boot/dts/socfpga_vt.dts +4 -0
index df3551f..407ba14 100644
@@ -56,5 +56,9 @@
 		serial1 at ffc03000 {
 			clock-frequency = <7372800>;
 		};
+
+		sysmgr at ffd08000 {
+			cpu1-start-addr = <0xffd08010>;
+		};
 	};
 };
arch/arm/mach-socfpga/socfpga.c +5 -15
index 2d1e8db..bb17810 100644
@@ -56,16 +56,6 @@ static void __init socfpga_scu_map_io(void)
 	iotable_init(&scu_io_desc, 1);
 }
 
-static void __init init_socfpga_vt(void)
-{
-	cpu1start_addr = 0xffd08010;
-}
-
-static void __init init_socfpga(void)
-{
-	cpu1start_addr = 0xffd080c4;
-}
-
 static void __init socfpga_map_io(void)
 {
 	socfpga_scu_map_io();

@@ -83,6 +73,11 @@ void __init socfpga_sysmgr_init(void)
 	struct device_node *np;
 
 	np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
+
+	if (of_property_read_u32(np, "cpu1-start-addr", (u32 *) &cpu1start_addr)) {
+		early_printk("Need cpu1-start-addr in device tree.\n");
+		panic("Need cpu1-start-addr in device tree.\n");
+	}
 	sys_manager_base_addr = of_iomap(np, 0);
 
 	np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");

@@ -93,11 +88,6 @@ static void __init gic_init_irq(void)
 {
 	of_irq_init(irq_match);
 	socfpga_sysmgr_init();
-
-	if (of_machine_is_compatible("altr,socfpga-vt"))
-		init_socfpga_vt();
-	else
-		init_socfpga();
 }
 
 static void socfpga_cyclone5_restart(char mode, const char *cmd)
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#31 lore raw

RFC 1/1 socfpga: make function static

In reply to dinguyen at altera.com

Hi!

While moving cpu1 start address into device tree, I noticed that sysmgr_init can be static. Trivial patch is below.

Signed-off-by Pavel Machek <[email protected]>

commit 11030de41d7da7a14ca0c77abb726d6eec3a2fb7

arch/arm/mach-socfpga/core.h +0 -1
index 323c74a..3ebd469 100644
@@ -26,7 +26,6 @@ extern void v7_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 
 extern void socfpga_init_clocks(void);
-extern void socfpga_sysmgr_init(void);
 
 extern struct smp_operations socfpga_smp_ops;
 extern char secondary_trampoline, secondary_trampoline_end;
arch/arm/mach-socfpga/socfpga.c +1 -1
index bb17810..334c330 100644
@@ -68,7 +68,7 @@ const static struct of_device_id irq_match[] = {
 	{}
 };
 
-void __init socfpga_sysmgr_init(void)
+static void __init socfpga_sysmgr_init(void)
 {
 	struct device_node *np;
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#32 lore raw

PATCH 5/5 arm: socfpga: Add SMP support for actual socfpga harware

In reply to dinguyen at altera.com

Hi!

arch/arm/mach-socfpga/core.h line 25

Quoted 11 lines

index 9941caa..5b76dd4 100644

arch/arm/mach-socfpga/core.h +1 -1
@@ -20,7 +20,7 @@
 #ifndef __MACH_CORE_H
 #define __MACH_CORE_H
 
-extern void secondary_startup(void);
+extern void v7_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;

One more thing. v7_secondary_startup() may be too generic name for a symbol. mach-imx already uses that.

Plus, mach-imx also has the useless #ifdef.

---

Remove useless #ifdef; headsmp.S is only compiled in CONFIG_SMP configuration.

Signed-off-by Pavel Machek <[email protected]>
arch/arm/mach-imx/headsmp.S +0 -2
index 7e49deb..4c9ec06 100644
@@ -64,12 +64,10 @@ ENTRY(v7_invalidate_l1)
 	mov	pc, lr
 ENDPROC(v7_invalidate_l1)
 
-#ifdef CONFIG_SMP
 ENTRY(v7_secondary_startup)
 	bl	v7_invalidate_l1
 	b	secondary_startup
 ENDPROC(v7_secondary_startup)
-#endif
 
 #ifdef CONFIG_PM
 /*

Thanks,
Pavel

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