ARM: cache-l2x0: add 'smc' identifier

PATCH New srinidhi kasagar 3 participants 8 messages Jan 29, 2013 – Jan 30, 2013

Subsystems (9)

Device tree bindings Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape +5 more subsystems

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srinidhi kasagar

author

2013-01-29 10:13 UTC #0 lore raw

PATCH 1/5 ARM: cache-l2x0: add 'smc' identifier

Add 'smc' (Secure Monitor Call) identifier to differentiates the platforms which implements this.

Signed-off-by srinidhi kasagar <[email protected]>

---
 arch/arm/boot/dts/omap4.dtsi                   |    1 +
 arch/arm/include/asm/hardware/cache-l2x0.h     |    2 +-
 arch/arm/mach-cns3xxx/core.c                   |    4 ++--
 arch/arm/mach-exynos/common.c                  |    4 ++--
 arch/arm/mach-imx/mm-imx3.c                    |    4 ++--
 arch/arm/mach-nomadik/cpu-8815.c               |    4 ++--
 arch/arm/mach-omap2/omap4-common.c             |    2 +-
 arch/arm/mach-realview/realview_eb.c           |    4 ++--
 arch/arm/mach-realview/realview_pb1176.c       |    4 ++--
 arch/arm/mach-realview/realview_pb11mp.c       |    4 ++--
 arch/arm/mach-realview/realview_pbx.c          |    4 ++--
 arch/arm/mach-shmobile/board-ag5evm.c          |    2 +-
 arch/arm/mach-shmobile/board-armadillo800eva.c |    4 ++--
 arch/arm/mach-shmobile/board-bonito.c          |    4 ++--
 arch/arm/mach-shmobile/board-kota2.c           |    4 ++--
 arch/arm/mach-shmobile/board-kzm9g.c           |    4 ++--
 arch/arm/mach-shmobile/setup-r8a7779.c         |    4 ++--
 arch/arm/mach-spear13xx/spear13xx.c            |    2 +-
 arch/arm/mach-ux500/cache-l2x0.c               |    2 +-
 arch/arm/mach-vexpress/ct-ca9x4.c              |    2 +-
 arch/arm/mm/cache-l2x0.c                       |   18 ++++++++++++++----
 21 files changed, 47 insertions(+), 36 deletions(-)

arch/arm/boot/dts/omap4.dtsi +1 -0

index 739bb79..9eaac63 100644
@@ -51,6 +51,7 @@
 		reg = <0x48242000 0x1000>;
 		cache-unified;
 		cache-level = <2>;
+		smc;
 	};
 
 	local-timer at 0x48240600 {

arch/arm/include/asm/hardware/cache-l2x0.h +1 -1

index 3b2c40b..49ac638 100644
@@ -107,7 +107,7 @@
 #define L2X0_WAY_SIZE_SHIFT		3
 
 #ifndef __ASSEMBLY__
-extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
+extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask, bool smc);
 #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
 extern int l2x0_of_init(u32 aux_val, u32 aux_mask);
 #else

arch/arm/mach-cns3xxx/core.c +2 -2

index 031805b..446bd99 100644
@@ -282,8 +282,8 @@ void __init cns3xxx_l2x0_init(void)
 	val &= 0xfffff888;
 	writel(val, base + L2X0_DATA_LATENCY_CTRL);
 
-	/* 32 KiB, 8-way, parity disable */
-	l2x0_init(base, 0x00540000, 0xfe000fff);
+	/* 32 KiB, 8-way, parity disable, no secure monitor call (smc) */
+	l2x0_init(base, 0x00540000, 0xfe000fff, false);
 }
 
 #endif /* CONFIG_CACHE_L2X0 */

arch/arm/mach-exynos/common.c +2 -2

index 1a89824..6624acc 100644
@@ -754,8 +754,8 @@ static int __init exynos4_l2x0_cache_init(void)
 		clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 		clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 	}
-
-	l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
+	/* no secure monitor call (smc) implemented */
+	l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK, false);
 	return 0;
 }
 early_initcall(exynos4_l2x0_cache_init);

arch/arm/mach-imx/mm-imx3.c +2 -2

index cefa047..74eedb7 100644
@@ -111,8 +111,8 @@ void __init imx3_init_l2x0(void)
 		printk(KERN_ERR "remapping L2 cache area failed\n");
 		return;
 	}
-
-	l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+	/* no secure monitor call (smc) implemented */
+	l2x0_init(l2x0_base, 0x00030024, 0x00000000, false);
 #endif
 }

arch/arm/mach-nomadik/cpu-8815.c +2 -2

index 1273931..7f27151 100644
@@ -145,8 +145,8 @@ void __init cpu8815_init_irq(void)
  void __init cpu8815_platform_init(void)
 {
 #ifdef CONFIG_CACHE_L2X0
-	/* At full speed latency must be >=2, so 0x249 in low bits */
-	l2x0_init(io_p2v(NOMADIK_L2CC_BASE), 0x00730249, 0xfe000fff);
+	/* At full speed latency must be >=2, so 0x249 in low bits, no smc */
+	l2x0_init(io_p2v(NOMADIK_L2CC_BASE), 0x00730249, 0xfe000fff, false);
 #endif
 	 return;
 }

arch/arm/mach-omap2/omap4-common.c +1 -1

index 6897ae2..a440fc4 100644
@@ -214,7 +214,7 @@ static int __init omap_l2_cache_init(void)
 	if (of_have_populated_dt())
 		l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
 	else
-		l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
+		l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK, true);
 
 	/*
 	 * Override default outer_cache.disable with a OMAP4

arch/arm/mach-realview/realview_eb.c +2 -2

index 28511d4..ca5e75c 100644
@@ -445,9 +445,9 @@ static void __init realview_eb_init(void)
 		realview_eb11mp_fixup();
 
 #ifdef CONFIG_CACHE_L2X0
-		/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
+		/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled, no smc
 		 * Bits:  .... ...0 0111 1001 0000 .... .... .... */
-		l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
+		l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff, false);
 #endif
 		platform_device_register(&pmu_device);
 	}

arch/arm/mach-realview/realview_pb1176.c +2 -2

index 07d6672..f2e851d 100644
@@ -358,8 +358,8 @@ static void __init realview_pb1176_init(void)
 	int i;
 
 #ifdef CONFIG_CACHE_L2X0
-	/* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */
-	l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
+	/* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled, no smc */
+	l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff, false);
 #endif
 
 	realview_flash_register(realview_pb1176_flash_resources,

arch/arm/mach-realview/realview_pb11mp.c +2 -2

index 7ed53d7..6cb7f60 100644
@@ -340,9 +340,9 @@ static void __init realview_pb11mp_init(void)
 	int i;
 
 #ifdef CONFIG_CACHE_L2X0
-	/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
+	/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled, no smc
 	 * Bits:  .... ...0 0111 1001 0000 .... .... .... */
-	l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
+	l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff, false);
 #endif
 
 	realview_flash_register(realview_pb11mp_flash_resource,

arch/arm/mach-realview/realview_pbx.c +2 -2

index 4f486f0..d90bdbd 100644
@@ -376,9 +376,9 @@ static void __init realview_pbx_init(void)
 		writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
 		writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
 
-		/* 16KB way size, 8-way associativity, parity disabled
+		/* 16KB way size, 8-way associativity, parity disabled, no smc
 		 * Bits:  .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */
-		l2x0_init(l2x0_base, 0x02520000, 0xc0000fff);
+		l2x0_init(l2x0_base, 0x02520000, 0xc0000fff, false);
 		platform_device_register(&pmu_device);
 	}
 #endif

arch/arm/mach-shmobile/board-ag5evm.c +1 -1

index 032d108..788dc1f 100644
@@ -656,7 +656,7 @@ static void __init ag5evm_init(void)
 
 #ifdef CONFIG_CACHE_L2X0
 	/* Shared attribute override enable, 64K*8way */
-	l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
+	l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff, false);
 #endif
 	sh73a0_add_standard_devices();
 	platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));

arch/arm/mach-shmobile/board-armadillo800eva.c +2 -2

index 5353adf..2ff7e81 100644
@@ -1163,8 +1163,8 @@ static void __init eva_init(void)
 
 
 #ifdef CONFIG_CACHE_L2X0
-	/* Early BRESP enable, Shared attribute override enable, 32K*8way */
-	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
+	/* Early BRESP enable, Shared attribute override enable, 32K*8way, no smc */
+	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff, false);
 #endif
 
 	i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));

arch/arm/mach-shmobile/board-bonito.c +2 -2

index cb8c994..eca8b32 100644
@@ -380,8 +380,8 @@ static void __init bonito_init(void)
 	 */
 
 #ifdef CONFIG_CACHE_L2X0
-	/* Early BRESP enable, Shared attribute override enable, 32K*8way */
-	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
+	/* Early BRESP enable, Shared attribute override enable, 32K*8way, no smc */
+	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff, false);
 #endif
 
 	r8a7740_add_standard_devices();

arch/arm/mach-shmobile/board-kota2.c +2 -2

index bf88f9a..57d0732 100644
@@ -537,8 +537,8 @@ static void __init kota2_init(void)
 	gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
 
 #ifdef CONFIG_CACHE_L2X0
-	/* Early BRESP enable, Shared attribute override enable, 64K*8way */
-	l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
+	/* Early BRESP enable, Shared attribute override enable, 64K*8way, no smc */
+	l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff, false);
 #endif
 	sh73a0_add_standard_devices();
 	platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices));

arch/arm/mach-shmobile/board-kzm9g.c +2 -2

index c02448d..31e9d1a 100644
@@ -762,8 +762,8 @@ static void __init kzm_init(void)
 	gpio_request(GPIO_FN_VBUS_0,	NULL);
 
 #ifdef CONFIG_CACHE_L2X0
-	/* Early BRESP enable, Shared attribute override enable, 64K*8way */
-	l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
+	/* Early BRESP enable, Shared attribute override enable, 64K*8way, no smc */
+	l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff, false);
 #endif
 
 	i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));

arch/arm/mach-shmobile/setup-r8a7779.c +2 -2

index 7a1ad4f..15db786 100644
@@ -323,8 +323,8 @@ static struct platform_device *r8a7779_late_devices[] __initdata = {
 void __init r8a7779_add_standard_devices(void)
 {
 #ifdef CONFIG_CACHE_L2X0
-	/* Early BRESP enable, Shared attribute override enable, 64K*16way */
-	l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
+	/* Early BRESP enable, Shared attribute override enable, 64K*16way, no smc */
+	l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff, false);
 #endif
 	r8a7779_pm_init();

arch/arm/mach-spear13xx/spear13xx.c +1 -1

index c4af775..83671be 100644
@@ -102,7 +102,7 @@ void __init spear13xx_l2x0_init(void)
 	 */
 	writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL);
 	writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL);
-	l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
+	l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff, false);
 }
 
 /*

arch/arm/mach-ux500/cache-l2x0.c +1 -1

index 75d5b51..e770156 100644
@@ -58,7 +58,7 @@ static int __init ux500_l2x0_init(void)
 	if (of_have_populated_dt())
 		l2x0_of_init(aux_val, 0xc0000fff);
 	else
-		l2x0_init(l2x0_base, aux_val, 0xc0000fff);
+		l2x0_init(l2x0_base, aux_val, 0xc0000fff, false);
 
 	/*
 	 * We can't disable l2 as we are in non secure mode, currently

arch/arm/mach-vexpress/ct-ca9x4.c +1 -1

index 60838dd..e3e6644 100644
@@ -148,7 +148,7 @@ static void __init ct_ca9x4_init(void)
 	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
 	writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
 
-	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
+	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff, false);
 #endif
 
 	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)

arch/arm/mm/cache-l2x0.c +14 -4

index c2f3739..432fef0 100644
@@ -320,7 +320,7 @@ static void l2x0_unlock(u32 cache_id)
 	}
 }
 
-void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
+void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask, bool smc)
 {
 	u32 aux;
 	u32 cache_id;

@@ -352,8 +352,10 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		/* Unmapped register. */
 		sync_reg_offset = L2X0_DUMMY_REG;
 #endif
-		if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0)
+		if (smc)
 			outer_cache.set_debug = pl310_set_debug;
+		else
+			outer_cache.set_debug = NULL;
 		break;
 	case L2X0_CACHE_ID_PART_L210:
 		ways = (aux >> 13) & 0xf;

@@ -425,6 +427,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 
 #ifdef CONFIG_OF
 static int l2_wt_override;
+static bool is_smc;
 
 /*
  * Note that the end addresses passed to Linux primitives are

@@ -590,6 +593,14 @@ static void __init pl310_of_setup(const struct device_node *np,
 		writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
 			       l2x0_base + L2X0_ADDR_FILTER_START);
 	}
+
+	is_smc = of_property_read_bool(np, "smc");
+
+	if (is_smc) {
+		/* set the debug interface */
+		outer_cache.set_debug = pl310_set_debug;
+	}
+
 }
 
 static void __init pl310_save(void)

@@ -725,7 +736,6 @@ static const struct l2x0_of_data pl310_data = {
 		.flush_all   = l2x0_flush_all,
 		.inv_all     = l2x0_inv_all,
 		.disable     = l2x0_disable,
-		.set_debug   = pl310_set_debug,
 	},
 };

@@ -814,7 +824,7 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 		data->save();
 
 	of_init = true;
-	l2x0_init(l2x0_base, aux_val, aux_mask);
+	l2x0_init(l2x0_base, aux_val, aux_mask, is_smc);
 
 	memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));

Signature · 1 line

1.7.2.dirty

Russell King - ARM Linux

2013-01-29 11:33 UTC #1 lore raw

PATCH 1/5 ARM: cache-l2x0: add 'smc' identifier

Quoted 2 lines · srinidhi kasagar

Add 'smc' (Secure Monitor Call) identifier to differentiates the platforms which implements this.

This patch makes no sense.

So, if setting 'smc' in the DT description is supposed to mean that the platform has a secure monitor then...

arch/arm/mm/cache-l2x0.c static void __init pl310_of_setup(const struct device_node *np, · line 602

Quoted 6 lines

arch/arm/mm/cache-l2x0.c +6 -0

+	is_smc = of_property_read_bool(np, "smc");
+
+	if (is_smc) {
+		/* set the debug interface */
+		outer_cache.set_debug = pl310_set_debug;
+	}

Now, let's look at what pl310_set_debug() does:

static void pl310_set_debug(unsigned long val)

{
        writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
}

Can you explain where the secure monitor call is there please, because I can't see one. In fact, this is the function used when there _isn't_ a secure monitor. So this patch just seems totally wrong to me.

Srinidhi Kasagar

author

2013-01-29 11:38 UTC #2 lore raw

PATCH 1/5 ARM: cache-l2x0: add 'smc' identifier

Quoted 18 lines · Russell King - ARM Linux

Quoted 2 lines · srinidhi kasagar
Add 'smc' (Secure Monitor Call) identifier to differentiates the platforms which implements this.
This patch makes no sense.
So, if setting 'smc' in the DT description is supposed to mean that the platform has a secure monitor then...
Review
Quoted 6 lines
(quoted diff) +6 -0
+	is_smc = of_property_read_bool(np, "smc");
+
+	if (is_smc) {
+		/* set the debug interface */
+		outer_cache.set_debug = pl310_set_debug;
+	}
Now, let's look at what pl310_set_debug() does:

Quoted 8 lines

static void pl310_set_debug(unsigned long val)
{
        writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
}
Can you explain where the secure monitor call is there please, because I can't see one. In fact, this is the function used when there _isn't_ a secure monitor. So this patch just seems totally wrong to me.

Today, one and only platform is omap. Please check below snapshot:

arch/arm/boot/dts/omap4.dtsi +1 -0

@@ -51,6 +51,7 @@
 		reg = <0x48242000 0x1000>;
 		cache-unified;
 		cache-level = <2>;
+		smc;
 	};

[...]

arch/arm/mach-omap2/omap4-common.c +1 -1

@@ -214,7 +214,7 @@ static int __init omap_l2_cache_init(void)
 	if (of_have_populated_dt())
 		l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
 	else
-		l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
+		l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK, true);

regards/srinidhi

Russell King - ARM Linux

2013-01-29 11:44 UTC #3 lore raw

PATCH 1/5 ARM: cache-l2x0: add 'smc' identifier

Quoted 24 lines · Srinidhi Kasagar

Quoted 23 lines · Russell King - ARM Linux
Quoted 2 lines · srinidhi kasagar
Add 'smc' (Secure Monitor Call) identifier to differentiates the platforms which implements this.
This patch makes no sense.
So, if setting 'smc' in the DT description is supposed to mean that the platform has a secure monitor then...
Review
Quoted 6 lines
(quoted diff) +6 -0
+	is_smc = of_property_read_bool(np, "smc");
+
+	if (is_smc) {
+		/* set the debug interface */
+		outer_cache.set_debug = pl310_set_debug;
+	}
Now, let's look at what pl310_set_debug() does:
static void pl310_set_debug(unsigned long val)
{
        writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
}

Quoted 5 lines

Quoted 3 lines
Can you explain where the secure monitor call is there please, because I can't see one. In fact, this is the function used when there _isn't_ a secure monitor. So this patch just seems totally wrong to me.
Today, one and only platform is omap. Please check below snapshot:

I don't think you understood my point at all.

OMAP sets outer_cache.set_debug to point at its own function to issue a SMC to set the debug register.

pl310_set_debug() is not that code; pl310_set_debug() is used on non-OMAP platforms to write to this register directly.

Your patch disables the whole workaround if 'smc' is not specified in DT or 'true' is passed into the l2x0 init function.

Therefore, this patch is just rubbish IMHO. I don't think you've taken the time to understand the code you're modifying, nor have you understood the point that I made above.

Srinidhi Kasagar

author

2013-01-29 11:49 UTC #4 lore raw

PATCH 1/5 ARM: cache-l2x0: add 'smc' identifier

In reply to Russell King - ARM Linux

Quoted 18 lines · Russell King - ARM Linux

Quoted 2 lines · srinidhi kasagar
Add 'smc' (Secure Monitor Call) identifier to differentiates the platforms which implements this.
This patch makes no sense.
So, if setting 'smc' in the DT description is supposed to mean that the platform has a secure monitor then...
arch/arm/mm/cache-l2x0.c static void __init pl310_of_setup(const struct device_node *np, · line 602
Quoted 6 lines
arch/arm/mm/cache-l2x0.c +6 -0
+	is_smc = of_property_read_bool(np, "smc");
+
+	if (is_smc) {
+		/* set the debug interface */
+		outer_cache.set_debug = pl310_set_debug;
+	}
Now, let's look at what pl310_set_debug() does:

Quoted 3 lines

static void pl310_set_debug(unsigned long val)
{
        writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);

You can do this operation (write to DEBUG_CTRL) only if SMC is implemented.

Quoted 5 lines

}
Can you explain where the secure monitor call is there please, because I can't see one. In fact, this is the function used when there _isn't_ a secure monitor. So this patch just seems totally wrong to me.

regards/srinidhi

Russell King - ARM Linux

2013-01-29 12:22 UTC #5 lore raw

PATCH 1/5 ARM: cache-l2x0: add 'smc' identifier

Quoted 19 lines · Srinidhi Kasagar

Quoted 18 lines · Russell King - ARM Linux
Quoted 2 lines · srinidhi kasagar
Add 'smc' (Secure Monitor Call) identifier to differentiates the platforms which implements this.
This patch makes no sense.
So, if setting 'smc' in the DT description is supposed to mean that the platform has a secure monitor then...
arch/arm/mm/cache-l2x0.c static void __init pl310_of_setup(const struct device_node *np, · line 602
Quoted 6 lines
arch/arm/mm/cache-l2x0.c +6 -0
+	is_smc = of_property_read_bool(np, "smc");
+
+	if (is_smc) {
+		/* set the debug interface */
+		outer_cache.set_debug = pl310_set_debug;
+	}
Now, let's look at what pl310_set_debug() does:

Quoted 5 lines

Quoted 3 lines
static void pl310_set_debug(unsigned long val)
{
        writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
You can do this operation (write to DEBUG_CTRL) only if SMC is implemented.

Err... no. You can do it if you're running in secure mode without a secure monitor, because the security stuff doesn't get in the way.

What other platforms do is up to them, and up to *how* the secure monitor is implemented, not *if*.

Quoted 5 lines

Quoted 5 lines
}
Can you explain where the secure monitor call is there please, because I can't see one. In fact, this is the function used when there _isn't_ a secure monitor. So this patch just seems totally wrong to me.

So this is going to be difficult because you only ever answer half an email? So, I repeat the question above.

Srinidhi Kasagar

author

2013-01-30 05:06 UTC #6 lore raw

PATCH 1/5 ARM: cache-l2x0: add 'smc' identifier

Quoted 20 lines · Russell King - ARM Linux

Quoted 19 lines · Srinidhi Kasagar
Quoted 18 lines · Russell King - ARM Linux
Quoted 2 lines · srinidhi kasagar
Add 'smc' (Secure Monitor Call) identifier to differentiates the platforms which implements this.
This patch makes no sense.
So, if setting 'smc' in the DT description is supposed to mean that the platform has a secure monitor then...
arch/arm/mm/cache-l2x0.c static void __init pl310_of_setup(const struct device_node *np, · line 602
Quoted 6 lines
arch/arm/mm/cache-l2x0.c +6 -0
+	is_smc = of_property_read_bool(np, "smc");
+
+	if (is_smc) {
+		/* set the debug interface */
+		outer_cache.set_debug = pl310_set_debug;
+	}
Now, let's look at what pl310_set_debug() does:

Quoted 8 lines

Quoted 5 lines
Quoted 3 lines
static void pl310_set_debug(unsigned long val)
{
        writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
You can do this operation (write to DEBUG_CTRL) only if SMC is implemented.
Err... no. You can do it if you're running in secure mode without a secure monitor, because the security stuff doesn't get in the way.

Yes, you are right as always. I was totally wrong, I overlooked the code. I will drop this patch, it does not make sense.

Quoted 4 lines

What other platforms do is up to them, and up to *how* the secure monitor is implemented, not *if*.

Quoted 8 lines

Quoted 5 lines
Quoted 5 lines
}
Can you explain where the secure monitor call is there please, because I can't see one. In fact, this is the function used when there _isn't_ a secure monitor. So this patch just seems totally wrong to me.
So this is going to be difficult because you only ever answer half an email? So, I repeat the question above.

Yes, there is no secure monitor call. I mixed up two things and end up in a mess.

Thanks,srinidhi

Tomasz Figa

2013-01-29 15:37 UTC #7 lore raw

PATCH 1/5 ARM: cache-l2x0: add 'smc' identifier

In reply to srinidhi kasagar

Hi Srinidhi,

Quoted 26 lines · On Tuesday 29 of January 2013 15:43:31 srinidhi kasagar wrote:

Add 'smc' (Secure Monitor Call) identifier to differentiates the platforms which implements this.

Signed-off-by srinidhi kasagar <[email protected]>

---
 arch/arm/boot/dts/omap4.dtsi                   |    1 +
 arch/arm/include/asm/hardware/cache-l2x0.h     |    2 +-
 arch/arm/mach-cns3xxx/core.c                   |    4 ++--
 arch/arm/mach-exynos/common.c                  |    4 ++--
 arch/arm/mach-imx/mm-imx3.c                    |    4 ++--
 arch/arm/mach-nomadik/cpu-8815.c               |    4 ++--
 arch/arm/mach-omap2/omap4-common.c             |    2 +-
 arch/arm/mach-realview/realview_eb.c           |    4 ++--
 arch/arm/mach-realview/realview_pb1176.c       |    4 ++--
 arch/arm/mach-realview/realview_pb11mp.c       |    4 ++--
 arch/arm/mach-realview/realview_pbx.c          |    4 ++--
 arch/arm/mach-shmobile/board-ag5evm.c          |    2 +-
 arch/arm/mach-shmobile/board-armadillo800eva.c |    4 ++--
 arch/arm/mach-shmobile/board-bonito.c          |    4 ++--
 arch/arm/mach-shmobile/board-kota2.c           |    4 ++--
 arch/arm/mach-shmobile/board-kzm9g.c           |    4 ++--
 arch/arm/mach-shmobile/setup-r8a7779.c         |    4 ++--
 arch/arm/mach-spear13xx/spear13xx.c            |    2 +-
 arch/arm/mach-ux500/cache-l2x0.c               |    2 +-
 arch/arm/mach-vexpress/ct-ca9x4.c              |    2 +-
 arch/arm/mm/cache-l2x0.c                       |   18

Quoted 1 line

++++++++++++++---- 21 files changed, 47 insertions(+), 36 deletions(-)

I'd recommend you to take a look at this series:
http://thread.gmane.org/gmane.linux.ports.arm.kernel/202224/

It's already queued up for 3.9 in Samsung tree and most likely provides an interface needed for what you want to achieve.

Best regards,

Signature · 3 lines

Tomasz Figa
Samsung Poland R&D Center
SW Solution Development, Linux Platform