at91: add sama5d3 support

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index cacc0b5..8af8d96 100644
@@ -20,7 +20,9 @@ struct clk {
 	const char	*name;		/* unique clock name */
 	struct clk_lookup cl;
 	unsigned long	rate_hz;
+	unsigned	div;		/* parent clock divider */
 	struct clk	*parent;
+	unsigned	pid;		/* peripheral ID */
 	u32		pmc_mask;
 	void		(*mode)(struct clk *, int);
 	unsigned	id:3;		/* PCK0..4, or 32k/main/a/b */

index 6fcbf40..6107871 100644
@@ -163,13 +163,19 @@
 #define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
 #define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */
 
-#define AT91_PMC_VER		(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
+#define AT91_PMC_VER		0xfc			/* PMC Module Version [AT91CAP9 only] */
 
-#define AT91_PMC_PCR		(AT91_PMC + 0x10c)	/* Peripheral Control Register [some SAM9] */
+#define AT91_PMC_PCR		0x10c			/* Peripheral Control Register [some SAM9] */
 #define		AT91_PMC_PCR_PID	(0x3f  <<  0)		/* Peripheral ID */
 #define		AT91_PMC_PCR_CMD	(0x1  <<  12)		/* Command */
-#define		AT91_PMC_PCR_DIV	(0x3  <<  16)		/* Divisor Value */
-#define		AT91_PMC_PCRDIV(n)	(((n) <<  16) & AT91_PMC_PCR_DIV)
+#define		AT91_PMC_PCR_DIV(n)	((n) <<  16)	/* Divisor value */
+#define			AT91_PMC_PCR_DIV0	0x0		/* Peripheral clock is MCK */
+#define			AT91_PMC_PCR_DIV2	0x1		/* Peripheral clock is MCK/2 */
+#define			AT91_PMC_PCR_DIV4	0x2		/* Peripheral clock is MCK/4 */
+#define			AT91_PMC_PCR_DIV8	0x3		/* Peripheral clock is MCK/8 */
 #define		AT91_PMC_PCR_EN		(0x1  <<  28)		/* Enable */
 
+#define	AT91_PMC_PCER1		0x100			/* Peripheral Clock Enable Register 1 */
+#define	AT91_PMC_PCDR1		0x104			/* Peripheral Clock Disable Register 1 */
+#define	AT91_PMC_PCSR1		0x108			/* Peripheral Clock Status Register 1 */
 #endif

index f8699d7..2614f97 100644
@@ -218,6 +218,43 @@ static inline u32 at91sam9n12_get_ddram_size(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_SAMA5
+static inline u32 at91sama5_get_ddram_size(void)
+{
+	u32 cr;
+	u32 mdr;
+	u32 size;
+	void * __iomem base = IOMEM(SAMA5D3_BASE_MPDDRC);
+
+	cr = __raw_readl(base + AT91_DDRSDRC_CR);
+	mdr = __raw_readl(base + AT91_DDRSDRC_MDR);
+
+	/* Formula:
+	 * size = bank << (col + row + 1);
+	 * if (bandwidth == 32 bits)
+	 *	size <<= 1;
+	 */
+	size = 1;
+	/* COL */
+	size += (cr & AT91_DDRSDRC_NC) + 9;
+	/* ROW */
+	size += ((cr & AT91_DDRSDRC_NR) >> 2) + 11;
+	/* BANK */
+	size = ((cr & AT91_DDRSDRC_NB) ? 8 : 4) << size;
+
+	/* bandwidth */
+	if (!(mdr & AT91_DDRSDRC_DBW))
+		size <<= 1;
+
+	return size;
+}
+#else
+static inline u32 at91sama5_get_ddram_size(void)
+{
+	return 0;
+}
+#endif
+
 #endif
 
 #endif

index b6504c1..7132489 100644
@@ -26,6 +26,7 @@
 #define ARCH_ID_AT91SAM9G45ES	0x819b05a1	/* 9G45-ES (Engineering Sample) */
 #define ARCH_ID_AT91SAM9X5	0x819a05a0
 #define ARCH_ID_AT91SAM9N12	0x819a07a0
+#define ARCH_ID_SAMA5D3		0x8A5C07C0
 
 #define ARCH_ID_AT91SAM9XE128	0x329973a0
 #define ARCH_ID_AT91SAM9XE256	0x329a93a0

@@ -47,6 +48,11 @@
 #define ARCH_EXID_AT91SAM9G25	0x00000003
 #define ARCH_EXID_AT91SAM9X25	0x00000004
 
+#define ARCH_EXID_SAMA5D31	0x00444300
+#define ARCH_EXID_SAMA5D33	0x00414300
+#define ARCH_EXID_SAMA5D34	0x00414301
+#define ARCH_EXID_SAMA5D35	0x00584300
+
 #define ARCH_FAMILY_AT91X92	0x09200000
 #define ARCH_FAMILY_AT91SAM9	0x01900000
 #define ARCH_FAMILY_AT91SAM9XE	0x02900000

@@ -75,6 +81,9 @@ enum at91_soc_type {
 	/* SAM9N12 */
 	AT91_SOC_SAM9N12,
 
+	/* SAMA5D3 */
+	AT91_SOC_SAMA5D3,
+
 	/* Unknown type */
 	AT91_SOC_NONE
 };

@@ -93,6 +102,10 @@ enum at91_soc_subtype {
 	AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
 	AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
 
+	/* SAMA5D3 */
+	AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
+	AT91_SOC_SAMA5D35,
+
 	/* Unknown subtype */
 	AT91_SOC_SUBTYPE_NONE
 };

@@ -187,6 +200,20 @@ static inline int at91_soc_is_detected(void)
 #define cpu_is_at91sam9n12()	(0)
 #endif
 
+#ifdef CONFIG_ARCH_SAMA5D3
+#define cpu_is_sama5d3()	(at91_soc_initdata.type == AT91_SOC_SAMA5D3)
+#define cpu_is_sama5d31()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D31)
+#define cpu_is_sama5d33()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D33)
+#define cpu_is_sama5d34()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D34)
+#define cpu_is_sama5d35()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D35)
+#else
+#define cpu_is_sama5d3()	(0)
+#define cpu_is_sama5d31()	(0)
+#define cpu_is_sama5d33()	(0)
+#define cpu_is_sama5d34()	(0)
+#define cpu_is_sama5d35()	(0)
+#endif
+
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.

index e283b9d..8f004de 100644
@@ -38,6 +38,8 @@
 #include <mach/at91sam9n12.h>
 #elif defined(CONFIG_ARCH_AT91SAM9X5)
 #include <mach/at91sam9x5.h>
+#elif defined(CONFIG_ARCH_SAMA5D3)
+#include <mach/sama5d3.h>
 #elif defined(CONFIG_ARCH_AT91CAP9)
 #include <mach/at91cap9.h>
 #elif defined(CONFIG_ARCH_AT91X40)

@@ -56,6 +58,12 @@
 #define AT91_CHIPSELECT_6	0x70000000
 #define AT91_CHIPSELECT_7	0x80000000
 
+#define SAMA5_CHIPSELECT_0	0x10000000
+#define SAMA5_DDRCS		0x20000000
+#define SAMA5_CHIPSELECT_1	0x40000000
+#define SAMA5_CHIPSELECT_2	0x50000000
+#define SAMA5_CHIPSELECT_3	0x60000000
+
 /* SDRAM */
 #ifdef CONFIG_DRAM_BASE
 #define AT91_SDRAM_BASE		CONFIG_DRAM_BASE

152 lines not on this page · raw message

new file mode 100644
index 0000000..8176b38
@@ -0,0 +1,15 @@
+/*
+ * Matrix-centric header file for the SAMA5D3 family
+ *
+ *  Copyright (C) 2009-2012 Atmel Corporation.
+ *
+ * Only EBI related registers.
+ * Write Protect register definitions may be useful.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef SAMA5D3_MATRIX_H
+#define SAMA5D3_MATRIX_H
+
+#endif

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index 9b73bcf..0444a5f 100644
@@ -87,6 +87,11 @@ static void __init soc_detect(u32 dbgu_base)
 		at91_soc_initdata.type = AT91_SOC_SAM9N12;
 		at91_boot_soc = at91sam9n12_soc;
 		break;
+
+	case ARCH_ID_SAMA5D3:
+		at91_soc_initdata.type = AT91_SOC_SAMA5D3;
+		at91_boot_soc = at91sama5d3_soc;
+		break;
 	}
 
 	/* at91sam9g10 */

@@ -142,6 +147,23 @@ static void __init soc_detect(u32 dbgu_base)
 			break;
 		}
 	}
+
+	if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
+		switch (at91_soc_initdata.exid) {
+		case ARCH_EXID_SAMA5D31:
+			at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
+			break;
+		case ARCH_EXID_SAMA5D33:
+			at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
+			break;
+		case ARCH_EXID_SAMA5D34:
+			at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
+			break;
+		case ARCH_EXID_SAMA5D35:
+			at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
+			break;
+		}
+	}
 }
 
 static const char *soc_name[] = {

@@ -155,6 +177,7 @@ static const char *soc_name[] = {
 	[AT91_SOC_SAM9RL]	= "at91sam9rl",
 	[AT91_SOC_SAM9X5]	= "at91sam9x5",
 	[AT91_SOC_SAM9N12]	= "at91sam9n12",
+	[AT91_SOC_SAMA5D3]	= "sama5d3",
 	[AT91_SOC_NONE]		= "Unknown"
 };
 

@@ -177,6 +200,10 @@ static const char *soc_subtype_name[] = {
 	[AT91_SOC_SAM9X35]	= "at91sam9x35",
 	[AT91_SOC_SAM9G25]	= "at91sam9g25",
 	[AT91_SOC_SAM9X25]	= "at91sam9x25",
+	[AT91_SOC_SAMA5D31]	= "sama5d31",
+	[AT91_SOC_SAMA5D33]	= "sama5d33",
+	[AT91_SOC_SAMA5D34]	= "sama5d34",
+	[AT91_SOC_SAMA5D35]	= "sama5d35",
 	[AT91_SOC_SUBTYPE_NONE]	= "Unknown"
 };
 

index 8019ced..b2278a5 100644
@@ -18,6 +18,7 @@ extern struct at91_init_soc at91sam9g45_soc;
 extern struct at91_init_soc at91sam9rl_soc;
 extern struct at91_init_soc at91sam9x5_soc;
 extern struct at91_init_soc at91sam9n12_soc;
+extern struct at91_init_soc at91sama5d3_soc;
 
 #define AT91_SOC_START(_name)				\
 struct at91_init_soc __initdata at91##_name##_soc	\

@@ -64,3 +65,7 @@ static inline int at91_soc_is_enabled(void)
 #if !defined(CONFIG_SOC_AT91SAM9N12)
 #define at91sam9n12_soc	at91_boot_soc
 #endif
+
+#if !defined(CONFIG_SOC_SAMA5)
+#define at91sama5d3_soc	at91_boot_soc
+#endif

new file mode 100644
index 0000000..d971810
@@ -0,0 +1,6 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
+
+#endif	/* __CONFIG_H */

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new file mode 100644
index 0000000..1976241
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ */
+
+#ifndef __HW_REVISION_H__
+#define __HW_REVISION_H__
+
+enum vendor_id {
+	VENDOR_UNKNOWN	= 0,
+	VENDOR_EMBEST	= 1,
+	VENDOR_FLEX	= 2,
+	VENDOR_RONETIX	= 3,
+	VENDOR_COGENT	= 4,
+	VENDOR_PDA	= 5,
+};
+
+bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid);
+bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid);
+bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid);
+void at91sama5d3xek_devices_detect_hw(void);
+
+#endif /* __HW_REVISION_H__ */

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