Add I2C support for Allwinner SoCs

PATCH Superseded Maxime Ripard 3 participants 15 messages May 27, 2013 – Jun 12, 2013

Subsystems (3)

Device tree bindings I2C subsystem host drivers Arm/Allwinner sunXi SoC support

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Maxime Ripard

author

2013-05-27 10:00 UTC #0 lore raw

v3 cover Add I2C support for Allwinner SoCs

Hi,

This patchset adds support for the I2C controller found on most of the Allwinner SoCs, especially the already supported A10 and A13, and the yet to come A31.

It has been tested on a A13-Olinuxino.

Thanks,
Maxime

Changes from v2:
* Slightly modified the switch comments again
* Removed the of_* calls in favor of platform_get_* functions

Changes from v1:
* Added comments to the switch statements to clarify when the fall through to the next case is made on purpose
* Use devm_ioremap_resource instead of of_iomap
* Moved the reset after enabling the clocks
* Added Emilio Lopez' patch to add the available i2c controllers to the cubieboard

Emilio L?pez (1):
ARM: sun4i: cubieboard: Enable the i2c controllers

Maxime Ripard (5):
i2c: sunxi: Add Allwinner A1X i2c driver
ARM: sunxi: dt: Add i2c controller nodes to the DTSI
ARM: sun4i: dt: Add i2c muxing options
ARM: sun5i: dt: Add i2c muxing options
ARM: sun5i: olinuxino: Enable the i2c controllers

 .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts         |  12 +
 arch/arm/boot/dts/sun4i-a10.dtsi                   |  48 +++
 arch/arm/boot/dts/sun5i-a13-olinuxino.dts          |  18 +
 arch/arm/boot/dts/sun5i-a13.dtsi                   |  48 +++
 drivers/i2c/busses/Kconfig                         |  10 +
 drivers/i2c/busses/Makefile                        |   1 +
 drivers/i2c/busses/i2c-sunxi.c                     | 444 +++++++++++++++++++++
 8 files changed, 600 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
 create mode 100644 drivers/i2c/busses/i2c-sunxi.c

Signature · 1 line

1.8.2.3

Maxime Ripard

author

2013-05-27 10:00 UTC #1 lore raw

PATCH v3 1/6 i2c: sunxi: Add Allwinner A1X i2c driver

This patch implements a basic driver for the I2C host driver found on the Allwinner A10, A13 and A31 SoCs.

Notable missing feature is 10-bit addressing.

Signed-off-by Maxime Ripard <[email protected]>

---
 .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
 drivers/i2c/busses/Kconfig                         |  10 +
 drivers/i2c/busses/Makefile                        |   1 +
 drivers/i2c/busses/i2c-sunxi.c                     | 444 +++++++++++++++++++++
 4 files changed, 474 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
 create mode 100644 drivers/i2c/busses/i2c-sunxi.c

Documentation/devicetree/bindings/i2c/i2c-sunxi.txt new file +19 -0

new file mode 100644
index 0000000..40c16d0
@@ -0,0 +1,19 @@
+Allwinner SoC I2C controller
+
+Required properties:
+- compatible : Should be "allwinner,sun4i-i2c".
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clocks : The parent clock feeding the I2C controller.
+
+Recommended properties:
+- clock-frequency : desired I2C bus clock frequency in Hz.
+
+Example:
+i2c0: i2c at 01c2ac00 {
+	compatible = "allwinner,sun4i-i2c";
+	reg = <0x01c2ac00 0x400>;
+	interrupts = <7>;
+	clocks = <&apb1_gates 0>;
+	clock-frequency = <100000>;
+};

drivers/i2c/busses/Kconfig +10 -0

index 631736e..1df8ba1 100644
@@ -706,6 +706,16 @@ config I2C_STU300
 	  This driver can also be built as a module. If so, the module
 	  will be called i2c-stu300.
 
+config I2C_SUNXI
+	tristate "Allwinner A1X I2C controller"
+	depends on ARCH_SUNXI
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C controller embedded in Allwinner A1X SoCs.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called i2c-sunxi.
+
 config I2C_TEGRA
 	tristate "NVIDIA Tegra internal I2C controller"
 	depends on ARCH_TEGRA

drivers/i2c/busses/Makefile +1 -0

index 8f4fc23..7225818 100644
@@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SH_MOBILE)	+= i2c-sh_mobile.o
 obj-$(CONFIG_I2C_SIMTEC)	+= i2c-simtec.o
 obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
+obj-$(CONFIG_I2C_SUNXI)		+= i2c-sunxi.o
 obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
 obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o

drivers/i2c/busses/i2c-sunxi.c new file +444 -0

444 lines not on this page · raw message

Signature · 1 line

1.8.2.3

Wolfram Sang

2013-06-05 13:39 UTC #2 lore raw

PATCH v3 1/6 i2c: sunxi: Add Allwinner A1X i2c driver

Quoted 26 lines

drivers/i2c/busses/i2c-sunxi.c new file +25 -0

+#define SUNXI_I2C_ADDR_REG		(0x00)
+#define SUNXI_I2C_ADDR_ADDR(v)			((v & 0x7f) << 1)
+#define SUNXI_I2C_XADDR_REG		(0x04)
+#define SUNXI_I2C_DATA_REG		(0x08)
+#define SUNXI_I2C_CNTR_REG		(0x0c)
+#define SUNXI_I2C_CNTR_ASSERT_ACK		BIT(2)
+#define SUNXI_I2C_CNTR_INT_FLAG			BIT(3)
+#define SUNXI_I2C_CNTR_MASTER_STOP		BIT(4)
+#define SUNXI_I2C_CNTR_MASTER_START		BIT(5)
+#define SUNXI_I2C_CNTR_BUS_ENABLE		BIT(6)
+#define SUNXI_I2C_CNTR_INT_ENABLE		BIT(7)
+#define SUNXI_I2C_STA_REG		(0x10)
+#define SUNXI_I2C_STA_BUS_ERROR			(0x00)
+#define SUNXI_I2C_STA_START			(0x08)
+#define SUNXI_I2C_STA_START_REPEAT		(0x10)
+#define SUNXI_I2C_STA_MASTER_WADDR_ACK		(0x18)
+#define SUNXI_I2C_STA_MASTER_WADDR_NAK		(0x20)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_ACK	(0x28)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_NAK	(0x30)
+#define SUNXI_I2C_STA_MASTER_RADDR_ACK		(0x40)
+#define SUNXI_I2C_STA_MASTER_RADDR_NAK		(0x48)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_ACK	(0x50)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_NAK	(0x58)
+#define SUNXI_I2C_CCR_REG		(0x14)
+#define SUNXI_I2C_CCR_DIV_N(val)		(val & 0x3)

drivers/i2c/busses/i2c-sunxi.c line 58

Quoted 10 lines

drivers/i2c/busses/i2c-sunxi.c new file +10 -0

+#define SUNXI_I2C_CCR_DIV_M(val)		((val & 0xf) << 3)
+#define SUNXI_I2C_SRST_REG		(0x18)
+#define SUNXI_I2C_SRST_RESET			BIT(0)
+#define SUNXI_I2C_EFR_REG		(0x1c)
+#define SUNXI_I2C_LCR_REG		(0x20)
+
+#define SUNXI_I2C_DONE			BIT(0)
+#define SUNXI_I2C_ERROR			BIT(1)
+#define SUNXI_I2C_NAK			BIT(2)
+#define SUNXI_I2C_BUS_ERROR		BIT(3)

The register set looks similar to i2c-mv64xxx.c. Has it been considered to merge the two drivers?

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Maxime Ripard

author

2013-06-05 21:31 UTC #3 lore raw

PATCH v3 1/6 i2c: sunxi: Add Allwinner A1X i2c driver

Hi Wolfram,

Quoted 31 lines · Wolfram Sang

Quoted 31 lines

drivers/i2c/busses/i2c-sunxi.c new file +30 -0

+#define SUNXI_I2C_ADDR_REG		(0x00)
+#define SUNXI_I2C_ADDR_ADDR(v)			((v & 0x7f) << 1)
+#define SUNXI_I2C_XADDR_REG		(0x04)
+#define SUNXI_I2C_DATA_REG		(0x08)
+#define SUNXI_I2C_CNTR_REG		(0x0c)
+#define SUNXI_I2C_CNTR_ASSERT_ACK		BIT(2)
+#define SUNXI_I2C_CNTR_INT_FLAG			BIT(3)
+#define SUNXI_I2C_CNTR_MASTER_STOP		BIT(4)
+#define SUNXI_I2C_CNTR_MASTER_START		BIT(5)
+#define SUNXI_I2C_CNTR_BUS_ENABLE		BIT(6)
+#define SUNXI_I2C_CNTR_INT_ENABLE		BIT(7)
+#define SUNXI_I2C_STA_REG		(0x10)
+#define SUNXI_I2C_STA_BUS_ERROR			(0x00)
+#define SUNXI_I2C_STA_START			(0x08)
+#define SUNXI_I2C_STA_START_REPEAT		(0x10)
+#define SUNXI_I2C_STA_MASTER_WADDR_ACK		(0x18)
+#define SUNXI_I2C_STA_MASTER_WADDR_NAK		(0x20)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_ACK	(0x28)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_NAK	(0x30)
+#define SUNXI_I2C_STA_MASTER_RADDR_ACK		(0x40)
+#define SUNXI_I2C_STA_MASTER_RADDR_NAK		(0x48)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_ACK	(0x50)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_NAK	(0x58)
+#define SUNXI_I2C_CCR_REG		(0x14)
+#define SUNXI_I2C_CCR_DIV_N(val)		(val & 0x3)
+#define SUNXI_I2C_CCR_DIV_M(val)		((val & 0xf) << 3)
+#define SUNXI_I2C_SRST_REG		(0x18)
+#define SUNXI_I2C_SRST_RESET			BIT(0)
+#define SUNXI_I2C_EFR_REG		(0x1c)
+#define SUNXI_I2C_LCR_REG		(0x20)

Quoted 8 lines

drivers/i2c/busses/i2c-sunxi.c line 58
Quoted 5 lines
drivers/i2c/busses/i2c-sunxi.c new file +5 -0
+
+#define SUNXI_I2C_DONE			BIT(0)
+#define SUNXI_I2C_ERROR			BIT(1)
+#define SUNXI_I2C_NAK			BIT(2)
+#define SUNXI_I2C_BUS_ERROR		BIT(3)
The register set looks similar to i2c-mv64xxx.c. Has it been considered to merge the two drivers?

Hmm, right, the logic seems surprisingly similar. I wasn't aware of such a driver, so I didn't put much thought into merging them :)

However, the register layout is quite different enough to be quite painful to support: the XADDR register here seems to be equivalent to the Marvell's EXT_SLAVE_ADDR register, yet in the allwinner case, the offset is 0x4, while it's 0x1c in Marvell's case, which offsets all the other registers obviously. The status and clock registers in marvell case looks to be merged together, while they are separate registers here, etc.

I guess it would make the code much more complicated for such simple drivers, so I wouldn't push too much for merging, but I guess it's your call.

Thanks!
Maxime

Maxime Ripard

author

2013-06-10 10:08 UTC #4 lore raw

PATCH v3 1/6 i2c: sunxi: Add Allwinner A1X i2c driver

Hi Wolfram,

Quoted 3 lines · Maxime Ripard

I guess it would make the code much more complicated for such simple drivers, so I wouldn't push too much for merging, but I guess it's your call.

I'd like this to be in 3.11, would merging the driver separately for this release and merging it with mv64xxx for 3.12 be acceptable to you ?

Maxime

Signature · 3 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Wolfram Sang

2013-06-11 18:22 UTC #5 lore raw

PATCH v3 1/6 i2c: sunxi: Add Allwinner A1X i2c driver

Quoted 9 lines · Maxime Ripard

Hi Wolfram,
Quoted 3 lines · Maxime Ripard
I guess it would make the code much more complicated for such simple drivers, so I wouldn't push too much for merging, but I guess it's your call.
I'd like this to be in 3.11, would merging the driver separately for this release and merging it with mv64xxx for 3.12 be acceptable to you ?

Thanks for the offer, but the chance of a regression is too high when switching drivers. Also, configs would need updates then, etc...

Wolfram Sang

2013-06-11 18:21 UTC #6 lore raw

PATCH v3 1/6 i2c: sunxi: Add Allwinner A1X i2c driver

In reply to Maxime Ripard

Quoted 43 lines · Maxime Ripard

Hi Wolfram,

Quoted 31 lines · Wolfram Sang

Quoted 31 lines

drivers/i2c/busses/i2c-sunxi.c new file +30 -0

+#define SUNXI_I2C_ADDR_REG		(0x00)
+#define SUNXI_I2C_ADDR_ADDR(v)			((v & 0x7f) << 1)
+#define SUNXI_I2C_XADDR_REG		(0x04)
+#define SUNXI_I2C_DATA_REG		(0x08)
+#define SUNXI_I2C_CNTR_REG		(0x0c)
+#define SUNXI_I2C_CNTR_ASSERT_ACK		BIT(2)
+#define SUNXI_I2C_CNTR_INT_FLAG			BIT(3)
+#define SUNXI_I2C_CNTR_MASTER_STOP		BIT(4)
+#define SUNXI_I2C_CNTR_MASTER_START		BIT(5)
+#define SUNXI_I2C_CNTR_BUS_ENABLE		BIT(6)
+#define SUNXI_I2C_CNTR_INT_ENABLE		BIT(7)
+#define SUNXI_I2C_STA_REG		(0x10)
+#define SUNXI_I2C_STA_BUS_ERROR			(0x00)
+#define SUNXI_I2C_STA_START			(0x08)
+#define SUNXI_I2C_STA_START_REPEAT		(0x10)
+#define SUNXI_I2C_STA_MASTER_WADDR_ACK		(0x18)
+#define SUNXI_I2C_STA_MASTER_WADDR_NAK		(0x20)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_ACK	(0x28)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_NAK	(0x30)
+#define SUNXI_I2C_STA_MASTER_RADDR_ACK		(0x40)
+#define SUNXI_I2C_STA_MASTER_RADDR_NAK		(0x48)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_ACK	(0x50)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_NAK	(0x58)
+#define SUNXI_I2C_CCR_REG		(0x14)
+#define SUNXI_I2C_CCR_DIV_N(val)		(val & 0x3)
+#define SUNXI_I2C_CCR_DIV_M(val)		((val & 0xf) << 3)
+#define SUNXI_I2C_SRST_REG		(0x18)
+#define SUNXI_I2C_SRST_RESET			BIT(0)
+#define SUNXI_I2C_EFR_REG		(0x1c)
+#define SUNXI_I2C_LCR_REG		(0x20)

Quoted 8 lines

drivers/i2c/busses/i2c-sunxi.c line 58
Quoted 5 lines
drivers/i2c/busses/i2c-sunxi.c new file +5 -0
+
+#define SUNXI_I2C_DONE			BIT(0)
+#define SUNXI_I2C_ERROR			BIT(1)
+#define SUNXI_I2C_NAK			BIT(2)
+#define SUNXI_I2C_BUS_ERROR		BIT(3)
The register set looks similar to i2c-mv64xxx.c. Has it been considered to merge the two drivers?

Quoted 2 lines

Hmm, right, the logic seems surprisingly similar. I wasn't aware of such a driver, so I didn't put much thought into merging them :)

Too late now, yet grepping for specific register names is a good thing to do before writing a new driber.

Quoted 11 lines

However, the register layout is quite different enough to be quite painful to support: the XADDR register here seems to be equivalent to the Marvell's EXT_SLAVE_ADDR register, yet in the allwinner case, the offset is 0x4, while it's 0x1c in Marvell's case, which offsets all the other registers obviously. The status and clock registers in marvell case looks to be merged together, while they are separate registers here, etc.
I guess it would make the code much more complicated for such simple drivers, so I wouldn't push too much for merging, but I guess it's your call.

The thing is: If there is a bug/errata found in one driver, it goes unnoticed that it probably should be fixed in the other, too. This is why sharing logic is a good thing from a maintenance view.

Register offsets are annoying, but one can handle them. There are examples in the kernel tree. If some registers are totally different they often can be encapsulated in specific functions processing them.

So, I'd like to ask you if you can prepare a list of what would be needed to merge this support into mv64xxx? Then I get a better picture of what way to go. Can you do this?

Thanks,

Wolfram

Maxime Ripard

author

2013-06-12 08:11 UTC #7 lore raw

PATCH v3 1/6 i2c: sunxi: Add Allwinner A1X i2c driver

Hi Wolfram,

Quoted 3 lines · Wolfram Sang

The thing is: If there is a bug/errata found in one driver, it goes unnoticed that it probably should be fixed in the other, too. This is why sharing logic is a good thing from a maintenance view.

Yes, I definitely understand that.

Quoted 7 lines

Register offsets are annoying, but one can handle them. There are examples in the kernel tree. If some registers are totally different they often can be encapsulated in specific functions processing them.
So, I'd like to ask you if you can prepare a list of what would be needed to merge this support into mv64xxx? Then I get a better picture of what way to go. Can you do this?

I had some time to work on this, I sent you the patches. Except for the register offset parts, the logic of the driver itself needed no modifications, so the only "big" change is to pass the register structure somehow.

Anyway, I just sent to you the patches I had.

Thanks!
Maxime

Signature · 3 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Maxime Ripard

author

2013-05-27 10:00 UTC #8 lore raw

PATCH v3 2/6 ARM: sunxi: dt: Add i2c controller nodes to the DTSI

In reply to Maxime Ripard

The Allwinner A10 and A13 both have 3 i2c controller embedded. Add those to the common sunxi dtsi.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun4i-a10.dtsi | 27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/sun5i-a13.dtsi | 27 +++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

arch/arm/boot/dts/sun4i-a10.dtsi +27 -0

index e7ef619..311dcd4 100644
@@ -292,5 +292,32 @@
 			clocks = <&apb1_gates 23>;
 			status = "disabled";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <7>;
+			clocks = <&apb1_gates 0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <8>;
+			clocks = <&apb1_gates 1>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <9>;
+			clocks = <&apb1_gates 2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
 	};
 };

arch/arm/boot/dts/sun5i-a13.dtsi +27 -0

index 8ba65c1..16df784 100644
@@ -215,5 +215,32 @@
 			clocks = <&apb1_gates 19>;
 			status = "disabled";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <7>;
+			clocks = <&apb1_gates 0>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <8>;
+			clocks = <&apb1_gates 1>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			compatible = "allwinner,sun4i-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <9>;
+			clocks = <&apb1_gates 2>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
 	};
 };

Signature · 1 line

1.8.2.3

Maxime Ripard

author

2013-05-27 10:00 UTC #9 lore raw

PATCH v3 3/6 ARM: sun4i: dt: Add i2c muxing options

In reply to Maxime Ripard

The i2c controller found on the Allwinner A10 has only one muxing option available for each controller. Add them to the dtsi

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun4i-a10.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

arch/arm/boot/dts/sun4i-a10.dtsi +21 -0

index 311dcd4..63f6716 100644
@@ -199,6 +199,27 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			i2c0_pins_a: i2c0 at 0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c1_pins_a: i2c1 at 0 {
+				allwinner,pins = "PB18", "PB19";
+				allwinner,function = "i2c1";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c2_pins_a: i2c2 at 0 {
+				allwinner,pins = "PB20", "PB21";
+				allwinner,function = "i2c2";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
 		};
 
 		timer at 01c20c00 {

Signature · 1 line

1.8.2.3

Maxime Ripard

author

2013-05-27 10:00 UTC #10 lore raw

PATCH v3 4/6 ARM: sun5i: dt: Add i2c muxing options

In reply to Maxime Ripard

The i2c controller found on the Allwinner A13 has only one muxing option available for each controller. Add them to the dtsi

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun5i-a13.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

arch/arm/boot/dts/sun5i-a13.dtsi +21 -0

index 16df784..450b410 100644
@@ -182,6 +182,27 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			i2c0_pins_a: i2c0 at 0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			i2c1_pins_a: i2c1 at 0 {
+				allwinner,pins = "PB15", "PB16";
+				allwinner,function = "i2c1";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
+
+			i2c2_pins_a: i2c2 at 0 {
+				allwinner,pins = "PB17", "PB18";
+				allwinner,function = "i2c2";
+				allwinner,drive = <0>;
+				allwinner,pull = <1>;
+			};
 		};
 
 		timer at 01c20c00 {

Signature · 1 line

1.8.2.3

Maxime Ripard

author

2013-05-27 10:00 UTC #11 lore raw

PATCH v3 5/6 ARM: sun5i: olinuxino: Enable the i2c controllers

In reply to Maxime Ripard

The A13-Olinuxino makes use of the 3 i2c controllers found on the Allwinner A13. Enable them in the device tree.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

arch/arm/boot/dts/sun5i-a13-olinuxino.dts +18 -0

index 3ca5506..80497e3 100644
@@ -37,6 +37,24 @@
 			pinctrl-0 = <&uart1_pins_b>;
 			status = "okay";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			status = "okay";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins_a>;
+			status = "okay";
+		};
+
+		i2c2: i2c at 01c2b400 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2_pins_a>;
+			status = "okay";
+		};
 	};
 
 	leds {

Signature · 1 line

1.8.2.3

Maxime Ripard

author

2013-05-27 10:00 UTC #12 lore raw

PATCH v3 6/6 ARM: sun4i: cubieboard: Enable the i2c controllers

In reply to Maxime Ripard

From: Emilio L?pez <[email protected]>

The Cubieboard makes use of the first two i2c controllers found on the Allwinner A10; i2c-0 is used internally for the PMIC, while i2c-1 is exposed on the board headers. This patch enables them in the device tree.

Signed-off-by Emilio L?pez <[email protected]>

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/boot/dts/sun4i-a10-cubieboard.dts +12 -0

index b70fe0d..0e22a28 100644
@@ -41,6 +41,18 @@
 			pinctrl-0 = <&uart0_pins_a>;
 			status = "okay";
 		};
+
+		i2c0: i2c at 01c2ac00 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins_a>;
+			status = "okay";
+		};
+
+		i2c1: i2c at 01c2b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pins_a>;
+			status = "okay";
+		};
 	};
 
 	leds {

Signature · 1 line

1.8.2.3

Tomasz Figa

2013-05-27 19:17 UTC #13 lore raw

v3 cover Add I2C support for Allwinner SoCs

In reply to Maxime Ripard

Hi Maxime,

Quoted 33 lines · On Monday 27 of May 2013 12:00:37 Maxime Ripard wrote:

Hi,
This patchset adds support for the I2C controller found on most of the Allwinner SoCs, especially the already supported A10 and A13, and the yet to come A31.
It has been tested on a A13-Olinuxino.
Thanks,
Maxime
Changes from v2:
* Slightly modified the switch comments again
* Removed the of_* calls in favor of platform_get_* functions
Changes from v1:
* Added comments to the switch statements to clarify when the fall
through to the next case is made on purpose
* Use devm_ioremap_resource instead of of_iomap
* Moved the reset after enabling the clocks
* Added Emilio Lopez' patch to add the available i2c controllers to
the cubieboard
Emilio L?pez (1):
ARM: sun4i: cubieboard: Enable the i2c controllers
Maxime Ripard (5):
i2c: sunxi: Add Allwinner A1X i2c driver
ARM: sunxi: dt: Add i2c controller nodes to the DTSI
ARM: sun4i: dt: Add i2c muxing options
ARM: sun5i: dt: Add i2c muxing options
ARM: sun5i: olinuxino: Enable the i2c controllers

Quoted 11 lines

 .../devicetree/bindings/i2c/i2c-sunxi.txt          |  19 +
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts         |  12 +
 arch/arm/boot/dts/sun4i-a10.dtsi                   |  48 +++
 arch/arm/boot/dts/sun5i-a13-olinuxino.dts          |  18 +
 arch/arm/boot/dts/sun5i-a13.dtsi                   |  48 +++
 drivers/i2c/busses/Kconfig                         |  10 +
 drivers/i2c/busses/Makefile                        |   1 +
 drivers/i2c/busses/i2c-sunxi.c                     | 444
+++++++++++++++++++++ 8 files changed, 600 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
 create mode 100644 drivers/i2c/busses/i2c-sunxi.c

All the patches look good to me.

Reviewed-by Tomasz Figa <[email protected]>

Best regards,
Tomasz

Maxime Ripard

author

2013-05-29 07:34 UTC #14 lore raw

v3 cover Add I2C support for Allwinner SoCs

Hi Thomas,

Quoted 3 lines · Tomasz Figa

All the patches look good to me.
Reviewed-by Tomasz Figa <[email protected]>

Thanks!
Maxime

Signature · 3 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com