Add I2C support for Allwinner SoCs

The Allwinner i2c controller uses the same logic as the Marvell one, but with slightly different register offsets.

Introduce a structure that will be passed by either the pdata or associated to the compatible strings, and that holds the various registers that might be needed.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/i2c/busses/i2c-mv64xxx.c | 81 +++++++++++++++++++++-------------------
 include/linux/mv643xx_i2c.h      | 27 ++++++++++++--
 2 files changed, 66 insertions(+), 42 deletions(-)

drivers/i2c/busses/i2c-mv64xxx.c +42 -39

index d70a2fda..f9e076e 100644
@@ -19,20 +19,12 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/of_irq.h>
 #include <linux/of_i2c.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 
-/* Register defines */
-#define	MV64XXX_I2C_REG_SLAVE_ADDR			0x00
-#define	MV64XXX_I2C_REG_DATA				0x04
-#define	MV64XXX_I2C_REG_CONTROL				0x08
-#define	MV64XXX_I2C_REG_STATUS				0x0c
-#define	MV64XXX_I2C_REG_BAUD				0x0c
-#define	MV64XXX_I2C_REG_EXT_SLAVE_ADDR			0x10
-#define	MV64XXX_I2C_REG_SOFT_RESET			0x1c
-
 #define MV64XXX_I2C_ADDR_ADDR(val)			((val & 0x7f) << 1)
 #define MV64XXX_I2C_BAUD_DIV_N(val)			(val & 0x7)
 #define MV64XXX_I2C_BAUD_DIV_M(val)			((val & 0xf) << 3)

@@ -98,6 +90,7 @@ struct mv64xxx_i2c_data {
 	u32			aborting;
 	u32			cntl_bits;
 	void __iomem		*reg_base;
+	struct mv64xxx_i2c_regs	*regs;
 	u32			addr1;
 	u32			addr2;
 	u32			bytes_left;

@@ -154,13 +147,13 @@ mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
 static void
 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
 {
-	writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
+	writel(0, drv_data->reg_base + drv_data->regs->soft_reset);
 	writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
-		drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
-	writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
-	writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
+		drv_data->reg_base + drv_data->regs->clock);
+	writel(0, drv_data->reg_base + drv_data->regs->addr);
+	writel(0, drv_data->reg_base + drv_data->regs->ext_addr);
 	writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
-		drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+		drv_data->reg_base + drv_data->regs->control);
 	drv_data->state = MV64XXX_I2C_STATE_IDLE;
 }
 

@@ -282,7 +275,7 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
 
 		drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START;
 		writel(drv_data->cntl_bits,
-			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+			drv_data->reg_base + drv_data->regs->control);
 
 		drv_data->msgs++;
 		drv_data->num_msgs--;

@@ -300,48 +293,48 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
 
 	case MV64XXX_I2C_ACTION_CONTINUE:
 		writel(drv_data->cntl_bits,
-			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+			drv_data->reg_base + drv_data->regs->control);
 		break;
 
 	case MV64XXX_I2C_ACTION_SEND_START:
 		writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
-			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+			drv_data->reg_base + drv_data->regs->control);
 		break;
 
 	case MV64XXX_I2C_ACTION_SEND_ADDR_1:
 		writel(drv_data->addr1,
-			drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+			drv_data->reg_base + drv_data->regs->data);
 		writel(drv_data->cntl_bits,
-			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+			drv_data->reg_base + drv_data->regs->control);
 		break;
 
 	case MV64XXX_I2C_ACTION_SEND_ADDR_2:
 		writel(drv_data->addr2,
-			drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+			drv_data->reg_base + drv_data->regs->data);
 		writel(drv_data->cntl_bits,
-			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+			drv_data->reg_base + drv_data->regs->control);
 		break;
 
 	case MV64XXX_I2C_ACTION_SEND_DATA:
 		writel(drv_data->msg->buf[drv_data->byte_posn++],
-			drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+			drv_data->reg_base + drv_data->regs->data);
 		writel(drv_data->cntl_bits,
-			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+			drv_data->reg_base + drv_data->regs->control);
 		break;
 
 	case MV64XXX_I2C_ACTION_RCV_DATA:
 		drv_data->msg->buf[drv_data->byte_posn++] =
-			readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+			readl(drv_data->reg_base + drv_data->regs->data);
 		writel(drv_data->cntl_bits,
-			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+			drv_data->reg_base + drv_data->regs->control);
 		break;
 
 	case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
 		drv_data->msg->buf[drv_data->byte_posn++] =
-			readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+			readl(drv_data->reg_base + drv_data->regs->data);
 		drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
 		writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
-			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+			drv_data->reg_base + drv_data->regs->control);
 		drv_data->block = 0;
 		wake_up(&drv_data->waitq);
 		break;

@@ -356,7 +349,7 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
 	case MV64XXX_I2C_ACTION_SEND_STOP:
 		drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
 		writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
-			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+			drv_data->reg_base + drv_data->regs->control);
 		drv_data->block = 0;
 		wake_up(&drv_data->waitq);
 		break;

@@ -372,9 +365,9 @@ mv64xxx_i2c_intr(int irq, void *dev_id)
 	irqreturn_t	rc = IRQ_NONE;
 
 	spin_lock_irqsave(&drv_data->lock, flags);
-	while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) &
+	while (readl(drv_data->reg_base + drv_data->regs->control) &
 						MV64XXX_I2C_REG_CONTROL_IFLG) {
-		status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS);
+		status = readl(drv_data->reg_base + drv_data->regs->status);
 		mv64xxx_i2c_fsm(drv_data, status);
 		mv64xxx_i2c_do_action(drv_data);
 		rc = IRQ_HANDLED;

@@ -496,6 +489,12 @@ static const struct i2c_algorithm mv64xxx_i2c_algo = {
  *****************************************************************************
  */
 #ifdef CONFIG_OF
+static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
+	{ .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
+	{}
+};
+MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
+
 static int
 mv64xxx_calc_freq(const int tclk, const int n, const int m)
 {

@@ -528,8 +527,10 @@ mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n,
 
 static int
 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
-		  struct device_node *np)
+		  struct device *dev)
 {
+	const struct of_device_id *device;
+	struct device_node *np = dev->of_node;
 	u32 bus_freq, tclk;
 	int rc = 0;
 

@@ -558,6 +559,13 @@ mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
 	 * So hard code the value to 1 second.
 	 */
 	drv_data->adapter.timeout = HZ;
+
+	device = of_match_device(mv64xxx_i2c_of_match_table, dev);
+	if (!device)
+		return -ENODEV;
+
+	drv_data->regs = (struct mv64xxx_i2c_regs *)device->data;
+
 out:
 	return rc;
 #endif

@@ -565,7 +573,7 @@ out:
 #else /* CONFIG_OF */
 static int
 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
-		  struct device_node *np)
+		  struct device *dev)
 {
 	return -ENODEV;
 }

@@ -611,8 +619,9 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 		drv_data->freq_n = pdata->freq_n;
 		drv_data->irq = platform_get_irq(pd, 0);
 		drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
+		drv_data->regs = pdata->regs;
 	} else if (pd->dev.of_node) {
-		rc = mv64xxx_of_config(drv_data, pd->dev.of_node);
+		rc = mv64xxx_of_config(drv_data, &pd->dev);
 		if (rc)
 			goto exit_clk;
 	}

@@ -680,12 +689,6 @@ mv64xxx_i2c_remove(struct platform_device *dev)
 	return 0;
 }
 
-static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
-	{ .compatible = "marvell,mv64xxx-i2c", },
-	{}
-};
-MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
-
 static struct platform_driver mv64xxx_i2c_driver = {
 	.probe	= mv64xxx_i2c_probe,
 	.remove	= mv64xxx_i2c_remove,

include/linux/mv643xx_i2c.h +24 -3

index 5db5152..9304c94 100644
@@ -12,11 +12,32 @@
 
 #define MV64XXX_I2C_CTLR_NAME	"mv64xxx_i2c"
 
+struct mv64xxx_i2c_regs {
+	u8	addr;
+	u8	ext_addr;
+	u8	data;
+	u8	control;
+	u8	status;
+	u8	clock;
+	u8	soft_reset;
+};
+
+struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
+	.addr		= 0x00,
+	.ext_addr	= 0x10,
+	.data		= 0x04,
+	.control	= 0x08,
+	.status		= 0x0c,
+	.clock		= 0x0c,
+	.soft_reset	= 0x1c,
+};
+
 /* i2c Platform Device, Driver Data */
 struct mv64xxx_i2c_pdata {
-	u32	freq_m;
-	u32	freq_n;
-	u32	timeout;	/* In milliseconds */
+	u32			freq_m;
+	u32			freq_n;
+	struct mv64xxx_i2c_regs *regs;
+	u32			timeout;	/* In milliseconds */
 };
 
 #endif /*_MV64XXX_I2C_H_*/

Signature · 1 line

1.8.3

Quoted 6 lines · Maxime Ripard

The Allwinner i2c controller uses the same logic as the Marvell one, but with slightly different register offsets.

Introduce a structure that will be passed by either the pdata or associated to the compatible strings, and that holds the various registers that might be needed.

Hi Maxime

I don't think this change is bisectable. It assumes the platform data passes the registers, which is not true until the next patch.

Please can you re-arrange the order. Add the extra information to the platform data, and then make use of it, not the other way around.

The Allwinner i2c controller uses the same logic as the Marvell one, but with slightly different register offsets.

Introduce a structure that will be passed by either the pdata or associated to the compatible strings, and that holds the various registers that might be needed.

Quoted 3 lines · Maxime Ripard

The Allwinner i2c controller uses the same logic as the Marvell one, but with slightly different register offsets.

Quoted 3 lines

Introduce a structure that will be passed by either the pdata or associated to the compatible strings, and that holds the various registers that might be needed.

I don't like this change. It introduces further indirection where it's not really necessary, and it's also using platform data to specify this which is in the opposite direction to what's required for moving towards DT.

drivers/i2c/busses/i2c-mv64xxx.c mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data, · line 150

Quoted 6 lines

drivers/i2c/busses/i2c-mv64xxx.c +1 -1

@@ -154,13 +147,13 @@ mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
 static void
 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
 {
-	writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
+	writel(0, drv_data->reg_base + drv_data->regs->soft_reset);

It'd be much better to copy the offsets themselves in drv_data. You're only talking about 7 bytes here, so there's no worry about bloating the drv_data structure.

drivers/i2c/busses/i2c-mv64xxx.c mv64xxx_i2c_probe(struct platform_device *pd) · line 624

Quoted 9 lines

drivers/i2c/busses/i2c-mv64xxx.c +2 -1

@@ -611,8 +619,9 @@ mv64xxx_i2c_probe(struct platform_device *pd)
 		drv_data->freq_n = pdata->freq_n;
 		drv_data->irq = platform_get_irq(pd, 0);
 		drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
+		drv_data->regs = pdata->regs;
 	} else if (pd->dev.of_node) {
-		rc = mv64xxx_of_config(drv_data, pd->dev.of_node);
+		rc = mv64xxx_of_config(drv_data, &pd->dev);

I'd suggest making the default register offsets be the drivers existing offsets, and allowing it to be overriden. That nicely sorts out the next comment below, and also gets rid of it in platform data. Moreover, if you're going to re-use this driver, you should do it via a different "compatible" name in DT, which the driver can then use to identify the different register set layout.

include/linux/mv643xx_i2c.h line 33

Quoted 10 lines

include/linux/mv643xx_i2c.h +9 -0

+struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
+	.addr		= 0x00,
+	.ext_addr	= 0x10,
+	.data		= 0x04,
+	.control	= 0x08,
+	.status		= 0x0c,
+	.clock		= 0x0c,
+	.soft_reset	= 0x1c,
+};

No, this means every file which includes this header ends up defining this structure, which is globally visiable, and therefore its a recipe for link failures.

Hi Russel,

Quoted 3 lines · Russell King - ARM Linux

It'd be much better to copy the offsets themselves in drv_data. You're only talking about 7 bytes here, so there's no worry about bloating the drv_data structure.

It was more about keeping things separated. Moreover, the probe function gets smaller, since you have only a pointer to pass on, instead of assigning those 7 bytes.

Quoted 10 lines · Maxime Ripard

Hi Russel,

Quoted 3 lines · Russell King - ARM Linux

It'd be much better to copy the offsets themselves in drv_data. You're only talking about 7 bytes here, so there's no worry about bloating the drv_data structure.

It was more about keeping things separated. Moreover, the probe function gets smaller, since you have only a pointer to pass on, instead of assigning those 7 bytes.

	struct driver_data {
		struct mv64xxx_i2c_regs reg_offsets;
	};

	struct driver_data *drv_data;

	memcpy(drv_data->reg_offsets, reg_offsets, sizeof(drv_data->reg_offsets));

No need to write it each member as a separate assignment.

Hi Russel,

Quoted 8 lines · Russell King - ARM Linux

Quoted 6 lines · Maxime Ripard

The Allwinner i2c controller uses the same logic as the Marvell one, but with slightly different register offsets.

Introduce a structure that will be passed by either the pdata or associated to the compatible strings, and that holds the various registers that might be needed.

Quoted 4 lines

I don't like this change. It introduces further indirection where it's not really necessary, and it's also using platform data to specify this which is in the opposite direction to what's required for moving towards DT.

Well, some users of this aren't converted to DT, hence why I made the changes to the platform_data.

Quoted 6 lines

I'd suggest making the default register offsets be the drivers existing offsets, and allowing it to be overriden. That nicely sorts out the next comment below, and also gets rid of it in platform data. Moreover, if you're going to re-use this driver, you should do it via a different "compatible" name in DT, which the driver can then use to identify the different register set layout.

The logic here will change quite a bit in the next iteration thanks to the comments I received.

I'm now using a platform_device_id structure to match the name of the driver just like what was done with the DT in that patchset. This also removes the need to add the regs field to the platform data and ...

Quoted 16 lines · Maxime Ripard

Hi Russel,

Quoted 12 lines · Russell King - ARM Linux

Quoted 6 lines · Maxime Ripard

The Allwinner i2c controller uses the same logic as the Marvell one, but with slightly different register offsets.

Introduce a structure that will be passed by either the pdata or associated to the compatible strings, and that holds the various registers that might be needed.

I don't like this change. It introduces further indirection where it's not really necessary, and it's also using platform data to specify this which is in the opposite direction to what's required for moving towards DT.

Quoted 2 lines

Well, some users of this aren't converted to DT, hence why I made the changes to the platform_data.

Actually, this is not quite true. Yes of course, there are still users of non-DT Marvell SoCs and it is still in the progress of full-DT. But also ppc is using DT, except that they parse it and put in in platform_data. Reasonable since back then, there was no global DT API available.

IMHO for the time in between (i.e. now) check for pdev->dev.of_node and !pdev->dev.platform_data will allow you to distinguish all users perfectly:

- non-DT has platform_data set only
- ppc DT has of_node and platform_data set
- pure DT has of_node set only

This will allow you to limit your register offset modifications to Allwinner exclusively and for pure DT (if that is what you want for Allwinner).

Checkout mv643xx_eth in net-next where the above discrimination strategy was chosen.

[...]

Quoted 10 lines

Quoted 6 lines

I'd suggest making the default register offsets be the drivers existing offsets, and allowing it to be overriden. That nicely sorts out the next comment below, and also gets rid of it in platform data. Moreover, if you're going to re-use this driver, you should do it via a different "compatible" name in DT, which the driver can then use to identify the different register set layout.

The logic here will change quite a bit in the next iteration thanks to the comments I received.

Quoted 3 lines

I'm now using a platform_device_id structure to match the name of the driver just like what was done with the DT in that patchset. This also removes the need to add the regs field to the platform data and ...

Also here, if Allwinner is pure DT, you can call some mv643xx_i2c_of_probe() for pure DT only with the above discrimination.

Convert the existing platform data users of the MV64XXX i2c driver to pass the registers offset structure along with the platform data.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/plat-orion/common.c | 2 ++
 1 file changed, 2 insertions(+)

arch/arm/plat-orion/common.c +2 -0

index c019b7a..c166fc9 100644
@@ -509,6 +509,7 @@ void __init orion_ge00_switch_init(struct
 dsa_platform_data *d, int irq)
 ***********************************************************************
 *****/ static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
 	.freq_n		= 3,
+	.regs		= &mv64xxx_i2c_regs_mv64xxx,
 	.timeout	= 1000, /* Default timeout of 1 second */
 };

@@ -524,6 +525,7 @@ static struct platform_device orion_i2c = {
 
 static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = {
 	.freq_n		= 3,
+	.regs		= &mv64xxx_i2c_regs_mv64xxx,
 	.timeout	= 1000, /* Default timeout of 1 second */
 };

Add the compatible string for the Allwinner A10 i2c controller and the associated register layout.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/i2c/busses/Kconfig       |  3 ++-
 drivers/i2c/busses/i2c-mv64xxx.c |  1 +
 include/linux/mv643xx_i2c.h      | 10 ++++++++++
 3 files changed, 13 insertions(+), 1 deletion(-)

drivers/i2c/busses/Kconfig +0 -0

index 631736e..5dc4148 100644

drivers/i2c/busses/Kconfig +1 -0

+	  This driver is also used for Allwinner SoCs I2C controllers.
 
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-mv64xxx.

(quoted diff) +0 -0

b/drivers/i2c/busses/i2c-mv64xxx.c index f9e076e..febf5ba 100644

drivers/i2c/busses/i2c-mv64xxx.c +0 -0

@@ -490,6 +490,7 @@ static const struct i2c_algorithm mv64xxx_i2c_algo =

{ */
#ifdef CONFIG_OF
static const struct of_device_id mv64xxx_i2c_of_match_table[] = {

drivers/i2c/busses/i2c-mv64xxx.c +1 -0

+	{ .compatible = "allwinner,sun4i-i2c", .data =

&mv64xxx_i2c_regs_sun4i}, { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, {}

};

include/linux/mv643xx_i2c.h +0 -0

index 9304c94..737108e 100644
@@ -32,6 +32,16 @@ struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
 	.soft_reset	= 0x1c,
 };
 

include/linux/mv643xx_i2c.h +0 -0

 /* i2c Platform Device, Driver Data */
 struct mv64xxx_i2c_pdata {
 	u32			freq_m;

Hi Maxime,

Quoted 15 lines · On Wednesday 12 of June 2013 10:07:13 Maxime Ripard wrote:

Add the compatible string for the Allwinner A10 i2c controller and the associated register layout.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/i2c/busses/Kconfig       |  3 ++-
 drivers/i2c/busses/i2c-mv64xxx.c |  1 +
 include/linux/mv643xx_i2c.h      | 10 ++++++++++
 3 files changed, 13 insertions(+), 1 deletion(-)

drivers/i2c/busses/Kconfig +0 -0

index 631736e..5dc4148 100644

drivers/i2c/busses/Kconfig config I2C_MPC · line 513

Quoted 8 lines

drivers/i2c/busses/Kconfig +1 -1

@@ -507,10 +507,11 @@ config I2C_MPC
 
 config I2C_MV64XXX
 	tristate "Marvell mv64xxx I2C Controller"
-	depends on (MV64X60 || PLAT_ORION)
+	depends on (MV64X60 || PLAT_ORION || ARCH_SUNXI)
 	help
 	  If you say yes to this option, support will be included for the
 	  built-in I2C interface on the Marvell 64xxx line of host 

bridges.

Quoted 11 lines

drivers/i2c/busses/Kconfig +1 -0

+	  This driver is also used for Allwinner SoCs I2C controllers.
 
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-mv64xxx.

(quoted diff) +0 -0

b/drivers/i2c/busses/i2c-mv64xxx.c index f9e076e..febf5ba 100644

drivers/i2c/busses/i2c-mv64xxx.c +0 -0

@@ -490,6 +490,7 @@ static const struct i2c_algorithm mv64xxx_i2c_algo =

{ */
#ifdef CONFIG_OF

Quoted 4 lines

static const struct of_device_id mv64xxx_i2c_of_match_table[] = {

drivers/i2c/busses/i2c-mv64xxx.c +1 -0

+	{ .compatible = "allwinner,sun4i-i2c", .data =

&mv64xxx_i2c_regs_sun4i}, { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, {}

Ah, OK, here you use compatible matching to get variant-specific data, fine. Still I think the same method (based on platform device name) should be used for non-DT variant.

Quoted 9 lines

};

include/linux/mv643xx_i2c.h +0 -0

index 9304c94..737108e 100644
@@ -32,6 +32,16 @@ struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
 	.soft_reset	= 0x1c,
 };
 

include/linux/mv643xx_i2c.h struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = { · line 44

Quoted 10 lines

include/linux/mv643xx_i2c.h +10 -0

+struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
+	.addr		= 0x00,
+	.ext_addr	= 0x04,
+	.data		= 0x08,
+	.control	= 0x0c,
+	.status		= 0x10,
+	.clock		= 0x14,
+	.soft_reset	= 0x18,
+};
+

Hmm, header doesn't look like a correct place for a structure definition, especially when the structure isn't even static.

Add the compatible string for the Allwinner A10 i2c controller and the associated register layout.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/i2c/busses/Kconfig       |  3 ++-
 drivers/i2c/busses/i2c-mv64xxx.c |  1 +
 include/linux/mv643xx_i2c.h      | 10 ++++++++++
 3 files changed, 13 insertions(+), 1 deletion(-)

drivers/i2c/busses/Kconfig +0 -0

index 631736e..5dc4148 100644

Quoted 15 lines · Maxime Ripard

Add the compatible string for the Allwinner A10 i2c controller and the associated register layout.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/i2c/busses/Kconfig       |  3 ++-
 drivers/i2c/busses/i2c-mv64xxx.c |  1 +
 include/linux/mv643xx_i2c.h      | 10 ++++++++++
 3 files changed, 13 insertions(+), 1 deletion(-)

drivers/i2c/busses/Kconfig +0 -0

index 631736e..5dc4148 100644

drivers/i2c/busses/Kconfig config I2C_MPC · line 510

Quoted 5 lines

drivers/i2c/busses/Kconfig +1 -1

@@ -507,10 +507,11 @@ config I2C_MPC
 
 config I2C_MV64XXX
 	tristate "Marvell mv64xxx I2C Controller"
-	depends on (MV64X60 || PLAT_ORION)
+	depends on (MV64X60 || PLAT_ORION || ARCH_SUNXI)

Hi Maxime.

What about MV64X60? It also needs to pass the registers in its platform data.

ons 2013-06-12 klockan 10:07 +0200 skrev Maxime Ripard:

arch/arm/boot/dts/sun5i-a13.dtsi line 192

Quoted 5 lines

arch/arm/boot/dts/sun5i-a13.dtsi +5 -0

+			i2c0_pins_a: i2c0 at 0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;

Is this right? All other use pull = 1.

I guess it's board dependent depending on if there is external pullups or not on the i2c bus. I have seen Allwinner designs both with and without external pullups.

It will not work well if there is neither internal or external pullup. And may stress the i2c components a bit if there is both..

This patchset adds support for the I2C controller found on most of the Allwinner SoCs, especially the already supported A10 and A13, and the yet to come A31.

This driver leverages the Marvel mv64xxx i2c controller driver, that has an almost identical logic, with a slightly different register layout.

It has been tested on a A13-Olinuxino and an A10s-Olinuxino.

Quoted 5 lines · On Wednesday 12 June 2013 10:07:09 Maxime Ripard wrote:

This patchset adds support for the I2C controller found on most of the Allwinner SoCs, especially the already supported A10 and A13, and the yet to come A31.

Quoted 4 lines

This driver leverages the Marvel mv64xxx i2c controller driver, that has an almost identical logic, with a slightly different register layout.

It has been tested on a A13-Olinuxino and an A10s-Olinuxino.

It doesn't really matter, but can someone clarify why this driver can be reused? Did marvell and allwinner license the same hardware block or is just a really simple driver that does things in an obvious way?

The Marvell and Allwinner controllers share the exact same logic (which is definitely not trivial), based on a finite state machine that triggers interrupts at each change of state, each state being a state in the I2C protocol (like address sent, data received with an ACK, etc.).

The weird thing is that the only difference between the two controllers is the register offsets, and that's it. The state numbers, bit index, etc, are exactly the same.

So yes, I think they both licensed the same IP.

Quoted 8 lines · Maxime Ripard

The Marvell and Allwinner controllers share the exact same logic (which is definitely not trivial), based on a finite state machine that triggers interrupts at each change of state, each state being a state in the I2C protocol (like address sent, data received with an ACK, etc.).

The weird thing is that the only difference between the two controllers is the register offsets, and that's it. The state numbers, bit index, etc, are exactly the same.

Ok, cool. Great someone noticed!

Quoted 1 line

So yes, I think they both licensed the same IP.

I wonder if it's the Mentor Graphics Inventra mi2c block, which would make sense given that Allwinner also uses musb.

Quoted 4 lines

The weird thing is that the only difference between the two controllers is the register offsets, and that's it. The state numbers, bit index, etc, are exactly the same.

Ok, cool. Great someone noticed!