arm: add basic support for Rockchip Cortex-A9 SoCs
Subsystems (5)
Heiko Stübner
maintainerv4 cover arm: add basic support for Rockchip Cortex-A9 SoCs
Fourth version of basic Rockchip A9 support.
Changes since v3:
- split out standalone dw_mmc patches (submitted to linux-mmc)
- Remove divider and mux clocks and use fixed rate clocks instead until divider and mux clocks have got their generic dt bindings
- Make the gate clock use CLK_OF_DECLARE and document the bindings
Changes since v2:
- use common (pending review) HIWORD_MASK clock flag from Haojian Zhuang and me
- pinctrl driver is already in the pinctrl tree
- add core-periph clock that supplies the twd
- split "mmc: dw_mmc-pltfm: add Rockchip variant" into move and feature parts as suggested by Andy Shevchenko
Changes since v1:
- addressed Linus Walleij's comments to the pinctrl driver, including the move to generic pinconfig (hopefully I did catch all)
- renamed the clocks to use the SoC name of the initial user as suggested by Olof Johansson
- fixed the uart address, found by Arnd Bergmann
- address Arnd's comments on the board file (use of_clk_init and friends, remove map_io, use real soc names)
- removed Makefile.boot as suggested by Thomas Petazzoni
Dependencies:
- the 3 clock changes of "support Hisilicon SoC" from Haojian Zhuang (HIWORD_MASK)
- series "dw_apb_timer: osc as sched_clock, clocks and clocksource_of support" which is in arm-soc already
Heiko Stuebner (4):
clk: add support for Rockchip gate clocks
arm: Add basic clocks for Rockchip rk3066a SoCs
arm: add debug uarts for rockchip rk29xx and rk3xxx series
arm: add basic support for Rockchip RK3066a boards
.../devicetree/bindings/clock/rockchip.txt | 74 ++++ arch/arm/Kconfig | 2 + arch/arm/Kconfig.debug | 34 ++ arch/arm/Makefile | 1 + arch/arm/boot/dts/rk3066a-clocks.dtsi | 300 +++++++++++++++ arch/arm/boot/dts/rk3066a.dtsi | 390 ++++++++++++++++++++ arch/arm/include/debug/rockchip.S | 42 +++ arch/arm/mach-rockchip/Kconfig | 16 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rockchip.c | 54 +++ drivers/clk/Makefile | 1 + drivers/clk/rockchip/Makefile | 5 + drivers/clk/rockchip/clk-rockchip.c | 94 +++++ 13 files changed, 1014 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip.txt create mode 100644 arch/arm/boot/dts/rk3066a-clocks.dtsi create mode 100644 arch/arm/boot/dts/rk3066a.dtsi create mode 100644 arch/arm/include/debug/rockchip.S create mode 100644 arch/arm/mach-rockchip/Kconfig create mode 100644 arch/arm/mach-rockchip/Makefile create mode 100644 arch/arm/mach-rockchip/rockchip.c create mode 100644 drivers/clk/rockchip/Makefile create mode 100644 drivers/clk/rockchip/clk-rockchip.c
Signature · 1 line
1.7.10.4
Heiko Stübner
maintainerPATCH v4 1/4 clk: add support for Rockchip gate clocks
This adds basic support for gate-clocks on Rockchip SoCs. There are 16 gates in each register and use the HIWORD_MASK mechanism for changing gate settings.
The gate registers form a continuos block which makes the dt node structure a matter of taste, as either all 160 gates can be put into one gate clock spanning all registers or they can be divided into the 10 individual gates containing 16 clocks each.
The code supports both approaches.
--- .../devicetree/bindings/clock/rockchip.txt | 74 +++++++++++++++ drivers/clk/Makefile | 1 + drivers/clk/rockchip/Makefile | 5 ++ drivers/clk/rockchip/clk-rockchip.c | 94 ++++++++++++++++++++ 4 files changed, 174 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip.txt create mode 100644 drivers/clk/rockchip/Makefile create mode 100644 drivers/clk/rockchip/clk-rockchip.c
Documentation/devicetree/bindings/clock/rockchip.txt new file +74 -0
@@ -0,0 +1,74 @@ +Device Tree Clock bindings for arch-rockchip + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +== Gate clocks == + +The gate registers form a continuos block which makes the dt node +structure a matter of taste, as either all gates can be put into +one gate clock spanning all registers or they can be divided into +the 10 individual gates containing 16 clocks each. +The code supports both approaches. + +Required properties: +- compatible : "rockchip,rk2928-gate-clk" +- reg : shall be the control register address(es) for the clock. +- #clock-cells : from common clock binding; shall be set to 1 +- clock-output-names : the corresponding gate names that the clock controls +- clocks : should contain the parent clock for each individual gate, + therefore the number of clocks elements should match the number of + clock-output-names + +Example using multiple gate clocks: + + clk_gates0: gate-clk at 200000d0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d0 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_core_periph", "gate_cpu_gpll", + "gate_ddrphy", "gate_aclk_cpu", + "gate_hclk_cpu", "gate_pclk_cpu", + "gate_atclk_cpu", "gate_i2s0", + "gate_i2s0_frac", "gate_i2s1", + "gate_i2s1_frac", "gate_i2s2", + "gate_i2s2_frac", "gate_spdif", + "gate_spdif_frac", "gate_testclk"; + + #clock-cells = <1>; + }; + + clk_gates1: gate-clk at 200000d4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d4 0x4>; + clocks = <&xin24m>, <&xin24m>, + <&xin24m>, <&dummy>, + <&dummy>, <&xin24m>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>; + + clock-output-names = + "gate_timer0", "gate_timer1", + "gate_timer2", "gate_jtag", + "gate_aclk_lcdc1_src", "gate_otgphy0", + "gate_otgphy1", "gate_ddr_gpll", + "gate_uart0", "gate_frac_uart0", + "gate_uart1", "gate_frac_uart1", + "gate_uart2", "gate_frac_uart2", + "gate_uart3", "gate_frac_uart3"; + + #clock-cells = <1>; + };
drivers/clk/Makefile +1 -0
@@ -25,6 +25,7 @@ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endif obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
drivers/clk/rockchip/Makefile new file +5 -0
@@ -0,0 +1,5 @@ +# +# Rockchip Clock specific Makefile +# + +obj-y += clk-rockchip.o
drivers/clk/rockchip/clk-rockchip.c new file +94 -0
94 lines not on this page · raw message
Signature · 1 line
1.7.10.4
PATCH v4 1/4 clk: add support for Rockchip gate clocks
Quoting Heiko St?bner (2013-06-13 07:59:40)
Quoted 11 lines
This adds basic support for gate-clocks on Rockchip SoCs. There are 16 gates in each register and use the
HIWORD_MASKmechanism for changing gate settings.The gate registers form a continuos block which makes the dt node structure a matter of taste, as either all 160 gates can be put into one gate clock spanning all registers or they can be divided into the 10 individual gates containing 16 clocks each.
The code supports both approaches.Signed-off-by Heiko Stuebner <[email protected]>
I've taken this patch into clk-next for 3.11. Perhaps in the future the gate-clock binding can be enhanced to allow for this kind of clock globbing and this driver can disappear entirely.
Regards,
Mike
Quoted 215 lines
--- .../devicetree/bindings/clock/rockchip.txt | 74 +++++++++++++++ drivers/clk/Makefile | 1 + drivers/clk/rockchip/Makefile | 5 ++ drivers/clk/rockchip/clk-rockchip.c | 94 ++++++++++++++++++++ 4 files changed, 174 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip.txt create mode 100644 drivers/clk/rockchip/Makefile create mode 100644 drivers/clk/rockchip/clk-rockchip.cDocumentation/devicetree/bindings/clock/rockchip.txt new file +74
-0@@ -0,0 +1,74 @@ +Device Tree Clock bindings for arch-rockchip + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +== Gate clocks == + +The gate registers form a continuos block which makes the dt node +structure a matter of taste, as either all gates can be put into +one gate clock spanning all registers or they can be divided into +the 10 individual gates containing 16 clocks each. +The code supports both approaches. + +Required properties: +- compatible : "rockchip,rk2928-gate-clk" +- reg : shall be the control register address(es) for the clock. +- #clock-cells : from common clock binding; shall be set to 1 +- clock-output-names : the corresponding gate names that the clock controls +- clocks : should contain the parent clock for each individual gate, + therefore the number of clocks elements should match the number of + clock-output-names + +Example using multiple gate clocks: + + clk_gates0: gate-clk at 200000d0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d0 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_core_periph", "gate_cpu_gpll", + "gate_ddrphy", "gate_aclk_cpu", + "gate_hclk_cpu", "gate_pclk_cpu", + "gate_atclk_cpu", "gate_i2s0", + "gate_i2s0_frac", "gate_i2s1", + "gate_i2s1_frac", "gate_i2s2", + "gate_i2s2_frac", "gate_spdif", + "gate_spdif_frac", "gate_testclk"; + + #clock-cells = <1>; + }; + + clk_gates1: gate-clk at 200000d4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d4 0x4>; + clocks = <&xin24m>, <&xin24m>, + <&xin24m>, <&dummy>, + <&dummy>, <&xin24m>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>; + + clock-output-names = + "gate_timer0", "gate_timer1", + "gate_timer2", "gate_jtag", + "gate_aclk_lcdc1_src", "gate_otgphy0", + "gate_otgphy1", "gate_ddr_gpll", + "gate_uart0", "gate_frac_uart0", + "gate_uart1", "gate_frac_uart1", + "gate_uart2", "gate_frac_uart2", + "gate_uart3", "gate_frac_uart3"; + + #clock-cells = <1>; + };drivers/clk/Makefile +1
-0@@ -25,6 +25,7 @@ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endif obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.odrivers/clk/rockchip/Makefile new file +5
-0@@ -0,0 +1,5 @@ +# +# Rockchip Clock specific Makefile +# + +obj-y += clk-rockchip.odrivers/clk/rockchip/clk-rockchip.c new file +94
-0@@ -0,0 +1,94 @@ +/* +* Copyright (c) 2013 MundoReader S.L. +* Author: Heiko Stuebner <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/clk-provider.h> +#include <linux/clkdev.h> +#include <linux/of.h> +#include <linux/of_address.h> + +static DEFINE_SPINLOCK (clk_lock); + +/* +* Gate clocks +*/ + +static void __init rk2928_gate_clk_init (struct device_node *node, +void *data) +{ +struct clk_onecell_data *clk_data; +const char *clk_parent; +const char *clk_name; +void __iomem *reg; +void __iomem *reg_idx; +int flags; +int qty; +int reg_bit; +int clkflags =CLK_SET_RATE_PARENT ; +int i; + + qty =of_property_count_strings (node,"clock-output-names" ); +if (qty <0 ) { +pr_err ("%s: error in clock-output-names %d\n" , __func__, qty); +return ; + } + +if (qty ==0 ) { +pr_info ("%s: nothing to do\n" , __func__); +return ; + } + + reg =of_iomap (node,0 ); + + clk_data =kzalloc (sizeof (struct clk_onecell_data ),GFP_KERNEL ); +if (!clk_data) +return ; + + clk_data->clks =kzalloc (qty *sizeof (struct clk *),GFP_KERNEL ); +if (!clk_data->clks) { +kfree (clk_data); +return ; + } + + flags =CLK_GATE_HIWORD_MASK |CLK_GATE_SET_TO_DISABLE ; + +for (i =0 ; i < qty; i++) { +of_property_read_string_index (node,"clock-output-names" , + i, &clk_name); + +/* ignore empty slots */ +if (!strcmp ("reserved" , clk_name)) +continue ; + + clk_parent =of_clk_get_parent_name (node, i); + +/* keep all gates untouched for now */ + clkflags |=CLK_IGNORE_UNUSED ; + + reg_idx = reg + (4 * (i /16 )); + reg_bit = (i %16 ); + + clk_data->clks[i] =clk_register_gate (NULL , clk_name, + clk_parent, clkflags, + reg_idx, reg_bit, + flags, + &clk_lock); +WARN_ON (IS_ERR (clk_data->clks[i])); + } + + clk_data->clk_num = qty; + +of_clk_add_provider (node, of_clk_src_onecell_get, clk_data); +} +CLK_OF_DECLARE (rk2928_gate,"rockchip,rk2928-gate-clk" , rk2928_gate_clk_init);Signature · 1 line
1.7.10.4
Heiko Stübner
maintainerPATCH v4 2/4 arm: Add basic clocks for Rockchip rk3066a SoCs
In reply to Heiko StübnerThis adds a basic clock setup for rk3066a SoCs. Only the gates are set up currently, as the mux and dividers should use the upcoming generic devicetree bindings.
Clocks whose rates need to be known are supplied by fixed-rate "dummy"-clocks that provide the correct rate. This is uncritical insofar that the only bootloader currently in existence for Rockchip devices is the propietary Rockchip one that always setups the clocks in the necessary way.
--- arch/arm/boot/dts/rk3066a-clocks.dtsi | 300 +++++++++++++++++++++++++++++++++ 1 file changed, 300 insertions(+) create mode 100644 arch/arm/boot/dts/rk3066a-clocks.dtsi
arch/arm/boot/dts/rk3066a-clocks.dtsi new file +300 -0
@@ -0,0 +1,300 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + clocks { + compatible = "rockchip,clocks"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + dummy: dummy { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + dummy48m: dummy48m { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + dummy150m: dummy150m { + compatible = "fixed-clock"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_gates0: gate-clk at 200000d0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d0 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_core_periph", "gate_cpu_gpll", + "gate_ddrphy", "gate_aclk_cpu", + "gate_hclk_cpu", "gate_pclk_cpu", + "gate_atclk_cpu", "gate_i2s0", + "gate_i2s0_frac", "gate_i2s1", + "gate_i2s1_frac", "gate_i2s2", + "gate_i2s2_frac", "gate_spdif", + "gate_spdif_frac", "gate_testclk"; + + #clock-cells = <1>; + }; + + clk_gates1: gate-clk at 200000d4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d4 0x4>; + clocks = <&xin24m>, <&xin24m>, + <&xin24m>, <&dummy>, + <&dummy>, <&xin24m>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>; + + clock-output-names = + "gate_timer0", "gate_timer1", + "gate_timer2", "gate_jtag", + "gate_aclk_lcdc1_src", "gate_otgphy0", + "gate_otgphy1", "gate_ddr_gpll", + "gate_uart0", "gate_frac_uart0", + "gate_uart1", "gate_frac_uart1", + "gate_uart2", "gate_frac_uart2", + "gate_uart3", "gate_frac_uart3"; + + #clock-cells = <1>; + }; + + clk_gates2: gate-clk at 200000d8 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d8 0x4>; + clocks = <&clk_gates2 1>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&clk_gates2 3>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy48m>, + <&dummy>, <&dummy48m>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_periph_src", "gate_aclk_periph", + "gate_hclk_periph", "gate_pclk_periph", + "gate_smc", "gate_mac", + "gate_hsadc", "gate_hsadc_frac", + "gate_saradc", "gate_spi0", + "gate_spi1", "gate_mmc0", + "gate_mac_lbtest", "gate_mmc1", + "gate_emmc", "gate_tsadc"; + + #clock-cells = <1>; + }; + + clk_gates3: gate-clk at 200000dc { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000dc 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", + "gate_dclk_lcdc1", "gate_pclkin_cif0", + "gate_pclkin_cif1", "reserved", + "reserved", "gate_cif0_out", + "gate_cif1_out", "gate_aclk_vepu", + "gate_hclk_vepu", "gate_aclk_vdpu", + "gate_hclk_vdpu", "gate_gpu_src", + "reserved", "gate_xin27m"; + + #clock-cells = <1>; + }; + + clk_gates4: gate-clk at 200000e0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e0 0x4>; + clocks = <&clk_gates2 2>, <&clk_gates2 3>, + <&clk_gates2 1>, <&clk_gates2 1>, + <&clk_gates2 1>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates2 2>, + <&clk_gates0 4>, <&clk_gates0 4>, + <&clk_gates0 3>, <&clk_gates0 3>, + <&clk_gates0 3>, <&clk_gates2 3>, + <&clk_gates0 4>; + + clock-output-names = + "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", + "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", + "gate_aclk_pei_niu", "gate_hclk_usb_peri", + "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", + "gate_hclk_cpubus", "gate_hclk_ahb2apb", + "gate_aclk_strc_sys", "gate_aclk_l2mem_con", + "gate_aclk_intmem", "gate_pclk_tsadc", + "gate_hclk_hdmi"; + + #clock-cells = <1>; + }; + + clk_gates5: gate-clk at 200000e4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e4 0x4>; + clocks = <&clk_gates0 3>, <&clk_gates2 1>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 4>, <&clk_gates0 5>, + <&clk_gates2 1>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates4 5>, + <&clk_gates4 5>, <&dummy>; + + clock-output-names = + "gate_aclk_dmac1", "gate_aclk_dmac2", + "gate_pclk_efuse", "gate_pclk_tzpc", + "gate_pclk_grf", "gate_pclk_pmu", + "gate_hclk_rom", "gate_pclk_ddrupctl", + "gate_aclk_smc", "gate_hclk_nandc", + "gate_hclk_mmc0", "gate_hclk_mmc1", + "gate_hclk_emmc", "gate_hclk_otg0", + "gate_hclk_otg1", "gate_aclk_gpu"; + + #clock-cells = <1>; + }; + + clk_gates6: gate-clk at 200000e8 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e8 0x4>; + clocks = <&clk_gates3 0>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates0 4>, <&clk_gates3 0>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates3 0>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates0 4>, <&clk_gates3 0>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_aclk_lcdc0", "gate_hclk_lcdc0", + "gate_hclk_lcdc1", "gate_aclk_lcdc1", + "gate_hclk_cif0", "gate_aclk_cif0", + "gate_hclk_cif1", "gate_aclk_cif1", + "gate_aclk_ipp", "gate_hclk_ipp", + "gate_hclk_rga", "gate_aclk_rga", + "gate_hclk_vio_bus", "gate_aclk_vio0", + "gate_aclk_vcodec", "gate_shclk_vio_h2h"; + + #clock-cells = <1>; + }; + + clk_gates7: gate-clk at 200000ec { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000ec 0x4>; + clocks = <&clk_gates2 2>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates2 3>; + + clock-output-names = + "gate_hclk_emac", "gate_hclk_spdif", + "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch", + "gate_hclk_i2s_8ch", "gate_hclk_hsadc", + "gate_hclk_pidf", "gate_pclk_timer0", + "gate_pclk_timer1", "gate_pclk_timer2", + "gate_pclk_pwm01", "gate_pclk_pwm23", + "gate_pclk_spi0", "gate_pclk_spi1", + "gate_pclk_saradc", "gate_pclk_wdt"; + + #clock-cells = <1>; + }; + + clk_gates8: gate-clk at 200000f0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000f0 0x4>; + clocks = <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&dummy>, <&clk_gates0 5>; + + clock-output-names = + "gate_pclk_uart0", "gate_pclk_uart1", + "gate_pclk_uart2", "gate_pclk_uart3", + "gate_pclk_i2c0", "gate_pclk_i2c1", + "gate_pclk_i2c2", "gate_pclk_i2c3", + "gate_pclk_i2c4", "gate_pclk_gpio0", + "gate_pclk_gpio1", "gate_pclk_gpio2", + "gate_pclk_gpio3", "gate_pclk_gpio4", + "reserved", "gate_pclk_gpio6"; + + #clock-cells = <1>; + }; + + clk_gates9: gate-clk at 200000f4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000f4 0x4>; + clocks = <&dummy>, <&clk_gates0 5>, + <&dummy>, <&dummy>, + <&dummy>, <&clk_gates1 4>, + <&clk_gates0 5>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>; + + clock-output-names = + "gate_clk_core_dbg", "gate_pclk_dbg", + "gate_clk_trace", "gate_atclk", + "gate_clk_l2c", "gate_aclk_vio1", + "gate_pclk_publ", "gate_aclk_intmem0", + "gate_aclk_intmem1", "gate_aclk_intmem2", + "gate_aclk_intmem3"; + + #clock-cells = <1>; + }; + }; + +};
Signature · 1 line
1.7.10.4
Heiko Stübner
maintainerPATCH v4 3/4 arm: add debug uarts for rockchip rk29xx and rk3xxx series
In reply to Heiko StübnerUarts on all recent Rockchip SoCs are Synopsis DesignWare 8250 types. Only their addresses vary very much.
This patch adds the necessary definitions to use any of the uart ports for early debug purposes.
--- arch/arm/Kconfig.debug | 34 ++++++++++++++++++++++++++++++ arch/arm/include/debug/rockchip.S | 42 +++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 arch/arm/include/debug/rockchip.S
arch/arm/Kconfig.debug +34 -0
@@ -360,6 +360,13 @@ choice their output to the standard serial port on the RealView PB1176 platform. + config DEBUG_ROCKCHIP_UART + bool "Kernel low-level debugging messages via Rockchip UART" + depends on ARCH_ROCKCHIP + help + Say Y here if you want kernel low-level debugging support + on Rockchip based platforms. + config DEBUG_S3C_UART0 depends on PLAT_SAMSUNG select DEBUG_EXYNOS_UART if ARCH_EXYNOS
@@ -597,6 +604,32 @@ endchoice choice prompt "Low-level debug console UART" + depends on DEBUG_ROCKCHIP_UART + + config DEBUG_RK29_UART0 + bool "RK29 UART0" + + config DEBUG_RK29_UART1 + bool "RK29 UART1" + + config DEBUG_RK29_UART2 + bool "RK29 UART2" + + config DEBUG_RK3X_UART0 + bool "RK3X UART0" + + config DEBUG_RK3X_UART1 + bool "RK3X UART1" + + config DEBUG_RK3X_UART2 + bool "RK3X UART2" + + config DEBUG_RK3X_UART3 + bool "RK3X UART3" +endchoice + +choice + prompt "Low-level debug console UART" depends on DEBUG_LL && DEBUG_TEGRA_UART config TEGRA_DEBUG_UART_AUTO_ODMDATA
@@ -648,6 +681,7 @@ config DEBUG_LL_INCLUDE default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \ DEBUG_MMP_UART3 + default "debug/rockchip.S" if DEBUG_ROCKCHIP_UART default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
arch/arm/include/debug/rockchip.S new file +42 -0
42 lines not on this page · raw message
Signature · 1 line
1.7.10.4
Heiko Stübner
maintainerPATCH v4 4/4 arm: add basic support for Rockchip RK3066a boards
In reply to Heiko StübnerThis adds a generic devicetree board file and a dtsi for boards based on the RK3066a SoCs from Rockchip.
Apart from the generic parts (gic, clocks, pinctrl) the only components currently supported are the timers, uarts and mmc ports (all DesignWare- based).
--- arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/boot/dts/rk3066a.dtsi | 390 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 16 ++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rockchip.c | 54 +++++ 6 files changed, 464 insertions(+) create mode 100644 arch/arm/boot/dts/rk3066a.dtsi create mode 100644 arch/arm/mach-rockchip/Kconfig create mode 100644 arch/arm/mach-rockchip/Makefile create mode 100644 arch/arm/mach-rockchip/rockchip.c
arch/arm/Kconfig +2 -0
@@ -983,6 +983,8 @@ source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-realview/Kconfig" +source "arch/arm/mach-rockchip/Kconfig" + source "arch/arm/mach-sa1100/Kconfig" source "arch/arm/plat-samsung/Kconfig"
arch/arm/Makefile +1 -0
@@ -172,6 +172,7 @@ machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell machine-$(CONFIG_ARCH_PRIMA2) += prima2 machine-$(CONFIG_ARCH_PXA) += pxa machine-$(CONFIG_ARCH_REALVIEW) += realview +machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_RPC) += rpc machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx
arch/arm/boot/dts/rk3066a.dtsi new file +390 -0
390 lines not on this page · raw message
arch/arm/mach-rockchip/Kconfig new file +16 -0
@@ -0,0 +1,16 @@ +config ARCH_ROCKCHIP + bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7 + select PINCTRL + select PINCTRL_ROCKCHIP + select ARCH_REQUIRE_GPIOLIB + select ARM_GIC + select CACHE_L2X0 + select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_SMP + select LOCAL_TIMERS if SMP + select COMMON_CLK + select GENERIC_CLOCKEVENTS + select DW_APB_TIMER_OF + help + Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs + containing the RK2928, RK30xx and RK31xx series.
arch/arm/mach-rockchip/Makefile new file +1 -0
@@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
arch/arm/mach-rockchip/rockchip.c new file +54 -0
54 lines not on this page · raw message
Signature · 1 line
1.7.10.4
PATCH v4 4/4 arm: add basic support for Rockchip RK3066a boards
Hi,
Just some small comments below. Once fixed:
Review
Quoted 2 lines · Heiko St?bner
(quoted diff) +2
-0+ dwmmc at 10214000 { + compatible = "rockchip,rk2928-dw-mshc";
does it make sense to fall back and also specify "snps,dw-mshc"?
Quoted 34 lines
arch/arm/mach-rockchip/rockchip.c new file +28
-0@@ -0,0 +1,54 @@ +/* +* Device Tree support for Rockchip SoCs +* +* Copyright (c) 2013 MundoReader S.L. +* Author: Heiko Stuebner <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/of_platform.h> +#include <linux/irqchip.h> +#include <linux/dw_apb_timer.h> +#include <linux/clk-provider.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/hardware/cache-l2x0.h> + +static void __init rockchip_timer_init (void )
arch/arm/mach-rockchip/rockchip.c line 38
Quoted 10 lines
arch/arm/mach-rockchip/rockchip.c new file +10
-0+{ +of_clk_init (NULL ); +clocksource_of_init (); +} + +static void __init rockchip_dt_init (void ) +{ +#ifdef CONFIG_CACHE_L2X0 +l2x0_of_init (0 , ~0UL ); +#endif
No need to ifdef, there's a stub if CONFIG_CACHE_L2X0 isn't defined.
Side comment: I think it would be nice if the generic code did this init if a l2x0 device node was in the device tree, since the only reason to override init_machine is to do this call in addition to of_platform_populate().
Quoted 16 lines
arch/arm/mach-rockchip/rockchip.c new file +16
-0+of_platform_populate (NULL , of_default_bus_match_table,NULL ,NULL ); +} + +static const char *const rockchip_board_dt_compat[] = { +"rockchip,rk2928" , +"rockchip,rk3066a" , +"rockchip,rk3066b" , +"rockchip,rk3188" , +NULL , +}; + +DT_MACHINE_START (ROCKCHIP_DT ,"Rockchip Cortex-A9 (Device Tree)" ) + .init_machine = rockchip_dt_init, + .init_time = rockchip_timer_init, + .dt_compat = rockchip_board_dt_compat, +MACHINE_END
Heiko Stübner
maintainerPATCH v4 4/4 arm: add basic support for Rockchip RK3066a boards
Am Montag, 17. Juni 2013, 23:35:15 schrieb Olof Johansson:
Quoted 11 lines
Hi,
Just some small comments below. Once fixed:
Acked-by Olof Johansson <[email protected]>Review
Quoted 2 lines · Heiko St?bner
(quoted diff) +2
-0+ dwmmc at 10214000 { + compatible = "rockchip,rk2928-dw-mshc";does it make sense to fall back and also specify "snps,dw-mshc"?
nope, the rockchip-variant is necessary, with the regular dw-mshc it doesn't work at all.
Quoted 38 lines
Quoted 38 lines
(quoted diff) +0
-0
b/arch/arm/mach-rockchip/rockchip.cnew file mode 100644 index 0000000..0933e17arch/arm/mach-rockchip/rockchip.c new file +32
-0@@ -0,0 +1,54 @@ +/* +* Device Tree support for Rockchip SoCs +* +* Copyright (c) 2013 MundoReader S.L. +* Author: Heiko Stuebner <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/of_platform.h> +#include <linux/irqchip.h> +#include <linux/dw_apb_timer.h> +#include <linux/clk-provider.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/hardware/cache-l2x0.h> + +static void __init rockchip_timer_init (void ) +{ +of_clk_init (NULL ); +clocksource_of_init (); +}
Quoted 8 lines
arch/arm/mach-rockchip/rockchip.c line 38
Quoted 6 lines
arch/arm/mach-rockchip/rockchip.c new file +6
-0+ +static void __init rockchip_dt_init (void ) +{ +#ifdef CONFIG_CACHE_L2X0 +l2x0_of_init (0 , ~0UL ); +#endif No need to ifdef, there's a stub if
CONFIG_CACHE_L2X0isn't defined.
ok
Quoted 4 lines
Side comment: I think it would be nice if the generic code did this init if a l2x0 device node was in the device tree, since the only reason to override
init_machineis to do this call in addition toof_platform_populate().
Arnd said similar things in the initial version :-).
Currently I'm wondering if it wouldn't be enough to call always l2x0_of_init somewhere, because it does the checking for the dt nodes itself already.
The only obstacle would be platforms having the need to use special aux-values or which are currently calling the function from some other parts of the boot process (tegra inits the cache in its tegra_init_early function for example).
Quoted 16 lines
Quoted 16 lines
arch/arm/mach-rockchip/rockchip.c new file +16
-0+of_platform_populate (NULL , of_default_bus_match_table,NULL ,NULL ); +} + +static const char *const rockchip_board_dt_compat[] = { +"rockchip,rk2928" , +"rockchip,rk3066a" , +"rockchip,rk3066b" , +"rockchip,rk3188" , +NULL , +}; + +DT_MACHINE_START (ROCKCHIP_DT ,"Rockchip Cortex-A9 (Device Tree)" ) + .init_machine = rockchip_dt_init, + .init_time = rockchip_timer_init, + .dt_compat = rockchip_board_dt_compat, +MACHINE_END
PATCH v4 4/4 arm: add basic support for Rockchip RK3066a boards
Quoted 5 lines · Heiko St?bner
Quoted 4 lines
Side comment: I think it would be nice if the generic code did this init if a l2x0 device node was in the device tree, since the only reason to override
init_machineis to do this call in addition toof_platform_populate().
Quoted 8 lines
Arnd said similar things in the initial version :-).
Currently I'm wondering if it wouldn't be enough to call always
l2x0_of_initsomewhere, because it does the checking for the dt nodes itself already.The only obstacle would be platforms having the need to use special aux-values or which are currently calling the function from some other parts of the boot process (tegra inits the cache in its
tegra_init_earlyfunction for example).
I think we can handle this by ensuring the function only gets called once, and all platforms with special requirements call it before the common code does.
I tried to understand what the requirement for non-zero argument is however and couldn't figure it out. Shouldn't we just be able to specify all the bits as DT properties all the time?
Arnd