support Hisilicon SoC

PATCH Superseded Haojian Zhuang 5 participants 18 messages Jun 8, 2013 – Jun 18, 2013

Subsystems (5)

Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +1 more subsystems

lore

Share & tools

lore

Haojian Zhuang

author

2013-06-08 14:47 UTC #0 lore raw

v4 cover support Hisilicon SoC

Changelog:
v4:
1. Add clk gate with HIWORD mask for Rockchip.
2. Update comments and code of HIWORD flags for mux/divider.
3. Append a mux without HIWORD mask in Hisilicon 3620.
4. Fix the pinmux setting in Hi4511.

v3:
1. Use clk_register_mux_table().

v2:
1. Reuse mux & divider driver. So append CLK_MUX_HIWORD_MASK & CLK_DIVIDER_HIWORD_MASK for Hi3620 SoC.
2. Fix system timer running too fast because wrong divider is choosen.
3. Remove .init_irq in DT machine descriptor.

Haojian Zhuang

author

2013-06-08 14:47 UTC #1 lore raw

PATCH v4 1/7 clk: mux: add CLK_MUX_HIWORD_MASK

In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits.

When b01 should be set as switching mux, it also needs to indicate the change by setting hiword mask (b11 << 16).

The patch adds mux flag for this usage.

Signed-off-by Heiko Stuebner <[email protected]>

Signed-off-by Haojian Zhuang <[email protected]>

---
 drivers/clk/clk-mux.c        | 17 +++++++++++++++--
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 20 insertions(+), 2 deletions(-)

drivers/clk/clk-mux.c +15 -2

index 25b1734..614444c 100644
@@ -86,8 +86,12 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 	if (mux->lock)
 		spin_lock_irqsave(mux->lock, flags);
 
-	val = readl(mux->reg);
-	val &= ~(mux->mask << mux->shift);
+	if (mux->flags & CLK_MUX_HIWORD_MASK) {
+		val = mux->mask << (mux->shift + 16);
+	} else {
+		val = readl(mux->reg);
+		val &= ~(mux->mask << mux->shift);
+	}
 	val |= index << mux->shift;
 	writel(val, mux->reg);

@@ -111,6 +115,15 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
 	struct clk_mux *mux;
 	struct clk *clk;
 	struct clk_init_data init;
+	u8 width = 0;
+
+	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
+		width = fls(mask) - ffs(mask) + 1;
+		if (width + shift > 16) {
+			pr_err("mux value exceeds LOWORD field\n");
+			return ERR_PTR(-EINVAL);
+		}
+	}
 
 	/* allocate the mux */
 	mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);

include/linux/clk-provider.h +5 -0

index 1186098..fecef88 100644
@@ -299,6 +299,10 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
  * Flags:
  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
+ * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
+ *   register, and mask of mux bits are in higher 16-bit of this register.
+ *   While setting the mux bits, higher 16-bit should also be updated to
+ *   indicate changing mux bits.
  */
 struct clk_mux {
 	struct clk_hw	hw;

@@ -312,6 +316,7 @@ struct clk_mux {
 
 #define CLK_MUX_INDEX_ONE		BIT(0)
 #define CLK_MUX_INDEX_BIT		BIT(1)
+#define CLK_MUX_HIWORD_MASK		BIT(2)
 
 extern const struct clk_ops clk_mux_ops;

Signature · 1 line

1.8.1.2

Haojian Zhuang

author

2013-06-08 14:47 UTC #2 lore raw

PATCH v4 2/7 clk: divider: add CLK_DIVIDER_HIWORD_MASK flag

In reply to Haojian Zhuang

In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits.

When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16).

The patch adds divider flag for this usage.

Signed-off-by Heiko Stuebner <[email protected]>

Signed-off-by Haojian Zhuang <[email protected]>

---
 drivers/clk/clk-divider.c    | 15 +++++++++++++--
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 18 insertions(+), 2 deletions(-)

drivers/clk/clk-divider.c +13 -2

index 6d96741..ce5cfe9 100644
@@ -217,8 +217,12 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 	if (divider->lock)
 		spin_lock_irqsave(divider->lock, flags);
 
-	val = readl(divider->reg);
-	val &= ~(div_mask(divider) << divider->shift);
+	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+		val = div_mask(divider) << (divider->shift + 16);
+	} else {
+		val = readl(divider->reg);
+		val &= ~(div_mask(divider) << divider->shift);
+	}
 	val |= value << divider->shift;
 	writel(val, divider->reg);

@@ -245,6 +249,13 @@ static struct clk *_register_divider(struct device *dev, const char *name,
 	struct clk *clk;
 	struct clk_init_data init;
 
+	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
+		if (width + shift > 16) {
+			pr_warn("divider value exceeds LOWORD field\n");
+			return ERR_PTR(-EINVAL);
+		}
+	}
+
 	/* allocate the divider */
 	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
 	if (!div) {

include/linux/clk-provider.h +5 -0

index fecef88..8e45fd9 100644
@@ -257,6 +257,10 @@ struct clk_div_table {
  *	Some hardware implementations gracefully handle this case and allow a
  *	zero divisor by not modifying their input clock
  *	(divide by one / bypass).
+ * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
+ *   of this register, and mask of divider bits are in higher 16-bit of this
+ *   register.  While setting the divider bits, higher 16-bit should also be
+ *   updated to indicate changing divider bits.
  */
 struct clk_divider {
 	struct clk_hw	hw;

@@ -271,6 +275,7 @@ struct clk_divider {
 #define CLK_DIVIDER_ONE_BASED		BIT(0)
 #define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
 #define CLK_DIVIDER_ALLOW_ZERO		BIT(2)
+#define CLK_DIVIDER_HIWORD_MASK		BIT(3)
 
 extern const struct clk_ops clk_divider_ops;
 struct clk *clk_register_divider(struct device *dev, const char *name,

Signature · 1 line

1.8.1.2

Haojian Zhuang

author

2013-06-08 14:47 UTC #3 lore raw

PATCH v4 3/7 clk: gate: add CLK_GATE_HIWORD_MASK

In reply to Haojian Zhuang

In Rockchip Cortex-A9 based chips, they don't use paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits.

When b1 should be set as gate, it also needs to indicate the change by setting hiword mask (b1 << 16).

The patch adds gate flag for this usage.

Signed-off-by Heiko Stuebner <[email protected]>

Signed-off-by Haojian Zhuang <[email protected]>

---
 drivers/clk/clk-gate.c       | 25 +++++++++++++++++++------
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 24 insertions(+), 6 deletions(-)

drivers/clk/clk-gate.c +19 -6

index 15114fe..790306e 100644
@@ -53,12 +53,18 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
 	if (gate->lock)
 		spin_lock_irqsave(gate->lock, flags);
 
-	reg = readl(gate->reg);
-
-	if (set)
-		reg |= BIT(gate->bit_idx);
-	else
-		reg &= ~BIT(gate->bit_idx);
+	if (gate->flags & CLK_GATE_HIWORD_MASK) {
+		reg = BIT(gate->bit_idx + 16);
+		if (set)
+			reg |= BIT(gate->bit_idx);
+	} else {
+		reg = readl(gate->reg);
+
+		if (set)
+			reg |= BIT(gate->bit_idx);
+		else
+			reg &= ~BIT(gate->bit_idx);
+	}
 
 	writel(reg, gate->reg);

@@ -121,6 +127,13 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
 	struct clk *clk;
 	struct clk_init_data init;
 
+	if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
+		if (bit_idx > 16) {
+			pr_err("gate bit exceeds LOWORD field\n");
+			return ERR_PTR(-EINVAL);
+		}
+	}
+
 	/* allocate the gate */
 	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
 	if (!gate) {

include/linux/clk-provider.h +5 -0

index 8e45fd9..8418b6f 100644
@@ -210,6 +210,10 @@ void of_fixed_clk_setup(struct device_node *np);
  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
  * 	enable the clock.  Setting this flag does the opposite: setting the bit
  * 	disable the clock and clearing it enables the clock
+ * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
+ *   of this register, and mask of gate bits are in higher 16-bit of this
+ *   register.  While setting the gate bits, higher 16-bit should also be
+ *   updated to indicate changing gate bits.
  */
 struct clk_gate {
 	struct clk_hw hw;

@@ -220,6 +224,7 @@ struct clk_gate {
 };
 
 #define CLK_GATE_SET_TO_DISABLE		BIT(0)
+#define CLK_GATE_HIWORD_MASK		BIT(1)
 
 extern const struct clk_ops clk_gate_ops;
 struct clk *clk_register_gate(struct device *dev, const char *name,

Signature · 1 line

1.8.1.2

Haojian Zhuang

author

2013-06-08 14:47 UTC #4 lore raw

PATCH v4 4/7 clk: hi3xxx: add clock support

In reply to Haojian Zhuang

Add clock support with device tree on Hisilicon SoC.

Signed-off-by Haojian Zhuang <[email protected]>

Cc Mike Turquette <[email protected]>

---
 .../devicetree/bindings/clock/hisilicon.txt        |  66 ++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-hi3xxx.c                           | 413 +++++++++++++++++++++
 3 files changed, 480 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hisilicon.txt
 create mode 100644 drivers/clk/clk-hi3xxx.c

Documentation/devicetree/bindings/clock/hisilicon.txt new file +66 -0

new file mode 100644
index 0000000..7f99805
@@ -0,0 +1,66 @@
+Device Tree Clock bindings for arch-hi3xxx
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties for mux clocks:
+ - compatible : Shall be "hisilicon,hi3620-clk-mux".
+ - clocks : shall be the input parent clock phandle for the clock. This should
+	be the reference clock.
+ - clock-output-names : shall be reference name.
+ - #clock-cells : from common clock binding; shall be set to 0.
+ - hisilicon,clkmux-reg : array of mux register offset & mask bits
+ - hisilicon,clkmux-table : array of mux select bits
+
+Required properties for Hi3620 gate clocks:
+ - compatible : Shall be "hisilicon,hi3620-clk-gate".
+ - clocks : shall be the input parent clock phandle for the clock. This should
+	be the reference clock.
+ - clock-output-names : shall be reference name.
+ - #clock-cells : from common clock binding; shall be set to 0.
+ - hisilicon,hi3620-clkgate : array of enable register offset & enable bits
+ - hisilicon,hi3620-clkreset : array of reset register offset & enable bits
+
+Required properties for clock divider:
+ - compatible : Shall be "hisilicon,hi3620-clk-div".
+ - clocks : shall be the input parent clock phandle for the clock. This should
+	be the reference clock.
+ - clock-output-names : shall be reference name.
+ - #clock-cells : from common clock binding; shall be set to 0.
+ - #hisilicon,clkdiv-table-cells : the number of parameters after phandle in
+   hisilicon,clkdiv-table property.
+ - hisilicon,clkdiv-table : list of value that are used to configure clock
+   divider. They're value of phandle, index & divider value.
+ - hisilicon,clkdiv : array of divider register offset & mask bits.
+
+Required properties for gate clocks:
+ - compatible : Shall be "hisilicon,clk-gate".
+ - clocks : shall be the input parent clock phandle for the clock. This should
+	be the reference clock.
+ - clock-output-names : shall be reference name.
+ - #clock-cells : from common clock binding; shall be set to 0.
+ - hisilicon,clkgate-inverted : bool value. True means that set-to-disable.
+
+For example:
+	timclk1: clkgate at 38 {
+		compatible = "hisilicon,clk-gate";
+		#clock-cells = <0>;
+		clocks = <&refclk_timer1>;
+		clock-output-names = "timclk1";
+		hisilicon,clkgate-inverted;
+		hisilicon,clkgate = <0 18>;
+	};
+
+	dtable: clkdiv at 0 {
+		#hisilicon,clkdiv-table-cells = <2>;
+	};
+
+	div_cfgaxi: clkdiv at 2 {
+		compatible = "hisilicon,hi3620-clk-div";
+		#clock-cells = <0>;
+		clocks = <&div_shareaxi>;
+		clock-output-names = "cfgAXI_div";
+		hisilicon,clkdiv-table = <&dtable 0x01 2>;
+		hisilicon,clkdiv = <0x100 0x60>;
+	};

drivers/clk/Makefile +1 -0

index 137d3e7..522e8d1 100644
@@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
 # SoCs specific
 obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835.o
 obj-$(CONFIG_ARCH_NOMADIK)	+= clk-nomadik.o
+obj-$(CONFIG_ARCH_HI3xxx)	+= clk-hi3xxx.o
 obj-$(CONFIG_ARCH_HIGHBANK)	+= clk-highbank.o
 obj-$(CONFIG_ARCH_MXS)		+= mxs/
 obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/

drivers/clk/clk-hi3xxx.c new file +413 -0

413 lines not on this page · raw message

Signature · 1 line

1.8.1.2

Haojian Zhuang

author

2013-06-08 14:47 UTC #5 lore raw

PATCH v4 5/7 ARM: debug: support debug ll on hisilicon soc

In reply to Haojian Zhuang

Support UART0 debug ll on hisilicon Hi3620 SoC.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig.debug             | 15 +++++++++++++++
 arch/arm/include/debug/hisilicon.S | 30 ++++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+)
 create mode 100644 arch/arm/include/debug/hisilicon.S

arch/arm/Kconfig.debug +15 -0

index 1d41908..7396572 100644
@@ -251,6 +251,20 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on i.MX6Q/DL.
 
+	config DEBUG_HI3620_UART
+		bool "Hisilicon HI3620 Debug UART"
+		depends on ARCH_HI3xxx
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on HI3620 UART.
+
+	config DEBUG_HI3716_UART
+		bool "Hisilicon Hi3716 Debug UART"
+		depends on ARCH_HI3xxx
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on HI3716 UART.
+
 	config DEBUG_MMP_UART2
 		bool "Kernel low-level debugging message via MMP UART2"
 		depends on ARCH_MMP

@@ -623,6 +637,7 @@ config DEBUG_LL_INCLUDE
 	default "debug/cns3xxx.S" if DEBUG_CNS3XXX
 	default "debug/exynos.S" if DEBUG_EXYNOS_UART
 	default "debug/highbank.S" if DEBUG_HIGHBANK_UART
+	default "debug/hisilicon.S" if DEBUG_HI3620_UART || DEBUG_HI3716_UART
 	default "debug/icedcc.S" if DEBUG_ICEDCC
 	default "debug/imx.S" if DEBUG_IMX1_UART || \
 				 DEBUG_IMX25_UART || \

arch/arm/include/debug/hisilicon.S new file +30 -0

new file mode 100644
index 0000000..47ad019
@@ -0,0 +1,30 @@
+/*
+ * Early serial output macro for Hisilicon SoC
+ *
+ * Copyright (C) 2012-2013 Hisilicon Technologies Co., Ltd.
+ * Copyright (C) 2012-2013 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#if defined(CONFIG_DEBUG_HI3620_UART)
+#define HS_UART_PHYS_BASE	0xfcb00000
+#define HS_UART_VIRT_BASE	0xfeb00000
+#elif defined(CONFIG_DEBUG_HI3716_UART)
+#define HS_UART_PHYS_BASE	0xf8b00000
+#define HS_UART_VIRT_BASE	0xfeb00000
+#endif
+
+#if defined(CONFIG_DEBUG_HI3620_UART) || defined(CONFIG_DEBUG_HI3716_UART)
+		.macro	addruart,rp,rv,tmp
+		ldr	\rp, =HS_UART_PHYS_BASE
+		ldr	\rv, =HS_UART_VIRT_BASE
+		.endm
+
+#include <asm/hardware/debug-pl01x.S>
+
+#endif

Signature · 1 line

1.8.1.2

Haojian Zhuang

author

2013-06-08 14:47 UTC #6 lore raw

PATCH v4 6/7 ARM: hi3xxx: add board support with device tree

In reply to Haojian Zhuang

Add board support with device tree for Hisilicon Hi36xx/Hi37xx platform.

Changelog:
v3:
1. Remove .map_io() in DT machine descriptor. Since debug_ll_io_init() is called by default.
2. Remove .init_machine() in DT machine descriptor. Since of_platform_populate() is called by default in DT mode.

v2:
1. Remove .init_irq() in DT machine descriptor. Since irqchip_init() is called by default in DT mode.

Signed-off-by Haojian Zhuang <[email protected]>

---
 .../bindings/arm/hisilicon/hisilicon.txt           | 10 ++++++
 arch/arm/Kconfig                                   |  2 ++
 arch/arm/Makefile                                  |  1 +
 arch/arm/mach-hi3xxx/Kconfig                       | 13 ++++++++
 arch/arm/mach-hi3xxx/Makefile                      |  5 +++
 arch/arm/mach-hi3xxx/hi3xxx.c                      | 37 ++++++++++++++++++++++
 6 files changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
 create mode 100644 arch/arm/mach-hi3xxx/Kconfig
 create mode 100644 arch/arm/mach-hi3xxx/Makefile
 create mode 100644 arch/arm/mach-hi3xxx/hi3xxx.c

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt new file +10 -0

new file mode 100644
index 0000000..3be60c8
@@ -0,0 +1,10 @@
+Hisilicon Platforms Device Tree Bindings
+----------------------------------------------------
+
+Hi3716 Development Board
+Required root node properties:
+	- compatible = "hisilicon,hi3716-dkb";
+
+Hi4511 Board
+Required root node properties:
+	- compatible = "hisilicon,hi3620-hi4511";

arch/arm/Kconfig +2 -0

index 49d993c..acd2358 100644
@@ -936,6 +936,8 @@ source "arch/arm/mach-footbridge/Kconfig"
 
 source "arch/arm/mach-gemini/Kconfig"
 
+source "arch/arm/mach-hi3xxx/Kconfig"
+
 source "arch/arm/mach-highbank/Kconfig"
 
 source "arch/arm/mach-integrator/Kconfig"

arch/arm/Makefile +1 -0

index 1ba358b..748a9ca 100644
@@ -147,6 +147,7 @@ machine-$(CONFIG_ARCH_DOVE)		+= dove
 machine-$(CONFIG_ARCH_EBSA110)		+= ebsa110
 machine-$(CONFIG_ARCH_EP93XX)		+= ep93xx
 machine-$(CONFIG_ARCH_GEMINI)		+= gemini
+machine-$(CONFIG_ARCH_HI3xxx)		+= hi3xxx
 machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_INTEGRATOR)	+= integrator
 machine-$(CONFIG_ARCH_IOP13XX)		+= iop13xx

arch/arm/mach-hi3xxx/Kconfig new file +13 -0

new file mode 100644
index 0000000..a991dee
@@ -0,0 +1,13 @@
+config ARCH_HI3xxx
+	bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
+	select ARM_AMBA
+	select ARM_GIC
+	select CACHE_L2X0
+	select CACHE_PL310
+	select CLKSRC_OF
+	select PINCTRL
+	select PINCTRL_SINGLE
+	select SERIAL_AMBA_PL011
+	select SERIAL_AMBA_PL011_CONSOLE
+	help
+	  Support for Hisilicon Hi36xx/Hi37xx processor family

arch/arm/mach-hi3xxx/Makefile new file +5 -0

new file mode 100644
index 0000000..d68ebb3
@@ -0,0 +1,5 @@
+#
+# Makefile for Hisilicon Hi36xx/Hi37xx processors line
+#
+
+obj-y	+= hi3xxx.o

arch/arm/mach-hi3xxx/hi3xxx.c new file +37 -0

new file mode 100644
index 0000000..064b303
@@ -0,0 +1,37 @@
+/*
+ * (Hisilicon's Hi36xx/Hi37xx SoC based) flattened device tree enabled machine
+ *
+ * Copyright (c) 2012-2013 Hisilicon Ltd.
+ * Copyright (c) 2012-2013 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+static void __init hi3xxx_timer_init(void)
+{
+	of_clk_init(NULL);
+	clocksource_of_init();
+}
+
+static const char *hs_compat[] __initdata = {
+	"hisilicon,hi3620-hi4511",
+	NULL,
+};
+
+DT_MACHINE_START(HI3xxx, "Hisilicon Hi36xx/Hi37xx (Flattened Device Tree)")
+	/* Maintainer: Haojian Zhuang <[email protected]> */
+	.init_time	= hi3xxx_timer_init,
+	.dt_compat	= hs_compat,
+MACHINE_END

Signature · 1 line

1.8.1.2

Olof Johansson

2013-06-12 19:54 UTC #7 lore raw

PATCH v4 6/7 ARM: hi3xxx: add board support with device tree

Quoted 33 lines · Haojian Zhuang

Add board support with device tree for Hisilicon Hi36xx/Hi37xx platform.
Changelog:
v3:
1. Remove .map_io() in DT machine descriptor. Since debug_ll_io_init() is called by default.
2. Remove .init_machine() in DT machine descriptor. Since of_platform_populate() is called by default in DT mode.
v2:
1. Remove .init_irq() in DT machine descriptor. Since irqchip_init() is called by default in DT mode.
Signed-off-by Haojian Zhuang <[email protected]>
---
 .../bindings/arm/hisilicon/hisilicon.txt           | 10 ++++++
 arch/arm/Kconfig                                   |  2 ++
 arch/arm/Makefile                                  |  1 +
 arch/arm/mach-hi3xxx/Kconfig                       | 13 ++++++++
 arch/arm/mach-hi3xxx/Makefile                      |  5 +++
 arch/arm/mach-hi3xxx/hi3xxx.c                      | 37 ++++++++++++++++++++++
 6 files changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
 create mode 100644 arch/arm/mach-hi3xxx/Kconfig
 create mode 100644 arch/arm/mach-hi3xxx/Makefile
 create mode 100644 arch/arm/mach-hi3xxx/hi3xxx.c
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt new file +0 -0
new file mode 100644
index 0000000..3be60c8

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt line 10

Quoted 10 lines

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt new file +10 -0

@@ -0,0 +1,10 @@
+Hisilicon Platforms Device Tree Bindings
+----------------------------------------------------
+
+Hi3716 Development Board
+Required root node properties:
+	- compatible = "hisilicon,hi3716-dkb";
+
+Hi4511 Board
+Required root node properties:
+	- compatible = "hisilicon,hi3620-hi4511";

Having the same namespace for boards and for SoCs is _extremely_ confusing. I know it's not something you made up, but if you have a chance to influence future naming, please do so. Or maybe consider using a different naming scheme than just "hixxxx" for boards in the sources.

Quoted 26 lines

arch/arm/mach-hi3xxx/hi3xxx.c new file +20 -0

new file mode 100644
index 0000000..064b303
@@ -0,0 +1,37 @@
+/*
+ * (Hisilicon's Hi36xx/Hi37xx SoC based) flattened device tree enabled machine
+ *
+ * Copyright (c) 2012-2013 Hisilicon Ltd.
+ * Copyright (c) 2012-2013 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>

arch/arm/mach-hi3xxx/hi3xxx.c line 30

Quoted 10 lines

arch/arm/mach-hi3xxx/hi3xxx.c new file +10 -0

+
+static void __init hi3xxx_timer_init(void)
+{
+	of_clk_init(NULL);
+	clocksource_of_init();
+}
+
+static const char *hs_compat[] __initdata = {
+	"hisilicon,hi3620-hi4511",
+	NULL,

Should you list the hisilicon,hi3716-dkb board here too, since you add the bindings doc for it?

-Olof

Haojian Zhuang

author

2013-06-17 01:06 UTC #8 lore raw

PATCH v4 6/7 ARM: hi3xxx: add board support with device tree

Quoted 41 lines · Olof Johansson

Quoted 40 lines · Haojian Zhuang
Add board support with device tree for Hisilicon Hi36xx/Hi37xx platform.
Changelog:
v3:
1. Remove .map_io() in DT machine descriptor. Since debug_ll_io_init() is called by default.
2. Remove .init_machine() in DT machine descriptor. Since of_platform_populate() is called by default in DT mode.
v2:
1. Remove .init_irq() in DT machine descriptor. Since irqchip_init() is called by default in DT mode.
Signed-off-by Haojian Zhuang <[email protected]>
---
 .../bindings/arm/hisilicon/hisilicon.txt           | 10 ++++++
 arch/arm/Kconfig                                   |  2 ++
 arch/arm/Makefile                                  |  1 +
 arch/arm/mach-hi3xxx/Kconfig                       | 13 ++++++++
 arch/arm/mach-hi3xxx/Makefile                      |  5 +++
 arch/arm/mach-hi3xxx/hi3xxx.c                      | 37 ++++++++++++++++++++++
 6 files changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
 create mode 100644 arch/arm/mach-hi3xxx/Kconfig
 create mode 100644 arch/arm/mach-hi3xxx/Makefile
 create mode 100644 arch/arm/mach-hi3xxx/hi3xxx.c
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt new file +7 -0
new file mode 100644
index 0000000..3be60c8
@@ -0,0 +1,10 @@
+Hisilicon Platforms Device Tree Bindings
+----------------------------------------------------
+
+Hi3716 Development Board
+Required root node properties:
+     - compatible = "hisilicon,hi3716-dkb";
+

Quoted 8 lines

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt line 10
Quoted 3 lines
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt new file +3 -0
+Hi4511 Board
+Required root node properties:
+     - compatible = "hisilicon,hi3620-hi4511";
Having the same namespace for boards and for SoCs is _extremely_ confusing. I know it's not something you made up, but if you have a chance to influence future naming, please do so. Or maybe consider using a different naming scheme than just "hixxxx" for boards in the sources.

Maybe. But it's still their choice.

Quoted 42 lines

Quoted 27 lines

arch/arm/mach-hi3xxx/hi3xxx.c new file +20 -0

new file mode 100644
index 0000000..064b303
@@ -0,0 +1,37 @@
+/*
+ * (Hisilicon's Hi36xx/Hi37xx SoC based) flattened device tree enabled machine
+ *
+ * Copyright (c) 2012-2013 Hisilicon Ltd.
+ * Copyright (c) 2012-2013 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>

arch/arm/mach-hi3xxx/hi3xxx.c line 30

Quoted 10 lines

arch/arm/mach-hi3xxx/hi3xxx.c new file +10 -0

+
+static void __init hi3xxx_timer_init(void)
+{
+     of_clk_init(NULL);
+     clocksource_of_init();
+}
+
+static const char *hs_compat[] __initdata = {
+     "hisilicon,hi3620-hi4511",
+     NULL,

Should you list the hisilicon,hi3716-dkb board here too, since you add the bindings doc for it?

Quoted 1 line

-Olof

If all of these patches are merged, I can submit hi3716-dkb continuously.

The more things what I add only cause me pending more time.

Regards
Haojian

Haojian Zhuang

author

2013-06-08 14:47 UTC #9 lore raw

PATCH v4 7/7 ARM: hi3xxx: enable hi4511 with device tree

In reply to Haojian Zhuang

Enable Hisilicon Hi4511 development platform with device tree support.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/boot/dts/Makefile          |    1 +
 arch/arm/boot/dts/hi3620.dtsi       | 1169 +++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/hi4511.dts        |  735 ++++++++++++++++++++++
 arch/arm/configs/multi_v7_defconfig |    1 +
 4 files changed, 1906 insertions(+)
 create mode 100644 arch/arm/boot/dts/hi3620.dtsi
 create mode 100644 arch/arm/boot/dts/hi4511.dts

arch/arm/boot/dts/Makefile +1 -0

index f0895c5..216f983 100644
@@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
 	exynos5250-smdk5250.dtb \
 	exynos5250-snow.dtb \
 	exynos5440-ssdk5440.dtb
+dtb-$(CONFIG_ARCH_HI3xxx) += hi4511.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
 	ecx-2000.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \

arch/arm/boot/dts/hi3620.dtsi new file +1169 -0

1,169 lines not on this page · raw message

arch/arm/boot/dts/hi4511.dts new file +735 -0

735 lines not on this page · raw message

arch/arm/configs/multi_v7_defconfig +1 -0

index 2e67a27..59f9753 100644
@@ -6,6 +6,7 @@ CONFIG_MACH_ARMADA_370=y
 CONFIG_ARCH_SIRF=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_HIGHBANK=y
+CONFIG_ARCH_HI3xxx=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_WM8850=y

Signature · 1 line

1.8.1.2

Olof Johansson

2013-06-12 20:00 UTC #10 lore raw

PATCH v4 7/7 ARM: hi3xxx: enable hi4511 with device tree

Hi,

Quoted 1,173 lines · Haojian Zhuang

Enable Hisilicon Hi4511 development platform with device tree support.

Signed-off-by Haojian Zhuang <[email protected]>

---
+ * publishhed by the Free Software Foundation.
+ */

arch/arm/boot/dts/hi3620.dtsi new file +1153 -0

+
+/include/ "skeleton.dtsi"
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+	};
+
+	osc32k: osc at 0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "osc32khz";
+	};
+	osc26m: osc at 1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+		clock-output-names = "osc26mhz";
+	};
+	pclk: clk at 0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+		clock-output-names = "apb_pclk";
+	};
+	pll_arm0: clk at 1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1600000000>;
+		clock-output-names = "armpll0";
+	};
+	pll_arm1: clk at 2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1600000000>;
+		clock-output-names = "armpll1";
+	};
+	pll_peri: clk at 3 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1440000000>;
+		clock-output-names = "armpll2";
+	};
+	pll_usb: clk at 4 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1440000000>;
+		clock-output-names = "armpll3";
+	};
+	pll_hdmi: clk at 5 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1188000000>;
+		clock-output-names = "armpll4";
+	};
+	pll_gpu: clk at 6 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1300000000>;
+		clock-output-names = "armpll5";
+	};
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		pmctrl: pmctrl at fca08000 {
+			compatible = "hisilicon,pmctrl";
+			reg = <0xfca08000 0x1000>;
+		};
+
+		sctrl: sctrl at fc802000 {
+			compatible = "hisilicon,sctrl";
+			reg = <0xfc802000 0x1000>;
+
+			uart0_mux: uart0_mux {
+				compatible = "hisilicon,hi3620-clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc26m &pclk>;
+				clock-output-names = "uart0_mux";
+				/* reg_offset, mask bits */
+				hisilicon,clkmux-reg = <0x100 0x80>;
+				/* each item value */
+				hisilicon,clkmux-table = <0 0x80>;
+			};
+			uart1_mux: uart1_mux {
+				compatible = "hisilicon,hi3620-clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc26m &pclk>;
+				clock-output-names = "uart1_mux";
+				hisilicon,clkmux-reg = <0x100 0x100>;
+				hisilicon,clkmux-table = <0x0 0x100>;
+			};
+			uart2_mux: uart2_mux {
+				compatible = "hisilicon,hi3620-clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc26m &pclk>;
+				clock-output-names = "uart2_mux";
+				hisilicon,clkmux-reg = <0x100 0x200>;
+				hisilicon,clkmux-table = <0 0x200>;
+			};
+			uart3_mux: uart3_mux {
+				compatible = "hisilicon,hi3620-clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc26m &pclk>;
+				clock-output-names = "uart3_mux";
+				hisilicon,clkmux-reg = <0x100 0x400>;
+				hisilicon,clkmux-table = <0 0x400>;
+			};
+			uart4_mux: uart4_mux {
+				compatible = "hisilicon,hi3620-clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc26m &pclk>;
+				clock-output-names = "uart4_mux";
+				hisilicon,clkmux-reg = <0x100 0x800>;
+				hisilicon,clkmux-table = <0 0x800>;
+			};
+			rclk_cfgaxi: rclk_cfgaxi {
+				compatible = "fixed-factor-clock";
+				#clock-cells = <0>;
+				clocks = <&pll_peri>;
+				clock-output-names = "rclk_cfgaxi";
+				clock-mult = <1>;
+				clock-div = <30>;
+			};
+			spi0_mux: spi0_mux {
+				compatible = "hisilicon,hi3620-clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc26m &rclk_cfgaxi>;
+				clock-output-names = "spi0_mux";
+				hisilicon,clkmux-reg = <0x100 0x1000>;
+				hisilicon,clkmux-table = <0 0x1000>;
+			};
+			spi1_mux: spi1_mux {
+				compatible = "hisilicon,hi3620-clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc26m &rclk_cfgaxi>;
+				clock-output-names = "spi1_mux";
+				hisilicon,clkmux-reg = <0x100 0x2000>;
+				hisilicon,clkmux-table = <0 0x2000>;
+			};
+			spi2_mux: spi2_mux {
+				compatible = "hisilicon,hi3620-clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc26m &rclk_cfgaxi>;
+				clock-output-names = "spi2_mux";
+				hisilicon,clkmux-reg = <0x100 0x4000>;
+				hisilicon,clkmux-table = <0 0x4000>;
+			};
+			pwm0_mux: pwm0_mux {
+				compatible = "hisilicon,hi3620-clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc32k &osc26m>;
+				clock-output-names = "pwm0_mux";
+				hisilicon,clkmux-reg = <0x104 0x400>;
+				hisilicon,clkmux-table = <0 0x400>;
+			};
+			pwm1_mux: pwm1_mux {
+				compatible = "hisilicon,hi3620-clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc32k &osc26m>;
+				clock-output-names = "pwm1_mux";
+				hisilicon,clkmux-reg = <0x104 0x800>;
+				hisilicon,clkmux-table = <0 0x800>;
+			};
+			timer0_mux: timer0_mux {
+				compatible = "hisilicon,clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc32k &timerclk01>;
+				clock-output-names = "timer0_mux";
+				hisilicon,clkmux-reg = <0 0x8000>;
+				hisilicon,clkmux-table = <0 0x8000>;
+			};
+			timer1_mux: timer1_mux {
+				compatible = "hisilicon,clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc32k &timerclk01>;
+				clock-output-names = "timer1_mux";
+				hisilicon,clkmux-reg = <0 0x20000>;
+				hisilicon,clkmux-table = <0 0x20000>;
+			};
+			timer2_mux: timer2_mux {
+				compatible = "hisilicon,clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc32k &timerclk23>;
+				clock-output-names = "timer2_mux";
+				hisilicon,clkmux-reg = <0 0x80000>;
+				hisilicon,clkmux-table = <0 0x80000>;
+			};
+			timer3_mux: timer3_mux {
+				compatible = "hisilicon,clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc32k &timerclk23>;
+				clock-output-names = "timer3_mux";
+				hisilicon,clkmux-reg = <0 0x200000>;
+				hisilicon,clkmux-table = <0 0x200000>;
+			};
+			timer4_mux: timer4_mux {
+				compatible = "hisilicon,clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc32k &timerclk45>;
+				clock-output-names = "timer4_mux";
+				hisilicon,clkmux-reg = <0x18 0x1>;
+				hisilicon,clkmux-table = <0 0x1>;
+			};
+			timer5_mux: timer5_mux {
+				compatible = "hisilicon,clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc32k &timerclk45>;
+				clock-output-names = "timer5_mux";
+				hisilicon,clkmux-reg = <0x18 0x4>;
+				hisilicon,clkmux-table = <0 0x4>;
+			};
+			timer6_mux: timer6_mux {
+				compatible = "hisilicon,clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc32k &timerclk67>;
+				clock-output-names = "timer6_mux";
+				hisilicon,clkmux-reg = <0x18 0x10>;
+				hisilicon,clkmux-table = <0 0x10>;
+			};
+			timer7_mux: timer7_mux {
+				compatible = "hisilicon,clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc32k &timerclk67>;
+				clock-output-names = "timer7_mux";
+				hisilicon,clkmux-reg = <0x18 0x40>;
+				hisilicon,clkmux-table = <0 0x40>;
+			};
+			timer8_mux: timer8_mux {
+				compatible = "hisilicon,clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc32k &timerclk89>;
+				clock-output-names = "timer8_mux";
+				hisilicon,clkmux-reg = <0x18 0x100>;
+				hisilicon,clkmux-table = <0 0x100>;
+			};
+			timer9_mux: timer9_mux {
+				compatible = "hisilicon,clk-mux";
+				#clock-cells = <0>;
+				clocks = <&osc32k &timerclk89>;
+				clock-output-names = "timer9_mux";
+				hisilicon,clkmux-reg = <0x18 0x400>;
+				hisilicon,clkmux-table = <0 0x400>;
+			};
+			rclk_shareAXI: rclk_shareAXI {
+				compatible = "hisilicon,hi3620-clk-mux";
+				#clock-cells = <0>;
+				clocks = <&pll_usb &pll_peri>;
+				clock-output-names = "rclk_shareAXI";
+				hisilicon,clkmux-reg = <0x100 0x8000>;
+				hisilicon,clkmux-table = <0 0x8000>;
+			};
+			uartclk0: uartclk0 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&uart0_mux>;
+				clock-output-names = "uartclk0";
+				hisilicon,hi3620-clkreset = <0x98 0x10000>;
+				hisilicon,hi3620-clkgate = <0x40 0x10000>;
+			};
+			uartclk1: uartclk1 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&uart1_mux>;
+				clock-output-names = "uartclk1";
+				hisilicon,hi3620-clkreset = <0x98 0x20000>;
+				hisilicon,hi3620-clkgate = <0x40 0x20000>;
+			};
+			uartclk2: uartclk2 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&uart2_mux>;
+				clock-output-names = "uartclk2";
+				hisilicon,hi3620-clkreset = <0x98 0x40000>;
+				hisilicon,hi3620-clkgate = <0x40 0x40000>;
+			};
+			uartclk3: uartclk3 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&uart3_mux>;
+				clock-output-names = "uartclk3";
+				hisilicon,hi3620-clkreset = <0x98 0x80000>;
+				hisilicon,hi3620-clkgate = <0x40 0x80000>;
+			};
+			uartclk4: uartclk4 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&uart4_mux>;
+				clock-output-names = "uartclk4";
+				hisilicon,hi3620-clkreset = <0x98 0x100000>;
+				hisilicon,hi3620-clkgate = <0x40 0x100000>;
+			};
+			gpioclk0: gpioclk0 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk0";
+				hisilicon,hi3620-clkreset = <0x80 0x100>;
+				hisilicon,hi3620-clkgate = <0x20 0x100>;
+			};
+			gpioclk1: gpioclk1 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk1";
+				hisilicon,hi3620-clkreset = <0x80 0x200>;
+				hisilicon,hi3620-clkgate = <0x20 0x200>;
+			};
+			gpioclk2: gpioclk2 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk2";
+				hisilicon,hi3620-clkreset = <0x80 0x400>;
+				hisilicon,hi3620-clkgate = <0x20 0x400>;
+			};
+			gpioclk3: gpioclk3 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk3";
+				hisilicon,hi3620-clkreset = <0x80 0x800>;
+				hisilicon,hi3620-clkgate = <0x20 0x800>;
+			};
+			gpioclk4: gpioclk4 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk4";
+				hisilicon,hi3620-clkreset = <0x80 0x1000>;
+				hisilicon,hi3620-clkgate = <0x20 0x1000>;
+			};
+			gpioclk5: gpioclk5 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk5";
+				hisilicon,hi3620-clkreset = <0x80 0x2000>;
+				hisilicon,hi3620-clkgate = <0x20 0x2000>;
+			};
+			gpioclk6: gpioclk6 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk6";
+				hisilicon,hi3620-clkreset = <0x80 0x4000>;
+				hisilicon,hi3620-clkgate = <0x20 0x4000>;
+			};
+			gpioclk7: gpioclk7 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk7";
+				hisilicon,hi3620-clkreset = <0x80 0x8000>;
+				hisilicon,hi3620-clkgate = <0x20 0x8000>;
+			};
+			gpioclk8: gpioclk8 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk8";
+				hisilicon,hi3620-clkreset = <0x80 0x10000>;
+				hisilicon,hi3620-clkgate = <0x20 0x10000>;
+			};
+			gpioclk9: gpioclk9 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk9";
+				hisilicon,hi3620-clkreset = <0x80 0x20000>;
+				hisilicon,hi3620-clkgate = <0x20 0x20000>;
+			};
+			gpioclk10: gpioclk10 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk10";
+				hisilicon,hi3620-clkreset = <0x80 0x40000>;
+				hisilicon,hi3620-clkgate = <0x20 0x40000>;
+			};
+			gpioclk11: gpioclk11 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk11";
+				hisilicon,hi3620-clkreset = <0x80 0x80000>;
+				hisilicon,hi3620-clkgate = <0x20 0x80000>;
+			};
+			gpioclk12: gpioclk12 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk12";
+				hisilicon,hi3620-clkreset = <0x80 0x100000>;
+				hisilicon,hi3620-clkgate = <0x20 0x100000>;
+			};
+			gpioclk13: gpioclk13 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk13";
+				hisilicon,hi3620-clkreset = <0x80 0x200000>;
+				hisilicon,hi3620-clkgate = <0x20 0x200000>;
+			};
+			gpioclk14: gpioclk14 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk14";
+				hisilicon,hi3620-clkreset = <0x80 0x400000>;
+				hisilicon,hi3620-clkgate = <0x20 0x400000>;
+			};
+			gpioclk15: gpioclk15 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk15";
+				hisilicon,hi3620-clkreset = <0x80 0x800000>;
+				hisilicon,hi3620-clkgate = <0x20 0x800000>;
+			};
+			gpioclk16: gpioclk16 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk16";
+				hisilicon,hi3620-clkreset = <0x80 0x1000000>;
+				hisilicon,hi3620-clkgate = <0x20 0x1000000>;
+			};
+			gpioclk17: gpioclk17 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk17";
+				hisilicon,hi3620-clkreset = <0x80 0x2000000>;
+				hisilicon,hi3620-clkgate = <0x20 0x2000000>;
+			};
+			gpioclk18: gpioclk18 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk18";
+				hisilicon,hi3620-clkreset = <0x80 0x4000000>;
+				hisilicon,hi3620-clkgate = <0x20 0x4000000>;
+			};
+			gpioclk19: gpioclk19 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk19";
+				hisilicon,hi3620-clkreset = <0x80 0x8000000>;
+				hisilicon,hi3620-clkgate = <0x20 0x8000000>;
+			};
+			gpioclk20: gpioclk20 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk20";
+				hisilicon,hi3620-clkreset = <0x80 0x10000000>;
+				hisilicon,hi3620-clkgate = <0x20 0x10000000>;
+			};
+			gpioclk21: gpioclk21 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "gpioclk21";
+				hisilicon,hi3620-clkreset = <0x80 0x20000000>;
+				hisilicon,hi3620-clkgate = <0x20 0x20000000>;
+			};
+			spiclk0: spiclk0 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&spi0_mux>;
+				clock-output-names = "spiclk0";
+				hisilicon,hi3620-clkreset = <0x98 0x200000>;
+				hisilicon,hi3620-clkgate = <0x40 0x200000>;
+			};
+			spiclk1: spiclk1 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&spi1_mux>;
+				clock-output-names = "spiclk1";
+				hisilicon,hi3620-clkreset = <0x98 0x400000>;
+				hisilicon,hi3620-clkgate = <0x40 0x400000>;
+			};
+			spiclk2: spiclk2 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&spi2_mux>;
+				clock-output-names = "spiclk2";
+				hisilicon,hi3620-clkreset = <0x98 0x800000>;
+				hisilicon,hi3620-clkgate = <0x40 0x800000>;
+			};
+			pwmclk0: pwmclk0 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pwm0_mux>;
+				clock-output-names = "pwmclk0";
+				hisilicon,hi3620-clkreset = <0x98 0x80>;
+				hisilicon,hi3620-clkgate = <0x40 0x80>;
+			};
+			pwmclk1: pwmclk1 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&pwm1_mux>;
+				clock-output-names = "pwmclk1";
+				hisilicon,hi3620-clkreset = <0x98 0x100>;
+				hisilicon,hi3620-clkgate = <0x40 0x100>;
+			};
+			timerclk01: timerclk01 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&osc26m>;
+				clock-output-names = "timerclk01";
+				hisilicon,hi3620-clkreset = <0x80 0x1>;
+				hisilicon,hi3620-clkgate = <0x20 0x3>;
+			};
+			timerclk23: timerclk23 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&osc26m>;
+				clock-output-names = "timerclk23";
+				hisilicon,hi3620-clkreset = <0x80 0x2>;
+				hisilicon,hi3620-clkgate = <0x20 0xc>;
+			};
+			timerclk45: timerclk45 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&osc26m>;
+				clock-output-names = "timerclk45";
+				hisilicon,hi3620-clkreset = <0x98 0x8>;
+				hisilicon,hi3620-clkgate = <0x40 0x8>;
+			};
+			timerclk67: timerclk67 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&osc26m>;
+				clock-output-names = "timerclk67";
+				hisilicon,hi3620-clkreset = <0x98 0x10>;
+				hisilicon,hi3620-clkgate = <0x40 0x10>;
+			};
+			timerclk89: timerclk89 {
+				compatible = "hisilicon,hi3620-clk-gate";
+				#clock-cells = <0>;
+				clocks = <&osc26m>;
+				clock-output-names = "timerclk89";
+				hisilicon,hi3620-clkreset = <0x98 0x20>;
+				hisilicon,hi3620-clkgate = <0x40 0x20>;
+			};
+			timclk0: timclk0 {
+				compatible = "hisilicon,clk-gate";
+				#clock-cells = <0>;
+				clocks = <&timer0_mux>;
+				clock-output-names = "timclk0";
+				hisilicon,clkgate-inverted;
+				hisilicon,clkgate = <0 16>;
+			};
+			timclk1: timclk1 {
+				compatible = "hisilicon,clk-gate";
+				#clock-cells = <0>;
+				clocks = <&timer1_mux>;
+				clock-output-names = "timclk1";
+				hisilicon,clkgate-inverted;
+				hisilicon,clkgate = <0 18>;
+			};
+			timclk2: timclk2 {
+				compatible = "hisilicon,clk-gate";
+				#clock-cells = <0>;
+				clocks = <&timer2_mux>;
+				clock-output-names = "timclk2";
+				hisilicon,clkgate-inverted;
+				hisilicon,clkgate = <0 20>;
+			};
+			timclk3: timclk3 {
+				compatible = "hisilicon,clk-gate";
+				#clock-cells = <0>;
+				clocks = <&timer3_mux>;
+				clock-output-names = "timclk3";
+				hisilicon,clkgate-inverted;
+				hisilicon,clkgate = <0 22>;
+			};
+			timclk4: timclk4 {
+				compatible = "hisilicon,clk-gate";
+				#clock-cells = <0>;
+				clocks = <&timer4_mux>;
+				clock-output-names = "timclk4";
+				hisilicon,clkgate-inverted;
+				hisilicon,clkgate = <0x18 0>;
+			};
+			timclk5: timclk5 {
+				compatible = "hisilicon,clk-gate";
+				#clock-cells = <0>;
+				clocks = <&timer5_mux>;
+				clock-output-names = "timclk5";
+				hisilicon,clkgate-inverted;
+				hisilicon,clkgate = <0x18 2>;
+			};
+			timclk6: timclk6 {
+				compatible = "hisilicon,clk-gate";
+				#clock-cells = <0>;
+				clocks = <&timer6_mux>;
+				clock-output-names = "timclk6";
+				hisilicon,clkgate-inverted;
+				hisilicon,clkgate = <0x18 4>;
+			};
+			timclk7: timclk7 {
+				compatible = "hisilicon,clk-gate";
+				#clock-cells = <0>;
+				clocks = <&timer7_mux>;
+				clock-output-names = "timclk7";
+				hisilicon,clkgate-inverted;
+				hisilicon,clkgate = <0x18 6>;
+			};
+			timclk8: timclk8 {
+				compatible = "hisilicon,clk-gate";
+				#clock-cells = <0>;
+				clocks = <&timer8_mux>;
+				clock-output-names = "timclk8";
+				hisilicon,clkgate-inverted;
+				hisilicon,clkgate = <0x18 8>;
+			};
+			timclk9: timclk9 {
+				compatible = "hisilicon,clk-gate";
+				#clock-cells = <0>;
+				clocks = <&timer9_mux>;
+				clock-output-names = "timclk9";
+				hisilicon,clkgate-inverted;
+				hisilicon,clkgate = <0x18 10>;
+			};
+			dtable: dtable {
+				#hisilicon,clkdiv-table-cells = <2>;
+			};
+			div_shareaxi: div_shareaxi {
+				compatible = "hisilicon,hi3620-clk-div";
+				#clock-cells = <0>;
+				clocks = <&rclk_shareAXI>;
+				clock-output-names = "shareAXI_div";
+				hisilicon,clkdiv-table = <
+					&dtable 0 1 &dtable 1 2 &dtable 2 3 &dtable 3 4
+					&dtable 4 5 &dtable 5 6 &dtable 6 7 &dtable 7 8
+					&dtable 8 9 &dtable 9 10 &dtable 10 11 &dtable 11 12
+					&dtable 12 13 &dtable 13 14 &dtable 14 15 &dtable 15 16
+					&dtable 16 17 &dtable 17 18 &dtable 18 19 &dtable 19 20
+					&dtable 20 21 &dtable 21 22 &dtable 22 23 &dtable 23 24
+					&dtable 24 25 &dtable 25 26 &dtable 26 27 &dtable 27 28
+					&dtable 28 29 &dtable 29 30 &dtable 30 31 &dtable 31 32>;
+				/* divider register offset, mask */
+				hisilicon,clkdiv = <0x100 0x1f>;
+			};
+			div_cfgaxi: div_cfgaxi {
+				compatible = "hisilicon,hi3620-clk-div";
+				#clock-cells = <0>;
+				clocks = <&div_shareaxi>;
+				clock-output-names = "cfgAXI_div";
+				hisilicon,clkdiv-table = <&dtable 0x01 2>;
+				hisilicon,clkdiv = <0x100 0x60>;
+			};
+		};
+
+		l2: l2-cache {
+			compatible = "arm,pl310-cache";
+			reg = <0xfc10000 0x100000>;
+			interrupts = <0 15 4>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		intc: interrupt-controller at fc001000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			/* gic dist base, gic cpu base */
+			reg = <0xfc001000 0x1000>, <0xfc000100 0x100>;
+		};
+
+		timer0: timer at fc800000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0xfc800000 0x1000>;
+			/* timer00 & timer01 */
+			interrupts = <0 0 4>, <0 1 4>;
+			clocks = <&timclk0 &timclk1>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		timer1: timer at fc801000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0xfc801000 0x1000>;
+			/* timer10 & timer11 */
+			interrupts = <0 2 4>, <0 3 4>;
+			clocks = <&timclk2 &timclk3>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		timer2: timer at fca01000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0xfca01000 0x1000>;
+			/* timer20 & timer21 */
+			interrupts = <0 4 4>, <0 5 4>;
+			clocks = <&timclk4 &timclk5>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		timer3: timer at fca02000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0xfca02000 0x1000>;
+			/* timer30 & timer31 */
+			interrupts = <0 6 4>, <0 7 4>;
+			clocks = <&timclk6 &timclk7>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		timer4: timer at fca03000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0xfca03000 0x1000>;
+			/* timer40 & timer41 */
+			interrupts = <0 96 4>, <0 97 4>;
+			clocks = <&timclk8 &timclk9>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		uart0: uart at fcb00000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xfcb00000 0x1000>;
+			interrupts = <0 20 4>;
+			clocks = <&uartclk0>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		uart1: uart at fcb01000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xfcb01000 0x1000>;
+			interrupts = <0 21 4>;
+			clocks = <&uartclk1>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		uart2: uart at fcb02000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xfcb02000 0x1000>;
+			interrupts = <0 22 4>;
+			clocks = <&uartclk2>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		uart3: uart at fcb03000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xfcb03000 0x1000>;
+			interrupts = <0 23 4>;
+			clocks = <&uartclk3>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		uart4: uart at fcb04000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xfcb04000 0x1000>;
+			interrupts = <0 24 4>;
+			clocks = <&uartclk4>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		gpio0: gpio at fc806000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc806000 0x1000>;
+			interrupts = <0 64 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
+					&pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk0>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio1: gpio at fc807000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc807000 0x1000>;
+			interrupts = <0 65 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
+					&pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
+					&pmx0 6 5 1 &pmx0 7 6 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk1>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio2: gpio at fc808000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc808000 0x1000>;
+			interrupts = <0 66 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
+					&pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
+					&pmx0 6 3 1 &pmx0 7 3 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk2>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio3: gpio at fc809000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc809000 0x1000>;
+			interrupts = <0 67 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
+					&pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
+					&pmx0 6 11 1 &pmx0 7 11 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk3>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio4: gpio at fc80a000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc80a000 0x1000>;
+			interrupts = <0 68 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
+					&pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
+					&pmx0 6 13 1 &pmx0 7 13 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk4>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio5: gpio at fc80b000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc80b000 0x1000>;
+			interrupts = <0 69 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
+					&pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
+					&pmx0 6 16 1 &pmx0 7 16 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk5>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio6: gpio at fc80c000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc80c000 0x1000>;
+			interrupts = <0 70 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
+					&pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
+					&pmx0 6 18 1 &pmx0 7 19 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk6>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio7: gpio at fc80d000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc80d000 0x1000>;
+			interrupts = <0 71 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
+					&pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
+					&pmx0 6 25 1 &pmx0 7 26 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk7>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio8: gpio at fc80e000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc80e000 0x1000>;
+			interrupts = <0 72 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
+					&pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
+					&pmx0 6 33 1 &pmx0 7 34 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk8>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio9: gpio at fc80f000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc80f000 0x1000>;
+			interrupts = <0 73 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
+					&pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
+					&pmx0 6 41 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk9>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio10: gpio at fc810000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc810000 0x1000>;
+			interrupts = <0 74 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
+					&pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk10>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio11: gpio at fc811000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc811000 0x1000>;
+			interrupts = <0 75 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
+					&pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
+					&pmx0 6 49 1 &pmx0 7 49 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk11>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio12: gpio at fc812000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc812000 0x1000>;
+			interrupts = <0 76 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
+					&pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
+					&pmx0 6 51 1 &pmx0 7 52 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk12>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio13: gpio at fc813000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc813000 0x1000>;
+			interrupts = <0 77 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
+					&pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
+					&pmx0 6 55 1 &pmx0 7 56 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk13>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio14: gpio at fc814000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc814000 0x1000>;
+			interrupts = <0 78 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
+					&pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
+					&pmx0 6 60 1 &pmx0 7 61 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk14>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio15: gpio at fc815000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc815000 0x1000>;
+			interrupts = <0 79 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
+					&pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
+					&pmx0 6 64 1 &pmx0 7 65 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk15>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio16: gpio at fc816000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc816000 0x1000>;
+			interrupts = <0 80 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
+					&pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
+					&pmx0 6 72 1 &pmx0 7 73 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk16>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio17: gpio at fc817000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc817000 0x1000>;
+			interrupts = <0 81 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
+					&pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
+					&pmx0 6 80 1 &pmx0 7 81 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk17>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio18: gpio at fc818000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc818000 0x1000>;
+			interrupts = <0 82 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
+					&pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
+					&pmx0 6 86 1 &pmx0 7 87 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk18>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio19: gpio at fc819000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc819000 0x1000>;
+			interrupts = <0 83 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
+					&pmx0 3 88 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk19>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio20: gpio at fc81a000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc81a000 0x1000>;
+			interrupts = <0 84 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
+					&pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk20>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		gpio21: gpio at fc81b000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0xfc81b000 0x1000>;
+			interrupts = <0 85 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <	&pmx0 3 94 1 &pmx0 7 96 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&gpioclk21>;
+			clock-names = "apb_pclk";
+			status = "disable";
+		};
+
+		pmx0: pinmux at fc803000 {
+			compatible = "pinctrl-single";
+			reg = <0xfc803000 0x188>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#gpio-range-cells = <3>;
+			ranges;
+
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <7>;
+			/* pin base, nr pins & gpio function */
+			pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
+						&range 12 1 0 &range 13 29 1
+						&range 43 1 0 &range 44 49 1
+						&range 94 1 1 &range 96 2 1>;
+
+			range: gpio-range {
+				#pinctrl-single,gpio-range-cells = <3>;
+			};
+		};
+
+		pmx1: pinmux at fc803800 {
+			compatible = "pinconf-single";
+			reg = <0xfc803800 0x2dc>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			pinctrl-single,register-width = <32>;
+		};
+	};
+};

arch/arm/boot/dts/hi4511.dts new file +8 -0

new file mode 100644
index 0000000..746b8eb
@@ -0,0 +1,735 @@
+/*
+ *  Copyright (C) 2012-2013 Linaro Ltd.
+ *  Author: Haojian Zhuang <[email protected]>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */

arch/arm/boot/dts/hi4511.dts line 18

Quoted 10 lines

arch/arm/boot/dts/hi4511.dts new file +10 -0

+
+/dts-v1/;
+/include/ "hi3620.dtsi"
+
+/ {
+	model = "Hisilicon Hi4511 Development Board";
+	compatible = "hisilicon,hi3620-hi4511";
+
+	chosen {
+		bootargs = "console=ttyAMA0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on mem=512m earlyprintk";

It probably doesn't make sense to specify your network and nfsroot parameters here, since they will differ from install environment to install enviroment.

Also, mem=<x> isn't needed here since you ahve a proper memory node below.

Quoted 39 lines

arch/arm/boot/dts/hi4511.dts new file +39 -0

+	};
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	amba {
+		timer0: timer at fc800000 {
+			status = "ok";
+		};
+
+		uart0: uart at fcb00000 {	/* console */
+			pinctrl-names = "default", "idle";
+			pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
+			pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
+			status = "ok";
+		};
+
+		uart1: uart at fcb01000 { /* modem */
+			pinctrl-names = "default", "idle";
+			pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
+			pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>;
+			status = "ok";
+		};
+
+		uart2: uart at fcb02000 { /* audience */
+			pinctrl-names = "default", "idle";
+			pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
+			pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>;
+			status = "ok";
+		};
+
+		uart3: uart at fcb03000 {
+			pinctrl-names = "default", "idle";
+			pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
+			pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>;
+			status = "ok";
+		};
+

arch/arm/boot/dts/hi4511.dts line 67

Quoted 10 lines

arch/arm/boot/dts/hi4511.dts new file +10 -0

+		uart4: uart at fcb04000 {
+			pinctrl-names = "default", "idle";
+			pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
+			pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>;
+			status = "ok";
+		};
+
+		gpio0: gpio at fc806000 {
+			status = "ok";
+		};

In general, only devices that are likely to not use on all boards are status = disable in the dtsi. For things like these gpio entries, are all boards expected to need to enable them anyway? if so, then it's just silly to mark them disabled in the dtsi.

arch/arm/boot/dts/hi4511.dts line 161

Quoted 9 lines

arch/arm/boot/dts/hi4511.dts new file +9 -0

+		gpio-keys {
+			compatible = "gpio-keys";
+
+			call {
+				label = "call";
+				gpios = <&gpio17 2 0>;
+				linux,code = <169>;	/* KEY_PHONE */
+			};
+		};

This doesn't really belong under the amba node. Please push to the top instead.

arch/arm/boot/dts/hi4511.dts line 170

Quoted 9 lines

arch/arm/boot/dts/hi4511.dts new file +9 -0

+
+		pmx0: pinmux at fc803000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&board_pmx_pins>;
+
+			board_pmx_pins: board_pmx_pins {
+				pinctrl-single,pins = <
+					0x008 0x0	/* GPIO -- eFUSE_DOUT */
+					0x100 0x0	/* USIM_CLK & USIM_DATA (IOMG63) */

Please consider using the new preprocessor functions here instead of hardcoded hex values, if it makes sense for your platform -- I think it does?

Also, it's nice when most of the pinctrl stuff can go in the dtsi file and keep the board file as clean as possible, since you ended up doing a lot of pinctrl entries in this board dts.

-Olof

Haojian Zhuang

author

2013-06-17 01:21 UTC #11 lore raw

PATCH v4 7/7 ARM: hi3xxx: enable hi4511 with device tree

Quoted 1,191 lines · Olof Johansson

Hi,

Quoted 1,173 lines · Haojian Zhuang

Enable Hisilicon Hi4511 development platform with device tree support.

Signed-off-by Haojian Zhuang <[email protected]>

---
+ * publishhed by the Free Software Foundation.
+ */

arch/arm/boot/dts/hi3620.dtsi new file +1153 -0

+
+/include/ "skeleton.dtsi"
+             serial1 = &uart1;
+             serial2 = &uart2;
+             serial3 = &uart3;
+             serial4 = &uart4;
+     };
+
+     osc32k: osc at 0 {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <32768>;
+             clock-output-names = "osc32khz";
+     };
+     osc26m: osc at 1 {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <26000000>;
+             clock-output-names = "osc26mhz";
+     };
+     pclk: clk at 0 {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <26000000>;
+             clock-output-names = "apb_pclk";
+     };
+     pll_arm0: clk at 1 {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <1600000000>;
+             clock-output-names = "armpll0";
+     };
+     pll_arm1: clk at 2 {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <1600000000>;
+             clock-output-names = "armpll1";
+     };
+     pll_peri: clk at 3 {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <1440000000>;
+             clock-output-names = "armpll2";
+     };
+     pll_usb: clk at 4 {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <1440000000>;
+             clock-output-names = "armpll3";
+     };
+     pll_hdmi: clk at 5 {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <1188000000>;
+             clock-output-names = "armpll4";
+     };
+     pll_gpu: clk at 6 {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <1300000000>;
+             clock-output-names = "armpll5";
+     };
+
+     amba {
+             #address-cells = <1>;
+             #size-cells = <1>;
+             compatible = "arm,amba-bus";
+             interrupt-parent = <&intc>;
+             ranges;
+
+             pmctrl: pmctrl at fca08000 {
+                     compatible = "hisilicon,pmctrl";
+                     reg = <0xfca08000 0x1000>;
+             };
+
+             sctrl: sctrl at fc802000 {
+                     compatible = "hisilicon,sctrl";
+                     reg = <0xfc802000 0x1000>;
+
+                     uart0_mux: uart0_mux {
+                             compatible = "hisilicon,hi3620-clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m &pclk>;
+                             clock-output-names = "uart0_mux";
+                             /* reg_offset, mask bits */
+                             hisilicon,clkmux-reg = <0x100 0x80>;
+                             /* each item value */
+                             hisilicon,clkmux-table = <0 0x80>;
+                     };
+                     uart1_mux: uart1_mux {
+                             compatible = "hisilicon,hi3620-clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m &pclk>;
+                             clock-output-names = "uart1_mux";
+                             hisilicon,clkmux-reg = <0x100 0x100>;
+                             hisilicon,clkmux-table = <0x0 0x100>;
+                     };
+                     uart2_mux: uart2_mux {
+                             compatible = "hisilicon,hi3620-clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m &pclk>;
+                             clock-output-names = "uart2_mux";
+                             hisilicon,clkmux-reg = <0x100 0x200>;
+                             hisilicon,clkmux-table = <0 0x200>;
+                     };
+                     uart3_mux: uart3_mux {
+                             compatible = "hisilicon,hi3620-clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m &pclk>;
+                             clock-output-names = "uart3_mux";
+                             hisilicon,clkmux-reg = <0x100 0x400>;
+                             hisilicon,clkmux-table = <0 0x400>;
+                     };
+                     uart4_mux: uart4_mux {
+                             compatible = "hisilicon,hi3620-clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m &pclk>;
+                             clock-output-names = "uart4_mux";
+                             hisilicon,clkmux-reg = <0x100 0x800>;
+                             hisilicon,clkmux-table = <0 0x800>;
+                     };
+                     rclk_cfgaxi: rclk_cfgaxi {
+                             compatible = "fixed-factor-clock";
+                             #clock-cells = <0>;
+                             clocks = <&pll_peri>;
+                             clock-output-names = "rclk_cfgaxi";
+                             clock-mult = <1>;
+                             clock-div = <30>;
+                     };
+                     spi0_mux: spi0_mux {
+                             compatible = "hisilicon,hi3620-clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m &rclk_cfgaxi>;
+                             clock-output-names = "spi0_mux";
+                             hisilicon,clkmux-reg = <0x100 0x1000>;
+                             hisilicon,clkmux-table = <0 0x1000>;
+                     };
+                     spi1_mux: spi1_mux {
+                             compatible = "hisilicon,hi3620-clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m &rclk_cfgaxi>;
+                             clock-output-names = "spi1_mux";
+                             hisilicon,clkmux-reg = <0x100 0x2000>;
+                             hisilicon,clkmux-table = <0 0x2000>;
+                     };
+                     spi2_mux: spi2_mux {
+                             compatible = "hisilicon,hi3620-clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m &rclk_cfgaxi>;
+                             clock-output-names = "spi2_mux";
+                             hisilicon,clkmux-reg = <0x100 0x4000>;
+                             hisilicon,clkmux-table = <0 0x4000>;
+                     };
+                     pwm0_mux: pwm0_mux {
+                             compatible = "hisilicon,hi3620-clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc32k &osc26m>;
+                             clock-output-names = "pwm0_mux";
+                             hisilicon,clkmux-reg = <0x104 0x400>;
+                             hisilicon,clkmux-table = <0 0x400>;
+                     };
+                     pwm1_mux: pwm1_mux {
+                             compatible = "hisilicon,hi3620-clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc32k &osc26m>;
+                             clock-output-names = "pwm1_mux";
+                             hisilicon,clkmux-reg = <0x104 0x800>;
+                             hisilicon,clkmux-table = <0 0x800>;
+                     };
+                     timer0_mux: timer0_mux {
+                             compatible = "hisilicon,clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc32k &timerclk01>;
+                             clock-output-names = "timer0_mux";
+                             hisilicon,clkmux-reg = <0 0x8000>;
+                             hisilicon,clkmux-table = <0 0x8000>;
+                     };
+                     timer1_mux: timer1_mux {
+                             compatible = "hisilicon,clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc32k &timerclk01>;
+                             clock-output-names = "timer1_mux";
+                             hisilicon,clkmux-reg = <0 0x20000>;
+                             hisilicon,clkmux-table = <0 0x20000>;
+                     };
+                     timer2_mux: timer2_mux {
+                             compatible = "hisilicon,clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc32k &timerclk23>;
+                             clock-output-names = "timer2_mux";
+                             hisilicon,clkmux-reg = <0 0x80000>;
+                             hisilicon,clkmux-table = <0 0x80000>;
+                     };
+                     timer3_mux: timer3_mux {
+                             compatible = "hisilicon,clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc32k &timerclk23>;
+                             clock-output-names = "timer3_mux";
+                             hisilicon,clkmux-reg = <0 0x200000>;
+                             hisilicon,clkmux-table = <0 0x200000>;
+                     };
+                     timer4_mux: timer4_mux {
+                             compatible = "hisilicon,clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc32k &timerclk45>;
+                             clock-output-names = "timer4_mux";
+                             hisilicon,clkmux-reg = <0x18 0x1>;
+                             hisilicon,clkmux-table = <0 0x1>;
+                     };
+                     timer5_mux: timer5_mux {
+                             compatible = "hisilicon,clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc32k &timerclk45>;
+                             clock-output-names = "timer5_mux";
+                             hisilicon,clkmux-reg = <0x18 0x4>;
+                             hisilicon,clkmux-table = <0 0x4>;
+                     };
+                     timer6_mux: timer6_mux {
+                             compatible = "hisilicon,clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc32k &timerclk67>;
+                             clock-output-names = "timer6_mux";
+                             hisilicon,clkmux-reg = <0x18 0x10>;
+                             hisilicon,clkmux-table = <0 0x10>;
+                     };
+                     timer7_mux: timer7_mux {
+                             compatible = "hisilicon,clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc32k &timerclk67>;
+                             clock-output-names = "timer7_mux";
+                             hisilicon,clkmux-reg = <0x18 0x40>;
+                             hisilicon,clkmux-table = <0 0x40>;
+                     };
+                     timer8_mux: timer8_mux {
+                             compatible = "hisilicon,clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc32k &timerclk89>;
+                             clock-output-names = "timer8_mux";
+                             hisilicon,clkmux-reg = <0x18 0x100>;
+                             hisilicon,clkmux-table = <0 0x100>;
+                     };
+                     timer9_mux: timer9_mux {
+                             compatible = "hisilicon,clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&osc32k &timerclk89>;
+                             clock-output-names = "timer9_mux";
+                             hisilicon,clkmux-reg = <0x18 0x400>;
+                             hisilicon,clkmux-table = <0 0x400>;
+                     };
+                     rclk_shareAXI: rclk_shareAXI {
+                             compatible = "hisilicon,hi3620-clk-mux";
+                             #clock-cells = <0>;
+                             clocks = <&pll_usb &pll_peri>;
+                             clock-output-names = "rclk_shareAXI";
+                             hisilicon,clkmux-reg = <0x100 0x8000>;
+                             hisilicon,clkmux-table = <0 0x8000>;
+                     };
+                     uartclk0: uartclk0 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&uart0_mux>;
+                             clock-output-names = "uartclk0";
+                             hisilicon,hi3620-clkreset = <0x98 0x10000>;
+                             hisilicon,hi3620-clkgate = <0x40 0x10000>;
+                     };
+                     uartclk1: uartclk1 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&uart1_mux>;
+                             clock-output-names = "uartclk1";
+                             hisilicon,hi3620-clkreset = <0x98 0x20000>;
+                             hisilicon,hi3620-clkgate = <0x40 0x20000>;
+                     };
+                     uartclk2: uartclk2 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&uart2_mux>;
+                             clock-output-names = "uartclk2";
+                             hisilicon,hi3620-clkreset = <0x98 0x40000>;
+                             hisilicon,hi3620-clkgate = <0x40 0x40000>;
+                     };
+                     uartclk3: uartclk3 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&uart3_mux>;
+                             clock-output-names = "uartclk3";
+                             hisilicon,hi3620-clkreset = <0x98 0x80000>;
+                             hisilicon,hi3620-clkgate = <0x40 0x80000>;
+                     };
+                     uartclk4: uartclk4 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&uart4_mux>;
+                             clock-output-names = "uartclk4";
+                             hisilicon,hi3620-clkreset = <0x98 0x100000>;
+                             hisilicon,hi3620-clkgate = <0x40 0x100000>;
+                     };
+                     gpioclk0: gpioclk0 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk0";
+                             hisilicon,hi3620-clkreset = <0x80 0x100>;
+                             hisilicon,hi3620-clkgate = <0x20 0x100>;
+                     };
+                     gpioclk1: gpioclk1 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk1";
+                             hisilicon,hi3620-clkreset = <0x80 0x200>;
+                             hisilicon,hi3620-clkgate = <0x20 0x200>;
+                     };
+                     gpioclk2: gpioclk2 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk2";
+                             hisilicon,hi3620-clkreset = <0x80 0x400>;
+                             hisilicon,hi3620-clkgate = <0x20 0x400>;
+                     };
+                     gpioclk3: gpioclk3 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk3";
+                             hisilicon,hi3620-clkreset = <0x80 0x800>;
+                             hisilicon,hi3620-clkgate = <0x20 0x800>;
+                     };
+                     gpioclk4: gpioclk4 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk4";
+                             hisilicon,hi3620-clkreset = <0x80 0x1000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x1000>;
+                     };
+                     gpioclk5: gpioclk5 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk5";
+                             hisilicon,hi3620-clkreset = <0x80 0x2000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x2000>;
+                     };
+                     gpioclk6: gpioclk6 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk6";
+                             hisilicon,hi3620-clkreset = <0x80 0x4000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x4000>;
+                     };
+                     gpioclk7: gpioclk7 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk7";
+                             hisilicon,hi3620-clkreset = <0x80 0x8000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x8000>;
+                     };
+                     gpioclk8: gpioclk8 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk8";
+                             hisilicon,hi3620-clkreset = <0x80 0x10000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x10000>;
+                     };
+                     gpioclk9: gpioclk9 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk9";
+                             hisilicon,hi3620-clkreset = <0x80 0x20000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x20000>;
+                     };
+                     gpioclk10: gpioclk10 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk10";
+                             hisilicon,hi3620-clkreset = <0x80 0x40000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x40000>;
+                     };
+                     gpioclk11: gpioclk11 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk11";
+                             hisilicon,hi3620-clkreset = <0x80 0x80000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x80000>;
+                     };
+                     gpioclk12: gpioclk12 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk12";
+                             hisilicon,hi3620-clkreset = <0x80 0x100000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x100000>;
+                     };
+                     gpioclk13: gpioclk13 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk13";
+                             hisilicon,hi3620-clkreset = <0x80 0x200000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x200000>;
+                     };
+                     gpioclk14: gpioclk14 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk14";
+                             hisilicon,hi3620-clkreset = <0x80 0x400000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x400000>;
+                     };
+                     gpioclk15: gpioclk15 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk15";
+                             hisilicon,hi3620-clkreset = <0x80 0x800000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x800000>;
+                     };
+                     gpioclk16: gpioclk16 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk16";
+                             hisilicon,hi3620-clkreset = <0x80 0x1000000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x1000000>;
+                     };
+                     gpioclk17: gpioclk17 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk17";
+                             hisilicon,hi3620-clkreset = <0x80 0x2000000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x2000000>;
+                     };
+                     gpioclk18: gpioclk18 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk18";
+                             hisilicon,hi3620-clkreset = <0x80 0x4000000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x4000000>;
+                     };
+                     gpioclk19: gpioclk19 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk19";
+                             hisilicon,hi3620-clkreset = <0x80 0x8000000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x8000000>;
+                     };
+                     gpioclk20: gpioclk20 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk20";
+                             hisilicon,hi3620-clkreset = <0x80 0x10000000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x10000000>;
+                     };
+                     gpioclk21: gpioclk21 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pclk>;
+                             clock-output-names = "gpioclk21";
+                             hisilicon,hi3620-clkreset = <0x80 0x20000000>;
+                             hisilicon,hi3620-clkgate = <0x20 0x20000000>;
+                     };
+                     spiclk0: spiclk0 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&spi0_mux>;
+                             clock-output-names = "spiclk0";
+                             hisilicon,hi3620-clkreset = <0x98 0x200000>;
+                             hisilicon,hi3620-clkgate = <0x40 0x200000>;
+                     };
+                     spiclk1: spiclk1 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&spi1_mux>;
+                             clock-output-names = "spiclk1";
+                             hisilicon,hi3620-clkreset = <0x98 0x400000>;
+                             hisilicon,hi3620-clkgate = <0x40 0x400000>;
+                     };
+                     spiclk2: spiclk2 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&spi2_mux>;
+                             clock-output-names = "spiclk2";
+                             hisilicon,hi3620-clkreset = <0x98 0x800000>;
+                             hisilicon,hi3620-clkgate = <0x40 0x800000>;
+                     };
+                     pwmclk0: pwmclk0 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pwm0_mux>;
+                             clock-output-names = "pwmclk0";
+                             hisilicon,hi3620-clkreset = <0x98 0x80>;
+                             hisilicon,hi3620-clkgate = <0x40 0x80>;
+                     };
+                     pwmclk1: pwmclk1 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&pwm1_mux>;
+                             clock-output-names = "pwmclk1";
+                             hisilicon,hi3620-clkreset = <0x98 0x100>;
+                             hisilicon,hi3620-clkgate = <0x40 0x100>;
+                     };
+                     timerclk01: timerclk01 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m>;
+                             clock-output-names = "timerclk01";
+                             hisilicon,hi3620-clkreset = <0x80 0x1>;
+                             hisilicon,hi3620-clkgate = <0x20 0x3>;
+                     };
+                     timerclk23: timerclk23 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m>;
+                             clock-output-names = "timerclk23";
+                             hisilicon,hi3620-clkreset = <0x80 0x2>;
+                             hisilicon,hi3620-clkgate = <0x20 0xc>;
+                     };
+                     timerclk45: timerclk45 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m>;
+                             clock-output-names = "timerclk45";
+                             hisilicon,hi3620-clkreset = <0x98 0x8>;
+                             hisilicon,hi3620-clkgate = <0x40 0x8>;
+                     };
+                     timerclk67: timerclk67 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m>;
+                             clock-output-names = "timerclk67";
+                             hisilicon,hi3620-clkreset = <0x98 0x10>;
+                             hisilicon,hi3620-clkgate = <0x40 0x10>;
+                     };
+                     timerclk89: timerclk89 {
+                             compatible = "hisilicon,hi3620-clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&osc26m>;
+                             clock-output-names = "timerclk89";
+                             hisilicon,hi3620-clkreset = <0x98 0x20>;
+                             hisilicon,hi3620-clkgate = <0x40 0x20>;
+                     };
+                     timclk0: timclk0 {
+                             compatible = "hisilicon,clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&timer0_mux>;
+                             clock-output-names = "timclk0";
+                             hisilicon,clkgate-inverted;
+                             hisilicon,clkgate = <0 16>;
+                     };
+                     timclk1: timclk1 {
+                             compatible = "hisilicon,clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&timer1_mux>;
+                             clock-output-names = "timclk1";
+                             hisilicon,clkgate-inverted;
+                             hisilicon,clkgate = <0 18>;
+                     };
+                     timclk2: timclk2 {
+                             compatible = "hisilicon,clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&timer2_mux>;
+                             clock-output-names = "timclk2";
+                             hisilicon,clkgate-inverted;
+                             hisilicon,clkgate = <0 20>;
+                     };
+                     timclk3: timclk3 {
+                             compatible = "hisilicon,clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&timer3_mux>;
+                             clock-output-names = "timclk3";
+                             hisilicon,clkgate-inverted;
+                             hisilicon,clkgate = <0 22>;
+                     };
+                     timclk4: timclk4 {
+                             compatible = "hisilicon,clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&timer4_mux>;
+                             clock-output-names = "timclk4";
+                             hisilicon,clkgate-inverted;
+                             hisilicon,clkgate = <0x18 0>;
+                     };
+                     timclk5: timclk5 {
+                             compatible = "hisilicon,clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&timer5_mux>;
+                             clock-output-names = "timclk5";
+                             hisilicon,clkgate-inverted;
+                             hisilicon,clkgate = <0x18 2>;
+                     };
+                     timclk6: timclk6 {
+                             compatible = "hisilicon,clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&timer6_mux>;
+                             clock-output-names = "timclk6";
+                             hisilicon,clkgate-inverted;
+                             hisilicon,clkgate = <0x18 4>;
+                     };
+                     timclk7: timclk7 {
+                             compatible = "hisilicon,clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&timer7_mux>;
+                             clock-output-names = "timclk7";
+                             hisilicon,clkgate-inverted;
+                             hisilicon,clkgate = <0x18 6>;
+                     };
+                     timclk8: timclk8 {
+                             compatible = "hisilicon,clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&timer8_mux>;
+                             clock-output-names = "timclk8";
+                             hisilicon,clkgate-inverted;
+                             hisilicon,clkgate = <0x18 8>;
+                     };
+                     timclk9: timclk9 {
+                             compatible = "hisilicon,clk-gate";
+                             #clock-cells = <0>;
+                             clocks = <&timer9_mux>;
+                             clock-output-names = "timclk9";
+                             hisilicon,clkgate-inverted;
+                             hisilicon,clkgate = <0x18 10>;
+                     };
+                     dtable: dtable {
+                             #hisilicon,clkdiv-table-cells = <2>;
+                     };
+                     div_shareaxi: div_shareaxi {
+                             compatible = "hisilicon,hi3620-clk-div";
+                             #clock-cells = <0>;
+                             clocks = <&rclk_shareAXI>;
+                             clock-output-names = "shareAXI_div";
+                             hisilicon,clkdiv-table = <
+                                     &dtable 0 1 &dtable 1 2 &dtable 2 3 &dtable 3 4
+                                     &dtable 4 5 &dtable 5 6 &dtable 6 7 &dtable 7 8
+                                     &dtable 8 9 &dtable 9 10 &dtable 10 11 &dtable 11 12
+                                     &dtable 12 13 &dtable 13 14 &dtable 14 15 &dtable 15 16
+                                     &dtable 16 17 &dtable 17 18 &dtable 18 19 &dtable 19 20
+                                     &dtable 20 21 &dtable 21 22 &dtable 22 23 &dtable 23 24
+                                     &dtable 24 25 &dtable 25 26 &dtable 26 27 &dtable 27 28
+                                     &dtable 28 29 &dtable 29 30 &dtable 30 31 &dtable 31 32>;
+                             /* divider register offset, mask */
+                             hisilicon,clkdiv = <0x100 0x1f>;
+                     };
+                     div_cfgaxi: div_cfgaxi {
+                             compatible = "hisilicon,hi3620-clk-div";
+                             #clock-cells = <0>;
+                             clocks = <&div_shareaxi>;
+                             clock-output-names = "cfgAXI_div";
+                             hisilicon,clkdiv-table = <&dtable 0x01 2>;
+                             hisilicon,clkdiv = <0x100 0x60>;
+                     };
+             };
+
+             l2: l2-cache {
+                     compatible = "arm,pl310-cache";
+                     reg = <0xfc10000 0x100000>;
+                     interrupts = <0 15 4>;
+                     cache-unified;
+                     cache-level = <2>;
+             };
+
+             intc: interrupt-controller at fc001000 {
+                     compatible = "arm,cortex-a9-gic";
+                     #interrupt-cells = <3>;
+                     #address-cells = <0>;
+                     interrupt-controller;
+                     /* gic dist base, gic cpu base */
+                     reg = <0xfc001000 0x1000>, <0xfc000100 0x100>;
+             };
+
+             timer0: timer at fc800000 {
+                     compatible = "arm,sp804", "arm,primecell";
+                     reg = <0xfc800000 0x1000>;
+                     /* timer00 & timer01 */
+                     interrupts = <0 0 4>, <0 1 4>;
+                     clocks = <&timclk0 &timclk1>;
+                     clock-names = "apb_pclk";
+                     status = "disabled";
+             };
+
+             timer1: timer at fc801000 {
+                     compatible = "arm,sp804", "arm,primecell";
+                     reg = <0xfc801000 0x1000>;
+                     /* timer10 & timer11 */
+                     interrupts = <0 2 4>, <0 3 4>;
+                     clocks = <&timclk2 &timclk3>;
+                     clock-names = "apb_pclk";
+                     status = "disabled";
+             };
+
+             timer2: timer at fca01000 {
+                     compatible = "arm,sp804", "arm,primecell";
+                     reg = <0xfca01000 0x1000>;
+                     /* timer20 & timer21 */
+                     interrupts = <0 4 4>, <0 5 4>;
+                     clocks = <&timclk4 &timclk5>;
+                     clock-names = "apb_pclk";
+                     status = "disabled";
+             };
+
+             timer3: timer at fca02000 {
+                     compatible = "arm,sp804", "arm,primecell";
+                     reg = <0xfca02000 0x1000>;
+                     /* timer30 & timer31 */
+                     interrupts = <0 6 4>, <0 7 4>;
+                     clocks = <&timclk6 &timclk7>;
+                     clock-names = "apb_pclk";
+                     status = "disabled";
+             };
+
+             timer4: timer at fca03000 {
+                     compatible = "arm,sp804", "arm,primecell";
+                     reg = <0xfca03000 0x1000>;
+                     /* timer40 & timer41 */
+                     interrupts = <0 96 4>, <0 97 4>;
+                     clocks = <&timclk8 &timclk9>;
+                     clock-names = "apb_pclk";
+                     status = "disabled";
+             };
+
+             uart0: uart at fcb00000 {
+                     compatible = "arm,pl011", "arm,primecell";
+                     reg = <0xfcb00000 0x1000>;
+                     interrupts = <0 20 4>;
+                     clocks = <&uartclk0>;
+                     clock-names = "apb_pclk";
+                     status = "disabled";
+             };
+
+             uart1: uart at fcb01000 {
+                     compatible = "arm,pl011", "arm,primecell";
+                     reg = <0xfcb01000 0x1000>;
+                     interrupts = <0 21 4>;
+                     clocks = <&uartclk1>;
+                     clock-names = "apb_pclk";
+                     status = "disabled";
+             };
+
+             uart2: uart at fcb02000 {
+                     compatible = "arm,pl011", "arm,primecell";
+                     reg = <0xfcb02000 0x1000>;
+                     interrupts = <0 22 4>;
+                     clocks = <&uartclk2>;
+                     clock-names = "apb_pclk";
+                     status = "disabled";
+             };
+
+             uart3: uart at fcb03000 {
+                     compatible = "arm,pl011", "arm,primecell";
+                     reg = <0xfcb03000 0x1000>;
+                     interrupts = <0 23 4>;
+                     clocks = <&uartclk3>;
+                     clock-names = "apb_pclk";
+                     status = "disabled";
+             };
+
+             uart4: uart at fcb04000 {
+                     compatible = "arm,pl011", "arm,primecell";
+                     reg = <0xfcb04000 0x1000>;
+                     interrupts = <0 24 4>;
+                     clocks = <&uartclk4>;
+                     clock-names = "apb_pclk";
+                     status = "disabled";
+             };
+
+             gpio0: gpio at fc806000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc806000 0x1000>;
+                     interrupts = <0 64 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
+                                     &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk0>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio1: gpio at fc807000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc807000 0x1000>;
+                     interrupts = <0 65 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
+                                     &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
+                                     &pmx0 6 5 1 &pmx0 7 6 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk1>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio2: gpio at fc808000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc808000 0x1000>;
+                     interrupts = <0 66 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
+                                     &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
+                                     &pmx0 6 3 1 &pmx0 7 3 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk2>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio3: gpio at fc809000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc809000 0x1000>;
+                     interrupts = <0 67 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
+                                     &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
+                                     &pmx0 6 11 1 &pmx0 7 11 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk3>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio4: gpio at fc80a000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc80a000 0x1000>;
+                     interrupts = <0 68 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
+                                     &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
+                                     &pmx0 6 13 1 &pmx0 7 13 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk4>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio5: gpio at fc80b000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc80b000 0x1000>;
+                     interrupts = <0 69 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
+                                     &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
+                                     &pmx0 6 16 1 &pmx0 7 16 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk5>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio6: gpio at fc80c000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc80c000 0x1000>;
+                     interrupts = <0 70 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
+                                     &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
+                                     &pmx0 6 18 1 &pmx0 7 19 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk6>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio7: gpio at fc80d000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc80d000 0x1000>;
+                     interrupts = <0 71 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
+                                     &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
+                                     &pmx0 6 25 1 &pmx0 7 26 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk7>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio8: gpio at fc80e000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc80e000 0x1000>;
+                     interrupts = <0 72 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
+                                     &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
+                                     &pmx0 6 33 1 &pmx0 7 34 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk8>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio9: gpio at fc80f000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc80f000 0x1000>;
+                     interrupts = <0 73 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
+                                     &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
+                                     &pmx0 6 41 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk9>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio10: gpio at fc810000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc810000 0x1000>;
+                     interrupts = <0 74 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
+                                     &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk10>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio11: gpio at fc811000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc811000 0x1000>;
+                     interrupts = <0 75 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
+                                     &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
+                                     &pmx0 6 49 1 &pmx0 7 49 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk11>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio12: gpio at fc812000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc812000 0x1000>;
+                     interrupts = <0 76 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
+                                     &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
+                                     &pmx0 6 51 1 &pmx0 7 52 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk12>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio13: gpio at fc813000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc813000 0x1000>;
+                     interrupts = <0 77 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
+                                     &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
+                                     &pmx0 6 55 1 &pmx0 7 56 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk13>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio14: gpio at fc814000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc814000 0x1000>;
+                     interrupts = <0 78 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
+                                     &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
+                                     &pmx0 6 60 1 &pmx0 7 61 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk14>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio15: gpio at fc815000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc815000 0x1000>;
+                     interrupts = <0 79 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
+                                     &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
+                                     &pmx0 6 64 1 &pmx0 7 65 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk15>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio16: gpio at fc816000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc816000 0x1000>;
+                     interrupts = <0 80 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
+                                     &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
+                                     &pmx0 6 72 1 &pmx0 7 73 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk16>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio17: gpio at fc817000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc817000 0x1000>;
+                     interrupts = <0 81 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
+                                     &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
+                                     &pmx0 6 80 1 &pmx0 7 81 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk17>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio18: gpio at fc818000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc818000 0x1000>;
+                     interrupts = <0 82 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
+                                     &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
+                                     &pmx0 6 86 1 &pmx0 7 87 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk18>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio19: gpio at fc819000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc819000 0x1000>;
+                     interrupts = <0 83 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
+                                     &pmx0 3 88 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk19>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio20: gpio at fc81a000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc81a000 0x1000>;
+                     interrupts = <0 84 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
+                                     &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk20>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             gpio21: gpio at fc81b000 {
+                     compatible = "arm,pl061", "arm,primecell";
+                     reg = <0xfc81b000 0x1000>;
+                     interrupts = <0 85 0x4>;
+                     gpio-controller;
+                     #gpio-cells = <2>;
+                     gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     clocks = <&gpioclk21>;
+                     clock-names = "apb_pclk";
+                     status = "disable";
+             };
+
+             pmx0: pinmux at fc803000 {
+                     compatible = "pinctrl-single";
+                     reg = <0xfc803000 0x188>;
+                     #address-cells = <1>;
+                     #size-cells = <1>;
+                     #gpio-range-cells = <3>;
+                     ranges;
+
+                     pinctrl-single,register-width = <32>;
+                     pinctrl-single,function-mask = <7>;
+                     /* pin base, nr pins & gpio function */
+                     pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
+                                             &range 12 1 0 &range 13 29 1
+                                             &range 43 1 0 &range 44 49 1
+                                             &range 94 1 1 &range 96 2 1>;
+
+                     range: gpio-range {
+                             #pinctrl-single,gpio-range-cells = <3>;
+                     };
+             };
+
+             pmx1: pinmux at fc803800 {
+                     compatible = "pinconf-single";
+                     reg = <0xfc803800 0x2dc>;
+                     #address-cells = <1>;
+                     #size-cells = <1>;
+                     ranges;
+
+                     pinctrl-single,register-width = <32>;
+             };
+     };
+};

arch/arm/boot/dts/hi4511.dts new file +8 -0

new file mode 100644
index 0000000..746b8eb
@@ -0,0 +1,735 @@
+/*
+ *  Copyright (C) 2012-2013 Linaro Ltd.
+ *  Author: Haojian Zhuang <[email protected]>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */

arch/arm/boot/dts/hi4511.dts line 18

Quoted 10 lines

arch/arm/boot/dts/hi4511.dts new file +10 -0

+
+/dts-v1/;
+/include/ "hi3620.dtsi"
+
+/ {
+     model = "Hisilicon Hi4511 Development Board";
+     compatible = "hisilicon,hi3620-hi4511";
+
+     chosen {
+             bootargs = "console=ttyAMA0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on mem=512m earlyprintk";

It probably doesn't make sense to specify your network and nfsroot parameters here, since they will differ from install environment to install enviroment.

Quoted 2 lines

Also, mem=<x> isn't needed here since you ahve a proper memory node below.

Quoted 46 lines

arch/arm/boot/dts/hi4511.dts new file +46 -0

+     };
+
+     memory {
+             reg = <0x00000000 0x20000000>;
+     };
+
+     amba {
+             timer0: timer at fc800000 {
+                     status = "ok";
+             };
+
+             uart0: uart at fcb00000 {  /* console */
+                     pinctrl-names = "default", "idle";
+                     pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
+                     pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
+                     status = "ok";
+             };
+
+             uart1: uart at fcb01000 { /* modem */
+                     pinctrl-names = "default", "idle";
+                     pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
+                     pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>;
+                     status = "ok";
+             };
+
+             uart2: uart at fcb02000 { /* audience */
+                     pinctrl-names = "default", "idle";
+                     pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
+                     pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>;
+                     status = "ok";
+             };
+
+             uart3: uart at fcb03000 {
+                     pinctrl-names = "default", "idle";
+                     pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
+                     pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>;
+                     status = "ok";
+             };
+
+             uart4: uart at fcb04000 {
+                     pinctrl-names = "default", "idle";
+                     pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
+                     pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>;
+                     status = "ok";
+             };
+

Quoted 9 lines

arch/arm/boot/dts/hi4511.dts line 67
Quoted 3 lines
arch/arm/boot/dts/hi4511.dts new file +3 -0
+             gpio0: gpio at fc806000 {
+                     status = "ok";
+             };
In general, only devices that are likely to not use on all boards are status = disable in the dtsi. For things like these gpio entries, are all boards expected to need to enable them anyway? if so, then it's just silly to mark them disabled in the dtsi.

Quoted 11 lines

arch/arm/boot/dts/hi4511.dts line 161

Quoted 10 lines

arch/arm/boot/dts/hi4511.dts new file +9 -0

+             gpio-keys {
+                     compatible = "gpio-keys";
+
+                     call {
+                             label = "call";
+                             gpios = <&gpio17 2 0>;
+                             linux,code = <169>;     /* KEY_PHONE */
+                     };
+             };

Quoted 2 lines

This doesn't really belong under the amba node. Please push to the top instead.

Quoted 13 lines

arch/arm/boot/dts/hi4511.dts line 170
Quoted 9 lines
arch/arm/boot/dts/hi4511.dts new file +9 -0
+
+             pmx0: pinmux at fc803000 {
+                     pinctrl-names = "default";
+                     pinctrl-0 = <&board_pmx_pins>;
+
+                     board_pmx_pins: board_pmx_pins {
+                             pinctrl-single,pins = <
+                                     0x008 0x0       /* GPIO -- eFUSE_DOUT */
+                                     0x100 0x0       /* USIM_CLK & USIM_DATA (IOMG63) */
Please consider using the new preprocessor functions here instead of hardcoded hex values, if it makes sense for your platform -- I think it does?

Quoted 6 lines

Also, it's nice when most of the pinctrl stuff can go in the dtsi file and keep the board file as clean as possible, since you ended up doing a lot of pinctrl entries in this board dts.
-Olof

I don't like preprocessor functions here. Hardcoded hex values with comments is simple & straightforward enough.

There're different pinmux configurations on different boards. So I prefer them defined
in board dts file.

Regards
Haojian

Linus Walleij

2013-06-18 07:38 UTC #12 lore raw

PATCH v4 7/7 ARM: hi3xxx: enable hi4511 with device tree

In reply to Haojian Zhuang

Quoted 8 lines · Haojian Zhuang

arch/arm/boot/dts/hi3620.dtsi new file +8 -0

+                       uart0_mux: uart0_mux {
+                               compatible = "hisilicon,hi3620-clk-mux";
+                               #clock-cells = <0>;
+                               clocks = <&osc26m &pclk>;
+                               clock-output-names = "uart0_mux";
+                               /* reg_offset, mask bits */
+                               hisilicon,clkmux-reg = <0x100 0x80>;
+                               /* each item value */

arch/arm/boot/dts/hi3620.dtsi line 113

Quoted 10 lines

arch/arm/boot/dts/hi3620.dtsi new file +10 -0

+                               hisilicon,clkmux-table = <0 0x80>;
+                       };
+                       uart1_mux: uart1_mux {
+                               compatible = "hisilicon,hi3620-clk-mux";
+                               #clock-cells = <0>;
+                               clocks = <&osc26m &pclk>;
+                               clock-output-names = "uart1_mux";
+                               hisilicon,clkmux-reg = <0x100 0x100>;
+                               hisilicon,clkmux-table = <0x0 0x100>;
+                       };

hisilicon,clkmux-reg and hisilicon,clkmux-table looks like a ladder of power of two.

If the -reg part is register offsets I think it is wrong, I think drivers should know register offsets, instead I would encode a clock ID in the device tree and look up these from a table in the driver. (However this is Mike's decision.)

In any case, #define all these constants with symbolic names using the <dt-bindings/clock/hisilicon.h> or something like that so they are not just magic power of two numbers.

#define HILSILICON_CLOCK_MUX_UART0 (1 << 7)
#define HILSILICON_CLOCK_MUX_UART1 (1 << 8)

hisilicon,clkmux-table = <0x0 HISLICON_CLOCK_MUX_UART0>;

(or similar etc)

arch/arm/boot/dts/hi3620.dtsi line 701

Quoted 5 lines

arch/arm/boot/dts/hi3620.dtsi new file +5 -0

+               timer0: timer at fc800000 {
+                       compatible = "arm,sp804", "arm,primecell";
+                       reg = <0xfc800000 0x1000>;
+                       /* timer00 & timer01 */
+                       interrupts = <0 0 4>, <0 1 4>;

Use

#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h>

And you can write
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/hi4511.dts line 441

Quoted 3 lines

arch/arm/boot/dts/hi4511.dts new file +3 -0

+                               pinctrl-single,bias-pulldown = <0 2 0 2>;
+                               pinctrl-single,bias-pullup = <1 1 0 1>;
+                               pinctrl-single,drive-strength = <0x30 0xf0>;

I think you should invent a <dt-bindings/pinctrl/pinctrl-single.h>
defining all of these magic values in the same manner as the flags above. It will make everything more readable.

Maybe single should simply be switched over to using the new generic pinconfig DT bindings we have in for -next? There we don't use magic cells at all, just string specifiers.

Yours,
Linus Walleij

Olof Johansson

2013-06-12 20:01 UTC #13 lore raw

v4 cover support Hisilicon SoC

In reply to Haojian Zhuang

Quoted 7 lines · Haojian Zhuang

Changelog:
v4:
1. Add clk gate with HIWORD mask for Rockchip.
2. Update comments and code of HIWORD flags for mux/divider.
3. Append a mux without HIWORD mask in Hisilicon 3620.
4. Fix the pinmux setting in Hi4511.

Quoted 9 lines

v3:
1. Use clk_register_mux_table().
v2:
1. Reuse mux & divider driver. So append CLK_MUX_HIWORD_MASK & CLK_DIVIDER_HIWORD_MASK for Hi3620 SoC.
2. Fix system timer running too fast because wrong divider is choosen.
3. Remove .init_irq in DT machine descriptor.

Hi,

I had some comments on the last two patches. I also haven't seen any acks from Mike on any of the clock changes, which would be needed before we can pick them up. He might want to merge them into his tree as well, if so we'll have to setup a shared branch.

-Olof

Heiko Stübner

2013-06-13 16:29 UTC #14 lore raw

v4 cover support Hisilicon SoC

Am Mittwoch, 12. Juni 2013, 22:01:42 schrieb Olof Johansson:

Quoted 17 lines · Haojian Zhuang

Quoted 7 lines
Changelog:
v4:
1. Add clk gate with HIWORD mask for Rockchip.
2. Update comments and code of HIWORD flags for mux/divider.
3. Append a mux without HIWORD mask in Hisilicon 3620.
4. Fix the pinmux setting in Hi4511.
Quoted 8 lines
v3:
1. Use clk_register_mux_table().
v2:
1. Reuse mux & divider driver. So append CLK_MUX_HIWORD_MASK & CLK_DIVIDER_HIWORD_MASK for Hi3620 SoC.
2. Fix system timer running too fast because wrong divider is choosen.
3. Remove .init_irq in DT machine descriptor.

Quoted 6 lines

Hi,
I had some comments on the last two patches. I also haven't seen any acks from Mike on any of the clock changes, which would be needed before we can pick them up. He might want to merge them into his tree as well, if so we'll have to setup a shared branch.

Also, if anything unexpected happens to the main hisilicon support, could you or Mike pick up the HIWORD_MASK patches anyway (if they are acceptable), because they're needed for the Rockchip stuff too.

Thanks
Heiko

Olof Johansson

2013-06-13 19:58 UTC #15 lore raw

v4 cover support Hisilicon SoC

Quoted 20 lines · Heiko St?bner

Am Mittwoch, 12. Juni 2013, 22:01:42 schrieb Olof Johansson:
Quoted 19 lines · Haojian Zhuang
Quoted 7 lines
Changelog:
v4:
1. Add clk gate with HIWORD mask for Rockchip.
2. Update comments and code of HIWORD flags for mux/divider.
3. Append a mux without HIWORD mask in Hisilicon 3620.
4. Fix the pinmux setting in Hi4511.
Quoted 8 lines
v3:
1. Use clk_register_mux_table().
v2:
1. Reuse mux & divider driver. So append CLK_MUX_HIWORD_MASK & CLK_DIVIDER_HIWORD_MASK for Hi3620 SoC.
2. Fix system timer running too fast because wrong divider is choosen.
3. Remove .init_irq in DT machine descriptor.
Hi,

Quoted 8 lines

Quoted 4 lines
I had some comments on the last two patches. I also haven't seen any acks from Mike on any of the clock changes, which would be needed before we can pick them up. He might want to merge them into his tree as well, if so we'll have to setup a shared branch.
Also, if anything unexpected happens to the main hisilicon support, could you or Mike pick up the HIWORD_MASK patches anyway (if they are acceptable), because they're needed for the Rockchip stuff too.

Ok, that definitely means a topic branch would be a good idea. Mike, can you collect these branches on a topic that we can just pull in as a dependency then, please? Assuming you're happy with them, of course.

Thanks!

-Olof

Mike Turquette

2013-06-16 04:08 UTC #16 lore raw

v4 cover support Hisilicon SoC

Quoting Olof Johansson (2013-06-13 12:58:01)

Quoted 26 lines · Heiko St?bner

Quoted 25 lines
Am Mittwoch, 12. Juni 2013, 22:01:42 schrieb Olof Johansson:
Quoted 23 lines · Haojian Zhuang
Quoted 7 lines
Changelog:
v4:
1. Add clk gate with HIWORD mask for Rockchip.
2. Update comments and code of HIWORD flags for mux/divider.
3. Append a mux without HIWORD mask in Hisilicon 3620.
4. Fix the pinmux setting in Hi4511.
Quoted 8 lines
v3:
1. Use clk_register_mux_table().
v2:
1. Reuse mux & divider driver. So append CLK_MUX_HIWORD_MASK & CLK_DIVIDER_HIWORD_MASK for Hi3620 SoC.
2. Fix system timer running too fast because wrong divider is choosen.
3. Remove .init_irq in DT machine descriptor.
Hi,
I had some comments on the last two patches. I also haven't seen any acks from Mike on any of the clock changes, which would be needed before we can pick them up. He might want to merge them into his tree as well, if so we'll have to setup a shared branch.

Quoted 7 lines

Quoted 3 lines
Also, if anything unexpected happens to the main hisilicon support, could you or Mike pick up the HIWORD_MASK patches anyway (if they are acceptable), because they're needed for the Rockchip stuff too.
Ok, that definitely means a topic branch would be a good idea. Mike, can you collect these branches on a topic that we can just pull in as a dependency then, please? Assuming you're happy with them, of course.

Do you mean s/branches/patches/ ?

I've pulled patches #1-#3 into clk-next, but I'd like a couple of rounds through linux-next before I state that a given commit is stable. So maybe early next week (it's still Saturday for me) I'll push out a clk-for-3.11 branch that will have the hiword patches in them and the sha1's will not change.

Regards,
Mike

Quoted 4 lines

Thanks!
-Olof

Olof Johansson

2013-06-16 04:32 UTC #17 lore raw

v4 cover support Hisilicon SoC

Quoted 31 lines · Mike Turquette

Quoting Olof Johansson (2013-06-13 12:58:01)
Quoted 30 lines · Heiko St?bner
Quoted 28 lines
Am Mittwoch, 12. Juni 2013, 22:01:42 schrieb Olof Johansson:
Quoted 17 lines · Haojian Zhuang
Quoted 7 lines
Changelog:
v4:
1. Add clk gate with HIWORD mask for Rockchip.
2. Update comments and code of HIWORD flags for mux/divider.
3. Append a mux without HIWORD mask in Hisilicon 3620.
4. Fix the pinmux setting in Hi4511.
Quoted 8 lines
v3:
1. Use clk_register_mux_table().
v2:
1. Reuse mux & divider driver. So append CLK_MUX_HIWORD_MASK & CLK_DIVIDER_HIWORD_MASK for Hi3620 SoC.
2. Fix system timer running too fast because wrong divider is choosen.
3. Remove .init_irq in DT machine descriptor.
Quoted 6 lines
Hi,
I had some comments on the last two patches. I also haven't seen any acks from Mike on any of the clock changes, which would be needed before we can pick them up. He might want to merge them into his tree as well, if so we'll have to setup a shared branch.
Also, if anything unexpected happens to the main hisilicon support, could you or Mike pick up the HIWORD_MASK patches anyway (if they are acceptable), because they're needed for the Rockchip stuff too.

Quoted 5 lines

Quoted 3 lines
Ok, that definitely means a topic branch would be a good idea. Mike, can you collect these branches on a topic that we can just pull in as a dependency then, please? Assuming you're happy with them, of course.
Do you mean s/branches/patches/ ?

Yes, sorry -- please collect the patches on a stable topic branch (i.e. not part of all of clk-next)

Quoted 5 lines

I've pulled patches #1-#3 into clk-next, but I'd like a couple of rounds through linux-next before I state that a given commit is stable. So maybe early next week (it's still Saturday for me) I'll push out a clk-for-3.11 branch that will have the hiword patches in them and the sha1's will not change.

Ok. We can pull in the larger clk-next branch if you are 100% confident that you won't have to rebase it. If you think there's even a minimal chance you will have to do so, it's better to do these on just a standalone branch that can still be stable commits. Either way works for us though.

-Olof