ARM: KVM: vgic: fix GICD_ICFGRn access
PATCH 1/1 ARM: KVM: vgic: fix GICD_ICFGRn access
All the code in handle_mmio_cfg_reg() assumes the offset has been shifted right to accomodate for the 2:1 bit compression, but this is only done when getting the register addess.
Shift the offset early so the code works mostly unchanged.
--- arch/arm/kvm/vgic.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
arch/arm/kvm/vgic.c +6 -2
@@ -541,8 +541,12 @@ static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) {u32 val; -u32 *reg =vgic_bitmap_get_reg (&vcpu->kvm->arch.vgic.irq_cfg, - vcpu->vcpu_id, offset >>1 ); +u32 *reg; + + offset >>=1 ; + reg =vgic_bitmap_get_reg (&vcpu->kvm->arch.vgic.irq_cfg, + vcpu->vcpu_id, offset); +if (offset &2 ) val = *reg >>16 ;else
Signature · 1 line
1.8.2.3
PATCH 1/1 ARM: KVM: vgic: fix GICD_ICFGRn access
Quoted 3 lines · Marc Zyngier
All the code in
handle_mmio_cfg_reg()assumes the offset has been shifted right to accomodate for the 2:1 bit compression, but this is only done when getting the register addess.
I personally think this is a funky assumption. The offset is called offset, because it's the offset, not a "compressed index" value, so I'd prefer to fix the comparison values instead.
If not, put a comment and explain the assumption, because it's not obvious.
Quoted 37 lines
Shift the offset early so the code works mostly unchanged.
Reported-by Zhaobo (Bob, ERC) <[email protected]>Signed-off-by Marc Zyngier <[email protected]>--- arch/arm/kvm/vgic.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)arch/arm/kvm/vgic.c +6
-2@@ -541,8 +541,12 @@ static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) {u32 val; -u32 *reg =vgic_bitmap_get_reg (&vcpu->kvm->arch.vgic.irq_cfg, - vcpu->vcpu_id, offset >>1 ); +u32 *reg; + + offset >>=1 ; + reg =vgic_bitmap_get_reg (&vcpu->kvm->arch.vgic.irq_cfg, + vcpu->vcpu_id, offset); +if (offset &2 ) val = *reg >>16 ;else Signature · 8 lines
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