ARM: tegra: Create a DT header defining swgroups ID

PATCH Superseded Hiroshi Doyu 2 participants 4 messages Jun 26, 2013

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Device tree bindings Tegra architecture support

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Hiroshi Doyu

author

2013-06-26 09:28 UTC #0 lore raw

PATCH 1/23 ARM: tegra: Create a DT header defining swgroups ID

Create a header file to define the swgroup IDs used by the IOMMU(SMMU) binding. "swgroup" is a group of H/W clients in Tegra SoC from S/W POV.

This will allow the same header to be used by both device tree files, and drivers implementing this binding, which guarantees that the two stay in sync. This also makes device trees more readable by using names instead of magic numbers.

Signed-off-by Hiroshi Doyu <[email protected]>

---
 include/dt-bindings/iommu/tegra-swgid.h | 47 +++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 include/dt-bindings/iommu/tegra-swgid.h

include/dt-bindings/iommu/tegra-swgid.h new file +47 -0

new file mode 100644
index 0000000..b429ce1
@@ -0,0 +1,47 @@
+/*
+ * This header provides constants for binding nvidia,swgroup ID
+ */
+
+#ifndef _DT_BINDINGS_IOMMU_TEGRA_SWGID_H
+#define _DT_BINDINGS_IOMMU_TEGRA_SWGID_H
+
+#define SWGID_AFI 0
+#define SWGID_AVPC 1
+#define SWGID_DC 2
+#define SWGID_DCB 3
+#define SWGID_EPP 4
+#define SWGID_G2 5
+#define SWGID_HC 6
+#define SWGID_HDA 7
+#define SWGID_ISP 8
+#define SWGID_ISP2 SWGID_ISP
+/* UNUSED: 9 */
+/* UNUSED: 10 */
+#define SWGID_MPE 11
+#define SWGID_MSENC SWGID_MPE
+#define SWGID_NV 12
+#define SWGID_NV2 13
+#define SWGID_PPCS 14
+#define SWGID_SATA2 15
+#define SWGID_SATA 16
+#define SWGID_VDE 17
+#define SWGID_VI 18
+#define SWGID_VIC 19
+#define SWGID_XUSB_HOST 20
+#define SWGID_XUSB_DEV 21
+#define SWGID_A9AVP 22
+#define SWGID_TSEC 23
+#define SWGID_PPCS1 24
+/* UNUSED: 25 */
+/* UNUSED: 26 */
+/* UNUSED: 27 */
+/* UNUSED: 28 */
+/* UNUSED: 29 */
+/* UNUSED: 30 */
+/* UNUSED: 31 */
+
+/* Reserved: 32-63 */
+
+#define SWGID(x)	(1ULL << SWGID_##x)
+
+#endif /* _DT_BINDINGS_IOMMU_TEGRA_SWGID_H */

Signature · 1 line

1.8.1.5

Thierry Reding

2013-06-26 10:06 UTC #1 lore raw

PATCH 1/23 ARM: tegra: Create a DT header defining swgroups ID

On Wed, Jun 26, 2013 at 12:28:04PM +0300, Hiroshi Doyu wrote:
[...]

Quoted 28 lines

include/dt-bindings/iommu/tegra-swgid.h new file +28 -0

+#define SWGID_AFI 0
+#define SWGID_AVPC 1
+#define SWGID_DC 2
+#define SWGID_DCB 3
+#define SWGID_EPP 4
+#define SWGID_G2 5
+#define SWGID_HC 6
+#define SWGID_HDA 7
+#define SWGID_ISP 8
+#define SWGID_ISP2 SWGID_ISP
+/* UNUSED: 9 */
+/* UNUSED: 10 */
+#define SWGID_MPE 11
+#define SWGID_MSENC SWGID_MPE
+#define SWGID_NV 12
+#define SWGID_NV2 13
+#define SWGID_PPCS 14
+#define SWGID_SATA2 15
+#define SWGID_SATA 16
+#define SWGID_VDE 17
+#define SWGID_VI 18
+#define SWGID_VIC 19
+#define SWGID_XUSB_HOST 20
+#define SWGID_XUSB_DEV 21
+#define SWGID_A9AVP 22
+#define SWGID_TSEC 23
+#define SWGID_PPCS1 24
+/* UNUSED: 25 */

include/dt-bindings/iommu/tegra-swgid.h line 45

Quoted 10 lines

include/dt-bindings/iommu/tegra-swgid.h new file +10 -0

+/* UNUSED: 26 */
+/* UNUSED: 27 */
+/* UNUSED: 28 */
+/* UNUSED: 29 */
+/* UNUSED: 30 */
+/* UNUSED: 31 */
+
+/* Reserved: 32-63 */
+
+#define SWGID(x)	(1ULL << SWGID_##x)

I'm not entirely sure where to find these mappings in the TRM. I see that there's a list of the groups in 15.10.11, but where do the numbers come from? And why are some of the names aliased? If it's for readability only maybe we could add some more for SWGID_HC -> SWGID_HOST1X and perhaps SWGID_NV -> SWGID_GR3D.

Thierry
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Hiroshi Doyu

author

2013-06-26 10:31 UTC #2 lore raw

PATCH 1/23 ARM: tegra: Create a DT header defining swgroups ID

Hi Thierry,

Thierry Reding <[email protected]> wrote @ Wed, 26 Jun 2013 12:06:49 +0200:
...

Quoted 3 lines

I'm not entirely sure where to find these mappings in the TRM. I see that there's a list of the groups in 15.10.11, but where do the numbers come from?

To convert swgroup ID bit to register address,

#define HWGRP_ASID_REG(x) ((x) * sizeof(u32) + SMMU_AFI_ASID)

in "[PATCH 15/23] iommu/tegra: smmu: Calculate ASID register offset by ID"

Quoted 3 lines

And why are some of the names aliased? If it's for readability only maybe we could add some more for SWGID_HC -> SWGID_HOST1X and perhaps SWGID_NV -> SWGID_GR3D.

I used the exact same name from TRM register definition. I thought that same naming in TRM may be better since this bit is converted to register, but I'm quite open to rename if needed.

Thierry Reding

2013-06-26 10:38 UTC #3 lore raw

PATCH 1/23 ARM: tegra: Create a DT header defining swgroups ID

Quoted 8 lines · Hiroshi Doyu

Hi Thierry,
Thierry Reding <[email protected]> wrote @ Wed, 26 Jun 2013 12:06:49 +0200:
...
Quoted 3 lines
I'm not entirely sure where to find these mappings in the TRM. I see that there's a list of the groups in 15.10.11, but where do the numbers come from?

Quoted 5 lines

To convert swgroup ID bit to register address,
#define HWGRP_ASID_REG(x) ((x) * sizeof(u32) + SMMU_AFI_ASID)
in "[PATCH 15/23] iommu/tegra: smmu: Calculate ASID register offset by ID"

Oh, I see. Thanks for pointing that out.

Quoted 7 lines

Quoted 3 lines
And why are some of the names aliased? If it's for readability only maybe we could add some more for SWGID_HC -> SWGID_HOST1X and perhaps SWGID_NV -> SWGID_GR3D.
I used the exact same name from TRM register definition. I thought that same naming in TRM may be better since this bit is converted to register, but I'm quite open to rename if needed.

I think it's fine to keep the names from the TRM. I was just wondering why some groups can be referenced using multiple names, like ISP2 -> ISP and MSENC -> MPE.