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Use scratch registers when MIPS_PGD_C0_CONTEXT is not set

PATCH Applied Jayachandran C 3 participants 7 messages Jun 23, 2013 – Jun 27, 2013 MIPS

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Jayachandran C

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#0 lore raw

cover Use scratch registers when MIPS_PGD_C0_CONTEXT is not set

This is the updated patchset that fixes issues reported during the last merge to upstream-sfr.

The first patch is a new change that moves the TLB handlers from arrays in .data to functions defined in tlb-funcs.S to fix the microMIPS issue reported.
(http://www.linux-mips.org/archives/linux-mips/2013-06/msg00415.html)

The second patch has the changes to use scratch registers when MIPS_PGD_C0_CONTEXT is not defined - this has not changed.

The third has a fix for the compile error on IP27 platform.
(http://www.linux-mips.org/archives/linux-mips/2013-06/msg00399.html)

Jonas already has posted http://patchwork.linux-mips.org/patch/5539/ for the other issue (crash on bcm63xx and mti platforms)

JC.

Jayachandran C (3):
MIPS: Move generated code to .text for microMIPS
MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT
MIPS: Move definition of SMP processor id register to header file

 arch/mips/include/asm/mmu_context.h |   28 ++---
 arch/mips/include/asm/stackframe.h  |   24 +---
 arch/mips/include/asm/thread_info.h |   33 +++++-
 arch/mips/mm/Makefile               |    2 +-
 arch/mips/mm/tlb-funcs.S            |   37 ++++++
 arch/mips/mm/tlbex.c                |  224 ++++++++++++++++-------------------
 6 files changed, 187 insertions(+), 161 deletions(-)
 create mode 100644 arch/mips/mm/tlb-funcs.S
Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH 1/3 MIPS: Move generated code to .text for microMIPS

Prepare of a next patch which will call tlbmiss_handler_setup_pgd on microMIPS. MicroMIPS complains if the called code s not in the .text section. To fix this we generate code into space reserved in arch/mips/mm/tlb-funcs.S

While there, move the rest of the generated functions (handle_tlbl, handle_tlbs, handle_tlbm) to the same file.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/include/asm/mmu_context.h |    6 +--
 arch/mips/mm/Makefile               |    2 +-
 arch/mips/mm/tlb-funcs.S            |   37 +++++++++++++++
 arch/mips/mm/tlbex.c                |   84 ++++++++++++++++++-----------------
 4 files changed, 83 insertions(+), 46 deletions(-)
 create mode 100644 arch/mips/mm/tlb-funcs.S
arch/mips/include/asm/mmu_context.h +1 -5
index 516e6e9..3b29079 100644
@@ -28,11 +28,7 @@
 
 #define TLBMISS_HANDLER_SETUP_PGD(pgd)					\
 do {									\
-	void (*tlbmiss_handler_setup_pgd)(unsigned long);		\
-	extern u32 tlbmiss_handler_setup_pgd_array[16];			\
-									\
-	tlbmiss_handler_setup_pgd =					\
-		(__typeof__(tlbmiss_handler_setup_pgd)) tlbmiss_handler_setup_pgd_array; \
+	extern void tlbmiss_handler_setup_pgd(unsigned long);		\
 	tlbmiss_handler_setup_pgd((unsigned long)(pgd));		\
 } while (0)
arch/mips/mm/Makefile +1 -1
index e87aae1..7f4f93a 100644
@@ -4,7 +4,7 @@
 
 obj-y				+= cache.o dma-default.o extable.o fault.o \
 				   gup.o init.o mmap.o page.o page-funcs.o \
-				   tlbex.o tlbex-fault.o uasm-mips.o
+				   tlbex.o tlbex-fault.o tlb-funcs.o uasm-mips.o
 
 obj-$(CONFIG_32BIT)		+= ioremap.o pgtable-32.o
 obj-$(CONFIG_64BIT)		+= pgtable-64.o
arch/mips/mm/tlb-funcs.S new file +37 -0
new file mode 100644
index 0000000..30a494d
@@ -0,0 +1,37 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Micro-assembler generated tlb handler functions.
+ *
+ * Copyright (C) 2013  Broadcom Corporation.
+ *
+ * Based on mm/page-funcs.c
+ * Copyright (C) 2012  MIPS Technologies, Inc.
+ * Copyright (C) 2012  Ralf Baechle <[email protected]>
+ */
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+#define FASTPATH_SIZE	128
+
+LEAF(tlbmiss_handler_setup_pgd)
+	.space		16 * 4
+END(tlbmiss_handler_setup_pgd)
+EXPORT(tlbmiss_handler_setup_pgd_end)
+
+LEAF(handle_tlbm)
+	.space		FASTPATH_SIZE * 4
+END(handle_tlbm)
+EXPORT(handle_tlbm_end)
+
+LEAF(handle_tlbs)
+	.space		FASTPATH_SIZE * 4
+END(handle_tlbs)
+EXPORT(handle_tlbs_end)
+
+LEAF(handle_tlbl)
+	.space		FASTPATH_SIZE * 4
+END(handle_tlbl)
+EXPORT(handle_tlbl_end)
arch/mips/mm/tlbex.c +44 -40

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1.7.9.5
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#2 lore raw

PATCH 2/3 MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT

In reply to Jayachandran C

Allow usage of scratch register for current pgd even when MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set for 64r2 platforms to indicate availability of Xcontext for saving cpuid, thus freeing Context to be used for saving PGD. This option was also tied to using a scratch register for storing PGD.

This commit will allow usage of scratch register to store the current pgd if one can be allocated for the platform, even when MIPS_PGD_C0_CONTEXT is not set. The cpuid will be kept in the CP0 Context register in this case.

The code to store the current pgd for the TLB miss handler is now generated in all cases. When scratch register is available, the PGD is also stored in the scratch register.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/include/asm/mmu_context.h |    6 +-
 arch/mips/mm/tlbex.c                |  147 ++++++++++++++++++++++-------------
 2 files changed, 92 insertions(+), 61 deletions(-)
arch/mips/include/asm/mmu_context.h +1 -5
index 3b29079..c846d45 100644
@@ -24,14 +24,13 @@
 #endif /* SMTC */
 #include <asm-generic/mm_hooks.h>
 
-#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
-
 #define TLBMISS_HANDLER_SETUP_PGD(pgd)					\
 do {									\
 	extern void tlbmiss_handler_setup_pgd(unsigned long);		\
 	tlbmiss_handler_setup_pgd((unsigned long)(pgd));		\
 } while (0)
 
+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
 #define TLBMISS_HANDLER_SETUP()						\
 	do {								\
 		TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);		\

@@ -47,9 +46,6 @@ do {									\
  */
 extern unsigned long pgd_current[];
 
-#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
-	pgd_current[smp_processor_id()] = (unsigned long)(pgd)
-
 #ifdef CONFIG_32BIT
 #define TLBMISS_HANDLER_SETUP()						\
 	write_c0_context((unsigned long) smp_processor_id() << 25);	\
arch/mips/mm/tlbex.c +91 -56

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1.7.9.5
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#3 lore raw

PATCH 3/3 MIPS: Move definition of SMP processor id register to header file

In reply to Jayachandran C

The definition of the CP0 register used to save the smp processor id is repicated in many files, move them all to thread_info.h.

Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/include/asm/mmu_context.h |   16 +++-----
 arch/mips/include/asm/stackframe.h  |   24 +++--------
 arch/mips/include/asm/thread_info.h |   33 ++++++++++++++-
 arch/mips/mm/tlbex.c                |   75 +++++------------------------------
 4 files changed, 53 insertions(+), 95 deletions(-)
arch/mips/include/asm/mmu_context.h +5 -11
index c846d45..e277bba 100644
@@ -34,10 +34,11 @@ do {									\
 #define TLBMISS_HANDLER_SETUP()						\
 	do {								\
 		TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);		\
-		write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
+		write_c0_xcontext((unsigned long) smp_processor_id() <<	\
+						SMP_CPUID_REGSHIFT);	\
 	} while (0)
 
-#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
+#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
 
 /*
  * For the fast tlb miss handlers, we keep a per cpu array of pointers

@@ -46,18 +47,11 @@ do {									\
  */
 extern unsigned long pgd_current[];
 
-#ifdef CONFIG_32BIT
 #define TLBMISS_HANDLER_SETUP()						\
-	write_c0_context((unsigned long) smp_processor_id() << 25);	\
+	write_c0_context((unsigned long) smp_processor_id() <<		\
+						SMP_CPUID_REGSHIFT);	\
 	back_to_back_c0_hazard();					\
 	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
-#endif
-#ifdef CONFIG_64BIT
-#define TLBMISS_HANDLER_SETUP()						\
-	write_c0_context((unsigned long) smp_processor_id() << 26);	\
-	back_to_back_c0_hazard();					\
-	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
-#endif
 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
arch/mips/include/asm/stackframe.h +6 -18
index a89d1b1..1728933 100644
@@ -17,6 +17,7 @@
 #include <asm/asmmacro.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
 
 /*
  * For SMTC kernel, global IE should be left set, and interrupts

@@ -85,21 +86,8 @@
 		.endm
 
 #ifdef CONFIG_SMP
-#ifdef CONFIG_MIPS_MT_SMTC
-#define PTEBASE_SHIFT	19	/* TCBIND */
-#define CPU_ID_REG CP0_TCBIND
-#define CPU_ID_MFC0 mfc0
-#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
-#define PTEBASE_SHIFT	48	/* XCONTEXT */
-#define CPU_ID_REG CP0_XCONTEXT
-#define CPU_ID_MFC0 MFC0
-#else
-#define PTEBASE_SHIFT	23	/* CONTEXT */
-#define CPU_ID_REG CP0_CONTEXT
-#define CPU_ID_MFC0 MFC0
-#endif
 		.macro	get_saved_sp	/* SMP variation */
-		CPU_ID_MFC0	k0, CPU_ID_REG
+		ASM_CPUID_MFC0	k0, ASM_SMP_CPUID_REG
 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
 		lui	k1, %hi(kernelsp)
 #else

@@ -109,17 +97,17 @@
 		daddiu	k1, %hi(kernelsp)
 		dsll	k1, 16
 #endif
-		LONG_SRL	k0, PTEBASE_SHIFT
+		LONG_SRL	k0, SMP_CPUID_PTRSHIFT
 		LONG_ADDU	k1, k0
 		LONG_L	k1, %lo(kernelsp)(k1)
 		.endm
 
 		.macro	set_saved_sp stackp temp temp2
-		CPU_ID_MFC0	\temp, CPU_ID_REG
-		LONG_SRL	\temp, PTEBASE_SHIFT
+		ASM_CPUID_MFC0	\temp, ASM_SMP_CPUID_REG
+		LONG_SRL	\temp, SMP_CPUID_PTRSHIFT
 		LONG_S	\stackp, kernelsp(\temp)
 		.endm
-#else
+#else /* !CONFIG_SMP */
 		.macro	get_saved_sp	/* Uniprocessor variation */
 #ifdef CONFIG_CPU_JUMP_WORKAROUNDS
 		/*
arch/mips/include/asm/thread_info.h +32 -1
index 61215a3..e0c8cf3 100644
@@ -147,6 +147,37 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_ALLWORK_MASK	(_TIF_NOHZ | _TIF_WORK_MASK |		\
 				 _TIF_WORK_SYSCALL_EXIT)
 
-#endif /* __KERNEL__ */
+/*
+ * We stash processor id into a COP0 register to retrieve it fast
+ * at kernel exception entry.
+ */
+#if defined(CONFIG_MIPS_MT_SMTC)
+#define SMP_CPUID_REG		2, 2	/* TCBIND */
+#define ASM_SMP_CPUID_REG	$2, 2
+#define SMP_CPUID_PTRSHIFT	19
+#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
+#define SMP_CPUID_REG		20, 0	/* XCONTEXT */
+#define ASM_SMP_CPUID_REG	$20
+#define SMP_CPUID_PTRSHIFT	48
+#else
+#define SMP_CPUID_REG		4, 0	/* CONTEXT */
+#define ASM_SMP_CPUID_REG	$4
+#define SMP_CPUID_PTRSHIFT	23
+#endif
 
+#ifdef CONFIG_64BIT
+#define SMP_CPUID_REGSHIFT	(SMP_CPUID_PTRSHIFT + 3)
+#else
+#define SMP_CPUID_REGSHIFT	(SMP_CPUID_PTRSHIFT + 2)
+#endif
+
+#ifdef CONFIG_MIPS_MT_SMTC
+#define ASM_CPUID_MFC0		mfc0
+#define UASM_i_CPUID_MFC0	uasm_i_mfc0
+#else
+#define ASM_CPUID_MFC0		MFC0
+#define UASM_i_CPUID_MFC0	UASM_i_MFC0
+#endif
+
+#endif /* __KERNEL__ */
 #endif /* _ASM_THREAD_INFO_H */
arch/mips/mm/tlbex.c +10 -65

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#5 lore raw
In reply to Jayachandran C
Quoted 6 lines · Jayachandran C

Jayachandran C (3):
MIPS: Move generated code to .text for microMIPS
MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT
MIPS: Move definition of SMP processor id register to header file

Quoted 9 lines
  arch/mips/include/asm/mmu_context.h |   28 ++---
  arch/mips/include/asm/stackframe.h  |   24 +---
  arch/mips/include/asm/thread_info.h |   33 +++++-
  arch/mips/mm/Makefile               |    2 +-
  arch/mips/mm/tlb-funcs.S            |   37 ++++++
  arch/mips/mm/tlbex.c                |  224 ++++++++++++++++-------------------
  6 files changed, 187 insertions(+), 161 deletions(-)

create mode 100644 arch/mips/mm/tlb-funcs.S

The microMIPS kernel compiles, but fails to boot. It stops at:

Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)

and does not go any further. I will look at this later this evening.

-Steve

#6 lore raw
Quoted 14 lines · Steven J. Hill
Quoted 5 lines

Jayachandran C (3):
MIPS: Move generated code to .text for microMIPS
MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT
MIPS: Move definition of SMP processor id register to header file

Quoted 9 lines
 arch/mips/include/asm/mmu_context.h |   28 ++---
 arch/mips/include/asm/stackframe.h  |   24 +---
 arch/mips/include/asm/thread_info.h |   33 +++++-
 arch/mips/mm/Makefile               |    2 +-
 arch/mips/mm/tlb-funcs.S            |   37 ++++++
 arch/mips/mm/tlbex.c                |  224 ++++++++++++++++-------------------
 6 files changed, 187 insertions(+), 161 deletions(-)
 create mode 100644 arch/mips/mm/tlb-funcs.S
Quoted 5 lines

The microMIPS kernel compiles, but fails to boot. It stops at:

   Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)

and does not go any further. I will look at this later this evening.

I'll leave the series applied for now then.

Ralf