Add DVFS support on APE6EVM

PATCH New Guennadi Liakhovetski 3 participants 10 messages Jun 21, 2013 – Jun 27, 2013

Subsystems (5)

Device tree bindings Arm (32-bit) Arm sub-architectures SuperH +1 more subsystems

lore

Share & tools

lore

Guennadi Liakhovetski

author

2013-06-21 07:10 UTC #0 lore raw

cover Add DVFS support on APE6EVM

Having added CPUFreq support to the Cortex A15 cores on APE6 (r8a73a4) and DT support to the max8973 regulator driver it is now possible to implement CA15 CPUFreq support on APE6EVM, using a max8972 PMU to adjust SoC's DVFS voltage. This series depends on earlier

"ARM: shmobile: r8a73a4: wait for completion when kicking the clock"
https://patchwork.kernel.org/patch/2601071/
"ARM: shmobile: r8a73a4: implement CPU clock scaling for CPUFreq"
https://patchwork.kernel.org/patch/2601111/

and requires the following max8973 patches:

"regulators: max8973: fix multiple instance support"
http://www.mail-archive.com/linux-kernel at vger.kernel.org/msg456101.html "regulators: max8973: initial DT support"
http://www.mail-archive.com/linux-kernel at vger.kernel.org/msg456102.html

Cc Guennadi Liakhovetski <[email protected]>

Guennadi Liakhovetski (4):
ARM: shmobile: r8a73a4: safeguard against wrong clk_set_rate() uses
ARM: shmobile: r8a73a4: add I2C DT nodes and required clocks
ARM: shmobile: ape6evm: add CPUFreq support
ARM: shmobile: r8a73a4: add Z2 clock support

 arch/arm/boot/dts/r8a73a4-ape6evm.dts  |   26 ++++++++++
 arch/arm/boot/dts/r8a73a4.dtsi         |   81 ++++++++++++++++++++++++++++++++
 arch/arm/mach-shmobile/clock-r8a73a4.c |   56 +++++++++++++++++++++-
 3 files changed, 160 insertions(+), 3 deletions(-)

Signature · 8 lines

1.7.2.5

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/

Guennadi Liakhovetski

author

2013-06-21 07:10 UTC #1 lore raw

PATCH 1/4 ARM: shmobile: r8a73a4: safeguard against wrong clk_set_rate() uses

clk_set_rate() should only be called with exact rates, returned by clk_round_rate(). However, it is still good to verify, that the value, passed to clock's .set_rate() method is at least valid. This patch adds such a check for the Z-clock on r8a73a4.

Signed-off-by Guennadi Liakhovetski <[email protected]>

---
 arch/arm/mach-shmobile/clock-r8a73a4.c |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

arch/arm/mach-shmobile/clock-r8a73a4.c +13 -1

index eb42740..cbf9852 100644
@@ -225,16 +225,28 @@ static int zclk_set_rate(struct clk *clk, unsigned long rate)
 		goto done;
 	}
 
-	frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
+	/*
+	 * Users are supposed to first call clk_set_rate() only with
+	 * clk_round_rate() results. So, we don't fix wrong rates here, but
+	 * guard against them anyway
+	 */
 
 	p_rate = clk_get_rate(clk->parent);
 	if (rate == p_rate) {
 		val = 0;
 	} else {
 		step = DIV_ROUND_CLOSEST(p_rate, 32);
+
+		if (rate > p_rate || rate < step) {
+			ret = -EINVAL;
+			goto done;
+		}
+
 		val = 32 - rate / step;
 	}
 
+	frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
+
 	iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
 		  (val << clk->enable_bit), frqcrc);

Signature · 1 line

1.7.2.5

Simon Horman

2013-06-27 07:16 UTC #2 lore raw

PATCH 1/4 ARM: shmobile: r8a73a4: safeguard against wrong clk_set_rate() uses

Quoted 6 lines · Guennadi Liakhovetski

clk_set_rate() should only be called with exact rates, returned by clk_round_rate(). However, it is still good to verify, that the value, passed to clock's .set_rate() method is at least valid. This patch adds such a check for the Z-clock on r8a73a4.
Signed-off-by Guennadi Liakhovetski <[email protected]>

Thanks, I have queued this up for v3.12 in the soc branch.

Quoted 46 lines

---
 arch/arm/mach-shmobile/clock-r8a73a4.c |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

arch/arm/mach-shmobile/clock-r8a73a4.c +13 -1

index eb42740..cbf9852 100644
@@ -225,16 +225,28 @@ static int zclk_set_rate(struct clk *clk, unsigned long rate)
 		goto done;
 	}
 
-	frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
+	/*
+	 * Users are supposed to first call clk_set_rate() only with
+	 * clk_round_rate() results. So, we don't fix wrong rates here, but
+	 * guard against them anyway
+	 */
 
 	p_rate = clk_get_rate(clk->parent);
 	if (rate == p_rate) {
 		val = 0;
 	} else {
 		step = DIV_ROUND_CLOSEST(p_rate, 32);
+
+		if (rate > p_rate || rate < step) {
+			ret = -EINVAL;
+			goto done;
+		}
+
 		val = 32 - rate / step;
 	}
 
+	frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
+
 	iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
 		  (val << clk->enable_bit), frqcrc);

Signature · 6 lines

1.7.2.5

--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in
the body of a message to majordomo at vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Guennadi Liakhovetski

author

2013-06-21 07:10 UTC #3 lore raw

PATCH 2/4 ARM: shmobile: r8a73a4: add I2C DT nodes and required clocks

In reply to Guennadi Liakhovetski

r8a73a4 SoCs have numerous I2C controllers, of which 9 are compatible with the i2c-sh_mobile.c driver. This patch adds Device Tree nodes and clock definitions for them.

Signed-off-by Guennadi Liakhovetski <[email protected]>

---
 arch/arm/boot/dts/r8a73a4.dtsi         |   81 ++++++++++++++++++++++++++++++++
 arch/arm/mach-shmobile/clock-r8a73a4.c |   25 +++++++++-
 2 files changed, 104 insertions(+), 2 deletions(-)

arch/arm/boot/dts/r8a73a4.dtsi +81 -0

index 4ff2019..4e1ddf0 100644
@@ -85,4 +85,85 @@
 		interrupt-parent = <&gic>;
 		interrupts = <0 69 4>;
 	};
+
+	i2c0: i2c at e6500000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6500000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 174 0x4>;
+	};
+
+	i2c1: i2c at e6510000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6510000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 175 0x4>;
+	};
+
+	i2c2: i2c at e6520000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6520000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 176 0x4>;
+	};
+
+	i2c3: i2c at e6530000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6530000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 177 0x4>;
+	};
+
+	i2c4: i2c at e6540000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6540000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 178 0x4>;
+	};
+
+	i2c5: i2c at e60b0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe60b0000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 179 0x4>;
+	};
+
+	i2c6: i2c at e6550000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6550000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 184 0x4>;
+	};
+
+	i2c7: i2c at e6560000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6560000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 185 0x4>;
+	};
+
+	i2c8: i2c at e6570000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6570000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 173 0x4>;
+	};
 };

arch/arm/mach-shmobile/clock-r8a73a4.c +23 -2

index cbf9852..508cb1e 100644
@@ -30,6 +30,7 @@
 
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR3 0xe615013c
+#define SMSTPCR4 0xe6150140
 #define SMSTPCR5 0xe6150144
 
 #define FRQCRA		0xE6150000

@@ -487,8 +488,10 @@ static struct clk div6_clks[DIV6_NR] = {
 /* MSTP */
 enum {
 	MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
-	MSTP315, MSTP314, MSTP313, MSTP312, MSTP305,
-	MSTP522,
+	MSTP323, MSTP318, MSTP317, MSTP316,
+	MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
+	MSTP411, MSTP410, MSTP409,
+	MSTP522, MSTP515,
 	MSTP_NR
 };

@@ -499,12 +502,21 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],	SMSTPCR2, 7, 0), /* SCIFB1 */
 	[MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],	SMSTPCR2, 16, 0), /* SCIFB2 */
 	[MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],	SMSTPCR2, 17, 0), /* SCIFB3 */
+	[MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3, 0, 0), /* IIC2 */
 	[MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
 	[MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
 	[MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
 	[MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
 	[MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
+	[MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3, 16, 0), /* IIC6 */
+	[MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3, 17, 0), /* IIC7 */
+	[MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3, 18, 0), /* IIC0 */
+	[MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3, 23, 0), /* IIC1 */
+	[MSTP409] = SH_CLK_MSTP32(&main_div2_clk,	SMSTPCR4, 9, 0), /* IIC5 */
+	[MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR4, 10, 0), /* IIC4 */
+	[MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR4, 11, 0), /* IIC3 */
 	[MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
+	[MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR5, 15, 0), /* IIC8 */
 };
 
 static struct clk_lookup lookups[] = {

@@ -549,6 +561,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
 	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
+	CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
 	CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
 	CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),

@@ -559,6 +572,14 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
 	CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
 	CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
+	CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
+	CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
+	CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
+	CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
+	CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
+	CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
+	CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
+	CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]),
 
 	/* for DT */
 	CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),

Signature · 1 line

1.7.2.5

Simon Horman

2013-06-27 07:19 UTC #4 lore raw

PATCH 2/4 ARM: shmobile: r8a73a4: add I2C DT nodes and required clocks

Quoted 5 lines · Guennadi Liakhovetski

r8a73a4 SoCs have numerous I2C controllers, of which 9 are compatible with the i2c-sh_mobile.c driver. This patch adds Device Tree nodes and clock definitions for them.
Signed-off-by Guennadi Liakhovetski <[email protected]>

Hi Guennadi,

please split this patch up into two patches.
One patch that touches r8a73a4.dtsi and another patch that touches clock-r8a73a4.c.

When you submit this patch split in two pleas also include the 3rd patch of this series - I have queued up the 1st and 4th patches of the series.

Please include the following when you submit the new series:

Acked-by Kuninori Morimoto <[email protected]>

Quoted 173 lines

---
 arch/arm/boot/dts/r8a73a4.dtsi         |   81 ++++++++++++++++++++++++++++++++
 arch/arm/mach-shmobile/clock-r8a73a4.c |   25 +++++++++-
 2 files changed, 104 insertions(+), 2 deletions(-)

arch/arm/boot/dts/r8a73a4.dtsi +81 -0

index 4ff2019..4e1ddf0 100644
@@ -85,4 +85,85 @@
 		interrupt-parent = <&gic>;
 		interrupts = <0 69 4>;
 	};
+
+	i2c0: i2c at e6500000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6500000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 174 0x4>;
+	};
+
+	i2c1: i2c at e6510000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6510000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 175 0x4>;
+	};
+
+	i2c2: i2c at e6520000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6520000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 176 0x4>;
+	};
+
+	i2c3: i2c at e6530000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6530000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 177 0x4>;
+	};
+
+	i2c4: i2c at e6540000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6540000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 178 0x4>;
+	};
+
+	i2c5: i2c at e60b0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe60b0000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 179 0x4>;
+	};
+
+	i2c6: i2c at e6550000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6550000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 184 0x4>;
+	};
+
+	i2c7: i2c at e6560000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6560000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 185 0x4>;
+	};
+
+	i2c8: i2c at e6570000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,rmobile-iic";
+		reg = <0 0xe6570000 0 0x428>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 173 0x4>;
+	};
 };

arch/arm/mach-shmobile/clock-r8a73a4.c +23 -2

index cbf9852..508cb1e 100644
@@ -30,6 +30,7 @@
 
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR3 0xe615013c
+#define SMSTPCR4 0xe6150140
 #define SMSTPCR5 0xe6150144
 
 #define FRQCRA		0xE6150000

@@ -487,8 +488,10 @@ static struct clk div6_clks[DIV6_NR] = {
 /* MSTP */
 enum {
 	MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
-	MSTP315, MSTP314, MSTP313, MSTP312, MSTP305,
-	MSTP522,
+	MSTP323, MSTP318, MSTP317, MSTP316,
+	MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
+	MSTP411, MSTP410, MSTP409,
+	MSTP522, MSTP515,
 	MSTP_NR
 };

@@ -499,12 +502,21 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],	SMSTPCR2, 7, 0), /* SCIFB1 */
 	[MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],	SMSTPCR2, 16, 0), /* SCIFB2 */
 	[MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],	SMSTPCR2, 17, 0), /* SCIFB3 */
+	[MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3, 0, 0), /* IIC2 */
 	[MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
 	[MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
 	[MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
 	[MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
 	[MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
+	[MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3, 16, 0), /* IIC6 */
+	[MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3, 17, 0), /* IIC7 */
+	[MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3, 18, 0), /* IIC0 */
+	[MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR3, 23, 0), /* IIC1 */
+	[MSTP409] = SH_CLK_MSTP32(&main_div2_clk,	SMSTPCR4, 9, 0), /* IIC5 */
+	[MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR4, 10, 0), /* IIC4 */
+	[MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR4, 11, 0), /* IIC3 */
 	[MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
+	[MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR5, 15, 0), /* IIC8 */
 };
 
 static struct clk_lookup lookups[] = {

@@ -549,6 +561,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
 	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
+	CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
 	CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
 	CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),

@@ -559,6 +572,14 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
 	CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
 	CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
+	CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
+	CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
+	CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
+	CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
+	CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
+	CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
+	CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
+	CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]),
 
 	/* for DT */
 	CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),

Signature · 6 lines

1.7.2.5

--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in
the body of a message to majordomo at vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Guennadi Liakhovetski

author

2013-06-21 07:10 UTC #5 lore raw

PATCH 3/4 ARM: shmobile: ape6evm: add CPUFreq support

In reply to Guennadi Liakhovetski

This patch adds OPPs to the CA15 DT node and a max8973 DT node to support clock and voltage scaling, using the cpufreq-cpu0 CPUFreq driver.

Signed-off-by Guennadi Liakhovetski <[email protected]>

---
 arch/arm/boot/dts/r8a73a4-ape6evm.dts |   26 ++++++++++++++++++++++++++
 1 files changed, 26 insertions(+), 0 deletions(-)

arch/arm/boot/dts/r8a73a4-ape6evm.dts +26 -0

index 4fb0102..af6bd40 100644
@@ -52,3 +52,29 @@
 		};
 	};
 };
+
+&i2c5 {
+	max8973 at 1b {
+		compatible = "maxium,max8973";
+		reg = <0x1b>;
+
+		regulators {
+			vdd_dvfs: dcdc {
+				regulator-min-microvolt = <935000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&cpu0 {
+	cpu0-supply = <&vdd_dvfs>;
+	operating-points = <
+		/* kHz  uV */
+		1950000 1115000
+		1462500  995000
+	>;
+	voltage-tolerance = <1>; /* 1% */
+};

Signature · 1 line

1.7.2.5

Guennadi Liakhovetski

author

2013-06-21 07:10 UTC #6 lore raw

PATCH 4/4 ARM: shmobile: r8a73a4: add Z2 clock support

In reply to Guennadi Liakhovetski

The Z2 clock on r8a73a4 is used to clock the 4 Cortex A7 cores on the SoC. Add a definition for this clock to later use it from the arm_big_little CPUFreq driver.

Signed-off-by Guennadi Liakhovetski <[email protected]>

---
 arch/arm/mach-shmobile/clock-r8a73a4.c |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)

arch/arm/mach-shmobile/clock-r8a73a4.c +17 -0

index 508cb1e..b717e98 100644
@@ -324,6 +324,21 @@ static struct clk z_clk = {
 	.ops = &zclk_ops,
 };
 
+/*
+ * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
+ * switching is only available in auto-DVFS mode
+ */
+SH_FIXED_RATIO_CLK(pll0_div2_clk,	pll0_clk,		div2);
+
+static struct clk z2_clk = {
+	.parent = &pll0_div2_clk,
+	.div_mask = 0x1f,
+	.enable_bit = 0,
+	/* We'll need to access FRQCRB and FRQCRC */
+	.enable_reg = (void __iomem *)FRQCRB,
+	.ops = &zclk_ops,
+};
+
 static struct clk *main_clks[] = {
 	&extalr_clk,
 	&extal1_clk,

@@ -342,6 +357,8 @@ static struct clk *main_clks[] = {
 	&pll2s_clk,
 	&pll2h_clk,
 	&z_clk,
+	&pll0_div2_clk,
+	&z2_clk,
 };
 
 /* DIV4 */

Signature · 1 line

1.7.2.5

Simon Horman

2013-06-27 07:16 UTC #7 lore raw

PATCH 4/4 ARM: shmobile: r8a73a4: add Z2 clock support

Quoted 5 lines · Guennadi Liakhovetski

The Z2 clock on r8a73a4 is used to clock the 4 Cortex A7 cores on the SoC. Add a definition for this clock to later use it from the arm_big_little CPUFreq driver.
Signed-off-by Guennadi Liakhovetski <[email protected]>

Thanks, I have queued this up for v3.12 in the soc branch.

Quoted 42 lines

---
 arch/arm/mach-shmobile/clock-r8a73a4.c |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)

arch/arm/mach-shmobile/clock-r8a73a4.c +17 -0

index 508cb1e..b717e98 100644
@@ -324,6 +324,21 @@ static struct clk z_clk = {
 	.ops = &zclk_ops,
 };
 
+/*
+ * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
+ * switching is only available in auto-DVFS mode
+ */
+SH_FIXED_RATIO_CLK(pll0_div2_clk,	pll0_clk,		div2);
+
+static struct clk z2_clk = {
+	.parent = &pll0_div2_clk,
+	.div_mask = 0x1f,
+	.enable_bit = 0,
+	/* We'll need to access FRQCRB and FRQCRC */
+	.enable_reg = (void __iomem *)FRQCRB,
+	.ops = &zclk_ops,
+};
+
 static struct clk *main_clks[] = {
 	&extalr_clk,
 	&extal1_clk,

@@ -342,6 +357,8 @@ static struct clk *main_clks[] = {
 	&pll2s_clk,
 	&pll2h_clk,
 	&z_clk,
+	&pll0_div2_clk,
+	&z2_clk,
 };
 
 /* DIV4 */

Signature · 1 line

1.7.2.5

Simon Horman

2013-06-27 04:45 UTC #8 lore raw

cover Add DVFS support on APE6EVM

In reply to Guennadi Liakhovetski

Quoted 10 lines · Guennadi Liakhovetski

Having added CPUFreq support to the Cortex A15 cores on APE6 (r8a73a4) and DT support to the max8973 regulator driver it is now possible to implement CA15 CPUFreq support on APE6EVM, using a max8972 PMU to adjust SoC's DVFS voltage. This series depends on earlier
"ARM: shmobile: r8a73a4: wait for completion when kicking the clock"
https://patchwork.kernel.org/patch/2601071/
"ARM: shmobile: r8a73a4: implement CPU clock scaling for CPUFreq"
https://patchwork.kernel.org/patch/2601111/

Quoted 8 lines

and requires the following max8973 patches:
"regulators: max8973: fix multiple instance support"
http://www.mail-archive.com/linux-kernel at vger.kernel.org/msg456101.html "regulators: max8973: initial DT support"
http://www.mail-archive.com/linux-kernel at vger.kernel.org/msg456102.html
Cc Guennadi Liakhovetski <[email protected]>

Magnus, Morimoto-san,

could you take some time to review this?

Kuninori Morimoto

2013-06-27 05:29 UTC #9 lore raw

cover Add DVFS support on APE6EVM

In reply to Guennadi Liakhovetski

I have no objection.
For all patches

Acked-by Kuninori Morimoto <[email protected]>

Quoted 26 lines · Guennadi

Having added CPUFreq support to the Cortex A15 cores on APE6 (r8a73a4) and DT support to the max8973 regulator driver it is now possible to implement CA15 CPUFreq support on APE6EVM, using a max8972 PMU to adjust SoC's DVFS voltage. This series depends on earlier
"ARM: shmobile: r8a73a4: wait for completion when kicking the clock"
https://patchwork.kernel.org/patch/2601071/
"ARM: shmobile: r8a73a4: implement CPU clock scaling for CPUFreq"
https://patchwork.kernel.org/patch/2601111/
and requires the following max8973 patches:
"regulators: max8973: fix multiple instance support"
http://www.mail-archive.com/linux-kernel at vger.kernel.org/msg456101.html "regulators: max8973: initial DT support"
http://www.mail-archive.com/linux-kernel at vger.kernel.org/msg456102.html
Cc Guennadi Liakhovetski <[email protected]>
Guennadi Liakhovetski (4):
ARM: shmobile: r8a73a4: safeguard against wrong clk_set_rate() uses
ARM: shmobile: r8a73a4: add I2C DT nodes and required clocks
ARM: shmobile: ape6evm: add CPUFreq support
ARM: shmobile: r8a73a4: add Z2 clock support

Quoted 18 lines

 arch/arm/boot/dts/r8a73a4-ape6evm.dts  |   26 ++++++++++
 arch/arm/boot/dts/r8a73a4.dtsi         |   81 ++++++++++++++++++++++++++++++++
 arch/arm/mach-shmobile/clock-r8a73a4.c |   56 +++++++++++++++++++++-
 3 files changed, 160 insertions(+), 3 deletions(-)

Signature · 12 lines

1.7.2.5

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in
the body of a message to majordomo at vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

---
Kuninori Morimoto

??????????????
??????????????????????

                  ????????????????

Best regards
---
Kuninori Morimoto