ARM: shmobile: r8a7790 SMP prototype v2

PATCH New Magnus Damm 3 participants 7 messages Jun 26, 2013 – Jul 9, 2013

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Magnus Damm

author maintainer

2013-06-26 23:58 UTC #0 lore raw

PATCH 1/1 ARM: shmobile: r8a7790 SMP prototype v2

From: Magnus Damm <[email protected]>

Add SMP prototype support for r8a7790 by enabling one cluster of either 4 x Cortex-A7 or 4 x Cortex-A15.

This patch only adds support for booting, at this point no CPU Hotplug is included. The big cluster is known to work well, support for LITTLE needs more work.

On r8a7790 the MD6 pin control boot processor, and on the Lager board SW8.7 can be used to select big or LITTLE.

Signed-off-by Magnus Damm <[email protected]>

---

Written on top of renesas-next-20130620

 arch/arm/boot/dts/r8a7790.dtsi                |   49 ++++++
 arch/arm/mach-shmobile/Makefile               |    1 
 arch/arm/mach-shmobile/board-lager.c          |    1 
 arch/arm/mach-shmobile/include/mach/common.h  |    1 
 arch/arm/mach-shmobile/include/mach/r8a7790.h |    1 
 arch/arm/mach-shmobile/setup-r8a7790.c        |    1 
 arch/arm/mach-shmobile/smp-r8a7790.c          |  187 +++++++++++++++++++++++++
 7 files changed, 241 insertions(+)

arch/arm/boot/dts/r8a7790.dtsi +49 -0

@@ -24,6 +24,55 @@
 			reg = <0>;
 			clock-frequency = <1300000000>;
 		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <1>;
+			clock-frequency = <1300000000>;
+		};
+
+		cpu2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <2>;
+			clock-frequency = <1300000000>;
+		};
+
+		cpu3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <3>;
+			clock-frequency = <1300000000>;
+		};
+
+		cpu4: cpu at 4 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x100>;
+			clock-frequency = <780000000>;
+		};
+
+		cpu5: cpu at 5 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x101>;
+			clock-frequency = <780000000>;
+		};
+
+		cpu6: cpu at 6 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x102>;
+			clock-frequency = <780000000>;
+		};
+
+		cpu7: cpu at 7 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x103>;
+			clock-frequency = <780000000>;
+		};
 	};
 
 	gic: interrupt-controller at f1001000 {

arch/arm/mach-shmobile/Makefile +1 -0

@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.
 smp-y				:= platsmp.o headsmp.o
 smp-$(CONFIG_ARCH_SH73A0)	+= smp-sh73a0.o headsmp-scu.o
 smp-$(CONFIG_ARCH_R8A7779)	+= smp-r8a7779.o headsmp-scu.o
+smp-$(CONFIG_ARCH_R8A7790)	+= smp-r8a7790.o
 smp-$(CONFIG_ARCH_EMEV2)	+= smp-emev2.o headsmp-scu.o
 
 # IRQ objects

arch/arm/mach-shmobile/board-lager.c +1 -0

@@ -103,6 +103,7 @@ static const char *lager_boards_compat_d
 };
 
 DT_MACHINE_START(LAGER_DT, "lager")
+	.smp		= smp_ops(r8a7790_smp_ops),
 	.init_irq	= irqchip_init,
 	.init_time	= r8a7790_timer_init,
 	.init_machine	= lager_add_standard_devices,

arch/arm/mach-shmobile/include/mach/common.h +1 -0

@@ -11,6 +11,7 @@ extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
 extern unsigned long shmobile_boot_arg;
 extern void shmobile_boot_scu(void);
+extern void shmobile_invalidate_start(void);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);

arch/arm/mach-shmobile/include/mach/r8a7790.h +1 -0

@@ -5,5 +5,6 @@ void r8a7790_add_standard_devices(void);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
 void r8a7790_timer_init(void);
+extern struct smp_operations r8a7790_smp_ops;
 
 #endif /* __ASM_R8A7790_H__ */

arch/arm/mach-shmobile/setup-r8a7790.c +1 -0

@@ -188,6 +188,7 @@ static const char *r8a7790_boards_compat
 };
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
+	.smp		= smp_ops(r8a7790_smp_ops),
 	.init_irq	= irqchip_init,
 	.init_machine	= r8a7790_add_standard_devices_dt,
 	.init_time	= r8a7790_timer_init,

arch/arm/mach-shmobile/smp-r8a7790.c new file +187 -0

187 lines not on this page · raw message

Magnus Damm

author maintainer

2013-07-08 04:48 UTC #2 lore raw

PATCH 1/1 ARM: shmobile: r8a7790 SMP prototype v2

Quoted 7 lines · Russell King - ARM Linux

arch/arm/mach-shmobile/smp-r8a7790.c line 23
Quoted 4 lines · Magnus Damm
arch/arm/mach-shmobile/smp-r8a7790.c new file +4 -0
+#include <linux/smp.h>
+#include <linux/irqchip/arm-gic.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
Please always use linux/io.h

Will do, thanks!

/ magnus

Arnd Bergmann

2013-06-27 12:01 UTC #3 lore raw

PATCH 1/1 ARM: shmobile: r8a7790 SMP prototype v2

In reply to Magnus Damm

Quoted 9 lines · Magnus Damm

arch/arm/mach-shmobile/smp-r8a7790.c new file +9 -0

+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/smp_plat.h>
+
+#define SYSC	0xe6180000
+#define SYSCSR  0x0000
+
+#define RST	0xe6160000
+#define CA15BAR	0x6020

arch/arm/mach-shmobile/smp-r8a7790.c line 47

Quoted 10 lines

arch/arm/mach-shmobile/smp-r8a7790.c new file +10 -0

+#define CA15RESCNT 0x0040
+#define CA7BAR	0x4030
+#define CA7RESCNT 0x0044
+#define RESCNT	0x0050
+
+#define APMU	0xe6150000
+#define CA15WUPCR 0x2010
+#define CA7WUPCR 0x1010
+
+#define MERAM	0xe8080000

Please get the base addresses from device tree if you can, using of_iomap().

Quoted 10 lines

arch/arm/mach-shmobile/smp-r8a7790.c new file +10 -0

+#define r8a7790_clst_id(cpu) (cpu_logical_map((cpu)) >> 8)
+#define r8a7790_cpu_id(cpu) (cpu_logical_map((cpu)) & 0xff)
+
+static void r8a7790_deassert_reset(unsigned int cpu)
+{
+	void __iomem *p, *carescnt;
+	u32 bar, mask, magic;
+	unsigned int clst_id = r8a7790_clst_id(cpu);
+
+	/* setup reset vectors */

arch/arm/mach-shmobile/smp-r8a7790.c line 91

Quoted 10 lines

arch/arm/mach-shmobile/smp-r8a7790.c new file +10 -0

+	p = ioremap_nocache(RST, 0x7000);
+	bar = (MERAM >> 8) & 0xfffffc00;
+	__raw_writel(bar, p + r8a7790_clst[clst_id].cabar);
+	__raw_writel(bar | 0x10, p + r8a7790_clst[clst_id].cabar);
+
+	/* enable clocks for cluster */
+	if (r8a7790_clst[clst_id].use_count++ == 0) {
+		mask = 1 << r8a7790_clst[clst_id].rescnt_bit;
+		__raw_writel(__raw_readl(p + RESCNT) & ~mask, p + RESCNT);
+	}

If you cannot use writel_relaxed() here, add a comment. Otherwise change it to writel or writel_relaxed.

arch/arm/mach-shmobile/smp-r8a7790.c line 160

Quoted 11 lines

arch/arm/mach-shmobile/smp-r8a7790.c new file +11 -0

+static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
+{
+	void __iomem *p;
+	unsigned int k;
+
+	shmobile_boot_fn = virt_to_phys(shmobile_invalidate_start);
+
+	/* MERAM for jump stub, because BAR requires 256KB aligned address */
+	p = ioremap_nocache(MERAM, 16);
+	memcpy(p, shmobile_boot_vector, 16);
+	iounmap(p);

On the other hand here you have to use __raw_writel() or memcpy_toio() because memcpy cannot operate on __iomem tokens.

Also, if this is actually memory, you probably want to use ioremap_cached or ioremap_writecombine.

Arnd

Magnus Damm

author maintainer

2013-07-08 04:52 UTC #4 lore raw

PATCH 1/1 ARM: shmobile: r8a7790 SMP prototype v2

Hi Arnd,

Quoted 16 lines · Arnd Bergmann

Quoted 14 lines · Magnus Damm

arch/arm/mach-shmobile/smp-r8a7790.c new file +14 -0

+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/smp_plat.h>
+
+#define SYSC 0xe6180000
+#define SYSCSR  0x0000
+
+#define RST  0xe6160000
+#define CA15BAR      0x6020
+#define CA15RESCNT 0x0040
+#define CA7BAR       0x4030
+#define CA7RESCNT 0x0044
+#define RESCNT       0x0050
+

Quoted 8 lines

arch/arm/mach-shmobile/smp-r8a7790.c line 47
Quoted 5 lines
arch/arm/mach-shmobile/smp-r8a7790.c new file +5 -0
+#define APMU 0xe6150000
+#define CA15WUPCR 0x2010
+#define CA7WUPCR 0x1010
+
+#define MERAM        0xe8080000
Please get the base addresses from device tree if you can, using of_iomap().

Yes, that is my plan. Actually, I was hoping of moving out the APMU and SYSC bits from this file in the future.

Quoted 15 lines

arch/arm/mach-shmobile/smp-r8a7790.c new file +15 -0

+#define r8a7790_clst_id(cpu) (cpu_logical_map((cpu)) >> 8)
+#define r8a7790_cpu_id(cpu) (cpu_logical_map((cpu)) & 0xff)
+
+static void r8a7790_deassert_reset(unsigned int cpu)
+{
+     void __iomem *p, *carescnt;
+     u32 bar, mask, magic;
+     unsigned int clst_id = r8a7790_clst_id(cpu);
+
+     /* setup reset vectors */
+     p = ioremap_nocache(RST, 0x7000);
+     bar = (MERAM >> 8) & 0xfffffc00;
+     __raw_writel(bar, p + r8a7790_clst[clst_id].cabar);
+     __raw_writel(bar | 0x10, p + r8a7790_clst[clst_id].cabar);
+

Quoted 8 lines

arch/arm/mach-shmobile/smp-r8a7790.c line 91
Quoted 5 lines
arch/arm/mach-shmobile/smp-r8a7790.c new file +5 -0
+     /* enable clocks for cluster */
+     if (r8a7790_clst[clst_id].use_count++ == 0) {
+             mask = 1 << r8a7790_clst[clst_id].rescnt_bit;
+             __raw_writel(__raw_readl(p + RESCNT) & ~mask, p + RESCNT);
+     }
If you cannot use writel_relaxed() here, add a comment. Otherwise change it to writel or writel_relaxed.

Ok, I will git that a go.

Quoted 15 lines

arch/arm/mach-shmobile/smp-r8a7790.c line 160
Quoted 11 lines
arch/arm/mach-shmobile/smp-r8a7790.c new file +11 -0
+static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
+{
+     void __iomem *p;
+     unsigned int k;
+
+     shmobile_boot_fn = virt_to_phys(shmobile_invalidate_start);
+
+     /* MERAM for jump stub, because BAR requires 256KB aligned address */
+     p = ioremap_nocache(MERAM, 16);
+     memcpy(p, shmobile_boot_vector, 16);
+     iounmap(p);
On the other hand here you have to use __raw_writel() or memcpy_toio() because memcpy cannot operate on __iomem tokens.

Quoted 2 lines

Also, if this is actually memory, you probably want to use ioremap_cached or ioremap_writecombine.

Yeah, I realize this may be a bit of a mess. So say that I used ioremap_cached() here, I think I still need to flush the cache to make sure the secondary processors have valid code available then they boot. I suppose you're fine with that?

Thanks,

/ magnus

Arnd Bergmann

2013-07-08 23:21 UTC #5 lore raw

PATCH 1/1 ARM: shmobile: r8a7790 SMP prototype v2

Quoted 15 lines · Magnus Damm

Quoted 15 lines
arch/arm/mach-shmobile/smp-r8a7790.c line 160
Quoted 11 lines
arch/arm/mach-shmobile/smp-r8a7790.c new file +11 -0
+static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
+{
+     void __iomem *p;
+     unsigned int k;
+
+     shmobile_boot_fn = virt_to_phys(shmobile_invalidate_start);
+
+     /* MERAM for jump stub, because BAR requires 256KB aligned address */
+     p = ioremap_nocache(MERAM, 16);
+     memcpy(p, shmobile_boot_vector, 16);
+     iounmap(p);
On the other hand here you have to use __raw_writel() or memcpy_toio() because memcpy cannot operate on __iomem tokens.

Quoted 7 lines

Quoted 2 lines
Also, if this is actually memory, you probably want to use ioremap_cached or ioremap_writecombine.
Yeah, I realize this may be a bit of a mess. So say that I used ioremap_cached() here, I think I still need to flush the cache to make sure the secondary processors have valid code available then they boot. I suppose you're fine with that?

Is that required to get the data from dcache to icache? If so, that sounds right.

Arnd

Magnus Damm

author maintainer

2013-07-09 01:29 UTC #6 lore raw

PATCH 1/1 ARM: shmobile: r8a7790 SMP prototype v2

Quoted 19 lines · Arnd Bergmann

Quoted 18 lines · Magnus Damm
Quoted 17 lines
arch/arm/mach-shmobile/smp-r8a7790.c line 160
Quoted 11 lines
arch/arm/mach-shmobile/smp-r8a7790.c new file +11 -0
+static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
+{
+     void __iomem *p;
+     unsigned int k;
+
+     shmobile_boot_fn = virt_to_phys(shmobile_invalidate_start);
+
+     /* MERAM for jump stub, because BAR requires 256KB aligned address */
+     p = ioremap_nocache(MERAM, 16);
+     memcpy(p, shmobile_boot_vector, 16);
+     iounmap(p);
On the other hand here you have to use __raw_writel() or memcpy_toio() because memcpy cannot operate on __iomem tokens.
Also, if this is actually memory, you probably want to use ioremap_cached or ioremap_writecombine.

Quoted 7 lines

Quoted 4 lines
Yeah, I realize this may be a bit of a mess. So say that I used ioremap_cached() here, I think I still need to flush the cache to make sure the secondary processors have valid code available then they boot. I suppose you're fine with that?
Is that required to get the data from dcache to icache? If so, that sounds right.

Good point. I sort of assumed that the secondary CPU cores booted with cache disabled, but I may be wrong.

Thanks,

/ magnus