parisc: optimize mtsp(0,sr) inline assembly

PATCH New Helge Deller 1 participant 1 message Jun 29, 2013 PA-RISC architecture

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Helge Deller

author maintainer

2013-06-29 20:08 UTC #0 lore raw

PATCH 1/1 parisc: optimize mtsp(0,sr) inline assembly

If the value which should be moved into a space register is zero, we can optimize the inline assembly to become "mtsp %r0,%srX".

Signed-off-by Helge Deller <[email protected]>

arch/parisc/include/asm/special_insns.h +6 -3

index d306b75..e150930 100644
@@ -32,9 +32,12 @@ static inline void set_eiem(unsigned long val)
 	cr;				\
 })
 
-#define mtsp(gr, cr) \
-	__asm__ __volatile__("mtsp %0,%1" \
+#define mtsp(val, cr) \
+	{ if (__builtin_constant_p(val) && ((val) == 0)) \
+	 __asm__ __volatile__("mtsp %%r0,%0" : : "i" (cr) : "memory"); \
+	else \
+	 __asm__ __volatile__("mtsp %0,%1" \
 		: /* no outputs */ \
-		: "r" (gr), "i" (cr) : "memory")
+		: "r" (val), "i" (cr) : "memory"); }
 
 #endif /* __PARISC_SPECIAL_INSNS_H */