powerpc/85xx: Add C29x SoC support

PATCH New y at tx30smr01.am.freescale.net 2 participants 4 messages Jul 1, 2013 PowerPC

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y at tx30smr01.am.freescale.net

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2013-07-01 06:43 UTC #0 lore raw

PATCH 1/2 powerpc/85xx: Add C29x SoC support

From: Mingkai Hu <[email protected]>

The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features:

- 512K L2 Cache/SRAM and 512 KB platform SRAM
- DDR3/DDR3L 32bit DDR controller
- One PCI express (x1, x2, x4) Gen 2.0 Controller
- Trust Architecture 2.0
- SEC6.0 engine

Signed-off-by Mingkai Hu <[email protected]>

Signed-off-by Po Liu <[email protected]>

---
Base on git://git.denx.de/u-boot.git

 arch/powerpc/cpu/mpc85xx/Makefile         |  2 +
 arch/powerpc/cpu/mpc85xx/c29x_serdes.c    | 65 +++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc8xxx/cpu.c            |  3 ++
 arch/powerpc/include/asm/config_mpc85xx.h | 12 ++++++
 arch/powerpc/include/asm/fsl_law.h        |  1 +
 arch/powerpc/include/asm/immap_85xx.h     | 23 +++++++++++
 arch/powerpc/include/asm/processor.h      |  3 ++
 7 files changed, 109 insertions(+)
 create mode 100644 arch/powerpc/cpu/mpc85xx/c29x_serdes.c

arch/powerpc/cpu/mpc85xx/Makefile +2 -0

index 4669883..28f00af 100644
@@ -62,6 +62,7 @@ COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
 COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
 
 # supports ddr1/2/3
+COBJS-$(CONFIG_C29X)	+= ddr-gen3.o
 COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
 COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
 COBJS-$(CONFIG_MPC8569)	+= ddr-gen3.o

@@ -116,6 +117,7 @@ COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
 COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 
 # SoC specific SERDES support
+COBJS-$(CONFIG_C29X)	+= c29x_serdes.o
 COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
 COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o
 COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o

arch/powerpc/cpu/mpc85xx/c29x_serdes.c new file +65 -0

65 lines not on this page · raw message

arch/powerpc/cpu/mpc8xxx/cpu.c +3 -0

index bc26855..2eed872 100644
@@ -95,6 +95,9 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 	CPU_TYPE_ENTRY(BSC9132, 9132, 2),
 	CPU_TYPE_ENTRY(BSC9232, 9232, 2),
+	CPU_TYPE_ENTRY(C291, C291, 1),
+	CPU_TYPE_ENTRY(C292, C292, 1),
+	CPU_TYPE_ENTRY(C293, C293, 1),
 #elif defined(CONFIG_MPC86xx)
 	CPU_TYPE_ENTRY(8610, 8610, 1),
 	CPU_TYPE_ENTRY(8641, 8641, 2),

arch/powerpc/include/asm/config_mpc85xx.h +12 -0

index 1d46b14..ae52159 100644
@@ -626,6 +626,18 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
+#elif defined(CONFIG_C29X)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB	3
+#define CONFIG_TSECV2_1
+#define CONFIG_SYS_FSL_SEC_COMPAT	6
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+
 #else
 #error Processor type not defined for this platform
 #endif

arch/powerpc/include/asm/fsl_law.h +1 -0

index bea1636..9eb3e13 100644
@@ -92,6 +92,7 @@ enum law_trgt_if {
 	LAW_TRGT_IF_LBC = 0x04,
 	LAW_TRGT_IF_CCSR = 0x08,
 	LAW_TRGT_IF_DSP_CCSR = 0x09,
+	LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
 	LAW_TRGT_IF_DDR_INTRLV = 0x0b,
 	LAW_TRGT_IF_RIO = 0x0c,
 	LAW_TRGT_IF_RIO_2 = 0x0d,

arch/powerpc/include/asm/immap_85xx.h +23 -0

index db70d04..703a003 100644
@@ -2147,6 +2147,11 @@ typedef struct ccsr_gur {
 #ifdef CONFIG_MPC8536
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x3e000000
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	25
+#elif defined(CONFIG_C29X)
+#define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	(9 - ((gur->pordevsr2 \
+					& MPC85xx_PORDEVSR2_DDR_SPD_0) \
+					>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
 #else
 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00

@@ -2194,6 +2199,9 @@ typedef struct ccsr_gur {
 #elif defined(CONFIG_BSC9132)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00FE0000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	17
+#elif defined(CONFIG_C29X)
+#define MPC85xx_PORDEVSR_IO_SEL		0x00e00000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
 #else
 #define MPC85xx_PORDEVSR_IO_SEL		0x00780000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	19

@@ -2209,6 +2217,10 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
 	u32	pordbgmsr;	/* POR debug mode status */
 	u32	pordevsr2;	/* POR I/O device status 2 */
+#if defined(CONFIG_C29X)
+#define MPC85xx_PORDEVSR2_DDR_SPD_0	0x00000008
+#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT	3
+#endif
 /* The 8544 RM says this is bit 26, but it's really bit 24 */
 #define MPC85xx_PORDEVSR2_SEC_CFG	0x00000080
 	u8	res1[8];

@@ -2355,6 +2367,11 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR0_SIM_SEL_MASK	0x0003b000
 #define MPC85xx_PMUXCR0_SIM_SEL		0x00014000
 #endif
+#if defined(CONFIG_C29X)
+#define MPC85xx_PMUXCR_SPI_MASK			0x00000300
+#define MPC85xx_PMUXCR_SPI			0x00000000
+#define MPC85xx_PMUXCR_SPI_GPIO			0x00000100
+#endif
 	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
 #define MPC85xx_PMUXCR2_UART_GPIO		0x40000000

@@ -3024,12 +3041,18 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x23000
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET			0xB0000
+#elif defined(CONFIG_TSECV2_1)
+#define CONFIG_SYS_TSEC1_OFFSET			0x10000
 #else
 #define CONFIG_SYS_TSEC1_OFFSET			0x24000
 #endif
 #define CONFIG_SYS_MDIO1_OFFSET			0x24000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
+#if defined(CONFIG_C29X)
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x80000
+#else
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x30000
+#endif
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
 #define CONFIG_SYS_SNVS_OFFSET			0xE6000

arch/powerpc/include/asm/processor.h +3 -0

index 56b22d8..64a6f9c 100644
@@ -1119,6 +1119,9 @@
 #define SVR_T4240	0x824000
 #define SVR_T4120	0x824001
 #define SVR_T4160	0x824100
+#define SVR_C291	0x850000
+#define SVR_C292	0x850020
+#define SVR_C293	0x850030
 #define SVR_B4860	0X868000
 #define SVR_G4860	0x868001
 #define SVR_G4060	0x868003

Signature · 1 line

1.8.0

y at tx30smr01.am.freescale.net

author

2013-07-01 06:43 UTC #1 lore raw

PATCH 2/2 powerpc/c29xpcie: add support for C29XPCIE board

From: Mingkai Hu <[email protected]>

C29XPCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. It includes C293PCIE board, C293PCIE board and C291PCIE board.

- 512KB platform SRAM in addition to 512K L2 Cache/SRAM
- 512MB soldered DDR3 32bit memory
- CPLD System Logic
- 64MB x16 NOR flash and 4GB x8 NAND flash
- 16MB SPI flash

Signed-off-by Mingkai Hu <[email protected]>

Singed-off-by Po Liu <[email protected]>

---
Base on git://git.denx.de/u-boot.git

 board/freescale/c29xpcie/Makefile   |  34 +++
 board/freescale/c29xpcie/c29xpcie.c | 150 +++++++++++
 board/freescale/c29xpcie/cpld.c     | 155 ++++++++++++
 board/freescale/c29xpcie/cpld.h     |  53 ++++
 board/freescale/c29xpcie/ddr.c      |  89 +++++++
 board/freescale/c29xpcie/law.c      |  22 ++
 board/freescale/c29xpcie/tlb.c      |  89 +++++++
 boards.cfg                          |   2 +
 include/configs/C29XPCIE.h          | 490 ++++++++++++++++++++++++++++++++++++
 9 files changed, 1084 insertions(+)
 create mode 100644 board/freescale/c29xpcie/Makefile
 create mode 100644 board/freescale/c29xpcie/c29xpcie.c
 create mode 100644 board/freescale/c29xpcie/cpld.c
 create mode 100644 board/freescale/c29xpcie/cpld.h
 create mode 100644 board/freescale/c29xpcie/ddr.c
 create mode 100644 board/freescale/c29xpcie/law.c
 create mode 100644 board/freescale/c29xpcie/tlb.c
 create mode 100644 include/configs/C29XPCIE.h

board/freescale/c29xpcie/Makefile new file +34 -0

new file mode 100644
index 0000000..15bef9a
@@ -0,0 +1,34 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= cpld.o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/c29xpcie/c29xpcie.c new file +150 -0

150 lines not on this page · raw message

board/freescale/c29xpcie/cpld.c new file +155 -0

155 lines not on this page · raw message

board/freescale/c29xpcie/cpld.h new file +53 -0

53 lines not on this page · raw message

board/freescale/c29xpcie/ddr.c new file +89 -0

89 lines not on this page · raw message

board/freescale/c29xpcie/law.c new file +22 -0

new file mode 100644
index 0000000..064fa71
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
+					LAW_TRGT_IF_PLATFORM_SRAM),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/c29xpcie/tlb.c new file +89 -0

89 lines not on this page · raw message

boards.cfg +2 -0

index c0c4282..4c68e9f 100644
@@ -771,6 +771,8 @@ MPC8569MDS_NAND              powerpc     mpc85xx     mpc8569mds          freesca
 MPC8572DS                    powerpc     mpc85xx     mpc8572ds           freescale      -           MPC8572DS
 MPC8572DS_36BIT              powerpc     mpc85xx     mpc8572ds           freescale      -           MPC8572DS:36BIT
 MPC8572DS_NAND               powerpc     mpc85xx     mpc8572ds           freescale      -           MPC8572DS:NAND
+C29XPCIE                     powerpc     mpc85xx     c29xpcie            freescale      -           C29XPCIE:C29XPCIE,36BIT
+C29XPCIE_SPIFLASH            powerpc     mpc85xx     c29xpcie            freescale      -           C29XPCIE:C29XPCIE,36BIT,SPIFLASH
 P1010RDB_36BIT_NAND          powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB,36BIT,NAND
 P1010RDB_36BIT_NAND_SECBOOT  powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT
 P1010RDB_36BIT_NOR           powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB,36BIT

include/configs/C29XPCIE.h new file +490 -0

490 lines not on this page · raw message

Signature · 1 line

1.8.0

Wolfgang Denk

2013-07-01 09:54 UTC #2 lore raw

PATCH 2/2 powerpc/c29xpcie: add support for C29XPCIE board

Dear y at tx30smr01.am.freescale.net,

Quoted 26 lines · In message <1372661036-11828-2-git-send-email-y> you wrote:

From: Mingkai Hu <[email protected]>
C29XPCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. It includes C293PCIE board, C293PCIE board and C291PCIE board.
- 512KB platform SRAM in addition to 512K L2 Cache/SRAM
- 512MB soldered DDR3 32bit memory
- CPLD System Logic
- 64MB x16 NOR flash and 4GB x8 NAND flash
- 16MB SPI flash
Signed-off-by Mingkai Hu <[email protected]>
Singed-off-by Po Liu <[email protected]>
---
Base on git://git.denx.de/u-boot.git
 board/freescale/c29xpcie/Makefile   |  34 +++
 board/freescale/c29xpcie/c29xpcie.c | 150 +++++++++++
 board/freescale/c29xpcie/cpld.c     | 155 ++++++++++++
 board/freescale/c29xpcie/cpld.h     |  53 ++++
 board/freescale/c29xpcie/ddr.c      |  89 +++++++
 board/freescale/c29xpcie/law.c      |  22 ++
 board/freescale/c29xpcie/tlb.c      |  89 +++++++
 boards.cfg                          |   2 +
 include/configs/C29XPCIE.h          | 490 ++++++++++++++++++++++++++++++++++++
 9 files changed, 1084 insertions(+)

Quoted 8 lines

 create mode 100644 board/freescale/c29xpcie/Makefile
 create mode 100644 board/freescale/c29xpcie/c29xpcie.c
 create mode 100644 board/freescale/c29xpcie/cpld.c
 create mode 100644 board/freescale/c29xpcie/cpld.h
 create mode 100644 board/freescale/c29xpcie/ddr.c
 create mode 100644 board/freescale/c29xpcie/law.c
 create mode 100644 board/freescale/c29xpcie/tlb.c
 create mode 100644 include/configs/C29XPCIE.h

Patch versionmissing.
History of pach changes missing.

Entry to MAINTAINERS file missing.

include/configs/C29XPCIE.h line 438

Quoted 7 lines

include/configs/C29XPCIE.h new file +7 -0

+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */

Scott asked you before to clean up this file. Please do not simply ignore review comments like that!!

Best regards,

Wolfgang Denk

Signature · 4 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Der Dativ ist dem Genitiv sein Tod.

Wolfgang Denk

2013-07-01 09:45 UTC #3 lore raw

PATCH 1/2 powerpc/85xx: Add C29x SoC support

In reply to y at tx30smr01.am.freescale.net

Dear y at tx30smr01.am.freescale.net,

Quoted 6 lines · In message <1372661036-11828-1-git-send-email-y> you wrote:

From: Mingkai Hu <[email protected]>
The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features:

Quoted 8 lines

- 512K L2 Cache/SRAM and 512 KB platform SRAM
- DDR3/DDR3L 32bit DDR controller
- One PCI express (x1, x2, x4) Gen 2.0 Controller
- Trust Architecture 2.0
- SEC6.0 engine
Signed-off-by Mingkai Hu <[email protected]>
Signed-off-by Po Liu <[email protected]>

What exactly is this? A plain resend of the patch submitted on April
24? Or a resend of the patch of June 26? Or a new version? If so, what exactly has been changed?

Adding a patch version to the Subject line and a history of changes to the comment section (as documented for example here [1]) is not something you can just ignore - this is a mandatory requirement to have your patches accepted.

[1] http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions

arch/powerpc/include/asm/config_mpc85xx.h line 629

Quoted 7 lines

arch/powerpc/include/asm/config_mpc85xx.h +1 -0

@@ -626,6 +626,18 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
+#elif defined(CONFIG_C29X)

All other names in this list use the form CONFIG_PPC_<name>, and then they define a core ID. Can youy please do the same? And please, keep this list sorted.

arch/powerpc/include/asm/immap_85xx.h typedef struct ccsr_gur { · line 2150

Quoted 7 lines

arch/powerpc/include/asm/immap_85xx.h +1 -0

@@ -2147,6 +2147,11 @@ typedef struct ccsr_gur {
 #ifdef CONFIG_MPC8536
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x3e000000
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	25
+#elif defined(CONFIG_C29X)

Can we please sort this list of #if defined() lines?

Thanks!

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The IQ of the group is the lowest IQ of a member of the group divided
by the number of people in the group.