ARM: omap3: Add option to disable errata workarounds.
A message that is not in the archive (sent off-list or not yet received): [email protected]
RFC 1/1 ARM: omap3: Add option to disable errata workarounds.
Hi,
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx
When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear.
So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism?
regards,
Andreas
PS. Does anybody have the "ARM Core Cortex-A8 (AT400/AT401) errata" document to make sure my assumption above holds true?
--- arch/arm/cpu/armv7/omap3/board.c | 2 ++ 1 file changed, 2 insertions(+)
(quoted diff) +0 -0
b/arch/arm/cpu/armv7/omap3/board.c
index b72fadc..84045d8 100644
arch/arm/cpu/armv7/omap3/board.c +2 -0
@@ -236,8 +236,10 @@ void s_init(void)try_unlock_memory (); +#ifndef CONFIG_SYS_DISABLE_CORTEXA8_ERRATA_WORKAROUNDS /* Errata workarounds */ omap3_setup_aux_cr (); +#endif #ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */
Signature · 1 line
1.8.3.1
Hi Andreas,
Quoted 33 lines · Andreas Naumann
Hi,
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspxWhen still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear.
So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism?regards,
AndreasPS. Does anybody have the "ARM Core Cortex-A8 (AT400/AT401) errata" document to make sure my assumption above holds true?
--- arch/arm/cpu/armv7/omap3/board.c | 2 ++ 1 file changed, 2 insertions(+)arch/arm/cpu/armv7/omap3/board.c +0
-0
arch/arm/cpu/armv7/omap3/board.c void s_init(void) · line 245
Quoted 10 lines
arch/arm/cpu/armv7/omap3/board.c +2
-0@@ -236,8 +236,10 @@ void s_init(void)try_unlock_memory (); +#ifndef CONFIG_SYS_DISABLE_CORTEXA8_ERRATA_WORKAROUNDS /* Errata workarounds */ omap3_setup_aux_cr (); +#endif #ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */
Two remarks:
1. I would prefer the option to be the other way around, i.e. forcing the inclusion of the workaround when defined rather than when not defined; e.g. CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATA
2. (if applicable) I would prefer erratum-specific options, e.g. CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATUM_430973 -- ok, "ERRATA" will be fine too; what I want is easing the search for errata by number.
Amicalement,
Signature · 1 line
Albert.
Hi Andreas,
Quoted 14 lines · Albert ARIBAUD
Hi Andreas,
Quoted 9 lines · Andreas Naumann
Hi,
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspxWhen still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear.
I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that.
Quoted 11 lines
Quoted 11 lines
So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism?
regards,
AndreasPS. Does anybody have the "ARM Core Cortex-A8 (AT400/AT401) errata" document to make sure my assumption above holds true?
I have rev 20.0 from 13-Apr-10. The three mentioned errata should be fixed in r2p1.
<snip>
Quoted 9 lines
Two remarks:
1. I would prefer the option to be the other way around, i.e. forcing the inclusion of the workaround when defined rather than when not defined; e.g.
CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATA2. (if applicable) I would prefer erratum-specific options, e.g.
CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATUM_430973-- ok, "ERRATA" will be fine too; what I want is easing the search for errata by number.
I join Albert's suggestion. Another solution could be to read the silicon revision and enable erratum workarounds on that information. It would be a step towards single binary.
Best regards
Andreas Bie?mann
Hi Andreas,
Quoted 3 lines · Andreas Bie?mann
Another solution could be to read the
silicon revision and enable erratum workarounds on that information. It would be a step towards single binary.
Seconded.
Quoted 3 lines
Best regards
Andreas Bie?mann
Amicalement,
Signature · 1 line
Albert.
Hi,
Quoted 11 lines
Quoted 7 lines
Quoted 7 lines
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspxWhen still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear.
I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that.
I dont know what bootloader the guy used, but he states that he needs to enable the errata fix in the kernel for the segfaults to disappear. I found exactly the same: Initially I had no errata fixes configured for the kernel, only when I added them the segfaults disappeared. However they also disappear if I remove the workarounds from kernel as well as u-boot, hence this patch.
Quoted 9 lines
Quoted 9 lines
Quoted 9 lines
So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism?
regards,
Andreas
Quoted 13 lines
Quoted 2 lines
Quoted 2 lines
PS. Does anybody have the "ARM Core Cortex-A8 (AT400/AT401) errata" document to make sure my assumption above holds true?
I have rev 20.0 from 13-Apr-10. The three mentioned errata should be fixed in r2p1.
<snip>
Quoted 5 lines
Two remarks:
1. I would prefer the option to be the other way around, i.e. forcing the inclusion of the workaround when defined rather than when not defined; e.g.
CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATA
If we do that, lots of board configs have to be adapted. People who have custom configs probably wont notice and loose their apropriate errata handling.
Quoted 7 lines
Quoted 3 lines
2. (if applicable) I would prefer erratum-specific options, e.g.
CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATUM_430973-- ok, "ERRATA" will be fine too; what I want is easing the search for errata by number.I join Albert's suggestion. Another solution could be to read the silicon revision and enable erratum workarounds on that information. It would be a step towards single binary.
So I'd rather do that, but can we map the ARM revision e.g. r2p1 to the TI die versions ES1.0, 1.1 and so on? Or can the ARM revision be read directly?
cheers,
Andreas
Hi Andreas,
Quoted 12 lines · Andreas Naumann
Quoted 11 lines
Quoted 7 lines
Quoted 7 lines
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspxWhen still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear.
I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that.
Quoted 6 lines
I dont know what bootloader the guy used, but he states that he needs to enable the errata fix in the kernel for the segfaults to disappear. I found exactly the same: Initially I had no errata fixes configured for the kernel, only when I added them the segfaults disappeared. However they also disappear if I remove the workarounds from kernel as well as u-boot, hence this patch.
Ok, understand.
<snip>
Quoted 7 lines
Quoted 3 lines
I join Albert's suggestion. Another solution could be to read the silicon revision and enable erratum workarounds on that information. It would be a step towards single binary.
So I'd rather do that, but can we map the ARM revision e.g. r2p1 to the TI die versions ES1.0, 1.1 and so on? Or can the ARM revision be read directly?
You should use the ARM revisions. They are available, but dunno how:
---8<---
~ cat /proc/cpuinfo
Processor : ARMv7 Processor rev 2 (v7l)
BogoMIPS : 512.57
Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc08
CPU revision : 2
--->8---
AFAIK is CPU variant 'r3' and CPU revision 'p2' for this cpuinfo.
Regards
Andreas Bie?mann
Hello,
Quoted 11 lines
Quoted 11 lines
Quoted 11 lines
Quoted 7 lines
Quoted 7 lines
It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspxWhen still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear.
I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that.
#430973 is still needed on latest Cortex-A8 silicon of DM3730 according to my testing; this is in contradiction to what TI and ARM claim
Quoted 2 lines
Quoted 2 lines
I dont know what bootloader the guy used, but he states that he needs to enable the errata fix in the kernel for the segfaults to disappear. I
the guy used u-boot 2012.10 and linux 3.7 :)
Quoted 4 lines
Quoted 4 lines
found exactly the same: Initially I had no errata fixes configured for the kernel, only when I added them the segfaults disappeared. However they also disappear if I remove the workarounds from kernel as well as u-boot, hence this patch.
interesting; I did not consider this dependency between u-boot and kernel here; will try it
regards, p.
Signature · 2 lines
Peter Meerwald +43-664-2444418 (mobile)