ARM: shmobile: r8a7790 SMP prototype v5

From: Shinya Kuribayashi <[email protected]>

Add SMP prototype support for r8a7790 by enabling one cluster of either 4 x Cortex-A7 or 4 x Cortex-A15.

This patch only adds support for booting, at this point no CPU Hotplug is included. In v5 both the big and the LITTLE clusters are working with either architected timers (in physical mode only for CA7) or CMT and broadcast timer.

On r8a7790 the MD6 pin control boot processor, and on the Lager board SW8.7 can be used to select big or LITTLE.

In big boot mode the CPU cores will be configured as:
- CPU0, CPU1, CPU2, CPU3: enabled (CA15)
- CPU4, CPU5, CPU6, CPU7: disabled (CA7)

In LITTLE boot mode the CPU cores will be configured as:
- CPU0, CPU5, CPU6, CPU7: enabled (CA7)
- CPU1, CPU2, CPU3, CPU4: disabled (CA15)

Base addresses for RST and APMU are still hard coded but DT will be used for them in future versions.

---

Changes since v4:
- Rolled in the following patches from Kuribayashi-san, thanks!
ARM: shmobile: smp-r8a7790: remove the obsolete RESCNT register
ARM: shmobile: smp-r8a7790: rename s/carescnt/rescnt/g
ARM: shmobile: smp-r8a7790: rename s/cabar/bar/g as well
ARM: shmobile: smp-r8a7790: power up a CPU core at .smp_boot_secondary stage

Written against kernel.org renesas git tag renesas-devel-20130717

 arch/arm/boot/dts/r8a7790.dtsi                 |   49 ++++++++
 arch/arm/mach-shmobile/Makefile                |    1 
 arch/arm/mach-shmobile/board-lager-reference.c |    1 
 arch/arm/mach-shmobile/board-lager.c           |    1 
 arch/arm/mach-shmobile/include/mach/common.h   |    1 
 arch/arm/mach-shmobile/include/mach/r8a7790.h  |    1 
 arch/arm/mach-shmobile/setup-r8a7790.c         |    1 
 arch/arm/mach-shmobile/smp-r8a7790.c           |  143 ++++++++++++++++++++++++
 8 files changed, 198 insertions(+)

@@ -24,6 +24,55 @@
 			reg = <0>;
 			clock-frequency = <1300000000>;
 		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <1>;
+			clock-frequency = <1300000000>;
+		};
+
+		cpu2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <2>;
+			clock-frequency = <1300000000>;
+		};
+
+		cpu3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <3>;
+			clock-frequency = <1300000000>;
+		};
+
+		cpu4: cpu at 4 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x100>;
+			clock-frequency = <780000000>;
+		};
+
+		cpu5: cpu at 5 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x101>;
+			clock-frequency = <780000000>;
+		};
+
+		cpu6: cpu at 6 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x102>;
+			clock-frequency = <780000000>;
+		};
+
+		cpu7: cpu at 7 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x103>;
+			clock-frequency = <780000000>;
+		};
 	};
 
 	gic: interrupt-controller at f1001000 {

@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.
 smp-y				:= platsmp.o headsmp.o
 smp-$(CONFIG_ARCH_SH73A0)	+= smp-sh73a0.o headsmp-scu.o
 smp-$(CONFIG_ARCH_R8A7779)	+= smp-r8a7779.o headsmp-scu.o
+smp-$(CONFIG_ARCH_R8A7790)	+= smp-r8a7790.o
 smp-$(CONFIG_ARCH_EMEV2)	+= smp-emev2.o headsmp-scu.o
 
 # IRQ objects

@@ -38,6 +38,7 @@ static const char *lager_boards_compat_d
 };
 
 DT_MACHINE_START(LAGER_DT, "lager")
+	.smp		= smp_ops(r8a7790_smp_ops),
 	.init_early	= r8a7790_init_delay,
 	.init_machine	= lager_add_standard_devices,
 	.init_time	= r8a7790_timer_init,

@@ -133,6 +133,7 @@ static const char *lager_boards_compat_d
 };
 
 DT_MACHINE_START(LAGER_DT, "lager")
+	.smp		= smp_ops(r8a7790_smp_ops),
 	.init_early	= r8a7790_init_delay,
 	.init_time	= r8a7790_timer_init,
 	.init_machine	= lager_add_standard_devices,

@@ -11,6 +11,7 @@ extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
 extern unsigned long shmobile_boot_arg;
 extern void shmobile_boot_scu(void);
+extern void shmobile_invalidate_start(void);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);

@@ -7,6 +7,7 @@ void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
 void r8a7790_init_delay(void);
 void r8a7790_timer_init(void);
+extern struct smp_operations r8a7790_smp_ops;
 
 #define MD(nr) BIT(nr)
 u32 r8a7790_read_mode_pins(void);

@@ -281,6 +281,7 @@ static const char *r8a7790_boards_compat
 };
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
+	.smp		= smp_ops(r8a7790_smp_ops),
 	.init_early	= r8a7790_init_delay,
 	.init_time	= r8a7790_timer_init,
 	.dt_compat	= r8a7790_boards_compat_dt,

Thanks for the update, looks good to me.
--
Shinya Kuribayashi
Renesas Electronics

Thanks.

This seems like it is ready to queue-up. Magnus, are there any outstanding reviews or issues?

I have placed this in topic/lager-smp-v5 in the renesas tree to aid review. It is not yet queued up for mainline.

topic/lager-smp still contains v3 of this patch.
Let me know if I can delete this branch.