arm: at91sam9n12: change EBI IO to high drive mode

As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12 and share the lower 8 bits data line. If use low drive of the data line, it will cause DDR data access corrupt in lower address, so change the data line to high drive mode

This will fix the Linux kernel boot issue when use Lower address

Hi Bo,

Quoted 5 lines · Bo Shen

As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12 and share the lower 8 bits data line. If use low drive of the data line, it will cause DDR data access corrupt in lower address, so change the data line to high drive mode

Quoted 1 line

This will fix the Linux kernel boot issue when use Lower address

Wait--does this mean that there is no separate chip selects for NAND and DDR on this SoC?

Amicalement,

Hi Albert,

Quoted 10 lines · Albert ARIBAUD

Hi Bo,

Quoted 5 lines · Bo Shen

As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12 and share the lower 8 bits data line. If use low drive of the data line, it will cause DDR data access corrupt in lower address, so change the data line to high drive mode

Quoted 4 lines

Quoted 1 line

This will fix the Linux kernel boot issue when use Lower address

Wait--does this mean that there is no separate chip selects for NAND and DDR on this SoC?

No. The NAND and DDR has there own chip selects.
This is chip specific. If DDR and NAND share data line, if we use low drive for EBI IO, it will cause DDR low memory address content corrupt. For example, if the DDR base address is 0x20000000, if we use 0x20008000 as entry address of Linux kernel, then it won't boot up successfully. So, if we need to use low memory address, we need this to fix.

Best Regards,
Bo Shen

I understand the symptom. What I don't undestand is how come NAND does not keep its data lines in high impedance when its chip select is inactive, which it is when DDR is being accessed.

Quoted 3 lines · Albert ARIBAUD

I understand the symptom. What I don't undestand is how come NAND does not keep its data lines in high impedance when its chip select is inactive, which it is when DDR is being accessed.

Chip selects prevent contention but they do not make the load vanish. A deselected chip is not electrically the same as a non-populated chip, especially at high frequencies.

Think of it another way. CMOS pins that are input-only are always high-z but they still must be counted as a load when adding up the fan out seen by the upstream output driver.

-Mike

Hi Michael,

Quoted 7 lines · Michael Cashwell

Chip selects prevent contention but they do not make the load vanish. A deselected chip is not electrically the same as a non-populated chip, especially at high frequencies.

Think of it another way. CMOS pins that are input-only are always high-z but they still must be counted as a load when adding up the fan out seen by the upstream output driver.

They must be counted as load alright, I understand this. But that leaves / leads to some questions:

- how come the issue never appeared so far? If this is so basic a problem, I would have expected it to show up as soon as the SoC gets frequent use.

- doesn't the driving lines' fan-out take this load into account? Again, I would expect a device's drive to be strong enough to overcome a few Hi-Zs, since that's an expected type of load.

- why is the issue not symmetric? Techno's CMOS or CMOS-like, I guess, so there is no reason to pull up rather than down. Unless there are pulldowns in the NAND or elsewhere, but then it's not Hi-Z any more.

Hi Bo,

Quoted 18 lines · Bo Shen

Hi Albert,

Quoted 10 lines · Albert ARIBAUD

Hi Bo,

Quoted 5 lines · Bo Shen

As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12 and share the lower 8 bits data line. If use low drive of the data line, it will cause DDR data access corrupt in lower address, so change the data line to high drive mode

Quoted 4 lines

Quoted 1 line

This will fix the Linux kernel boot issue when use Lower address

Wait--does this mean that there is no separate chip selects for NAND and DDR on this SoC?

Quoted 6 lines

No. The NAND and DDR has there own chip selects.
This is chip specific. If DDR and NAND share data line, if we use low drive for EBI IO, it will cause DDR low memory address content corrupt. For example, if the DDR base address is 0x20000000, if we use 0x20008000 as entry address of Linux kernel, then it won't boot up successfully. So, if we need to use low memory address, we need this to fix.

I understand the symptom. What I don't undestand is how come NAND does not keep its data lines in high impedance when its chip select is inactive, which it is when DDR is being accessed.

Quoted 2 lines

Best Regards,
Bo Shen

Amicalement,

Hi Albert,

Quoted 30 lines · Albert ARIBAUD

Hi Bo,

Quoted 18 lines · Bo Shen

Hi Albert,

Quoted 10 lines · Albert ARIBAUD

Hi Bo,

Quoted 5 lines · Bo Shen

As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12 and share the lower 8 bits data line. If use low drive of the data line, it will cause DDR data access corrupt in lower address, so change the data line to high drive mode

Quoted 4 lines

Quoted 1 line

This will fix the Linux kernel boot issue when use Lower address

Wait--does this mean that there is no separate chip selects for NAND and DDR on this SoC?

Quoted 6 lines

No. The NAND and DDR has there own chip selects.
This is chip specific. If DDR and NAND share data line, if we use low drive for EBI IO, it will cause DDR low memory address content corrupt. For example, if the DDR base address is 0x20000000, if we use 0x20008000 as entry address of Linux kernel, then it won't boot up successfully. So, if we need to use low memory address, we need this to fix.

Quoted 3 lines

I understand the symptom. What I don't undestand is how come NAND does not keep its data lines in high impedance when its chip select is inactive, which it is when DDR is being accessed.

So, I expect this patch be applied in v2013.07 release, would it be OK?

Hi Andreas,
If no objection from Albert, would it be possible to apply it and
include it in v2013.07 release.

Best Regards,
Bo Shen

As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12 and share the lower 8 bits data line. If use low drive of the data line, it will cause DDR data access corrupt in lower address, so change the data line to high drive mode

This will fix the Linux kernel boot issue when use Lower address

Signed-off-by Bo Shen <[email protected]>

---
 board/atmel/at91sam9n12ek/at91sam9n12ek.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

board/atmel/at91sam9n12ek/at91sam9n12ek.c +0 -0

index 3013a42..66c4c1f 100644

Quoted 23 lines · Bo Shen

As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12 and share the lower 8 bits data line. If use low drive of the data line, it will cause DDR data access corrupt in lower address, so change the data line to high drive mode

This will fix the Linux kernel boot issue when use Lower address

Signed-off-by Bo Shen <[email protected]>

---
 board/atmel/at91sam9n12ek/at91sam9n12ek.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

board/atmel/at91sam9n12ek/at91sam9n12ek.c +1 -1

index 3013a42..66c4c1f 100644
@@ -59,7 +59,7 @@ static void at91sam9n12ek_nand_hw_init(void)
 	/* Configure databus */
 	csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
 	/* Configure IO drive */
-	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
 

board/atmel/at91sam9n12ek/at91sam9n12ek.c static void at91sam9n12ek_nand_hw_init(void) · line 65

Quoted 2 lines

board/atmel/at91sam9n12ek/at91sam9n12ek.c +0 -0

 	writel(csa, &matrix->ebicsa);
 

So, the change is small and isolated, so I'm OK applying it to master directly, once we've got acks. But it sounds like there's a question of "why does this fix the problem" and "how does the problem even happen?".

To answer the second question we can have a look at the specs. I can presume by looking at the specs that we need to switch the drive strength for the data I/O pins to higher level for this board to fix the problem mentioned in the commit message. You have to know that this specific part (configuring EBI for NAND access) is copied from board to board (yes, another point to consolidate in near future). And this specific part is copied over from at91samx5ek which seems to work with lower drive strength. Unfortunately the concrete limit of EBI capacitance is not specified in specs for at91sam9n12 nor at91sam9x35 devices. More distracting this parameter (EBI_DRIVE) seems to have different reset values in at91sam9n12 and atsam9x35 devices, at least the specs say so ... Atmel guys, please have a look on that and update

your specs!
Especially fill the TBD field in at91sam9n12 spec p. 311 (EBI_DRIVE in CCFG_EBICSA) in version 11063I?ATARM?17-Apr-13. And possibly check why there is EBI_DRIVE default to 'low' for 9x5 and default to 'high' for 9n12. There is also another bug in the specs, when you have to decide between 'high' and 'low' you cant say the 'low' is required for 'capacitance < TBD pF' and 'high' is required for 'capacitance < TBD pF', presumably the 'high' part should be chosen for 'capacitance > TBD pF'.

So from my point of view this patch fixes an existing bug in a new board introduced in this releases MW. It uses a fairly new SoC which is first used in this new board. Therefore

Acked-by Andreas Bie?mann<[email protected]>

And Tom, please apply this patch directly.

Best regards

Andreas Bie?mann

As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12 and share the lower 8 bits data line. If use low drive of the data line, it will cause DDR data access corrupt in lower address, so change the data line to high drive mode

This will fix the Linux kernel boot issue when use Lower address

Signed-off-by Bo Shen <[email protected]>

Acked-by Andreas Bie??mann <[email protected]>