sunxi clk: PLL4/5/6 and module 0 support
Subsystems (4)
Emilio López
maintainercover sunxi clk: PLL4/5/6 and module 0 support
Hi everyone,
This patchset provides more clock support for the sunxi platform. Its main aim is to implement support for PLL4, 5 and 6, as well as MOD0-style clocks, used for various components such as MMC and IR.
The first patch fixes a small regression found while testing on 3.11-rc1. It does not affect the system in any way though, so there is no real need to submit it as an rc fix.
The second patch reworks the way factor clocks are registered. By doing so behind a composite clock, we gain the ability to divide, mux or gate these clocks. This comes in handy to implement PLL5, PLL6 and MOD0
The third patch adds gating support to PLL1, and by doing so, it also becomes bit-compatible with PLL4. The fourth patch adds a node on DT to get PLL4 supported this way.
The fifth and sixth patches implement support for PLL5 and 6 on the driver and adding the DT node, respectively.
Patches 7 and 8 implement support for module 0 style clocks and add all the corresponding DT nodes for sun4i.
I have marked this series as RFC as I still need to write the bindings for sun5i mod0 clocks and might change a thing or two on the other patches, but I wanted to get this code out there for review early this cycle.
As always, any comments will be highly appreciated.
Thanks,
Emilio
Emilio L?pez (8):
clk: sunxi: fix initialization of basic clocks
clk: sunxi: register factors clocks behind composite
clk: sunxi: add gating support to PLL1
ARM: sunxi: add PLL4 support
clk: sunxi: add PLL5 and PLL6 support
ARM: sunxi: add PLL5 and PLL6 support
clk: sunxi: mod0 support
ARM: sun4i: mod0 clocks
Documentation/devicetree/bindings/clock/sunxi.txt | 5 +- arch/arm/boot/dts/sun4i-a10.dtsi | 131 +++++++++- arch/arm/boot/dts/sun5i-a10s.dtsi | 26 +- arch/arm/boot/dts/sun5i-a13.dtsi | 26 +- drivers/clk/sunxi/clk-factors.c | 63 +---- drivers/clk/sunxi/clk-factors.h | 16 +- drivers/clk/sunxi/clk-sunxi.c | 285 +++++++++++++++++++++- 7 files changed, 466 insertions(+), 86 deletions(-)
Signature · 1 line
1.8.3.3
Emilio López
maintainerRFC PATCH 1/8 clk: sunxi: fix initialization of basic clocks
With the recent move towards CLK_OF_DECLARE(...), the driver stopped initializing osc32k, which is compatible "fixed-clock". This is because we never called of_clk_init(NULL). Fix this by moving the only other simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL) to initialize both of them.
--- drivers/clk/sunxi/clk-sunxi.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)
drivers/clk/sunxi/clk-sunxi.c +3 -6
@@ -411,10 +411,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node, }/* Matches for of_clk_init */ -static const __initconst struct of_device_id clk_match[] = { - {.compatible ="allwinner,sun4i-osc-clk" , .data = sunxi_osc_clk_setup,}, - {} -}; +CLK_OF_DECLARE (sunxi_osc,"allwinner,sun4i-osc-clk" , sunxi_osc_clk_setup);/* Matches for factors clocks */ static const __initconst struct of_device_id clk_factors_match[] = {
@@ -467,8 +464,8 @@ static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_matvoid __init sunxi_init_clocks (void ) { -/* Register all the simple sunxi clocks on DT */ -of_clk_init (clk_match); +/* Register all the simple and basic clocks on DT */ +of_clk_init (NULL );/* Register factor clocks */ of_sunxi_table_clock_setup (clk_factors_match, sunxi_factors_clk_setup);
Signature · 1 line
1.8.3.3
RFC PATCH 1/8 clk: sunxi: fix initialization of basic clocks
Hi Emilio,
Quoted 16 lines · Emilio L?pez
With the recent move towards
CLK_OF_DECLARE(...), the driver stopped initializing osc32k, which is compatible "fixed-clock". This is because we never calledof_clk_init(NULL). Fix this by moving the only other simple clock (osc24M) to useCLK_OF_DECLARE(...)and callof_clk_init(NULL)to initialize both of them.Signed-off-by Emilio L?pez <[email protected]>--- drivers/clk/sunxi/clk-sunxi.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)drivers/clk/sunxi/clk-sunxi.c +0
-0
drivers/clk/sunxi/clk-sunxi.c static void __init sunxi_gates_clk_setup(struct device_node *node, · line 414
Quoted 8 lines
drivers/clk/sunxi/clk-sunxi.c +1
-4@@ -411,10 +411,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node, }/* Matches for of_clk_init */ -static const __initconst struct of_device_id clk_match[] = { - {.compatible ="allwinner,sun4i-osc-clk" , .data = sunxi_osc_clk_setup,}, - {} -}; +CLK_OF_DECLARE (sunxi_osc,"allwinner,sun4i-osc-clk" , sunxi_osc_clk_setup);
Maybe we can drop the comment and the newline above?
Apart from this nitpick,
Thanks,
Maxime
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Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130723/2c6476d6/attachment.sig>
Emilio López
maintainerRFC PATCH 2/8 clk: sunxi: register factors clocks behind composite
In reply to Emilio LópezThis commit reworks factors clock registration to be done behind a composite clock. This allows us to additionally add a gate, mux or divisors, as it will be needed by some future PLLs.
--- drivers/clk/sunxi/clk-factors.c | 63 +-------------------------------------- drivers/clk/sunxi/clk-factors.h | 16 +++++----- drivers/clk/sunxi/clk-sunxi.c | 66 ++++++++++++++++++++++++++++++++++++++--- 3 files changed, 72 insertions(+), 73 deletions(-)
drivers/clk/sunxi/clk-factors.c +1 -62
@@ -30,14 +30,6 @@* parent - fixed parent. No clk_set_parent support */ -struct clk_factors { -struct clk_hw hw; -void __iomem *reg; -struct clk_factors_config *config; -void (*get_factors) (u32 *rate,u32 parent,u8 *n,u8 *k,u8 *m,u8 *p); -spinlock_t *lock; -}; -#define to_clk_factors (_hw) container_of(_hw, struct clk_factors, hw)#define SETMASK (len, pos) (((-1U) >> (31-len)) << (pos))
@@ -120,61 +112,8 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,return 0 ; } -static const struct clk_ops clk_factors_ops = { +const struct clk_ops clk_factors_ops = { .recalc_rate = clk_factors_recalc_rate, .round_rate = clk_factors_round_rate, .set_rate = clk_factors_set_rate, }; - -/** -* clk_register_factors - register a factors clock with -* the clock framework -* @dev: device registering this clock -* @name: name of this clock -* @parent_name: name of clock's parent -* @flags: framework-specific flags -* @reg: register address to adjust factors -* @config: shift and width of factors n, k, m and p -* @get_factors: function to calculate the factors for a given frequency -* @lock: shared register lock for this clock -*/ -struct clk *clk_register_factors (struct device *dev,const char *name, -const char *parent_name, -unsigned long flags,void __iomem *reg, -struct clk_factors_config *config, -void (*get_factors)(u32 *rate,u32 parent, -u8 *n,u8 *k,u8 *m,u8 *p), -spinlock_t *lock) -{ -struct clk_factors *factors; -struct clk *clk; -struct clk_init_data init; - -/* allocate the factors */ - factors =kzalloc (sizeof (struct clk_factors ),GFP_KERNEL ); -if (!factors) { -pr_err ("%s: could not allocate factors clk\n" , __func__); -return ERR_PTR (-ENOMEM ); - } - - init.name = name; - init.ops = &clk_factors_ops; - init.flags = flags; - init.parent_names = (parent_name ? &parent_name :NULL ); - init.num_parents = (parent_name ?1 :0 ); - -/* struct clk_factors assignments */ - factors->reg = reg; - factors->config = config; - factors->lock = lock; - factors->hw.init = &init; - factors->get_factors = get_factors; - -/* register the clock */ - clk =clk_register (dev, &factors->hw); - -if (IS_ERR (clk)) -kfree (factors); - -return clk; -}
drivers/clk/sunxi/clk-factors.h +9 -7
@@ -17,11 +17,13 @@ struct clk_factors_config { u8 pwidth; }; -struct clk *clk_register_factors (struct device *dev,const char *name, -const char *parent_name, -unsigned long flags,void __iomem *reg, -struct clk_factors_config *config, -void (*get_factors) (u32 *rate,u32 parent_rate, -u8 *n,u8 *k,u8 *m,u8 *p), -spinlock_t *lock); +struct clk_factors { +struct clk_hw hw; +void __iomem *reg; +struct clk_factors_config *config; +void (*get_factors) (u32 *rate,u32 parent,u8 *n,u8 *k,u8 *m,u8 *p); +spinlock_t *lock; +}; + +extern const struct clk_ops clk_factors_ops;#endif
drivers/clk/sunxi/clk-sunxi.c +62 -4
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Signature · 1 line
1.8.3.3
RFC PATCH 2/8 clk: sunxi: register factors clocks behind composite
Hi Emilio,
Quoted 3 lines · Emilio L?pez
This commit reworks factors clock registration to be done behind a composite clock. This allows us to additionally add a gate, mux or divisors, as it will be needed by some future PLLs.
Thanks for this patch, it looks fine.
I'm actually wondering if we could do this as well for the mux/gate/div that we have?
This way, we would cover all the cases, and could only have one clock defined per actual hardware clock.
Maxime
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Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130723/84a933b0/attachment-0001.sig>
Emilio López
maintainerRFC PATCH 3/8 clk: sunxi: add gating support to PLL1
In reply to Emilio LópezThis commit adds gating support to PLL1 on the clock driver. This makes the PLL1 implementation fully compatible with PLL4 as well.
--- Documentation/devicetree/bindings/clock/sunxi.txt | 2 +- drivers/clk/sunxi/clk-sunxi.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/sunxi.txt +1 -1
@@ -7,7 +7,7 @@ This binding uses the common clock binding[1]. Required properties: - compatible : shall be one of the following: "allwinner,sun4i-osc-clk" - for a gatable oscillator - "allwinner,sun4i-pll1-clk" - for the main PLL clock + "allwinner,sun4i-pll1-clk" - for the main PLL clock as well as PLL4 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock "allwinner,sun4i-axi-clk" - for the AXI clock "allwinner,sun4i-axi-gates-clk" - for the AXI gates
drivers/clk/sunxi/clk-sunxi.c +1 -0
@@ -201,6 +201,7 @@ static struct clk_factors_config apb1_config = { };static const __initconst struct factors_data pll1_data = { + .enable =31 , .table = &pll1_config, .getter = sunxi_get_pll1_factors, };
Signature · 1 line
1.8.3.3
RFC PATCH 3/8 clk: sunxi: add gating support to PLL1
Quoted 4 lines · Emilio L?pez
This commit adds gating support to PLL1 on the clock driver. This makes the PLL1 implementation fully compatible with PLL4 as well.
Signed-off-by Emilio L?pez <[email protected]>
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130723/10e37aeb/attachment.sig>
Emilio López
maintainerRFC PATCH 4/8 ARM: sunxi: add PLL4 support
In reply to Emilio LópezThis commit adds the PLL4 definition to the sun4i and sun5i device trees. PLL4 is compatible with PLL1.
--- arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++++++ arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++ 3 files changed, 21 insertions(+)
arch/arm/boot/dts/sun4i-a10.dtsi +7 -0
@@ -66,6 +66,13 @@ clocks = <&osc24M>; }; + pll4: pll4 at 01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + /* dummy is 200M */ cpu: cpu at 01c20054 { #clock-cells = <0>;
arch/arm/boot/dts/sun5i-a10s.dtsi +7 -0
@@ -63,6 +63,13 @@ clocks = <&osc24M>; }; + pll4: pll4 at 01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + /* dummy is 200M */ cpu: cpu at 01c20054 { #clock-cells = <0>;
arch/arm/boot/dts/sun5i-a13.dtsi +7 -0
@@ -67,6 +67,13 @@ clocks = <&osc24M>; }; + pll4: pll4 at 01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + /* dummy is 200M */ cpu: cpu at 01c20054 { #clock-cells = <0>;
Signature · 1 line
1.8.3.3
Emilio López
maintainerRFC PATCH 5/8 clk: sunxi: add PLL5 and PLL6 support
In reply to Emilio LópezThis commit implements PLL5 and PLL6 support on the sunxi clock driver. These PLLs use a similar factor clock, but differ on their outputs.
--- Documentation/devicetree/bindings/clock/sunxi.txt | 2 + drivers/clk/sunxi/clk-sunxi.c | 159 +++++++++++++++++++++- 2 files changed, 159 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/clock/sunxi.txt +2 -0
@@ -8,6 +8,8 @@ Required properties: - compatible : shall be one of the following: "allwinner,sun4i-osc-clk" - for a gatable oscillator "allwinner,sun4i-pll1-clk" - for the main PLL clock as well as PLL4 + "allwinner,sun4i-pll5-clk" - for the PLL5 clock + "allwinner,sun4i-pll6-clk" - for the PLL6 clock "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock "allwinner,sun4i-axi-clk" - for the AXI clock "allwinner,sun4i-axi-gates-clk" - for the AXI gates
drivers/clk/sunxi/clk-sunxi.c +157 -2
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1.8.3.3
RFC PATCH 5/8 clk: sunxi: add PLL5 and PLL6 support
Hi Emilio,
Quoted 27 lines · Emilio L?pez
This commit implements PLL5 and PLL6 support on the sunxi clock driver. These PLLs use a similar factor clock, but differ on their outputs.
Signed-off-by Emilio L?pez <[email protected]>--- Documentation/devicetree/bindings/clock/sunxi.txt | 2 + drivers/clk/sunxi/clk-sunxi.c | 159 +++++++++++++++++++++- 2 files changed, 159 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/clock/sunxi.txt +2
-0@@ -8,6 +8,8 @@ Required properties: - compatible : shall be one of the following: "allwinner,sun4i-osc-clk" - for a gatable oscillator "allwinner,sun4i-pll1-clk" - for the main PLL clock as well as PLL4 + "allwinner,sun4i-pll5-clk" - for the PLL5 clock + "allwinner,sun4i-pll6-clk" - for the PLL6 clock "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock "allwinner,sun4i-axi-clk" - for the AXI clock "allwinner,sun4i-axi-gates-clk" - for the AXI gatesdrivers/clk/sunxi/clk-sunxi.c +0
-0
drivers/clk/sunxi/clk-sunxi.c static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate, · line 132
Quoted 6 lines
drivers/clk/sunxi/clk-sunxi.c +3
-0@@ -127,6 +127,38 @@ static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate,/** +* sunxi_get_pll5_factors() - calculates n, k factors for PLL5 +* PLL5 rate is calculated as follows +* rate = parent_rate * n * (k + 1)
In the A10 and A10s datasheet, the given formula is:
for the DDR
rate = parent * n * (k + 1) / (m + 1)
and for the other output
rate = (parent * n * (k + 1)) >> (p + 1)
so it doesn't look very right to me here.
drivers/clk/sunxi/clk-sunxi.c static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate, · line 143
Quoted 11 lines
drivers/clk/sunxi/clk-sunxi.c +11
-0+* parent_rate is always 24Mhz +*/ + +static void sunxi_get_pll5_factors (u32 *freq,u32 parent_rate, +u8 *n,u8 *k,u8 *m,u8 *p) +{ +u8 div; + +/* Normalize value to a 24M multiple */ + div = *freq /24000000 ; + *freq =24000000 * div;
And that also means that we can generate frequencies that are not necessarily multiples of 24MHz, so the round up here is wrong as well.
Maxime
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Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130723/ce2aee0b/attachment.sig>
Emilio López
maintainerRFC PATCH 6/8 ARM: sunxi: add PLL5 and PLL6 support
In reply to Emilio LópezThis commit adds PLL5 and PLL6 nodes to the sun4i and sun5i device trees.
--- arch/arm/boot/dts/sun4i-a10.dtsi | 19 +++++++++++++++++-- arch/arm/boot/dts/sun5i-a10s.dtsi | 19 +++++++++++++++++-- arch/arm/boot/dts/sun5i-a13.dtsi | 19 +++++++++++++++++-- 3 files changed, 51 insertions(+), 6 deletions(-)
arch/arm/boot/dts/sun4i-a10.dtsi +17 -2
@@ -73,6 +73,22 @@ clocks = <&osc24M>; }; + pll5: pll5 at 01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: pll6 at 01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other"; + }; + /* dummy is 200M */ cpu: cpu at 01c20054 { #clock-cells = <0>;
@@ -138,12 +154,11 @@ "apb0_ir1", "apb0_keypad"; }; - /* dummy is pll62 */ apb1_mux: apb1_mux at 01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&dummy>, <&osc32k>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; }; apb1: apb1 at 01c20058 {
arch/arm/boot/dts/sun5i-a10s.dtsi +17 -2
@@ -70,6 +70,22 @@ clocks = <&osc24M>; }; + pll5: pll5 at 01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: pll6 at 01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other"; + }; + /* dummy is 200M */ cpu: cpu at 01c20054 { #clock-cells = <0>;
@@ -135,12 +151,11 @@ "apb0_ir1", "apb0_keypad"; }; - /* dummy is pll62 */ apb1_mux: apb1_mux at 01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&dummy>, <&osc32k>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; }; apb1: apb1 at 01c20058 {
arch/arm/boot/dts/sun5i-a13.dtsi +17 -2
@@ -74,6 +74,22 @@ clocks = <&osc24M>; }; + pll5: pll5 at 01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: pll6 at 01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other"; + }; + /* dummy is 200M */ cpu: cpu at 01c20054 { #clock-cells = <0>;
@@ -132,12 +148,11 @@ clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; }; - /* dummy is pll6 */ apb1_mux: apb1_mux at 01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&dummy>, <&osc32k>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; }; apb1: apb1 at 01c20058 {
Signature · 1 line
1.8.3.3
Emilio López
maintainerRFC PATCH 7/8 clk: sunxi: mod0 support
In reply to Emilio LópezThis commit implements support for the "module 0" type of clocks, as used by MMC, IR, NAND, SATA and other components.
--- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-sunxi.c | 54 +++++++++++++++++++++++ 2 files changed, 55 insertions(+)
Documentation/devicetree/bindings/clock/sunxi.txt +1 -0
@@ -23,6 +23,7 @@ Required properties: "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 + "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks Required properties for all clocks: - reg : shall be the control register address for the clock.
drivers/clk/sunxi/clk-sunxi.c +54 -0
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Signature · 1 line
1.8.3.3
RFC PATCH 7/8 clk: sunxi: mod0 support
Quoted 4 lines · Emilio L?pez
This commit implements support for the "module 0" type of clocks, as used by MMC, IR, NAND, SATA and other components.
Signed-off-by Emilio L?pez <[email protected]>
It looks right to me,
Thanks,
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130723/a39266d4/attachment.sig>
Emilio López
maintainerRFC PATCH 8/8 ARM: sun4i: mod0 clocks
In reply to Emilio LópezThis commit adds all the mod0 clocks present on sun4i to its device tree
--- arch/arm/boot/dts/sun4i-a10.dtsi | 105 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+)
arch/arm/boot/dts/sun4i-a10.dtsi +105 -0
@@ -180,6 +180,111 @@ "apb1_uart4", "apb1_uart5", "apb1_uart6", "apb1_uart7"; }; + + nand: nand at 01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + ms: ms at 01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + mmc0: mmc0 at 01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + mmc1: mmc1 at 01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + mmc2: mmc2 at 01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + mmc3: mmc3 at 01c20094 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20094 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + ts: ts at 01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + ss: ss at 01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + spi0: spi0 at 01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + spi1: spi0 at 01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + spi2: spi0 at 01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + pata: pata at 01c200ac { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200ac 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + ir0: ir0 at 01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + ir1: ir1 at 01c200b4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; + + spi3: spi3 at 01c200d4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200d4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + }; }; soc at 01c20000 {
Signature · 1 line
1.8.3.3