clk/exynos5250: add clocks for hdmi subsystem

PATCH Superseded Rahul Sharma 3 participants 10 messages Jul 25, 2013 – Jul 31, 2013

Subsystems (4)

Device tree bindings Common clk Arm Samsung Exynos Samsung SoC clock drivers

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Rahul Sharma

author

2013-07-25 04:44 UTC #0 lore raw

v4 cover clk/exynos5250: add clocks for hdmi subsystem

Add clock changes for hdmi subsystem for exynos5250 SoC. These include addition of new clocks like mout_hdmi and smmu_tv, associating ID to clk_hdmiphy and some essential corrections.

This set is based on kukjin's for-next branch at
http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.

V4:
1) Added Arun's patch hdmi clock number correction in this series.
2) Corrected clock number for smmu_mixer

V3:
1) Rebase to kgene for-next based on 3.11-rc1.
2) Added Tushar's patch in the series.

V2:
1) Dropped "clk/exynos5250: Fix HDMI clock number in documentation" as it already get merged.

Arun Kumar K (1):
clk/exynos5250: Fix HDMI clock number in documentation

Rahul Sharma (4):
clk/exynos5250: add mout_hdmi mux clock for hdmi clk/exynos5250: add sclk_hdmiphy in the list of special clocks clk/exynos5250: add clock for mixer sysmmu clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystem

Tushar Behera (1):
Documentation: exynos5250-clock: Add div_i2s1 and div_i2s2

 .../devicetree/bindings/clock/exynos5250-clock.txt |   14 +++++++++++++-
 drivers/clk/samsung/clk-exynos5250.c               |   20 ++++++++++++++------
 2 files changed, 27 insertions(+), 7 deletions(-)

Signature · 1 line

1.7.10.4

Rahul Sharma

author

2013-07-25 04:44 UTC #1 lore raw

PATCH v4 1/6 clk/exynos5250: Fix HDMI clock number in documentation

From: Arun Kumar K <[email protected]>

This patch corrects the HDMI clock number given wrongly in the documentation.

Signed-off-by Arun Kumar K <[email protected]>

Signed-off-by Rahul Sharma <[email protected]>

---
 Documentation/devicetree/bindings/clock/exynos5250-clock.txt |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Documentation/devicetree/bindings/clock/exynos5250-clock.txt +1 -1

index 781a627..1a05761 100644
@@ -154,7 +154,7 @@ clock which they consume.
   dsim0			341
   dp			342
   mixer			343
-  hdmi			345
+  hdmi			344
 
 Example 1: An example of a clock controller node is listed below.

Signature · 1 line

1.7.10.4

Mike Turquette

2013-07-30 21:00 UTC #2 lore raw

PATCH v4 1/6 clk/exynos5250: Fix HDMI clock number in documentation

Quoting Rahul Sharma (2013-07-24 22:07:32)

Quoted 7 lines

From: Arun Kumar K <[email protected]>
This patch corrects the HDMI clock number given wrongly in the documentation.
Signed-off-by Arun Kumar K <[email protected]>
Signed-off-by Rahul Sharma <[email protected]>

You can drop this patch as it is fixed in the clk-next branch already by commit "of/documentation: Fix a typo in exynos5250-clock.txt", 07c2ae9c.

Regards,
Mike

Quoted 19 lines

---
 Documentation/devicetree/bindings/clock/exynos5250-clock.txt |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Documentation/devicetree/bindings/clock/exynos5250-clock.txt +1 -1

index 781a627..1a05761 100644
@@ -154,7 +154,7 @@ clock which they consume.
   dsim0                        341
   dp                   342
   mixer                        343
-  hdmi                 345
+  hdmi                 344
 
 Example 1: An example of a clock controller node is listed below.

Signature · 1 line

1.7.10.4

Rahul Sharma

author

2013-07-25 04:44 UTC #3 lore raw

PATCH v4 2/6 Documentation: exynos5250-clock: Add div_i2s1 and div_i2s2

In reply to Rahul Sharma

From: Tushar Behera <[email protected]>

commit 79d743c177f9 ("clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2") added two new clock entries. Add the clock entry enum numbers to documentation.

Signed-off-by Tushar Behera <[email protected]>

---
 Documentation/devicetree/bindings/clock/exynos5250-clock.txt |    2 ++
 1 file changed, 2 insertions(+)

Documentation/devicetree/bindings/clock/exynos5250-clock.txt +2 -0

index 1a05761..bea503f 100644
@@ -59,6 +59,8 @@ clock which they consume.
   sclk_spi0		154
   sclk_spi1		155
   sclk_spi2		156
+  div_i2s1		157
+  div_i2s2		158
 
 
    [Peripheral Clock Gates]

Signature · 1 line

1.7.10.4

Rahul Sharma

author

2013-07-25 04:44 UTC #4 lore raw

PATCH v4 3/6 clk/exynos5250: add mout_hdmi mux clock for hdmi

In reply to Rahul Sharma

hdmi driver needs to change the parent of hdmi clock frequently between pixel clock and hdmiphy clock. hdmiphy is not stable after power on and for a short interval while changing the phy configuration. For this duration pixel clock is used to clock hdmi.

This patch is exposing the mux for changing parent.

Signed-off-by Rahul Sharma <[email protected]>

---
 Documentation/devicetree/bindings/clock/exynos5250-clock.txt |    8 ++++++++
 drivers/clk/samsung/clk-exynos5250.c                         |    5 ++++-
 2 files changed, 12 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/clock/exynos5250-clock.txt +8 -0

index bea503f..b3dfcad 100644
@@ -158,6 +158,14 @@ clock which they consume.
   mixer			343
   hdmi			344
 
+
+   [Clock Muxes]
+
+  Clock			ID
+  ----------------------------
+  mout_hdmi		1024
+
+
 Example 1: An example of a clock controller node is listed below.
 
 	clock: clock-controller@0x10010000 {

drivers/clk/samsung/clk-exynos5250.c +4 -1

index 6f767c5..df44419 100644
@@ -101,6 +101,9 @@ enum exynos5250_clks {
 	tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
 	wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
 
+	/* mux clocks */
+	mout_hdmi = 1024,
+
 	nr_clks,
 };

@@ -232,7 +235,7 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
 	MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
 	MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
 	MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
-	MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
+	MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
 	MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
 	MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
 	MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),

Signature · 1 line

1.7.10.4

Rahul Sharma

author

2013-07-25 04:44 UTC #5 lore raw

PATCH v4 4/6 clk/exynos5250: add sclk_hdmiphy in the list of special clocks

In reply to Rahul Sharma

hdmi driver needs hdmiphy clock which is one of the parent for hdmi mux clock. This is required while changing the parent of mux clock.

Signed-off-by Rahul Sharma <[email protected]>

Conflicts:
drivers/clk/samsung/clk-exynos5250.c

---
 Documentation/devicetree/bindings/clock/exynos5250-clock.txt |    1 +
 drivers/clk/samsung/clk-exynos5250.c                         |    4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

Documentation/devicetree/bindings/clock/exynos5250-clock.txt +1 -0

index b3dfcad..a489b5a 100644
@@ -61,6 +61,7 @@ clock which they consume.
   sclk_spi2		156
   div_i2s1		157
   div_i2s2		158
+  sclk_hdmiphy		159
 
 
    [Peripheral Clock Gates]

drivers/clk/samsung/clk-exynos5250.c +2 -2

index df44419..9579cfe 100644
@@ -87,7 +87,7 @@ enum exynos5250_clks {
 	sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
 	sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
 	sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
-	div_i2s1, div_i2s2,
+	div_i2s1, div_i2s2, sclk_hdmiphy,
 
 	/* gate clocks */
 	gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,

@@ -200,7 +200,7 @@ struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
 
 /* fixed rate clocks generated inside the soc */
 struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
-	FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
+	FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
 	FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
 	FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
 	FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),

Signature · 1 line

1.7.10.4

Rahul Sharma

author

2013-07-25 04:45 UTC #6 lore raw

PATCH v4 5/6 clk/exynos5250: add clock for mixer sysmmu

In reply to Rahul Sharma

Adding sysmmu clock for mixer for exynos5250 SoC. It also adds aclk200_disp1 mux which is the real parent of the disp1 block (contains hdmi, mixer, sysmmu_mixer).

Signed-off-by Rahul Sharma <[email protected]>

---
 Documentation/devicetree/bindings/clock/exynos5250-clock.txt |    1 +
 drivers/clk/samsung/clk-exynos5250.c                         |    7 ++++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/clock/exynos5250-clock.txt +1 -0

index a489b5a..84e098f 100644
@@ -158,6 +158,7 @@ clock which they consume.
   dp			342
   mixer			343
   hdmi			344
+  smmu_mixer		345
 
 
    [Clock Muxes]

drivers/clk/samsung/clk-exynos5250.c +6 -1

index 9579cfe..c727d9e 100644
@@ -24,6 +24,7 @@
 #define SRC_CORE1		0x4204
 #define SRC_TOP0		0x10210
 #define SRC_TOP2		0x10218
+#define SRC_TOP3		0x1021C
 #define SRC_GSCL		0x10220
 #define SRC_DISP1_0		0x1022c
 #define SRC_MAU			0x10240

@@ -99,7 +100,7 @@ enum exynos5250_clks {
 	spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
 	hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
 	tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
-	wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
+	wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, smmu_mixer,
 
 	/* mux clocks */
 	mout_hdmi = 1024,

@@ -172,6 +173,7 @@ PNAME(mout_mpll_user_p)	= { "fin_pll", "sclk_mpll" };
 PNAME(mout_bpll_user_p)	= { "fin_pll", "sclk_bpll" };
 PNAME(mout_aclk166_p)	= { "sclk_cpll", "sclk_mpll_user" };
 PNAME(mout_aclk200_p)	= { "sclk_mpll_user", "sclk_bpll_user" };
+PNAME(mout_aclk200_disp1_sub_p) = { "fin_pll", "aclk200" };
 PNAME(mout_hdmi_p)	= { "div_hdmi_pixel", "sclk_hdmiphy" };
 PNAME(mout_usb3_p)	= { "sclk_mpll_user", "sclk_cpll" };
 PNAME(mout_group1_p)	= { "fin_pll", "fin_pll", "sclk_hdmi27m",

@@ -227,6 +229,8 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
 	MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
 	MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
 	MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
+	MUX(none, "mout_aclk200_disp1", mout_aclk200_disp1_sub_p,
+			SRC_TOP3, 4, 1),
 	MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
 	MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
 	MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),

@@ -328,6 +332,7 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
 	GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
 	GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
 	GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
+	GATE(smmu_mixer, "smmu_mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 9, 0, 0),
 	GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
 	GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
 	GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),

Signature · 1 line

1.7.10.4

Rahul Sharma

author

2013-07-25 04:45 UTC #7 lore raw

PATCH v4 6/6 clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystem

In reply to Rahul Sharma

parent of hdmi and mixer block is mentioned as aclk200 which is not correct. It is clocked by the ouput of aclk200_disp1. Hence parent for mixer and hdmi clocks is changed to aclk200_disp1.

Signed-off-by Rahul Sharma <[email protected]>

---
 drivers/clk/samsung/clk-exynos5250.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/clk/samsung/clk-exynos5250.c +2 -2

index c727d9e..24a66b3 100644
@@ -469,8 +469,8 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
 	GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
 	GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
 	GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
-	GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
-	GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
+	GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
+	GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
 };
 
 static __initdata struct of_device_id ext_clk_match[] = {

Signature · 1 line

1.7.10.4

Mike Turquette

2013-07-30 21:08 UTC #8 lore raw

v4 cover clk/exynos5250: add clocks for hdmi subsystem

In reply to Rahul Sharma

Quoting Rahul Sharma (2013-07-24 22:07:31)

Quoted 6 lines

Add clock changes for hdmi subsystem for exynos5250 SoC. These include addition of new clocks like mout_hdmi and smmu_tv, associating ID to clk_hdmiphy and some essential corrections.
This set is based on kukjin's for-next branch at
http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.

I've taken patches 2-4 into the clk-next branch. Patch #1 can be dropped.

Patches 5 & 6 need to be rebased onto clk-next as the g2d clock has reserved mapping 345. Also I've cc'd Cho KyongHo who is rebasing his system mmu clock patch[1] onto clk-next. Can the two of your coordinate your changes to avoid mapping conflicts in the binding? Perhaps Rahul can carry Cho's patch in his next version when he rebases patches 5 & 6.

Thanks,
Mike

[1] https://lkml.org/lkml/2013/7/30/51

Quoted 31 lines

V4:
1) Added Arun's patch hdmi clock number correction in this series.
2) Corrected clock number for smmu_mixer
V3:
1) Rebase to kgene for-next based on 3.11-rc1.
2) Added Tushar's patch in the series.
V2:
1) Dropped "clk/exynos5250: Fix HDMI clock number in documentation" as it already get merged.
Arun Kumar K (1):
clk/exynos5250: Fix HDMI clock number in documentation
Rahul Sharma (4):
clk/exynos5250: add mout_hdmi mux clock for hdmi clk/exynos5250: add sclk_hdmiphy in the list of special clocks clk/exynos5250: add clock for mixer sysmmu clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystem
Tushar Behera (1):
Documentation: exynos5250-clock: Add div_i2s1 and div_i2s2
 .../devicetree/bindings/clock/exynos5250-clock.txt |   14 +++++++++++++-
 drivers/clk/samsung/clk-exynos5250.c               |   20 ++++++++++++++------
 2 files changed, 27 insertions(+), 7 deletions(-)
Signature · 1 line
1.7.10.4

Rahul Sharma

2013-07-31 05:25 UTC #9 lore raw

v4 cover clk/exynos5250: add clocks for hdmi subsystem

Quoted 11 lines · Mike Turquette

Quoting Rahul Sharma (2013-07-24 22:07:31)
Quoted 6 lines
Add clock changes for hdmi subsystem for exynos5250 SoC. These include addition of new clocks like mout_hdmi and smmu_tv, associating ID to clk_hdmiphy and some essential corrections.
This set is based on kukjin's for-next branch at
http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.
I've taken patches 2-4 into the clk-next branch. Patch #1 can be dropped.

Quoted 9 lines

Patches 5 & 6 need to be rebased onto clk-next as the g2d clock has reserved mapping 345. Also I've cc'd Cho KyongHo who is rebasing his system mmu clock patch[1] onto clk-next. Can the two of your coordinate your changes to avoid mapping conflicts in the binding? Perhaps Rahul can carry Cho's patch in his next version when he rebases patches 5 & 6.
Thanks,
Mike

Thanks Mike,

I will rebase and post 5, 6 on top of Cho's patches (based on clk-next) .

regards,
Rahul Sharma.

Quoted 33 lines

[1] https://lkml.org/lkml/2013/7/30/51
Quoted 31 lines
V4:
1) Added Arun's patch hdmi clock number correction in this series.
2) Corrected clock number for smmu_mixer
V3:
1) Rebase to kgene for-next based on 3.11-rc1.
2) Added Tushar's patch in the series.
V2:
1) Dropped "clk/exynos5250: Fix HDMI clock number in documentation" as it already get merged.
Arun Kumar K (1):
clk/exynos5250: Fix HDMI clock number in documentation
Rahul Sharma (4):
clk/exynos5250: add mout_hdmi mux clock for hdmi clk/exynos5250: add sclk_hdmiphy in the list of special clocks clk/exynos5250: add clock for mixer sysmmu clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystem
Tushar Behera (1):
Documentation: exynos5250-clock: Add div_i2s1 and div_i2s2
 .../devicetree/bindings/clock/exynos5250-clock.txt |   14 +++++++++++++-
 drivers/clk/samsung/clk-exynos5250.c               |   20 ++++++++++++++------
 2 files changed, 27 insertions(+), 7 deletions(-)
--
1.7.10.4