ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
From: Vaibhav Bedia <[email protected]>
The generic code is well equipped to differentiate between SMP and UP configurations.However, there are some devices which use Cortex-A9 MP core IP with 1 CPU as configuration. To let these SOCs to co-exist in a CONFIG_SMP=y build by leveraging the SMP_ON_UP support, we need to additionally check the number the cores in Cortex-A9 MPCore configuration. Without such a check in place, the startup code tries to execute ALT_SMP() set of instructions which lead to CPU faults.
The issue was spotted on TI's Aegis device and this patch makes now the device work with omap2plus_defconfig which enables SMP by default. The change is kept limited to only Cortex-A9 MPCore detection code.
--- arch/arm/kernel/head.S | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
arch/arm/kernel/head.S +17 -1
@@ -486,7 +486,23 @@ __fixup_smp: mrc p15, 0, r0, c0, c0, 5 @ read MPIDR and r0, r0, #0xc0000000 @ multiprocessing extensions and teq r0, #0x80000000 @ not part of a uniprocessor system? - moveq pc, lr @ yes, assume SMP + bne __fixup_smp_on_up @ no, assume UP + + @ Core indicates it is SMP. Check for Aegis SOC where a single + @ Cortex-A9 CPU is present but SMP operations fault. + mov r4, #0x41000000 + orr r4, r4, #0x0000c000 + orr r4, r4, #0x00000090 + teq r3, r4 @ Check for ARM Cortex-A9 + movne pc, lr @ Not ARM Cortex-A9, + + mrc p15, 4, r0, c15, c0 @ get SCU base address + teq r0, #0x0 @ '0' on actual UP A9 hardware + beq __fixup_smp_on_up @ So its an A9 UP + ldr r0, [r0, #4] @ read SCU Config + and r0, r0, #0x3 @ number of CPUs + teq r0, #0x0 @ is 1? + movne pc, lr __fixup_smp_on_up: adr r0, 1f
Signature · 1 line
1.7.9.5
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Quoted 38 lines · Santosh Shilimkar
From: Vaibhav Bedia <[email protected]>
The generic code is well equipped to differentiate between SMP and UP configurations.However, there are some devices which use Cortex-A9 MP core IP with 1 CPU as configuration. To let these SOCs to co-exist in a
CONFIG_SMP=ybuild by leveraging theSMP_ON_UPsupport, we need to additionally check the number the cores in Cortex-A9 MPCore configuration. Without such a check in place, the startup code tries to executeALT_SMP()set of instructions which lead to CPU faults.The issue was spotted on TI's Aegis device and this patch makes now the device work with
omap2plus_defconfigwhich enables SMP by default. The change is kept limited to only Cortex-A9 MPCore detection code.Cc Will Deacon <[email protected]>Cc Russell King <[email protected]>Acked-by Sricharan R <[email protected]>Signed-off-by Vaibhav Bedia <[email protected]>Signed-off-by Santosh Shilimkar <[email protected]>--- arch/arm/kernel/head.S | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)arch/arm/kernel/head.S +3
-1@@ -486,7 +486,23 @@ __fixup_smp: mrc p15, 0, r0, c0, c0, 5 @ read MPIDR and r0, r0, #0xc0000000 @ multiprocessing extensions and teq r0, #0x80000000 @ not part of a uniprocessor system? - moveq pc, lr @ yes, assume SMP + bne __fixup_smp_on_up @ no, assume UP + + @ Core indicates it is SMP. Check for Aegis SOC where a single
arch/arm/kernel/head.S __fixup_smp: · line 501
Quoted 10 lines
arch/arm/kernel/head.S +10
-0+ @ Cortex-A9 CPU is present but SMP operations fault. + mov r4, #0x41000000 + orr r4, r4, #0x0000c000 + orr r4, r4, #0x00000090 + teq r3, r4 @ Check for ARM Cortex-A9 + movne pc, lr @ Not ARM Cortex-A9, + + mrc p15, 4, r0, c15, c0 @ get SCU base address + teq r0, #0x0 @ '0' on actual UP A9 hardware + beq __fixup_smp_on_up @ So its an A9 UP
What if somebody builds an MP A9 with the private peripheral base address at 0x0?
Will
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Quoted 44 lines · Will Deacon
Quoted 43 lines · Santosh Shilimkar
From: Vaibhav Bedia <[email protected]>
The generic code is well equipped to differentiate between SMP and UP configurations.However, there are some devices which use Cortex-A9 MP core IP with 1 CPU as configuration. To let these SOCs to co-exist in a
CONFIG_SMP=ybuild by leveraging theSMP_ON_UPsupport, we need to additionally check the number the cores in Cortex-A9 MPCore configuration. Without such a check in place, the startup code tries to executeALT_SMP()set of instructions which lead to CPU faults.The issue was spotted on TI's Aegis device and this patch makes now the device work with
omap2plus_defconfigwhich enables SMP by default. The change is kept limited to only Cortex-A9 MPCore detection code.Cc Will Deacon <[email protected]>Cc Russell King <[email protected]>Acked-by Sricharan R <[email protected]>Signed-off-by Vaibhav Bedia <[email protected]>Signed-off-by Santosh Shilimkar <[email protected]>--- arch/arm/kernel/head.S | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)arch/arm/kernel/head.S +8
-1@@ -486,7 +486,23 @@ __fixup_smp: mrc p15, 0, r0, c0, c0, 5 @ read MPIDR and r0, r0, #0xc0000000 @ multiprocessing extensions and teq r0, #0x80000000 @ not part of a uniprocessor system? - moveq pc, lr @ yes, assume SMP + bne __fixup_smp_on_up @ no, assume UP + + @ Core indicates it is SMP. Check for Aegis SOC where a single + @ Cortex-A9 CPU is present but SMP operations fault. + mov r4, #0x41000000 + orr r4, r4, #0x0000c000 + orr r4, r4, #0x00000090 + teq r3, r4 @ Check for ARM Cortex-A9
Quoted 9 lines
arch/arm/kernel/head.S __fixup_smp: · line 501
Quoted 5 lines
arch/arm/kernel/head.S +5
-0+ movne pc, lr @ Not ARM Cortex-A9, + + mrc p15, 4, r0, c15, c0 @ get SCU base address + teq r0, #0x0 @ '0' on actual UP A9 hardware + beq __fixup_smp_on_up @ So its an A9 UPWhat if somebody builds an MP A9 with the private peripheral base address at
0x0?
Good point though we at least haven't seen one yet on the kernel lists. Any other way to avoid A9 UP case proceeding to the actual address 0 read which might be anything on a SOC.
Regards,
Santosh
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
In reply to Santosh ShilimkarQuoted 11 lines · Santosh Shilimkar
From: Vaibhav Bedia <[email protected]>
The generic code is well equipped to differentiate between SMP and UP configurations.However, there are some devices which use Cortex-A9 MP core IP with 1 CPU as configuration. To let these SOCs to co-exist in a
CONFIG_SMP=ybuild by leveraging theSMP_ON_UPsupport, we need to additionally check the number the cores in Cortex-A9 MPCore configuration. Without such a check in place, the startup code tries to executeALT_SMP()set of instructions which lead to CPU faults.
Quoted 4 lines
The issue was spotted on TI's Aegis device and this patch makes now the device work with
omap2plus_defconfigwhich enables SMP by default. The change is kept limited to only Cortex-A9 MPCore detection code.
Is there a specific reason why this can't happen for other processors such as A5/7/15?
Cheers
---Dave
Quoted 48 lines
Cc Will Deacon <[email protected]>Cc Russell King <[email protected]>Acked-by Sricharan R <[email protected]>Signed-off-by Vaibhav Bedia <[email protected]>Signed-off-by Santosh Shilimkar <[email protected]>--- arch/arm/kernel/head.S | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)arch/arm/kernel/head.S +17
-1@@ -486,7 +486,23 @@ __fixup_smp: mrc p15, 0, r0, c0, c0, 5 @ read MPIDR and r0, r0, #0xc0000000 @ multiprocessing extensions and teq r0, #0x80000000 @ not part of a uniprocessor system? - moveq pc, lr @ yes, assume SMP + bne __fixup_smp_on_up @ no, assume UP + + @ Core indicates it is SMP. Check for Aegis SOC where a single + @ Cortex-A9 CPU is present but SMP operations fault. + mov r4, #0x41000000 + orr r4, r4, #0x0000c000 + orr r4, r4, #0x00000090 + teq r3, r4 @ Check for ARM Cortex-A9 + movne pc, lr @ Not ARM Cortex-A9, + + mrc p15, 4, r0, c15, c0 @ get SCU base address + teq r0, #0x0 @ '0' on actual UP A9 hardware + beq __fixup_smp_on_up @ So its an A9 UP + ldr r0, [r0, #4] @ read SCU Config + and r0, r0, #0x3 @ number of CPUs + teq r0, #0x0 @ is 1? + movne pc, lr __fixup_smp_on_up: adr r0, 1fSignature · 7 lines
1.7.9.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel at lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Quoted 12 lines · Dave Martin
Quoted 11 lines · Santosh Shilimkar
From: Vaibhav Bedia <[email protected]>
The generic code is well equipped to differentiate between SMP and UP configurations.However, there are some devices which use Cortex-A9 MP core IP with 1 CPU as configuration. To let these SOCs to co-exist in a
CONFIG_SMP=ybuild by leveraging theSMP_ON_UPsupport, we need to additionally check the number the cores in Cortex-A9 MPCore configuration. Without such a check in place, the startup code tries to executeALT_SMP()set of instructions which lead to CPU faults.
Quoted 8 lines
Quoted 4 lines
The issue was spotted on TI's Aegis device and this patch makes now the device work with
omap2plus_defconfigwhich enables SMP by default. The change is kept limited to only Cortex-A9 MPCore detection code.Is there a specific reason why this can't happen for other processors such as A5/7/15?
The basic reason behind limiting to A9 was the SCU carrying the no. of CPU information is specific to A9. A7/A15 have that information encoded in L2 control register. Since same code won't work for the other ARM versions and we don't wanted to pollute the code much without need of it those versions are not considered.
Regards,
Santosh
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
In reply to Santosh ShilimkarQuoted 36 lines · Santosh Shilimkar
From: Vaibhav Bedia <[email protected]>
The generic code is well equipped to differentiate between SMP and UP configurations.However, there are some devices which use Cortex-A9 MP core IP with 1 CPU as configuration. To let these SOCs to co-exist in a
CONFIG_SMP=ybuild by leveraging theSMP_ON_UPsupport, we need to additionally check the number the cores in Cortex-A9 MPCore configuration. Without such a check in place, the startup code tries to executeALT_SMP()set of instructions which lead to CPU faults.The issue was spotted on TI's Aegis device and this patch makes now the device work with
omap2plus_defconfigwhich enables SMP by default. The change is kept limited to only Cortex-A9 MPCore detection code.Cc Will Deacon <[email protected]>Cc Russell King <[email protected]>Acked-by Sricharan R <[email protected]>Signed-off-by Vaibhav Bedia <[email protected]>Signed-off-by Santosh Shilimkar <[email protected]>--- arch/arm/kernel/head.S | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)arch/arm/kernel/head.S +1
-1@@ -486,7 +486,23 @@ __fixup_smp: mrc p15, 0, r0, c0, c0, 5 @ read MPIDR and r0, r0, #0xc0000000 @ multiprocessing extensions and teq r0, #0x80000000 @ not part of a uniprocessor system? - moveq pc, lr @ yes, assume SMP + bne __fixup_smp_on_up @ no, assume UP
arch/arm/kernel/head.S __fixup_smp: · line 499
Quoted 10 lines
arch/arm/kernel/head.S +10
-0+ + @ Core indicates it is SMP. Check for Aegis SOC where a single + @ Cortex-A9 CPU is present but SMP operations fault. + mov r4, #0x41000000 + orr r4, r4, #0x0000c000 + orr r4, r4, #0x00000090 + teq r3, r4 @ Check for ARM Cortex-A9 + movne pc, lr @ Not ARM Cortex-A9, + + mrc p15, 4, r0, c15, c0 @ get SCU base address
Correct me if I am interpreting this wrong, but CRn=15 here which is IMPLEMENTATION DEFINED registers.
If not, then I wonder why few platform have to read SCU base from DT or some header, why not this way ?
Regards,
Sudeep
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Quoted 50 lines · Sudeep KarkadaNagesha
Quoted 36 lines · Santosh Shilimkar
From: Vaibhav Bedia <[email protected]>
The generic code is well equipped to differentiate between SMP and UP configurations.However, there are some devices which use Cortex-A9 MP core IP with 1 CPU as configuration. To let these SOCs to co-exist in a
CONFIG_SMP=ybuild by leveraging theSMP_ON_UPsupport, we need to additionally check the number the cores in Cortex-A9 MPCore configuration. Without such a check in place, the startup code tries to executeALT_SMP()set of instructions which lead to CPU faults.The issue was spotted on TI's Aegis device and this patch makes now the device work with
omap2plus_defconfigwhich enables SMP by default. The change is kept limited to only Cortex-A9 MPCore detection code.Cc Will Deacon <[email protected]>Cc Russell King <[email protected]>Acked-by Sricharan R <[email protected]>Signed-off-by Vaibhav Bedia <[email protected]>Signed-off-by Santosh Shilimkar <[email protected]>--- arch/arm/kernel/head.S | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)arch/arm/kernel/head.S +1
-1@@ -486,7 +486,23 @@ __fixup_smp: mrc p15, 0, r0, c0, c0, 5 @ read MPIDR and r0, r0, #0xc0000000 @ multiprocessing extensions and teq r0, #0x80000000 @ not part of a uniprocessor system? - moveq pc, lr @ yes, assume SMP + bne __fixup_smp_on_up @ no, assume UParch/arm/kernel/head.S __fixup_smp: · line 499
Quoted 10 lines
arch/arm/kernel/head.S +10
-0+ + @ Core indicates it is SMP. Check for Aegis SOC where a single + @ Cortex-A9 CPU is present but SMP operations fault. + mov r4, #0x41000000 + orr r4, r4, #0x0000c000 + orr r4, r4, #0x00000090 + teq r3, r4 @ Check for ARM Cortex-A9 + movne pc, lr @ Not ARM Cortex-A9, + + mrc p15, 4, r0, c15, c0 @ get SCU base addressCorrect me if I am interpreting this wrong, but CRn=15 here which is IMPLEMENTATION DEFINED registers.
Quoted 3 lines
If not, then I wonder why few platform have to read SCU base from DT or some header, why not this way ?
I don't know if there is Cortex-A9 based SOC which don't implement SCU CP15 base address register, so can't comment really why not always use CP15 based method. I am not even sure if there are other reasons behind DT usage.
Regards,
Santosh
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Quoted 51 lines · Santosh Shilimkar
Quoted 50 lines · Sudeep KarkadaNagesha
Quoted 36 lines · Santosh Shilimkar
From: Vaibhav Bedia <[email protected]>
The generic code is well equipped to differentiate between SMP and UP configurations.However, there are some devices which use Cortex-A9 MP core IP with 1 CPU as configuration. To let these SOCs to co-exist in a
CONFIG_SMP=ybuild by leveraging theSMP_ON_UPsupport, we need to additionally check the number the cores in Cortex-A9 MPCore configuration. Without such a check in place, the startup code tries to executeALT_SMP()set of instructions which lead to CPU faults.The issue was spotted on TI's Aegis device and this patch makes now the device work with
omap2plus_defconfigwhich enables SMP by default. The change is kept limited to only Cortex-A9 MPCore detection code.Cc Will Deacon <[email protected]>Cc Russell King <[email protected]>Acked-by Sricharan R <[email protected]>Signed-off-by Vaibhav Bedia <[email protected]>Signed-off-by Santosh Shilimkar <[email protected]>--- arch/arm/kernel/head.S | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)arch/arm/kernel/head.S +1
-1@@ -486,7 +486,23 @@ __fixup_smp: mrc p15, 0, r0, c0, c0, 5 @ read MPIDR and r0, r0, #0xc0000000 @ multiprocessing extensions and teq r0, #0x80000000 @ not part of a uniprocessor system? - moveq pc, lr @ yes, assume SMP + bne __fixup_smp_on_up @ no, assume UParch/arm/kernel/head.S __fixup_smp: · line 499
Quoted 10 lines
arch/arm/kernel/head.S +10
-0+ + @ Core indicates it is SMP. Check for Aegis SOC where a single + @ Cortex-A9 CPU is present but SMP operations fault. + mov r4, #0x41000000 + orr r4, r4, #0x0000c000 + orr r4, r4, #0x00000090 + teq r3, r4 @ Check for ARM Cortex-A9 + movne pc, lr @ Not ARM Cortex-A9, + + mrc p15, 4, r0, c15, c0 @ get SCU base addressCorrect me if I am interpreting this wrong, but CRn=15 here which is IMPLEMENTATION DEFINED registers.
Quoted 8 lines
Quoted 3 lines
If not, then I wonder why few platform have to read SCU base from DT or some header, why not this way ?
I don't know if there is Cortex-A9 based SOC which don't implement SCU CP15 base address register, so can't comment really why not always use CP15 based method. I am not even sure if there are other reasons behind DT usage.
I may be wrong, but it's just my understanding as I see that ARM ARM clearly states CRn=15 space is IMPLEMENTATION DEFINED registers and we can't expect it to work on all IMPLEMENTATIONS.
I just had a glance at all the usage of CR15 space of CP15 register, its either platform specific or under specific errata/condition.
Will/Dave/Russell can confirm if it's safe to access these registers on any implementation or you may need to make it conditional.
Regards,
Sudeep
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Quoted 25 lines · Sudeep KarkadaNagesha
Quoted 12 lines · Santosh Shilimkar
Quoted 12 lines
arch/arm/kernel/head.S __fixup_smp: · line 499
Quoted 9 lines
arch/arm/kernel/head.S +9
-0+ @ Core indicates it is SMP. Check for Aegis SOC where a single + @ Cortex-A9 CPU is present but SMP operations fault. + mov r4, #0x41000000 + orr r4, r4, #0x0000c000 + orr r4, r4, #0x00000090 + teq r3, r4 @ Check for ARM Cortex-A9 + movne pc, lr @ Not ARM Cortex-A9, + + mrc p15, 4, r0, c15, c0 @ get SCU base addressCorrect me if I am interpreting this wrong, but CRn=15 here which is IMPLEMENTATION DEFINED registers.
Quoted 8 lines
Quoted 3 lines
If not, then I wonder why few platform have to read SCU base from DT or some header, why not this way ?
I don't know if there is Cortex-A9 based SOC which don't implement SCU CP15 base address register, so can't comment really why not always use CP15 based method. I am not even sure if there are other reasons behind DT usage.
I may be wrong, but it's just my understanding as I see that ARM ARM clearly states CRn=15 space is IMPLEMENTATION DEFINED registers and we can't expect it to work on all IMPLEMENTATIONS.
Quoted 5 lines
I just had a glance at all the usage of CR15 space of CP15 register, its either platform specific or under specific errata/condition.
Will/Dave/Russell can confirm if it's safe to access these registers on any implementation or you may need to make it conditional.
I think this an A9-specific register, which reads as 0 on UP A9 and reads as some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE is zero.
Will
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Will,
Quoted 29 lines · Will Deacon
Quoted 28 lines · Sudeep KarkadaNagesha
Quoted 12 lines · Santosh Shilimkar
Quoted 12 lines
arch/arm/kernel/head.S __fixup_smp: · line 499
Quoted 9 lines
arch/arm/kernel/head.S +9
-0+ @ Core indicates it is SMP. Check for Aegis SOC where a single + @ Cortex-A9 CPU is present but SMP operations fault. + mov r4, #0x41000000 + orr r4, r4, #0x0000c000 + orr r4, r4, #0x00000090 + teq r3, r4 @ Check for ARM Cortex-A9 + movne pc, lr @ Not ARM Cortex-A9, + + mrc p15, 4, r0, c15, c0 @ get SCU base addressCorrect me if I am interpreting this wrong, but CRn=15 here which is IMPLEMENTATION DEFINED registers.
Quoted 8 lines
Quoted 3 lines
If not, then I wonder why few platform have to read SCU base from DT or some header, why not this way ?
I don't know if there is Cortex-A9 based SOC which don't implement SCU CP15 base address register, so can't comment really why not always use CP15 based method. I am not even sure if there are other reasons behind DT usage.
I may be wrong, but it's just my understanding as I see that ARM ARM clearly states CRn=15 space is IMPLEMENTATION DEFINED registers and we can't expect it to work on all IMPLEMENTATIONS.
I just had a glance at all the usage of CR15 space of CP15 register, its either platform specific or under specific errata/condition.
Quoted 7 lines
Quoted 2 lines
Will/Dave/Russell can confirm if it's safe to access these registers on any implementation or you may need to make it conditional.
I think this an A9-specific register, which reads as 0 on UP A9 and reads as some form of
PERIPH_BASEfor SMP parts. The issue I have is whenPERIPH_BASEis zero.
What do we do here ? Should we document this in the code and proceed ? Mostly there is no platform with PERIPH_BASE = 0, so its should be fine but I am open for any other alternative.
Regards,
Santosh
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Quoted 8 lines · Santosh Shilimkar
Quoted 4 lines · Will Deacon
I think this an A9-specific register, which reads as 0 on UP A9 and reads as some form of
PERIPH_BASEfor SMP parts. The issue I have is whenPERIPH_BASEis zero.What do we do here ? Should we document this in the code and proceed ? Mostly there is no platform with
PERIPH_BASE= 0, so its should be fine but I am open for any other alternative.
The only other alternative I can think of is forcing people to have CONFIG_SMP=n, but that blows away single zImage for your platform.
Will
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Quoted 6 lines · Will Deacon
Quoted 5 lines · Santosh Shilimkar
Quoted 4 lines · Will Deacon
I think this an A9-specific register, which reads as 0 on UP A9 and reads as some form of
PERIPH_BASEfor SMP parts. The issue I have is whenPERIPH_BASEis zero.
Quoted 7 lines
Quoted 3 lines
What do we do here ? Should we document this in the code and proceed ? Mostly there is no platform with
PERIPH_BASE= 0, so its should be fine but I am open for any other alternative.The only other alternative I can think of is forcing people to have
CONFIG_SMP=n, but that blows away single zImage for your platform.
Yep which surely we don't want considering after so much effort we have it working first place. How about going ahead with assumption that PERIPH_BASE = 0 case doesn't work.
Regards,
Santosh
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Quoted 11 lines · Santosh Shilimkar
Quoted 10 lines · Will Deacon
Quoted 8 lines · Santosh Shilimkar
Quoted 4 lines · Will Deacon
I think this an A9-specific register, which reads as 0 on UP A9 and reads as some form of
PERIPH_BASEfor SMP parts. The issue I have is whenPERIPH_BASEis zero.What do we do here ? Should we document this in the code and proceed ? Mostly there is no platform with
PERIPH_BASE= 0, so its should be fine but I am open for any other alternative.
Quoted 6 lines
Quoted 3 lines
The only other alternative I can think of is forcing people to have
CONFIG_SMP=n, but that blows away single zImage for your platform.Yep which surely we don't want considering after so much effort we have it working first place. How about going ahead with assumption that
PERIPH_BASE= 0 case doesn't work.
I must be missing something but why cannot we use the SCU configuration register "CPU number" field to determine that its a UP? I do not have an OMAP4 board, but on AM437x, it certainly indicates only CPU0 present.
Thanks,
Sekhar
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Quoted 15 lines · Sekhar Nori
Quoted 14 lines · Santosh Shilimkar
Quoted 13 lines · Will Deacon
Quoted 8 lines · Santosh Shilimkar
Quoted 4 lines · Will Deacon
I think this an A9-specific register, which reads as 0 on UP A9 and reads as some form of
PERIPH_BASEfor SMP parts. The issue I have is whenPERIPH_BASEis zero.What do we do here ? Should we document this in the code and proceed ? Mostly there is no platform with
PERIPH_BASE= 0, so its should be fine but I am open for any other alternative.The only other alternative I can think of is forcing people to have
CONFIG_SMP=n, but that blows away single zImage for your platform.
Quoted 8 lines
Quoted 3 lines
Yep which surely we don't want considering after so much effort we have it working first place. How about going ahead with assumption that
PERIPH_BASE= 0 case doesn't work.I must be missing something but why cannot we use the SCU configuration register "CPU number" field to determine that its a UP? I do not have an OMAP4 board, but on AM437x, it certainly indicates only CPU0 present.
Thats what patch does. Yes, you are missing the point of dicussion. On real UP Cortex-A9, the base address read will return '0' which is treated as invalid address in the patch. Will D pointed out that one can build a SOC where PERIPH_BASE can be 0 so thats not safe. Thats the only contention left here.
Will, Russell,
Am just re-asking the question about whether we can ignore PERIPH_BASE = 0 and just document in the code about the limitation.
regards,
Santosh
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Quoted 20 lines · Santosh Shilimkar
Quoted 19 lines · Sekhar Nori
Quoted 17 lines · Santosh Shilimkar
Quoted 6 lines · Will Deacon
Quoted 5 lines · Santosh Shilimkar
Quoted 4 lines · Will Deacon
I think this an A9-specific register, which reads as 0 on UP A9 and reads as some form of
PERIPH_BASEfor SMP parts. The issue I have is whenPERIPH_BASEis zero.Quoted 7 lines
Quoted 3 lines
What do we do here ? Should we document this in the code and proceed ? Mostly there is no platform with
PERIPH_BASE= 0, so its should be fine but I am open for any other alternative.The only other alternative I can think of is forcing people to have
CONFIG_SMP=n, but that blows away single zImage for your platform.Yep which surely we don't want considering after so much effort we have it working first place. How about going ahead with assumption that
PERIPH_BASE= 0 case doesn't work.
Quoted 5 lines
Quoted 4 lines
I must be missing something but why cannot we use the SCU configuration register "CPU number" field to determine that its a UP? I do not have an OMAP4 board, but on AM437x, it certainly indicates only CPU0 present.
Thats what patch does. Yes, you are missing the point of dicussion.
Right, I see that now after actually reading the complete patch :)
Quoted 2 lines
On real UP Cortex-A9, the base address read will return '0' which is treated as invalid address in the patch. Will D pointed out that one
Is this something defined by spec for all UP Cortex-A9 or just an observation on AM437x implementation? It sounds like the later?
Thanks,
Sekhar
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
In reply to Santosh ShilimkarHi Santosh,
Quoted 11 lines · Santosh Shilimkar
Quoted 10 lines · Will Deacon
Quoted 8 lines · Santosh Shilimkar
Quoted 4 lines · Will Deacon
I think this an A9-specific register, which reads as 0 on UP A9 and reads as some form of
PERIPH_BASEfor SMP parts. The issue I have is whenPERIPH_BASEis zero.What do we do here ? Should we document this in the code and proceed ? Mostly there is no platform with
PERIPH_BASE= 0, so its should be fine but I am open for any other alternative.
Quoted 6 lines
Quoted 3 lines
The only other alternative I can think of is forcing people to have
CONFIG_SMP=n, but that blows away single zImage for your platform.Yep which surely we don't want considering after so much effort we have it working first place. How about going ahead with assumption that
PERIPH_BASE= 0 case doesn't work.
It's been over a month and I can't think of anything better than this without jeopardising the single zImage effort. However, it also doesn't seem fair if we rule out the possibility of single zImage for future SoCs which use 0x0 as their PERIPH_BASE (I don't know of any at the moment).
So how about we go ahead with this, but add a big fat comment to the code in head.S saying that, if a future SoC *does* use 0x0 as the PERIPH_BASE, then the check will need to be #ifdef'd or equivalent for the Aegis platform?
Will
PATCH 1/1 ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
Quoted 21 lines · Will Deacon
Hi Santosh,
Quoted 11 lines · Santosh Shilimkar
Quoted 10 lines · Will Deacon
Quoted 8 lines · Santosh Shilimkar
Quoted 4 lines · Will Deacon
I think this an A9-specific register, which reads as 0 on UP A9 and reads as some form of
PERIPH_BASEfor SMP parts. The issue I have is whenPERIPH_BASEis zero.What do we do here ? Should we document this in the code and proceed ? Mostly there is no platform with
PERIPH_BASE= 0, so its should be fine but I am open for any other alternative.Quoted 6 lines
Quoted 3 lines
The only other alternative I can think of is forcing people to have
CONFIG_SMP=n, but that blows away single zImage for your platform.Yep which surely we don't want considering after so much effort we have it working first place. How about going ahead with assumption that
PERIPH_BASE= 0 case doesn't work.
Quoted 9 lines
It's been over a month and I can't think of anything better than this without jeopardising the single zImage effort. However, it also doesn't seem fair if we rule out the possibility of single zImage for future SoCs which use
0x0as theirPERIPH_BASE(I don't know of any at the moment).So how about we go ahead with this, but add a big fat comment to the code in
head.Ssaying that, if a future SoC *does* use0x0as thePERIPH_BASE, then the check will need to be #ifdef'd or equivalent for the Aegis platform?
I agree. Updated patch end of the email. If you are fine with this version, will stick it into RMK's patch system.
Regards,
Santosh
Quoted 1 line
From
05b1b43324f3e8d10a38f78dbcbf7632d4c3530cMon Sep 17 00:00:00 2001
From: Vaibhav Bedia <[email protected]>
Date: Thu, 18 Jul 2013 13:01:53 -0400
Subject: [PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU
devices
The generic code is well equipped to differentiate between SMP and UP configurations.However, there are some devices which use Cortex-A9 MP core IP with 1 CPU as configuration. To let these SOCs to co-exist in a CONFIG_SMP=y build by leveraging the SMP_ON_UP support, we need to additionally check the number the cores in Cortex-A9 MPCore configuration. Without such a check in place, the startup code tries to execute ALT_SMP() set of instructions which lead to CPU faults.
The issue was spotted on TI's Aegis device and this patch makes now the device work with omap2plus_defconfig which enables SMP by default. The change is kept limited to only Cortex-A9 MPCore detection code.
Note that if any future SoC *does* use 0x0 as the PERIPH_BASE, then the SCU address check code needs to be #ifdef'd for for the Aegis platform.
--- arch/arm/kernel/head.S | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-)
arch/arm/kernel/head.S +20 -1
@@ -487,7 +487,26 @@ __fixup_smp: mrc p15, 0, r0, c0, c0, 5 @ read MPIDR and r0, r0, #0xc0000000 @ multiprocessing extensions and teq r0, #0x80000000 @ not part of a uniprocessor system? - moveq pc, lr @ yes, assume SMP + bne __fixup_smp_on_up @ no, assume UP + + @ Core indicates it is SMP. Check for Aegis SOC where a single + @ Cortex-A9 CPU is present but SMP operations fault. + mov r4, #0x41000000 + orr r4, r4, #0x0000c000 + orr r4, r4, #0x00000090 + teq r3, r4 @ Check for ARM Cortex-A9 + movne pc, lr @ Not ARM Cortex-A9, + + @ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the + @ below address check will need to be #ifdef'd or equivalent + @ for the Aegis platform. + mrc p15, 4, r0, c15, c0 @ get SCU base address + teq r0, #0x0 @ '0' on actual UP A9 hardware + beq __fixup_smp_on_up @ So its an A9 UP + ldr r0, [r0, #4] @ read SCU Config + and r0, r0, #0x3 @ number of CPUs + teq r0, #0x0 @ is 1? + movne pc, lr __fixup_smp_on_up: adr r0, 1f
Signature · 1 line
1.7.9.5