clk: exynos4: Fix incorrect placement of __initdata

PATCH New Sachin Kamat 2 participants 5 messages Aug 7, 2013

Subsystems (3)

Common clk Arm Samsung Exynos Samsung SoC clock drivers

lore

Share & tools

lore

Sachin Kamat

author

2013-08-07 04:48 UTC #0 lore raw

PATCH 1/4 clk: exynos4: Fix incorrect placement of __initdata

__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section.

Signed-off-by Sachin Kamat <[email protected]>

---
 drivers/clk/samsung/clk-exynos4.c |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

drivers/clk/samsung/clk-exynos4.c +5 -5

index fec319d..742b4c5 100644
@@ -194,7 +194,7 @@ enum exynos4_clks {
  * list of controller registers to be saved and restored during a
  * suspend/resume cycle.
  */
-static __initdata unsigned long exynos4210_clk_save[] = {
+static unsigned long exynos4210_clk_save[] __initdata = {
 	E4210_SRC_IMAGE,
 	E4210_SRC_LCD1,
 	E4210_SRC_MASK_LCD1,

@@ -205,7 +205,7 @@ static __initdata unsigned long exynos4210_clk_save[] = {
 	E4210_MPLL_CON0,
 };
 
-static __initdata unsigned long exynos4x12_clk_save[] = {
+static unsigned long exynos4x12_clk_save[] __initdata = {
 	E4X12_GATE_IP_IMAGE,
 	E4X12_GATE_IP_PERIR,
 	E4X12_SRC_CAM1,

@@ -214,7 +214,7 @@ static __initdata unsigned long exynos4x12_clk_save[] = {
 	E4X12_MPLL_CON0,
 };
 
-static __initdata unsigned long exynos4_clk_regs[] = {
+static unsigned long exynos4_clk_regs[] __initdata = {
 	SRC_LEFTBUS,
 	DIV_LEFTBUS,
 	GATE_IP_LEFTBUS,

@@ -978,13 +978,13 @@ static void __init exynos4_clk_register_finpll(unsigned long xom)
 
 }
 
-static __initdata struct of_device_id ext_clk_match[] = {
+static struct of_device_id ext_clk_match[] __initdata = {
 	{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
 	{ .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
 	{},
 };
 
-static struct __initdata samsung_pll_clock exynos4_plls[nr_plls] = {
+static struct samsung_pll_clock exynos4_plls[nr_plls] __initdata = {
 	[apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
 		APLL_CON0, "fout_apll", NULL),
 	[mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll",

Signature · 1 line

1.7.9.5

Sachin Kamat

author

2013-08-07 04:48 UTC #1 lore raw

PATCH 2/4 clk: exynos5250: Fix incorrect placement of __initdata

__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section.

Signed-off-by Sachin Kamat <[email protected]>

---
 drivers/clk/samsung/clk-exynos5250.c |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

drivers/clk/samsung/clk-exynos5250.c +5 -5

index 5865cef..a9916a4 100644
@@ -132,7 +132,7 @@ enum exynos5250_clks {
  * list of controller registers to be saved and restored during a
  * suspend/resume cycle.
  */
-static __initdata unsigned long exynos5250_clk_regs[] = {
+static unsigned long exynos5250_clk_regs[] __initdata = {
 	SRC_CPU,
 	DIV_CPU0,
 	SRC_CORE1,

@@ -494,7 +494,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
 	GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
 };
 
-static __initdata struct samsung_pll_rate_table vpll_24mhz_tbl[] = {
+static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
 	/* sorted in descending order */
 	/* PLL_36XX_RATE(rate, m, p, s, k) */
 	PLL_36XX_RATE(266000000, 266, 3, 3, 0),

@@ -503,7 +503,7 @@ static __initdata struct samsung_pll_rate_table vpll_24mhz_tbl[] = {
 	{ },
 };
 
-static __initdata struct samsung_pll_rate_table epll_24mhz_tbl[] = {
+static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
 	/* sorted in descending order */
 	/* PLL_36XX_RATE(rate, m, p, s, k) */
 	PLL_36XX_RATE(192000000, 64, 2, 2, 0),

@@ -517,7 +517,7 @@ static __initdata struct samsung_pll_rate_table epll_24mhz_tbl[] = {
 	{ },
 };
 
-static struct __initdata samsung_pll_clock exynos5250_plls[nr_plls] = {
+static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
 	[apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
 		APLL_CON0, "fout_apll", NULL),
 	[mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,

@@ -534,7 +534,7 @@ static struct __initdata samsung_pll_clock exynos5250_plls[nr_plls] = {
 		VPLL_LOCK, VPLL_CON0, NULL),
 };
 
-static __initdata struct of_device_id ext_clk_match[] = {
+static struct of_device_id ext_clk_match[] __initdata = {
 	{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
 	{ },
 };

Signature · 1 line

1.7.9.5

Sachin Kamat

author

2013-08-07 04:48 UTC #2 lore raw

PATCH 3/4 clk: exynos5420: Fix incorrect placement of __initdata

In reply to Sachin Kamat

__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section.

Signed-off-by Sachin Kamat <[email protected]>

---
 drivers/clk/samsung/clk-exynos5420.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/clk/samsung/clk-exynos5420.c +3 -3

index 872e13d..e035fd0 100644
@@ -147,7 +147,7 @@ enum exynos5420_clks {
  * list of controller registers to be saved and restored during a
  * suspend/resume cycle.
  */
-static __initdata unsigned long exynos5420_clk_regs[] = {
+static unsigned long exynos5420_clk_regs[] __initdata = {
 	SRC_CPU,
 	DIV_CPU0,
 	DIV_CPU1,

@@ -727,7 +727,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 	GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
 };
 
-static struct __initdata samsung_pll_clock exynos5420_plls[nr_plls] = {
+static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
 	[apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
 		APLL_CON0, NULL),
 	[cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,

@@ -752,7 +752,7 @@ static struct __initdata samsung_pll_clock exynos5420_plls[nr_plls] = {
 		KPLL_CON0, NULL),
 };
 
-static __initdata struct of_device_id ext_clk_match[] = {
+static struct of_device_id ext_clk_match[] __initdata = {
 	{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
 	{ },
 };

Signature · 1 line

1.7.9.5

Sachin Kamat

author

2013-08-07 04:48 UTC #3 lore raw

PATCH 4/4 clk: exynos5440: Fix incorrect placement of __initdata

In reply to Sachin Kamat

__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section.

Signed-off-by Sachin Kamat <[email protected]>

---
 drivers/clk/samsung/clk-exynos5440.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/clk/samsung/clk-exynos5440.c +1 -1

index 6d043a2..4ef38e0 100644
@@ -97,7 +97,7 @@ static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
 	GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
 };
 
-static __initdata struct of_device_id ext_clk_match[] = {
+static struct of_device_id ext_clk_match[] __initdata = {
 	{ .compatible = "samsung,clock-xtal", .data = (void *)0, },
 	{},
 };

Signature · 1 line

1.7.9.5

Mike Turquette

2013-08-07 17:27 UTC #4 lore raw

PATCH 1/4 clk: exynos4: Fix incorrect placement of __initdata

In reply to Sachin Kamat

Quoting Sachin Kamat (2013-08-06 21:48:37)

Quoted 4 lines

__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section.
Signed-off-by Sachin Kamat <[email protected]>

Applied on top of the "[PATCH 1/3] clk: exynos4: Make exynos4_plls static" series in clk-next.

Thanks for following up on this.

Regards,
Mike

Quoted 53 lines

---
 drivers/clk/samsung/clk-exynos4.c |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

drivers/clk/samsung/clk-exynos4.c +5 -5

index fec319d..742b4c5 100644
@@ -194,7 +194,7 @@ enum exynos4_clks {
  * list of controller registers to be saved and restored during a
  * suspend/resume cycle.
  */
-static __initdata unsigned long exynos4210_clk_save[] = {
+static unsigned long exynos4210_clk_save[] __initdata = {
        E4210_SRC_IMAGE,
        E4210_SRC_LCD1,
        E4210_SRC_MASK_LCD1,

@@ -205,7 +205,7 @@ static __initdata unsigned long exynos4210_clk_save[] = {
        E4210_MPLL_CON0,
 };
 
-static __initdata unsigned long exynos4x12_clk_save[] = {
+static unsigned long exynos4x12_clk_save[] __initdata = {
        E4X12_GATE_IP_IMAGE,
        E4X12_GATE_IP_PERIR,
        E4X12_SRC_CAM1,

@@ -214,7 +214,7 @@ static __initdata unsigned long exynos4x12_clk_save[] = {
        E4X12_MPLL_CON0,
 };
 
-static __initdata unsigned long exynos4_clk_regs[] = {
+static unsigned long exynos4_clk_regs[] __initdata = {
        SRC_LEFTBUS,
        DIV_LEFTBUS,
        GATE_IP_LEFTBUS,

@@ -978,13 +978,13 @@ static void __init exynos4_clk_register_finpll(unsigned long xom)
 
 }
 
-static __initdata struct of_device_id ext_clk_match[] = {
+static struct of_device_id ext_clk_match[] __initdata = {
        { .compatible = "samsung,clock-xxti", .data = (void *)0, },
        { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
        {},
 };
 
-static struct __initdata samsung_pll_clock exynos4_plls[nr_plls] = {
+static struct samsung_pll_clock exynos4_plls[nr_plls] __initdata = {
        [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
                APLL_CON0, "fout_apll", NULL),
        [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll",

Signature · 1 line

1.7.9.5