arm, am33xx, video: add video support for am33xx based boards

index ce24080..daaf13c 100644
@@ -219,7 +219,8 @@ struct cm_perpll {
 	unsigned int dcan1clkctrl;	/* offset 0xC4 */
 	unsigned int resv6[2];
 	unsigned int emiffwclkctrl;	/* offset 0xD0 */
-	unsigned int resv7[2];
+	unsigned int epwmss0clkctrl;	/* offset 0xD4 */
+	unsigned int epwmss2clkctrl;	/* offset 0xD8 */
 	unsigned int l3instrclkctrl;	/* offset 0xDC */
 	unsigned int l3clkctrl;		/* Offset 0xE0 */
 	unsigned int resv8[4];

@@ -230,12 +231,15 @@ struct cm_perpll {
 	unsigned int l4hsclkctrl;	/* offset 0x120 */
 	unsigned int resv10[8];
 	unsigned int cpswclkstctrl;	/* offset 0x144 */
+	unsigned int lcdcclkstctrl;	/* offset 0x148 */
 };
 
 /* Encapsulating Display pll registers */
 struct cm_dpll {
 	unsigned int resv1[2];
 	unsigned int clktimer2clk;	/* offset 0x08 */
+	unsigned int resv2[10];
+	unsigned int clklcdcpixelclk;	/* offset 0x34 */
 };
 
 /* Control Module RTC registers */

@@ -377,6 +381,35 @@ struct ctrl_dev {
 #define RGMII_INT_DELAY		(RGMII1_IDMODE | RGMII2_IDMODE)
 #define RMII_CHIPCKL_ENABLE     (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
 
+/* PWMSS */
+struct pwmss_regs {
+	unsigned int idver;
+	unsigned int sysconfig;
+	unsigned int clkconfig;
+	unsigned int clkstatus;
+};
+#define ECAP_CLK_EN		BIT(0)
+#define ECAP_CLK_STOP_REQ	BIT(1)
+
+struct pwmss_ecap_regs {
+	unsigned int tsctr;
+	unsigned int ctrphs;
+	unsigned int cap1;
+	unsigned int cap2;
+	unsigned int cap3;
+	unsigned int cap4;
+	unsigned int reserved[4];
+	unsigned short ecctl1;
+	unsigned short ecctl2;
+};
+
+/* Capture Control register 2 */
+#define ECTRL2_SYNCOSEL_MASK	(0x03 << 6)
+#define ECTRL2_MDSL_ECAP	BIT(9)
+#define ECTRL2_CTRSTP_FREERUN	BIT(4)
+#define ECTRL2_PLSL_LOW		BIT(10)
+#define ECTRL2_SYNC_EN		BIT(5)
+
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 

index 432f0c7..293ede2 100644
@@ -43,4 +43,11 @@
 /* RTC base address */
 #define RTC_BASE			0x44E3E000
 
+/* LCD Controller */
+#define	LCD_CNTL_BASE			0x4830E000
+
+/* PWMSS */
+#define PWMSS0_BASE			0x48300000
+#define AM33XX_ECAP0_BASE		0x48300100
+
 #endif /* __AM33XX_HARDWARE_AM33XX_H */

index c786997..89ee079 100644
@@ -24,7 +24,7 @@
 #include <asm/io.h>
 #include <asm/arch/davinci_misc.h>
 #include <asm/gpio.h>
-#include <asm/arch/da8xx-fb.h>
+#include "../../../drivers/video/da8xx-fb.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

index 373991d..dd7ce36 100644
@@ -24,7 +24,7 @@
 #include <asm/arch/hardware.h>
 
 #include "videomodes.h"
-#include <asm/arch/da8xx-fb.h>
+#include "da8xx-fb.h"
 
 #define DRIVER_NAME "da8xx_lcdc"
 

similarity index 99%
rename from arch/arm/include/asm/arch-davinci/da8xx-fb.h
rename to drivers/video/da8xx-fb.h
index c115034..f48fdfd 100644
@@ -17,7 +17,8 @@
 #define DA8XX_FB_H
 
 enum panel_type {
-	QVGA = 0
+	QVGA = 0,
+	WVGA
 };
 
 enum panel_shade {

index 02f5f8a..2dfcc2e 100644
@@ -78,4 +78,5 @@
 #define USB0_OTG_BASE			0x47401000
 #define USB1_OTG_BASE			0x47401800
 
+int clk_get(int clk);
 #endif /* __AM33XX_HARDWARE_H */

index 89ee079..c4444c7 100644
@@ -43,6 +43,30 @@ static const struct da8xx_panel lcd_panel = {
 	.invert_pxl_clk = 0,
 };
 
+static const struct display_panel disp_panel = {
+	QVGA,
+	16,
+	16,
+	COLOR_ACTIVE,
+};
+
+static const struct lcd_ctrl_config lcd_cfg = {
+	&disp_panel,
+	.ac_bias		= 255,
+	.ac_bias_intrpt		= 0,
+	.dma_burst_sz		= 16,
+	.bpp			= 16,
+	.fdd			= 255,
+	.tft_alt_mode		= 0,
+	.stn_565_mode		= 0,
+	.mono_8bit_mode		= 0,
+	.invert_line_clock	= 1,
+	.invert_frm_clock	= 1,
+	.sync_edge		= 0,
+	.sync_ctrl		= 1,
+	.raster_order		= 0,
+};
+
 /* SPI0 pin muxer settings */
 static const struct pinmux_config spi1_pins[] = {
 	{ pinmux(5), 1, 1 },

@@ -259,7 +283,7 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
 
-	da8xx_video_init(&lcd_panel, 16);
+	da8xx_video_init(&lcd_panel, &lcd_cfg, 16);
 
 	return 0;
 }

586 lines not on this page · raw message

index f48fdfd..6447a40 100644
@@ -109,6 +109,8 @@ struct lcd_sync_arg {
 	int pulse_width;
 };
 
-void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel);
+void da8xx_video_init(const struct da8xx_panel *panel,
+		      const struct lcd_ctrl_config *lcd_cfg,
+		      int bits_pixel);
 
 #endif  /* ifndef DA8XX_FB_H */

index b0bde2d..3a5f325 100644
@@ -959,6 +959,7 @@ void *video_hw_init(void)
 		printf("GLCD: malloc for frame buffer failed\n");
 		goto err_release_fb;
 	}
+	gd->fb_base = (int)par->vram_virt;
 
 	gpanel.frameAdrs = (unsigned int)par->vram_virt;
 	da8xx_fb_info->screen_base = (char *) par->vram_virt;

index b2ad3d5..2247adc 100644
@@ -179,7 +179,7 @@ int main (int argc, char *argv[])
 	printf("unsigned char bmp_logo_bitmap[] = {\n");
 	for (i=(b->height-1)*b->width; i>=0; i-=b->width) {
 		for (x = 0; x < b->width; x++) {
-			b->data[(uint16_t) i + x] = (uint8_t) fgetc (fp) \
+			b->data[i + x] = (uint8_t) fgetc(fp)
 						+ DEFAULT_CMAP_SIZE;
 		}
 	}

index 96ef8f9..822ed28 100644
@@ -431,6 +431,19 @@ static const int video_font_draw_table32[16][4] = {
 	{0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff}
 };
 
+/*
+ * Implement a weak default function for boards that optionally
+ * need to skip the cfb initialization.
+ */
+int __board_cfb_skip(void)
+{
+	/* As default, don't skip cfb init */
+	return 0;
+}
+
+int board_cfb_skip(void)
+	__attribute__ ((weak, alias("__board_cfb_skip")));
+
 static void video_drawchars(int xx, int yy, unsigned char *s, int count)
 {
 	u8 *cdat, *dest, *dest0;

@@ -1996,6 +2009,8 @@ static void *video_logo(void)
 		return video_fb_address + video_logo_height * VIDEO_LINE_LEN;
 	}
 #endif
+	if (board_cfb_skip())
+		return 0;
 
 	sprintf(info, " %s", version_string);
 

@@ -2205,6 +2220,9 @@ int drv_video_init(void)
 	/* Init video chip - returns with framebuffer cleared */
 	skip_dev_init = (video_init() == -1);
 
+	if (board_cfb_skip())
+		return 0;
+
 #if !defined(CONFIG_VGA_AS_SINGLE_DEVICE)
 	debug("KBD: Keyboard init ...\n");
 	skip_dev_init |= (VIDEO_KBD_INIT_FCT == -1);