mtd: gpmi: support two nand chips at most

Current gpmi-nand driver only supports one chips. But we may meet some embarrassing situation, such as Micron MT29F32G08QAA.
This nand chip has two DIEs internally. Each die has its own chip select pin, so this chip acts as two nand chips.

If we only scan one chip, we may find that we only get 2G for this chip, but in actually, this chip's size is 4G.

So scan two chips by default.

In order to support two nand chips, we have to do the following:
1.) We only have one dma channel now, so decouple the chip select
from the DMA channel, We can use the dma 0 to access all the nand chips.

2.) fix the wrong method of checking the ready/busy status.
In the imx6, all the ready/busy pins are binding together, we should check ready/busy status of chip 0 for the all the chips.

Tested this patch set with MT29F32G08QAA.

Huang Shijie (4):
mtd: gpmi: decouple the chip select from the DMA channel
mtd: gpmi: use DMA channel 0 for all the nand chips
mtd: gpmi: scan two nand chips
mtd: gpmi: imx6: fix the wrong method for checking ready/busy

 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |   14 ++++++++++++++
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |    7 +++----
 drivers/mtd/nand/gpmi-nand/gpmi-regs.h |    3 +++
 3 files changed, 20 insertions(+), 4 deletions(-)

Decouple the chip select from the DMA channel, we use the DMA channel 0 to accecc all the nand devices.

---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |    6 ++++++
 drivers/mtd/nand/gpmi-nand/gpmi-regs.h |    3 +++
 2 files changed, 9 insertions(+), 0 deletions(-)

index 4f8857f..7d56d87 100644
@@ -187,6 +187,12 @@ int gpmi_init(struct gpmi_nand_data *this)
 	/* Select BCH ECC. */
 	writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
 
+	/*
+	 * Decouple the chip select from dma channel. We use dma0 for all
+	 * the chips.
+	 */
+	writel(BM_GPMI_CTRL1_DECOUPLE_CS, r->gpmi_regs + HW_GPMI_CTRL1_SET);
+
 	gpmi_disable_clk(this);
 	return 0;
 err_out:

index 53397cc..82114cd 100644
@@ -108,6 +108,9 @@
 #define HW_GPMI_CTRL1_CLR				0x00000068
 #define HW_GPMI_CTRL1_TOG				0x0000006c
 
+#define BP_GPMI_CTRL1_DECOUPLE_CS			24
+#define BM_GPMI_CTRL1_DECOUPLE_CS	(1 << BP_GPMI_CTRL1_DECOUPLE_CS)
+
 #define BP_GPMI_CTRL1_WRN_DLY_SEL			22
 #define BM_GPMI_CTRL1_WRN_DLY_SEL	(0x3 << BP_GPMI_CTRL1_WRN_DLY_SEL)
 #define BF_GPMI_CTRL1_WRN_DLY_SEL(v)  \

1.7.1

We only have one DMA channel : the channel 0.
Use DMA channel 0 to access all the nand chips.

---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

index 25ecfa1..036e5e4 100644
@@ -226,9 +226,8 @@ int common_nfc_set_geometry(struct gpmi_nand_data *this)
 
 struct dma_chan *get_dma_chan(struct gpmi_nand_data *this)
 {
-	int chipnr = this->current_chip;
-
-	return this->dma_chans[chipnr];
+	/* We use the DMA channel 0 to access all the nand chips. */
+	return this->dma_chans[0];
 }
 
 /* Can we use the upper's buffer directly for DMA? */

1.7.1

Some nand chip has two DIEs in a single chip, such as Micron MT29F32G08QAA. Each die has its own chip select pin, so this chip acts as two nand chips.

If we only scan one chip, we may find that we only get 2G for this chip, but in actually, this chip's size is 4G.

So scan two chips by default.

---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

index 036e5e4..bb8af93 100644
@@ -1551,7 +1551,7 @@ static int gpmi_nfc_init(struct gpmi_nand_data *this)
 	if (ret)
 		goto err_out;
 
-	ret = nand_scan(mtd, 1);
+	ret = nand_scan(mtd, 2);
 	if (ret) {
 		pr_err("Chip scan failed\n");
 		goto err_out;

1.7.1

In the imx6, all the ready/busy pins are binding togeter. So we only need to check the chip 0 busy status.

For example, When the CS1 is enabled, we also should check the ready/busy of chip 0, if we check the ready/busy of chip 1, we will get the wrong result.

---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

index 7d56d87..660c5d7 100644
@@ -1079,6 +1079,14 @@ int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip)
 		mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
 		reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
 	} else if (GPMI_IS_MX28(this) || GPMI_IS_MX6Q(this)) {
+		/*
+		 * In the imx6, all the ready/busy pins are binding
+		 * togeter. So we only need to check the ready/busy status
+		 * of chip 0.
+		 */
+		if (GPMI_IS_MX6Q(this))
+			chip = 0;
+
 		/* MX28 shares the same R/B register as MX6Q. */
 		mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
 		reg = readl(r->gpmi_regs + HW_GPMI_STAT);

1.7.1

What's the status on this patch set? It doesn't look like it got merged. Do you have any testing for this? It looks sane enough to me.

Brian

Please ignore this patch set. I find a better solution to fix this issue. I will send a new version of this patch set when it is ready.

thanks
Huang Shijie