ARM: mxs: Added application UART driver
Subsystems (2)
RFC PATCH v2 1/1 ARM: mxs: Added application UART driver
The driver is ported from a driver that was implemented using u-boot 2009.
The driver makes it possible to use a regular application UART as the U-Boot output console for MXS CPUs.
---
Changes for v2:
- Added comment that regs-uartapp.h is pulled from LTIB
- BM_ prefixes removed and _MASK suffixes added instead
- BP_ prefixes removed and _OFFSET suffixes added instead
- BF_ defines removed altogether
- CONFIG_MXS_AUART_CLK renamed to MXS_AUART_CLK and guarding ifndef removed
- Added comments describing what is set and unset during init of driver
- Added newline that was accidently removed from serial.c
arch/arm/include/asm/arch-mxs/regs-uartapp.h | 236 +++++++++++++++++++++++++++ drivers/serial/Makefile | 1 + drivers/serial/mxs_auart.c | 139 ++++++++++++++++ drivers/serial/serial.c | 2 + 4 files changed, 378 insertions(+) create mode 100644 arch/arm/include/asm/arch-mxs/regs-uartapp.h create mode 100644 drivers/serial/mxs_auart.c
arch/arm/include/asm/arch-mxs/regs-uartapp.h new file +236 -0
@@ -0,0 +1,236 @@ +/* +* Freescale MXS UARTAPP Register Definitions +* +* Copyright (C) 2013 Andreas Wass <[email protected]> +* +* Based on code from LTIB: +* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ARCH_ARM___MXS_UARTAPP_H +#define __ARCH_ARM___MXS_UARTAPP_H + +#include <asm/imx-common/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mxs_uartapp_regs { + mxs_reg_32(hw_uartapp_ctrl0) + mxs_reg_32(hw_uartapp_ctrl1) + mxs_reg_32(hw_uartapp_ctrl2) + mxs_reg_32(hw_uartapp_linectrl) + mxs_reg_32(hw_uartapp_linectrl2) + mxs_reg_32(hw_uartapp_intr) + mxs_reg_32(hw_uartapp_data) + mxs_reg_32(hw_uartapp_stat) + mxs_reg_32(hw_uartapp_debug) + mxs_reg_32(hw_uartapp_version) + mxs_reg_32(hw_uartapp_autobaud) +}; +#endif + + +#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) +#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) +#define UARTAPP_CTRL0_RUN_MASK (1 << 29) +#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) +#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) +#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET (1 << 4) +#define UARTAPP_CTRL0_RXTIMEOUT_MASK 0x07FF0000 +#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL0_XFER_COUNT_MASK 0x0000FFFF + +#define UARTAPP_CTRL1_RSVD2_OFFSET 29 +#define UARTAPP_CTRL1_RSVD2_MASK 0xE0000000 + +#define UARTAPP_CTRL1_RUN_MASK (1 << 28) +#define UARTAPP_CTRL1_RSVD1_OFFSET 16 +#define UARTAPP_CTRL1_RSVD1_MASK 0x0FFF0000 + +#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL1_XFER_COUNT_MASK 0x0000FFFF + +#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) +#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) +#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) +#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) +#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) +#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) +#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) +#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) +#define UARTAPP_CTRL2_RSVD2_MASK (1 << 23) +#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 +#define UARTAPP_CTRL2_RXIFLSEL_MASK 0x00700000 + +#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY 0x0 +#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER 0x1 +#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF 0x2 +#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS 0x3 +#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS 0x4 +#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5 0x5 +#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6 0x6 +#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7 0x7 +#define UARTAPP_CTRL2_RSVD3_MASK (1 << 19) +#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 +#define UARTAPP_CTRL2_TXIFLSEL_MASK 0x00070000 +#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY 0x0 +#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER 0x1 +#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF 0x2 +#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS 0x3 +#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS 0x4 +#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5 0x5 +#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6 0x6 +#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7 0x7 +#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) +#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) +#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) +#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) +#define UARTAPP_CTRL2_RTS_MASK (1 << 11) +#define UARTAPP_CTRL2_DTR_MASK (1 << 10) +#define UARTAPP_CTRL2_RXE_MASK (1 << 9) +#define UARTAPP_CTRL2_TXE_MASK (1 << 8) +#define UARTAPP_CTRL2_LBE_MASK (1 << 7) +#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) +#define UARTAPP_CTRL2_RSVD4_OFFSET 3 +#define UARTAPP_CTRL2_RSVD4_MASK 0x00000038 + +#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) +#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) +#define UARTAPP_CTRL2_UARTEN_MASK (1 << 0) + +#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 +#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK 0xFFFF0000 + +#define UARTAPP_LINECTRL_RSVD_OFFSET 14 +#define UARTAPP_LINECTRL_RSVD_MASK 0x0000C000 + +#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 +#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK 0x00003F00 + +#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL_WLEN_OFFSET 5 +#define UARTAPP_LINECTRL_WLEN_MASK 0x00000060 + +#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) +#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) +#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) +#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) +#define UARTAPP_LINECTRL_BRK_MASK (1 << 0) + +#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 +#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK 0xFFFF0000 + +#define UARTAPP_LINECTRL2_RSVD_OFFSET 14 +#define UARTAPP_LINECTRL2_RSVD_MASK 0x0000C000 + +#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 +#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK 0x00003F00 + +#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL2_WLEN_OFFSET 5 +#define UARTAPP_LINECTRL2_WLEN_MASK 0x00000060 + +#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) +#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) +#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) +#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) +#define UARTAPP_LINECTRL2_RSVD1_MASK (1 << 0) + +#define UARTAPP_INTR_RSVD1_OFFSET 28 +#define UARTAPP_INTR_RSVD1_MASK 0xF0000000 + +#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) +#define UARTAPP_INTR_OEIEN_MASK (1 << 26) +#define UARTAPP_INTR_BEIEN_MASK (1 << 25) +#define UARTAPP_INTR_PEIEN_MASK (1 << 24) +#define UARTAPP_INTR_FEIEN_MASK (1 << 23) +#define UARTAPP_INTR_RTIEN_MASK (1 << 22) +#define UARTAPP_INTR_TXIEN_MASK (1 << 21) +#define UARTAPP_INTR_RXIEN_MASK (1 << 20) +#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) +#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) +#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) +#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) +#define UARTAPP_INTR_RSVD2_OFFSET 12 +#define UARTAPP_INTR_RSVD2_MASK 0x0000F000 + +#define UARTAPP_INTR_ABDIS_MASK (1 << 11) +#define UARTAPP_INTR_OEIS_MASK (1 << 10) +#define UARTAPP_INTR_BEIS_MASK (1 << 9) +#define UARTAPP_INTR_PEIS_MASK (1 << 8) +#define UARTAPP_INTR_FEIS_MASK (1 << 7) +#define UARTAPP_INTR_RTIS_MASK (1 << 6) +#define UARTAPP_INTR_TXIS_MASK (1 << 5) +#define UARTAPP_INTR_RXIS_MASK (1 << 4) +#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) +#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) +#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) +#define UARTAPP_INTR_RIMIS_MASK (1 << 0) + +#define UARTAPP_DATA_DATA_OFFSET 0 +#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF +#define UARTAPP_STAT_PRESENT_MASK (1 << 31) +#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_UARTAPP_STAT_PRESENT__AVAILABLE 0x1 + +#define UARTAPP_STAT_HISPEED_MASK (1 << 30) +#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE 0x0 +#define BV_UARTAPP_STAT_HISPEED__AVAILABLE 0x1 + +#define UARTAPP_STAT_BUSY_MASK (1 << 29) +#define UARTAPP_STAT_CTS_MASK (1 << 28) +#define UARTAPP_STAT_TXFE_MASK (1 << 27) +#define UARTAPP_STAT_RXFF_MASK (1 << 26) +#define UARTAPP_STAT_TXFF_MASK (1 << 25) +#define UARTAPP_STAT_RXFE_MASK (1 << 24) +#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 +#define UARTAPP_STAT_RXBYTE_INVALID_MASK 0x00F00000 + +#define UARTAPP_STAT_OERR_MASK (1 << 19) +#define UARTAPP_STAT_BERR_MASK (1 << 18) +#define UARTAPP_STAT_PERR_MASK (1 << 17) +#define UARTAPP_STAT_FERR_MASK (1 << 16) +#define UARTAPP_STAT_RXCOUNT_OFFSET 0 +#define UARTAPP_STAT_RXCOUNT_MASK 0x0000FFFF + +#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 +#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK 0xFFFF0000 + +#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 +#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK 0x0000FC00 + +#define UARTAPP_DEBUG_RSVD1_OFFSET 6 +#define UARTAPP_DEBUG_RSVD1_MASK 0x000003C0 + +#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) +#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) +#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) +#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) +#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) +#define UARTAPP_DEBUG_RXDMARQ_MASK (1 << 0) + +#define UARTAPP_VERSION_MAJOR_OFFSET 24 +#define UARTAPP_VERSION_MAJOR_MASK 0xFF000000 + +#define UARTAPP_VERSION_MINOR_OFFSET 16 +#define UARTAPP_VERSION_MINOR_MASK 0x00FF0000 + +#define UARTAPP_VERSION_STEP_OFFSET 0 +#define UARTAPP_VERSION_STEP_MASK 0x0000FFFF + +#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 +#define UARTAPP_AUTOBAUD_REFCHAR1_MASK 0xFF000000 + +#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 +#define UARTAPP_AUTOBAUD_REFCHAR0_MASK 0x00FF0000 + +#define UARTAPP_AUTOBAUD_RSVD1_OFFSET 5 +#define UARTAPP_AUTOBAUD_RSVD1_MASK 0x0000FFE0 + +#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) +#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) +#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) +#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) +#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK (1 << 0) +#endif /* __ARCH_ARM___UARTAPP_H */
drivers/serial/Makefile +1 -0
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o +COBJS-$(CONFIG_MXS_AUART) += mxs_auart.o ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.o
drivers/serial/mxs_auart.c new file +139 -0
139 lines not on this page · raw message
drivers/serial/serial.c +2 -0
@@ -159,6 +159,7 @@ serial_initfunc(pl01x_serial_initialize);serial_initfunc (s3c44b0_serial_initialize);serial_initfunc (sa1100_serial_initialize);serial_initfunc (sh_serial_initialize); +serial_initfunc (mxs_auart_initialize);/** * serial_register() - Register serial driver with serial driver core
@@ -251,6 +252,7 @@ void serial_initialize(void)s3c44b0_serial_initialize ();sa1100_serial_initialize ();sh_serial_initialize (); +mxs_auart_initialize ();serial_assign (default_serial_console ()->name); }
Signature · 1 line
1.8.1.4
RFC PATCH v2 1/1 ARM: mxs: Added application UART driver
Dear Andreas Wass,
Quoted 2 lines
The driver is ported from a driver that was implemented using u-boot 2009.
What driver? Anyway, this doesn't go here. If it's ported from LTIB, stick it into the file header in each file (see the other files , like the register definitions or so) for details.
Quoted 6 lines
The driver makes it possible to use a regular application UART as the U-Boot output console for MXS CPUs.
Signed-off-by Andreas Wass <[email protected]>Cc Fabio Estevam <[email protected]>Cc Marek Vasut <[email protected]>
Quoted 9 lines
---
Changes for v2:
- Added comment thatregs-uartapp.his pulled from LTIB
-BM_prefixes removed and_MASKsuffixes added instead
-BP_prefixes removed and_OFFSETsuffixes added instead
-BF_defines removed altogether
-CONFIG_MXS_AUART_CLKrenamed toMXS_AUART_CLKand guarding ifndef
removed - Added comments describing what is set and unset during init of driver - Added newline that was accidently removed fromserial.c
Nitpicks follow.
Quoted 78 lines
arch/arm/include/asm/arch-mxs/regs-uartapp.h | 236 +++++++++++++++++++++++++++ drivers/serial/Makefile | 1 + drivers/serial/mxs_auart.c | 139 ++++++++++++++++ drivers/serial/serial.c | 2 + 4 files changed, 378 insertions(+) create mode 100644 arch/arm/include/asm/arch-mxs/regs-uartapp.h create mode 100644 drivers/serial/mxs_auart.c(quoted diff) +0
-0
b/arch/arm/include/asm/arch-mxs/regs-uartapp.hnew file mode 100644 index 0000000..60a0812arch/arm/include/asm/arch-mxs/regs-uartapp.h new file +63
-0@@ -0,0 +1,236 @@ +/* +* Freescale MXS UARTAPP Register Definitions +* +* Copyright (C) 2013 Andreas Wass <[email protected]> +* +* Based on code from LTIB: +* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ARCH_ARM___MXS_UARTAPP_H +#define __ARCH_ARM___MXS_UARTAPP_H + +#include <asm/imx-common/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mxs_uartapp_regs { +mxs_reg_32 (hw_uartapp_ctrl0) + mxs_reg_32(hw_uartapp_ctrl1) +mxs_reg_32 (hw_uartapp_ctrl2) + mxs_reg_32(hw_uartapp_linectrl) +mxs_reg_32 (hw_uartapp_linectrl2) + mxs_reg_32(hw_uartapp_intr) +mxs_reg_32 (hw_uartapp_data) + mxs_reg_32(hw_uartapp_stat) +mxs_reg_32 (hw_uartapp_debug) + mxs_reg_32(hw_uartapp_version) + mxs_reg_32(hw_uartapp_autobaud) +}; +#endif + + +#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) +#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) +#define UARTAPP_CTRL0_RUN_MASK (1 << 29) +#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) +#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) +#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET (1 << 4) +#define UARTAPP_CTRL0_RXTIMEOUT_MASK 0x07FF0000 +#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL0_XFER_COUNT_MASK 0x0000FFFF + +#define UARTAPP_CTRL1_RSVD2_OFFSET 29 +#define UARTAPP_CTRL1_RSVD2_MASK 0xE0000000 + +#define UARTAPP_CTRL1_RUN_MASK (1 << 28) +#define UARTAPP_CTRL1_RSVD1_OFFSET 16 +#define UARTAPP_CTRL1_RSVD1_MASK 0x0FFF0000 + +#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL1_XFER_COUNT_MASK 0x0000FFFF + +#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) +#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) +#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) +#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) +#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) +#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) +#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) +#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) +#define UARTAPP_CTRL2_RSVD2_MASK (1 << 23) +#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
arch/arm/include/asm/arch-mxs/regs-uartapp.h line 73
Quoted 10 lines
arch/arm/include/asm/arch-mxs/regs-uartapp.h new file +10
-0+#define UARTAPP_CTRL2_RXIFLSEL_MASK 0x00700000 + +#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY 0x0 +#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER 0x1 +#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF 0x2 +#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS 0x3 +#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS 0x4 +#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5 0x5 +#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6 0x6 +#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7 0x7
BV ... this needs fixing. It's usually defined as (val << something)
[...]
Quoted 18 lines
drivers/serial/Makefile +1
-0@@ -38,6 +38,7 @@ COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o +COBJS-$(CONFIG_MXS_AUART) += mxs_auart.o ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.odrivers/serial/mxs_auart.c new file +0
-0
drivers/serial/mxs_auart.c line 3
Quoted 3 lines
drivers/serial/mxs_auart.c new file +3
-0@@ -0,0 +1,139 @@ +/* +* Driver to use an application UART as console output for Freescale +* MXS devices.
Freescale i.MX23/i.MX28 AUART driver
Quoted 35 lines
drivers/serial/mxs_auart.c new file +35
-0+* +* Copyright (C) 2013 Andreas Wass <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#include <common.h> +#include <asm/io.h> +#include <serial.h> +#include <linux/compiler.h> +#include <asm/arch/regs-base.h> +#include <asm/arch/regs-uartapp.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR ; + +#ifndef CONFIG_MXS_AUART_BASE +#error "CONFIG_MXS_AUART_BASE must be set to the base UART to use" +#endif + +/* AUART clock always supplied by XTAL and always 24MHz */ +#define MXS_AUART_CLK 24000000 + +static struct mxs_uartapp_regs *get_uartapp_registers (void ) +{ +return (struct mxs_uartapp_regs *)CONFIG_MXS_AUART_BASE ; +} + +/** +* Sets the baud rate and settings. +* The settings are: 8 data bits, no parit and 1 stop bit. +*/ +void mxs_auart_setbrg (void ) +{ +u32 div; +u32 linectrl =0 ;
drivers/serial/mxs_auart.c line 48
Quoted 10 lines
drivers/serial/mxs_auart.c new file +10
-0+struct mxs_uartapp_regs *regs =get_uartapp_registers (); + +/* +* From i.MX28 datasheet: +* div is calculated by calculating UARTCLK*32/baudrate, rounded to int +* div must be between 0xEC and 0x003FFFC0 inclusive +* Lowest 6 bits of div goes in BAUD_DIVFRAC part of LINECTRL register +* Next 16 bits goes in BAUD_DIVINT part of LINECTRL register +*/ + div = (MXS_AUART_CLK *32 ) /CONFIG_BAUDRATE ;
You're not checking the div value here.
drivers/serial/mxs_auart.c line 56
Quoted 8 lines
drivers/serial/mxs_auart.c new file +8
-0+ linectrl |= ((div &0x3F ) <<UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET ) + &UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK ; + linectrl |= ((div >>6 ) <<UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET ) + &UARTAPP_LINECTRL_BAUD_DIVINT_MASK ; + +/* Word length: 8 bits */ + linectrl |= ((0x03 ) <<UARTAPP_LINECTRL_WLEN_OFFSET ) + &UARTAPP_LINECTRL_WLEN_MASK ;
You should clean these three magic numbers above.
Quoted 10 lines
drivers/serial/mxs_auart.c new file +10
-0+/* Enable FIFOs. */ + linectrl |=UARTAPP_LINECTRL_FEN_MASK ; + +/* Write above settings, no parity, 1 stop bit */ +writel (linectrl, ®s->hw_uartapp_linectrl); +} + +int mxs_auart_init (void ) +{ +struct mxs_uartapp_regs *regs =get_uartapp_registers ();
drivers/serial/mxs_auart.c line 77
Quoted 10 lines
drivers/serial/mxs_auart.c new file +10
-0+/* Reset everything */ +mxs_reset_block (®s->hw_uartapp_ctrl0_reg); +/* Disable interrupts */ +writel (0 , ®s->hw_uartapp_intr); +/* Set baud rate and settings */ +serial_setbrg (); +/* +* Disable RTS and CTS, +* use values in LINECTRL register instead of LINECTRL2 +*/
Won't this fit on one line ?
[...]