assembler: error for the wrong syntax of SEND instruction on GEN6+

PATCH In review Ben Widawsky 3 participants 4 messages Aug 14, 2013 – Aug 20, 2013

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Ben Widawsky

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2013-08-14 21:22 UTC #0 lore raw

PATCH 1/1 assembler: error for the wrong syntax of SEND instruction on GEN6+

From: "Xiang, Haihao" <[email protected]>

predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions predicate SEND execsize dst sendleadreg payload imm32reg instoptions predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions

The above four syntaxes are only used on legacy platforms which support implied move from payload to dst.

Signed-off-by Xiang, Haihao <[email protected]>

Signed-off-by Ben Widawsky <[email protected]>

---

Somehow this ended up in our internal IGT. Anyone have an issue with me pushing it to igt proper?

---
 assembler/gram.y | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

assembler/gram.y +13 -3

index e58c1fe..8795797 100644
@@ -1215,6 +1215,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
 		}
 		| predicate sendop execsize dst sendleadreg payload directsrcoperand instoptions
 		{
+		  if (IS_GENp(6))
+                      error(&@2, "the syntax of send instruction\n");
+
 		  memset(&$$, 0, sizeof($$));
 		  set_instruction_opcode(&$$, $2);
 		  GEN(&$$)->header.destreg__conditionalmod = $5.nr; /* msg reg index */

@@ -1233,6 +1236,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
 		  }
 		| predicate sendop execsize dst sendleadreg payload imm32reg instoptions
                 {
+		  if (IS_GENp(6))
+                      error(&@2, "the syntax of send instruction\n");
+
 		  if ($7.reg.type != BRW_REGISTER_TYPE_UD &&
 		      $7.reg.type != BRW_REGISTER_TYPE_D &&
 		      $7.reg.type != BRW_REGISTER_TYPE_V) {

@@ -1336,6 +1342,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
 		}
 		| predicate sendop execsize dst sendleadreg payload sndopr imm32reg instoptions
 		{
+		  if (IS_GENp(6))
+                      error(&@2, "the syntax of send instruction\n");
+
 		  if ($8.reg.type != BRW_REGISTER_TYPE_UD &&
 		      $8.reg.type != BRW_REGISTER_TYPE_D &&
 		      $8.reg.type != BRW_REGISTER_TYPE_V) {

@@ -1355,15 +1364,16 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
 		  if (set_instruction_src1(&$$, &$8, &@8) != 0)
 		    YYERROR;
 
-		  if (IS_GENp(8)) {
-		      gen8_set_eot(GEN8(&$$), !!($7 & EX_DESC_EOT_MASK));
-		  } else if (IS_GENx(5)) {
+		  if (IS_GENx(5)) {
 		      GEN(&$$)->bits2.send_gen5.sfid = ($7 & EX_DESC_SFID_MASK);
 		      GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($7 & EX_DESC_EOT_MASK);
 		  }
 		}
 		| predicate sendop execsize dst sendleadreg payload exp directsrcoperand instoptions
 		{
+		  if (IS_GENp(6))
+                      error(&@2, "the syntax of send instruction\n");
+
 		  memset(&$$, 0, sizeof($$));
 		  set_instruction_opcode(&$$, $2);
 		  GEN(&$$)->header.destreg__conditionalmod = $5.nr; /* msg reg index */

Signature · 1 line

1.8.3.4

Damien Lespiau

Reviewed-by on v1 1/1

2013-08-15 11:00 UTC #1 lore raw

Quoted 10 lines · Ben Widawsky

From: "Xiang, Haihao" <[email protected]>
predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions predicate SEND execsize dst sendleadreg payload imm32reg instoptions predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions
The above four syntaxes are only used on legacy platforms which support implied move from payload to dst.

Quoted 6 lines

Signed-off-by Xiang, Haihao <[email protected]>
Signed-off-by Ben Widawsky <[email protected]>
---
Somehow this ended up in our internal IGT. Anyone have an issue with me pushing it to igt proper?

Maybe just a small rewording of "the syntax of send instruction" error message. Otherwise:

Reviewed-by Damien Lespiau <[email protected]>

Signature · 1 line

Damien

Quoted 66 lines

---
 assembler/gram.y | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

assembler/gram.y +13 -3

index e58c1fe..8795797 100644
@@ -1215,6 +1215,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
 		}
 		| predicate sendop execsize dst sendleadreg payload directsrcoperand instoptions
 		{
+		  if (IS_GENp(6))
+                      error(&@2, "the syntax of send instruction\n");
+
 		  memset(&$$, 0, sizeof($$));
 		  set_instruction_opcode(&$$, $2);
 		  GEN(&$$)->header.destreg__conditionalmod = $5.nr; /* msg reg index */

@@ -1233,6 +1236,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
 		  }
 		| predicate sendop execsize dst sendleadreg payload imm32reg instoptions
                 {
+		  if (IS_GENp(6))
+                      error(&@2, "the syntax of send instruction\n");
+
 		  if ($7.reg.type != BRW_REGISTER_TYPE_UD &&
 		      $7.reg.type != BRW_REGISTER_TYPE_D &&
 		      $7.reg.type != BRW_REGISTER_TYPE_V) {

@@ -1336,6 +1342,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
 		}
 		| predicate sendop execsize dst sendleadreg payload sndopr imm32reg instoptions
 		{
+		  if (IS_GENp(6))
+                      error(&@2, "the syntax of send instruction\n");
+
 		  if ($8.reg.type != BRW_REGISTER_TYPE_UD &&
 		      $8.reg.type != BRW_REGISTER_TYPE_D &&
 		      $8.reg.type != BRW_REGISTER_TYPE_V) {

@@ -1355,15 +1364,16 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
 		  if (set_instruction_src1(&$$, &$8, &@8) != 0)
 		    YYERROR;
 
-		  if (IS_GENp(8)) {
-		      gen8_set_eot(GEN8(&$$), !!($7 & EX_DESC_EOT_MASK));
-		  } else if (IS_GENx(5)) {
+		  if (IS_GENx(5)) {
 		      GEN(&$$)->bits2.send_gen5.sfid = ($7 & EX_DESC_SFID_MASK);
 		      GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($7 & EX_DESC_EOT_MASK);
 		  }
 		}
 		| predicate sendop execsize dst sendleadreg payload exp directsrcoperand instoptions
 		{
+		  if (IS_GENp(6))
+                      error(&@2, "the syntax of send instruction\n");
+
 		  memset(&$$, 0, sizeof($$));
 		  set_instruction_opcode(&$$, $2);
 		  GEN(&$$)->header.destreg__conditionalmod = $5.nr; /* msg reg index */

Signature · 6 lines

1.8.3.4

_______________________________________________
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Ben Widawsky

2013-08-15 21:47 UTC #2 lore raw

Quoted 15 lines · Damien Lespiau

Quoted 14 lines · Ben Widawsky
From: "Xiang, Haihao" <[email protected]>
predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions predicate SEND execsize dst sendleadreg payload imm32reg instoptions predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions
The above four syntaxes are only used on legacy platforms which support implied move from payload to dst.
Signed-off-by Xiang, Haihao <[email protected]>
Signed-off-by Ben Widawsky <[email protected]>
---

Quoted 8 lines

Quoted 2 lines
Somehow this ended up in our internal IGT. Anyone have an issue with me pushing it to igt proper?
Maybe just a small rewording of "the syntax of send instruction" error message. Otherwise:
Reviewed-by Damien Lespiau <[email protected]>

I forgot to reword... but I had meant to. Already pushed, feel free to fix up. Sorry.

Signature · 1 line

Ben Widawsky, Intel Open Source Technology Center

Damien Lespiau

2013-08-20 13:27 UTC #3 lore raw

Quoted 2 lines · Ben Widawsky

I forgot to reword... but I had meant to. Already pushed, feel free to fix up. Sorry.

Done! Hopefully slighty better.

Signature · 1 line

Damien